Chip classification method and apparatus, electronic device, and computer-readable medium

Abstract

The present application discloses a chip classification method and apparatus, an electronic device, and a computer-readable medium. The method comprises: acquiring test signals of a plurality of single modules in a chip under test; marking the test signals of the plurality of single modules, so as to obtain result marking signals for the test signals of the plurality of single modules, wherein the result marking signals are used to identify whether the single modules are faulty; on the basis of the result marking signals for the test signals of the plurality of single modules, determining a test result of the chip; and on the basis of the test result, classifying the chip to obtain a classification result.

Description

Chip classification method and device, electronic device, and computer-readable medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application CN 202311292053.0, filed on September 28, 2023, entitled “Chip binning method and device, electronic device, and computer-readable medium,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to chip testing technology, and in particular to a chip classification method and device, electronic equipment, and computer-readable medium. Background Art

[0004] As chip manufacturing process size continues to shrink and transistor density increases, how to improve chip yield is one of the technologies that must be focused on in the chip design, manufacturing and testing stages.

[0005] Chip binning (also known as chip boxing) technology can classify chips into different categories according to certain rules, adapting to different scenarios to improve chip yield. Traditional binning technology relies on manual observation, that is, the integrated circuit automatic test equipment (ATE) machine needs to rely on the test vectors of the functional modules on the input side that are separately constructed or the test vectors of the functional modules that are output on the output side that are separately output, and use professional test software to perform a huge amount of analysis work to obtain a fault-free (PASS) or faulty (FAIL) result. However, with the gradual increase in chip scale and complexity and the exponential growth of chip test vectors, facing high-complexity chips, the design stage often undergoes multiple iterations, and the test vectors and binning schemes need to change frequently. Therefore, traditional binning technology needs to be updated multiple times to adapt to the changes in chip iterations, which increases the difficulty of chip binning and reduces the efficiency of chip binning.

[0006] Summary of the Invention

[0007] The main purpose of this application is to provide a chip classification method and device, electronic device, and computer-readable medium to reduce the difficulty of chip binning and improve the efficiency of chip binning.

[0008] An embodiment of the present application provides a chip classification method, comprising: obtaining test signals of multiple single modules in a chip to be tested; marking the test signals of the multiple single modules to obtain result marking signals of the test signals of the multiple single modules, wherein the result marking signal is used to identify whether the single module has a fault signal; determining the test result of the chip to be tested based on the result marking signal of the test signals of the multiple single modules; and classifying the chip based on the test result to obtain a classification result.

[0009] An embodiment of the present application provides a chip classification device, including: an acquisition module, used to obtain test signals of multiple single modules in a chip to be tested; a marking module, used to mark the test signals of the multiple single modules, and obtain result marking signals of the test signals of the multiple single modules, and the result marking signal is used to identify whether the single module has a fault signal; a determination module, used to determine the test result of the chip to be tested based on the result marking signal of the test signals of the multiple single modules; and a classification module, used to classify the chip based on the test result and obtain a classification result.

[0010] An embodiment of the present application provides an electronic device, comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors implement the chip classification method according to the present application.

[0011] An embodiment of the present application provides a storage medium on which a computer program is stored. When the program is executed by a processor, the chip classification method according to the present application is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a flow chart of a chip classification method according to an embodiment of the present application;

[0013] FIG2 is a schematic structural diagram of a chip classification device according to an embodiment of the present application;

[0014] FIG3 is a schematic diagram illustrating the principle of automatic identification and shielding of a memory built-in self-test (MBIST) according to an embodiment of the present application;

[0015] FIG4 is a schematic diagram showing the principle of performing shielding logic on a test signal according to an embodiment of the present application;

[0016] FIG5 is a schematic structural diagram of a scanning unit according to an embodiment of the present application;

[0017] FIG6 is a circuit diagram of a scanning unit and a shielding module according to an embodiment of the present application;

[0018] FIG7 is a schematic structural diagram of a feature compression subunit according to an embodiment of the present application;

[0019] FIG8 is a schematic diagram of the structure of a data transfer network according to an embodiment of the present application;

[0020] FIG9 is a schematic diagram illustrating the principle of writing and reading compressed information in a one-time programmable memory (EFUSE) of a Design for Yield (DFY) control module according to an embodiment of the present application;

[0021] FIG10 is a schematic structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solution of the present application, the server provided in the present application is described in detail below with reference to the accompanying drawings.

[0023] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the scope of this application to those skilled in the art.

[0024] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] The terms used herein are used only to describe specific embodiments and are not intended to limit this application. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0026] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present application. Accordingly, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the elements, but are not intended to be limiting.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0028] Chips produced on wafers are often imperfect and need to be categorized based on functional modules, stable clock frequency, and required voltage. This categorization process is called "binning" or "boxing." Binned chips can be applied in different scenarios, maximizing the utilization of each chip and improving the overall chip yield.

[0029] Currently, a single wafer can be divided into several to hundreds of different "bins." Traditional chip binning technology relies on manual observation at the output side. Specifically, the ATE machine relies on test vectors for individually constructed functional modules or individually output functional modules, and uses test software to perform extensive analysis to bin the chips. However, with the gradual increase in chip size and complexity and the exponential growth in chip test vectors, traditional chip binning technology faces the following drawbacks:

[0030] 1) The large number of test vectors and the complexity of binning scenarios place extremely high demands on the analysis software of ATE equipment;

[0031] 2) When modules include mirrored modules, traditional chip binning technology cannot quickly identify and locate the faulty module, greatly affecting chip binning efficiency.

[0032] 3) When faced with highly complex chips, the design phase often undergoes multiple iterations, and test vectors and chip binning schemes need to change frequently. Traditional chip binning technology needs to be updated multiple times to adapt to changes in chip iterations, which increases the difficulty of chip binning and reduces the efficiency of chip binning.

[0033] Therefore, how to reduce the difficulty of chip binning and improve the efficiency of chip binning has become one of the technologies that urgently needs to be solved.

[0034] The present invention provides a chip classification method, and Figure 1 is a flowchart of the chip classification method according to the present invention. As shown in Figure 1, the chip classification method according to the present invention includes steps S101 to S104.

[0035] In step S101 , test signals of multiple single modules in a chip to be tested are obtained.

[0036] The test signal is the structural data signal inside the chip to be tested after the test vector is input into the chip to be tested. The test vector is the data vector used to test the chip.

[0037] In step S102, marking processing is performed on the test signals of the multiple single modules to obtain result marking signals of the test signals of the multiple single modules.

[0038] The result marking signal is used to identify whether a single module has a fault. The test signal of each single module is marked to obtain a corresponding result marking signal.

[0039] It should be noted that a single module can also be called a single-function module. Multiple single modules are set in the chip, and the functions of these single modules can be the same or different.

[0040] In step S103 , the test result of the chip to be tested is determined based on the result mark signals of the test signals of the multiple single modules.

[0041] In step S104 , the chips are classified based on the test results to obtain classification results.

[0042] According to the chip classification method provided by the embodiment of the present application, the test signal of a single module is marked and processed to obtain a result mark signal of the test signal. Since the result mark signal is used to identify whether a single module has a fault signal, and each single module has a corresponding result mark signal, during chip testing, it is only necessary to determine the test result of the chip to be tested based on the result mark signal of the test signal of multiple single modules, and no longer directly based on the test signal, which reduces the difficulty of analysis, thereby reducing the difficulty of chip binning and improving the efficiency of chip binning; moreover, since the chip test is only based on the result mark signal of a single module, even if the chip binning scheme and / or test vector changes, the result mark signal is not affected, and the efficiency of chip binning is not affected. In addition, since each single module has a corresponding result mark signal, even if there is a mirror module, the single module can be distinguished, the single module test result can be quickly identified, and the module positioning can be achieved.

[0043] In some embodiments, before determining the test result of the chip to be tested based on the result marking signals of the test signals of multiple single modules (ie, step S103), it also includes: shielding the test signal of the single module marked as faulty, and then retesting the chip to be tested.

[0044] In some embodiments, mask logic is used to select test signals to shield the test signals of faulty modules. After shielding the faulty test signals, the test vector is input into the chip again and retested through steps S101 to S104 until all test signals of unshielded modules are fault-free.

[0045] In some embodiments, the test signal of a single module includes an MBIST signal and a scan test signal. The MBIST signal and the scan test signal can be respectively subjected to marking processing to obtain corresponding result marking signals.

[0046] In some embodiments, the MBIST signal includes a ready status bit signal (ready_sms) and a fail status bit signal (sms_fail).

[0047] When the test signal of a single module is an MBIST signal, the test signals of multiple single modules are marked to obtain result marking signals of the test signals of multiple single modules (i.e., step S102), including: negating the ready state bit signal to obtain a ready state bit negated signal; and obtaining a result marking signal of the test signal based on the ready state bit negated signal and the fail state bit signal.

[0048] For example, the ready_sms signal is inverted to obtain the inverted signal of ready_sms, and then the inverted signal of ready_sms is ORed with the sms_fail signal to obtain a result mark signal of the test signal.

[0049] When the ready state bit signal ready_sms is 1, the sms_fail signal is 0, the negated signal of ready_sms is 0, and the result flag signal obtained by the negated signal of ready_sms and the sms_fail signal is 0, it means that the MBIST signal is fault-free. In the other cases (ready_sms is 0 or sms_fail signal is 1), the result flag signal obtained is 1, which means that the MBIST signal is faulty, as shown in Table 1.

[0050] Table 1 is the relationship between ready_sms, fail_sms and MBIST results

[0051] When the test signal of a single module is a scanning test signal, the test signals of multiple single modules are marked to obtain result marking signals of the test signals of multiple single modules (i.e., step S102), including: compressing the scanning test signal of the single module to obtain a test compression feature vector; comparing the test compression feature vector with a preset ideal feature vector to obtain a result marking signal of the test signal.

[0052] In some embodiments, the scan test signal of a single module includes n groups of scan test patterns, each group of scan test patterns includes k cycles, where n and k are integers greater than or equal to 1.

[0053] For the i-th cycle, compression processing is performed based on the scan test vector composed of the scan test signal of the i-th cycle of each group, the test compression feature vector of the i-1-th cycle and the feedback coefficient to obtain the test compression feature vector of the i-th cycle.

[0054] For the (i+1)th cycle, a test compression feature vector of the (i+1)th cycle is obtained based on the scan test vector of the (i+1)th cycle of each group, the test compression feature vector of the (i)th cycle, and the feedback coefficient.

[0055] Specifically, the scan test signal of a single module can be represented by a vector matrix D: D = [D0 D1 … D i … D k-1 ]

[0056] in,

[0057] D i Represents a scan test vector composed of the scan test signals of the i-th cycle of each group.

[0058] For the i-th cycle, scan the test vector D i After compression processing, the test compression feature vector Y of the i-th cycle is obtained i .

[0059] For the i+1th cycle, test the compressed feature vector Y i+1 The feature vector Y can be compressed by the test of the i-th cycle i and the scan test vector D of the i+1th cycle i+1 Get: Y i+1 =MISR(Y i ,D i+1 )

[0060] g n is the multiple-input signature register (MISR) feedback coefficient. Each feedback coefficient corresponds to the connection between the register and the XOR gate. The feedback coefficient determines the difference in the algorithm for generating the eigenvalue.

[0061] The MISR principle is expressed in vector matrix form as follows:

[0062] Among them, gj Represents the feedback coefficient corresponding to the j-th scan test signal.

[0063] The above compression processing is an effective feature compression processing method, through which the scan test signal is processed into a set of feature vectors.

[0064] In some embodiments, the step of comparing the test compression feature vector and the preset ideal feature vector to obtain a result marking signal of the test signal includes: comparing the test compression feature vector and the preset ideal feature vector to obtain a vector comparison result; and obtaining a result marking signal of the test signal based on the vector comparison result.

[0065] The ideal eigenvector refers to the eigenvector output by the correct circuit. Before the chips are binned, the ideal eigenvector output by the correct circuit can be known in advance.

[0066] In some embodiments, the test compressed feature vector, the ideal feature vector, and the vector comparison result have the same number of bits, for example, the number of bits is 8 bits.

[0067] The step of comparing the test compressed feature vector and the preset ideal feature vector to obtain a vector comparison result includes: comparing the eigenvalues ​​on the same bit in the test compressed feature vector and the ideal feature vector to obtain a bit comparison result, when the eigenvalues ​​are different, the bit comparison result is a first preset value, and when the eigenvalues ​​are the same, the bit comparison result is a second preset value; and determining the vector comparison result based on the bit comparison results of multiple bits.

[0068] This embodiment does not limit the first preset value and the second preset value. For example, the first preset value is "1" and the second preset value is "0." When the feature values ​​are different, the bit comparison result is 1, and when the feature values ​​are the same, the bit comparison result is 0.

[0069] When the number of bits is 8, the vector comparison result includes 8-bit comparison results.

[0070] In some embodiments, the step of obtaining a result marking signal of a test signal based on a vector comparison result includes: in the vector comparison result, if there is at least one bit comparison result that is a first preset value, then the result marking signal of the test signal is a faulty signal; in the vector comparison result, if all bit comparison results are a second preset value, then the result marking signal of the test signal is a non-faulty signal.

[0071] In an embodiment of the present application, the test signal is marked according to the comparison result of each bit in the vector comparison result. When there is at least one bit comparison result of "1" in the vector comparison result, that is, as long as there is a bit comparison result of "1" in the vector comparison result, the result marking signal of the test signal is a faulty signal; if all bit comparison results are "0", the result marking signal of the test signal is a non-faulty signal.

[0072] In some embodiments, before the step of compressing the scan test signal of a single module and obtaining a test compression feature vector, it also includes: processing the scan test pattern for unknown circuit state values, removing or shielding the unknown state of the circuit of the chip to be tested, and ensuring that the scan test pattern has no uncertain state values.

[0073] In the actual binning process, the unknown value (X-state) of the circuit in the chip is the main factor affecting the accuracy of feature compression. Generally speaking, the X-state comes from uninitialized memory cells, non-scan triggers, undriven inputs, erroneous behavior of analog-to-digital conversion and clock domain crossing in the circuit. In the process of generating the scan test pattern, multi-cycle paths will also bring certain X-state pollution (X-pollution) problems. Ultimately, the X-state will destroy the compressed features accumulated in multiple test cycles, which will lead to a decrease in the accuracy of feature compression or even failure. Therefore, in the process of generating the scan test pattern, it is necessary to solve the X-state problem through technologies such as X-state removal (X-clean) and X-state constraint (X-bounding), so as to obtain a higher quality test signal. This embodiment does not limit the circuit unknown value processing technology, and may include, for example, X-state removal (X-clean) and X-state constraint (X-bounding) technology.

[0074] In some embodiments, after obtaining the result mark signals of the test signals of multiple single modules (ie, step S102 ), the method further includes: transferring, storing, and downloading the result mark signals of the test signals to a yield design one-time programmable memory via a data transfer network.

[0075] After the result mark signal of the test signal is stored in the yield design one-time programmable memory (DFY_efuse), it can be compared through the comparison enable signal (comp_en signal) when needed, and the comparison result is output when the comp_en signal is pulled high.

[0076] In some embodiments, classifying the chips based on the test results to obtain the classification results (ie, step S104 ) includes classifying the chips based on the functions of the single modules corresponding to the fault-free result marking signals in the test results to obtain the classification results.

[0077] A chip includes multiple modules with different functions, which can be categorized based on their functions. For example, modules with a fault-free first function can be classified into the first category, while modules with a fault-free second function can be classified into the second category. The result flag signal can be used to determine which modules are fault-free and which are faulty. The chip can be categorized based on the combination of the fault-free modules and the result flag signal.

[0078] The present invention also provides a chip classification device. FIG2 is a schematic diagram of the structure of the chip classification device according to the present invention. As shown in FIG2 , the chip classification device 200 according to the present invention includes: an acquisition module 21, a marking module 22, a determination module 23, and a classification module 24.

[0079] The acquisition module 21 is used to acquire test signals of multiple single modules in the chip to be tested.

[0080] The test signal is the structural data signal inside the chip to be tested after the test vector is input into the chip to be tested. The test vector is the data vector used to test the chip.

[0081] The marking module 22 is used to perform marking processing on the test signals of the multiple single modules to obtain result marking signals of the test signals of the multiple single modules.

[0082] The result marking signal is used to identify whether a single module has a fault. The test signal of each single module is marked to obtain a corresponding result marking signal.

[0083] The determination module 23 is configured to determine the test result of the chip to be tested based on the result mark signals of the test signals of the multiple single modules.

[0084] The classification module 24 is used to classify the chips based on the test results to obtain classification results.

[0085] In some embodiments, the classification module 24 is configured to classify the chips based on the functions of the single modules corresponding to the fault-free result marking signals in the test results to obtain classification results.

[0086] According to the chip classification device provided by the embodiment of the present application, the acquisition module 21 acquires the test signals of multiple single modules in the chip to be tested, and the marking module 22 marks the test signals of the single modules to obtain the result marking signals of the test signals. Since the result marking signal is used to identify whether the single module has a fault signal, and each single module has a corresponding result marking signal, during chip testing, the determination module 23 only needs to determine the test result of the chip to be tested based on the result marking signals of the test signals of multiple single modules. The classification module 24 classifies the chip based on the test result to obtain the classification result, no longer directly based on the test signal, which reduces the difficulty of analysis, thereby reducing the difficulty of chip binning and improving the efficiency of chip binning; moreover, since the chip test is only based on the result marking signal of the single module, even if the chip binning scheme and / or test vector changes, the result marking signal is not affected, and the efficiency of chip binning is not affected. In addition, since each single module has a corresponding result marking signal, even if there is a mirror module, the single module can be distinguished, the single module test result can be quickly identified, and the module positioning can be achieved.

[0087] In some embodiments, the chip classification device further includes: a shielding module, configured to shield the test signal of a single module marked as faulty, that is, shield the test signal of the single module with fault for retesting.

[0088] FIG3 is a schematic diagram showing the principle of MBIST automatic identification and shielding according to an embodiment of the present application.

[0089] As shown in Figure 3, a plurality of single modules 20, an acquisition module 21, a marking module 22, a module controller 26, and a shielding module 25 are provided in the chip. Each single module 20 corresponds to an acquisition module 21, a marking module 22, a shielding module 25, and a module controller 26. The acquisition module 21 can be an MBIST unit, which is used to obtain the test signal of the single module 20. The marking module 22 is used to mark the test signal to obtain the result mark signal. The module controller 26 is used to control the path of the marking module 22 and the shielding module 25, and the flow direction of control data.

[0090] In some embodiments, the acquisition module 21 includes an MBIST unit, and the marking module 22 performs marking processing on the test signal output by the MBIST unit to obtain a result marking signal.

[0091] In some embodiments, the test signal output by the MBIST unit includes a ready state bit signal (ready_sms) and a fail state bit signal (sms_fail), and the marking module 22 inverts the ready state bit signal to obtain a ready state bit inverted signal; and, based on the ready state bit inverted signal and the fail state bit signal, obtains a result marking signal of the test signal.

[0092] For example, the ready_sms signal is inverted to obtain the inverted signal of ready_sms, and then the inverted signal of ready_sms is ORed with the sms_fail signal to obtain a result mark signal of the test signal.

[0093] The marking module 22 sends the result marking signal to the shielding module 25, and the shielding module 25 shields the test signal based on the result marking signal to shield the test signal of the faulty single module to prevent the faulty single module from outputting a signal.

[0094] Specifically, the shielding module 25 negates the result flag signal and then ANDs it with the MBIST signal. If the single module has no faults, the result flag signal is 0, and the test signal of the single module is not shielded, that is, the MBIST signal is not changed; if the single module has a fault, the result flag signal is 1, then the test signal of the single module is shielded, and the test signal of the single module is always set to 0.

[0095] FIG4 is a schematic diagram showing the principle of performing shielding logic on a test signal according to an embodiment of the present application.

[0096] In some embodiments, the test signal can be a key output signal of a single module, such as the bira_mode_r, current_error, current_error_int, and clr_err_reg signals. For example, the bira_mode_r signal is ANDed with the negated result flag signal. If the result flag signal is 0, the bira_mode_r signal is not masked, i.e., the output of the bira_mode_r signal remains unchanged. If the result flag signal is 1, the bira_mode_r signal is masked and is always set to 0.

[0097] In some embodiments, after obtaining the result flag signal, the result flag signal can also be stored in the yield design one-time programmable memory (DFY_efuse) module 27. When needed, the shielding module 25 can obtain the result flag signal of the test signal of a single module from the DFY_efuse module 27.

[0098] In some embodiments, the chip further includes a controller 28 and a central processing unit 29. The controller 28 is used to control the single module 20, the acquisition module 21, the marking module 22, and the module controller 26. The central processing unit 29 is used to process some data in the chip.

[0099] In some embodiments, the acquisition module 21 includes a scanning unit. FIG5 is a schematic structural diagram of the scanning unit according to an embodiment of the present application.

[0100] As shown in FIG5 , the scanning unit includes a test response subunit 51 , a feature compression subunit 52 and a comparison circuit subunit 53 .

[0101] The test response subunit 51 is used to obtain a scan test signal.

[0102] The test response subunit 51 responds to the test signal from the control circuit 54 to obtain a scan test signal. The scan test signal is the signal edt-out obtained by the test response subunit 51 from the circuit under test 56 when the circuit under test 56 executes the test vector edt-in after the test vector edt-in is input into the circuit under test 56 through the test stimulus module 55.

[0103] The feature compression subunit 52 is used to perform compression processing on the scan test signal to obtain a test compression feature vector.

[0104] The processing manner in which the feature compression subunit 52 compresses the scan test signal is the same as the compression processing manner described in the embodiment of the aforementioned chip classification method, and will not be repeated here.

[0105] In some embodiments, the test compressed feature vector may be stored in the DFY_efuse module 57 .

[0106] The comparison circuit subunit 53 is used to compare the test compression feature vector with a preset ideal feature vector to obtain a result mark signal of the test signal.

[0107] The ideal feature vector is stored in a storage module, for example, in the DFY_efuse module 57. The result flag signal includes a no-fault (PASS) signal and a fault (FAIL) signal.

[0108] FIG6 is a circuit diagram of a scanning unit and a shielding module according to an embodiment of the present application.

[0109] As shown in FIG6 , the scan test signal dcc_dft_edt_out output by the test response subunit 51 is input beat by beat into the feature compression subunit 52 for feature compression. The feature compression subunit 52 may be a multiple-input signature register (MISR). The feature compression subunit 52 calculates a test compression feature vector sig_out and transmits the test compression feature vector sig_out to the comparison circuit subunit 53.

[0110] In some embodiments, the scanning unit further includes a link subunit 58 , which is disposed between the feature compression subunit 52 and the comparison circuit subunit 53 and is configured to transmit the test compressed feature vector to the comparison circuit subunit 53 .

[0111] As shown in Figure 6, the link sub-unit 58 inputs the test compression feature vector sig_out into the first input end of the XOR in the comparison circuit sub-unit 53, and the ideal feature vector Golden_sig is input into the second input end of the XOR through the link sub-unit 58. The test compression feature vector sig_out and the ideal feature vector Golden_sig are compared at the bit level by XOR (exclusive OR processing), and OR processing is performed on the input to output the bit comparison result.

[0112] When the test compressed eigenvector sig_out is compared with the ideal eigenvector Golden_sig, if the eigenvalues ​​of the bits are the same, "0" is output, that is, a PASS signal is output; if the eigenvalues ​​of the bits are different, "1" is output, that is, a FAIL signal is output.

[0113] When the number of bits of the test compressed feature vector sig_out and the ideal feature vector Golden_sig is 8 bits, the number of bits of the bit comparison result is also 8 bits.

[0114] In the embodiment of the present application, the comparison enable (comp_en) signal can also be input into the comparison circuit subunit 53 through the link subunit 58. The comp_en signal can be used as a switch signal to control the output of the result flag signal, that is, to control the output of the bit comparison result.

[0115] It should be noted that the result mark signal output by the comparison circuit sub-unit 53 can also be shielded by the selection signal.

[0116] In some embodiments, the scanning unit further includes an EDT module 59 for implementing EDT compression logic.

[0117] In some embodiments, the scan test signal includes n groups of scan test patterns, each group of scan test patterns includes k cycles, where n and k are integers greater than or equal to 1. Accordingly, the feature compression subunit 52 includes a plurality of linear feedback shift registers (LFSRs), which are sequentially signal-connected.

[0118] FIG7 is a schematic structural diagram of a feature compression subunit according to an embodiment of the present application.

[0119] As shown in FIG7 , the feature compression subunit includes a plurality of feature registers DFF0, DFF1, DFF2, ... DFF n-1 ,The eigenvalue output by the feature register is the state of the register. The eigenvalue output by the feature register is not only related to the current state, but also to the eigenvalue of the real-time input.

[0120] As mentioned before, for the i-th cycle, the test compressed feature vector Y of the i-th cycle is i Expressed as:

[0121] For the i+1th cycle, the test compressed feature vector Y of the i+1th cycle i+1 The feature vector Y can be compressed by the test of the i-th cycle i and the scan test vector D of the i+1th cycle i+1 Get: Y i+1 =MISR(Y i ,D i+1 )

[0122] g n is the MISR feedback coefficient. Each feedback coefficient corresponds to the connection relationship between the register and the XOR gate. The feedback coefficient determines the difference in the algorithm for generating the eigenvalue.

[0123] In some embodiments, the device also includes a data transfer network, which includes: a control (sub_tap) module for transferring input and output test signals; a yield improvement module (DFY_sub_tap), and the control (sub_tap) module and the yield improvement module (DFY_sub_tap) jointly realize the transfer of the result marking signal of the test signal.

[0124] FIG8 is a schematic diagram of the structure of a data transfer network according to an embodiment of the present application.

[0125] As shown in FIG8 , the test results of the chip under test are written into the DFY_efuse module through the strobe module.

[0126] Specifically, the main control module 81 simultaneously turns on the enable signal tap_en of the control module 82 and the DFY control module 83 through dedicate_dr_chain, configures the yield mode (DFY_mode) to 01, and configures mux_1, mux_2 and mux_3 to 1, thereby realizing the upper and lower cascade relationship between the control module 82 and the DFY control module 83, thereby forming a loop from the main control module 81 to the control module 82 and then to the DFY control module 83.

[0127] Table 2 shows the correspondence between DFY_mode and mux, where mux represents the gating of the link.

[0128] Table 2

[0129] FIG9 is a schematic diagram showing the principle of writing and reading compressed information in efuse by a DFY control module according to an embodiment of the present application.

[0130] As shown in FIG. 9 , the control module 91 includes a yield_up_DR_chain module 911 , and the DFY control module 92 includes a DFY_efuse module 921 , an ef_ctrl_DR_chain 922 , an ef_w_DR_chain 923 , and an ef_r_DR_chain 924 .

[0131] JTAG_IRLOAD is used to select the yield_up_DR_chain module 911 and the write data register chain DR_chain (i.e., ef_w_DR_chain 923) of the DFY control module 92. The obs_pi data in the yield_up_DR_chain module 911 is shifted to the ef_w_DR_chain 923 of the DFY control module 92. At the same time, ef_w_DR_chain 923 is connected to the corresponding write bit in the DFY_efuse module 921. After enabling ef_ctrl_DR_chain 922 in the DFY control module 92, the ef_atuo_mode automatic data write mode is enabled, and the data in ef_w_DR_chain 923 is burned into the DFY_efuse module 921.

[0132] In Figure 8, the main control module 81 turns on the enable signal tap_en of the control module 82 and the DFY control module 83 at the same time through dedicate_dr_chain (sub_tap select_DR), configures DFY_mode to 10, and configures mux_1, mux_2 and mux_3 to 0, thereby realizing the upper and lower cascade relationship between the DFY control module 83 and the control module 82, thereby forming a loop from the main control module 81 to the DFY control module 83 and then to the control module 82.

[0133] As shown in Figure 9, JTAG_IRLOAD is used to select the read data register chain DR_chain (i.e., ef_r_DR_chain 924) and yield_up_DR_chain module 911 in DFY control module 92. The corresponding read bit of DFY_efuse module 921 is connected to ef_r_DR_chain 924, allowing the obs_pi data in ef_r_DR_chain 924 to be transferred to yield_up_DR_chain module 911. At the same time, ef_ctrl_DR_chain 922 in DFY control module 92 is configured and ef_atuo_mode is enabled to enter automatic data read mode, allowing data to be read from DFY_efuse module 921.

[0134] It should be noted that the chip classification method and device provided in the embodiments of the present application transmit data inside the chip during the identification, storage, downloading and retesting processes, without the need for auxiliary information processing outside the chip. It is a closed-loop process. Therefore, while reducing the difficulty of chip binning and improving the efficiency of chip binning, it is also highly automated, fast and efficient.

[0135] 10 , an embodiment of the present application provides an electronic device, comprising: one or more processors 1001; and a memory 1002 on which one or more programs are stored. When the one or more programs are executed by one or more processors, the one or more processors implement any one of the above-mentioned chip classification methods.

[0136] As shown in FIG. 10 , the electronic device may further include one or more I / O interfaces 1003 connected between the processor 1001 and the memory 1002 and configured to implement information interaction between the processor 1001 and the memory 1002 .

[0137] The processor 1001 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 1002 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 1003 is connected between the processor 1001 and the memory 1002, and can realize information interaction between the processor 1001 and the memory 1002, including but not limited to a data bus (Bus), etc.

[0138] In some embodiments, the processor 1001 , the memory 1002 , and the I / O interface 1003 are connected to each other via a bus, and further connected to other components of the computing device.

[0139] An embodiment of the present application provides a computer-readable medium having a computer program stored thereon, which implements any of the above-mentioned chip binning methods when the program is executed by a processor.

[0140] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods applied for above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0141] Example embodiments have been claimed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A chip classification method, comprising: Obtain test signals of multiple single modules in the chip under test; Marking the test signals of the multiple single modules to obtain result marking signals of the test signals of the multiple single modules, wherein the result marking signals are used to identify whether the single modules are faulty; Determining a test result of the chip to be tested based on result marking signals of the test signals of the multiple single modules; The chip is classified based on the test result to obtain a classification result.

2. The method according to claim 1, wherein: Before determining the test result of the chip to be tested based on the result mark signals of the test signals of the multiple single modules, the method further includes: The test signal of the single module marked as faulty is shielded, and then the chip to be tested is retested.

3. The method according to claim 1 or 2, wherein: The test signal comprises a memory built-in self-test MBIST signal, wherein the MBIST signal comprises a ready state bit signal and a fail state bit signal, Performing marking processing on the test signals of the multiple single modules to obtain result marking signals of the test signals of the multiple single modules includes: Performing an inversion process on the ready state bit signal to obtain an inverted ready state bit signal; A result flag signal of the test signal is obtained based on the ready state bit negation signal and the fail state bit signal.

4. The method according to claim 1 or 2, wherein: The test signal comprises a scanning test signal, The test signals of the plurality of single modules are marked to obtain the test signals of the plurality of single modules. The result marking signals of the module's test signals include: Performing compression processing on the scanning test signal of the single module to obtain a test compression feature vector; The test compression feature vector is compared with a preset ideal feature vector to obtain a result marking signal of the test signal.

5. The method according to claim 4, wherein: The scan test signal of the single module includes n groups of scan test patterns, each group of the scan test patterns includes k cycles, wherein: n and k are integers greater than or equal to 1; For the ith cycle, compression processing is performed based on the scan test vector composed of the scan test signal of the ith cycle of each group, the test compression feature vector of the i-1th cycle and the feedback coefficient to obtain the test compression feature vector of the ith cycle.

6. The method according to claim 5, wherein: Comparing the test compression feature vector with a preset ideal feature vector to obtain a result marking signal of the test signal includes: Comparing the test compressed feature vector with the preset ideal feature vector to obtain a vector comparison result; A result flag signal of the test signal is obtained based on the vector comparison result.

7. The method according to claim 6, wherein: The test compressed feature vector, the ideal feature vector and the vector comparison result have the same number of bits, Comparing the test compression feature vector with the preset ideal feature vector to obtain a vector comparison result includes: Comparing the eigenvalues ​​at the same bit position in the test compressed eigenvector and the ideal eigenvector to obtain a bit position comparison result, wherein when the eigenvalues ​​are different, the bit position comparison result is a first preset value, and when the eigenvalues ​​are the same, the bit position comparison result is a second preset value; The vector comparison result is determined based on the bit comparison results of the plurality of bits.

8. The method according to claim 7, wherein: Obtaining a result marking signal of the test signal based on the vector comparison result includes: In the vector comparison result, if there is at least one bit comparison result that is the first preset value, then the result marking signal of the test signal is a fault signal; In the vector comparison result, if all bit comparison results are the second preset value, the result mark signal of the test signal is a fault-free signal.

9. The method according to claim 5, wherein: Before compressing the scan test signal of the single module to obtain the test compression feature vector, the method further includes: The scan test pattern is processed with a circuit unknown state value to remove or shield the unknown state of the circuit of the chip to be tested.

10. The method according to claim 1, wherein: After obtaining result mark signals of the test signals of the plurality of single modules, the method further includes: The result marking signal of the test signal is transferred, stored and downloaded via a data transfer network.

11. The method according to claim 10, wherein: Classifying the chip based on the test result to obtain a classification result includes: The chip is classified based on the function of the single module corresponding to the result marking signal without fault in the test result to obtain the classification result.

12. A chip sorting device, comprising: An acquisition module is used to acquire test signals of multiple single modules in the chip to be tested; a marking module, used for marking the test signals of the plurality of single modules to obtain result marking signals of the test signals of the plurality of single modules, wherein the result marking signal is used to identify whether the single module has a fault; A determination module is used to mark the signal based on the result of the test signal of the plurality of single modules. Determine the test result of the chip to be tested; A classification module is used to classify the chip based on the test result to obtain a classification result.

13. The apparatus according to claim 12, further comprising: The shielding module is used to shield the test signal of a single module marked as faulty.

14. The device according to claim 12 or 13, wherein: The acquisition module includes an MBIST unit, and the test signal output by the MBIST unit includes a ready state bit signal and a failure state bit signal. The marking module is used for: Performing an inversion process on the ready state bit signal to obtain an inverted ready state bit signal; and A result flag signal of the test signal is obtained based on the ready state bit negation signal and the fail state bit signal.

15. The device according to claim 12 or 13, wherein: The acquisition module includes a scanning unit, and the scanning unit includes: A test response subunit, used for obtaining a scanning test signal; A feature compression subunit, used for compressing the scan test signal to obtain a test compression feature vector; The comparison circuit subunit is used to compare the test compression feature vector with a preset ideal feature vector to obtain a result marking signal of the test signal.

16. The device according to claim 15, wherein: The scanning unit also includes: A link subunit is provided between the feature compression subunit and the comparison circuit subunit, and is used for transmitting the test compression feature vector to the comparison circuit subunit.

17. The device according to claim 15, wherein: The feature compression subunit includes a plurality of linear feedback shift registers, and the plurality of linear feedback shift registers are signal-connected in sequence.

18. The device according to claim 12, wherein: The classification module is used to classify the chip based on the function of the single module corresponding to the result marking signal without fault in the test result to obtain the classification result.

19. An electronic device comprising: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1-11.

20. A computer readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 11.

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