Test arrangement and test method for measuring a semiconductor wafer

Abstract

A test arrangement (100) for measuring a semiconductor wafer (40) is specified, wherein the test arrangement (100) comprises : a carrier (1) for placing the semiconductor wafer (40), wherein the carrier (1) includes : an electrically insulating base body (2), a plurality of first conductive lines ( 3 ) and a plurality of second conductive lines ( 4 ), which are arranged on the base body (2) so as to face the semiconductor wafer (40) and which cross each other at crossing points (C), a test device (10), which comprises at least one pair of a first contact element (11) assigned to the first conductive lines (3) and a second contact element (12) assigned to the second conductive lines ( 4 ), wherein the at least one pair of the first contact element (11) and the second contact element (12) defines a test area (A) on the semiconductor wafer (40) comprising at least one crossing point (C), wherein the first conductive lines (3) are provided for supplying a driving current to the semiconductor wafer (40) at the crossing points (C), and the second conductive lines (4) are provided for determining an electrical characteristic value of the semiconductor wafer (40) at the crossing points (C). Moreover, a test method for measuring a semiconductor wafer is specified.

Description

[0001] Description

[0002] TEST ARRANGEMENT AND TEST METHOD FOR MEASURING A SEMICONDUCTOR WAFER

[0003] A test arrangement and a test method for measuring a semiconductor wafer are speci fied . For example , the semiconductor wafer is suited for the production of a plurality of semiconductor components . The semiconductor components may be LEDs , for example pLEDs , or VCSELs .

[0004] In order to obtain spatially resolved information about electrical characteristic values like driving current and voltage of a semiconductor wafer, rasteri zing methods are known, in which, for example , a measurement is made at each raster point . The measurement can be conducted, for example , by a 4-wire measurement at the top of the semiconductor wafer, wherein current driving wires and voltage sensing wires are separated as long as possible . The 4-wire measurement leads to a lower measurement deviation than a less complex 2-wire measurement because the voltage measurement can be carried out over wires which do not drive any current , whereas in the 2-wire measurement not only the voltage is sensed over the wires but also the voltage drop .

[0005] The 2-wire measurement may be conducted, for example , by contacting a metalli zed back side of the semiconductor wafer by a conductive metal carrier and supplying a driving current between the back side and the top side of the semiconductor wafer . Problems caused by contacting the back side of the semiconductor wafer by the conductive metal carrier are , for example , providing current to regions of the semiconductor wafer which are not meant to be powered and varying resistances over the entire contact area of the conductive metal carrier . The varying resistances may be caused on the one hand by di f ferent topographies of the wafer and the carrier and on the other hand by an inhomogeneity of the metalli zation of the back side . The hori zontal current spreading and the varying resistances lead to uncertain measurements .

[0006] One obj ect inter alia is to speci fy a test arrangement providing for an improved measurement accuracy of characteristic values of the semiconductor wafer . This obj ect is achieved inter alia by the test arrangement according to the independent claim . Further embodiments and further developments of the test arrangement are the subj ect-matter of the dependent claims .

[0007] Another obj ect inter alia is to speci fy a test method for measuring a semiconductor wafer providing for an improved measurement accuracy of characteristic values of a semiconductor wafer . This obj ect is achieved inter alia by the test method according to the independent claim . Further embodiments and further developments of the test method are the subj ect-matter of the dependent claims .

[0008] According to at least one embodiment of a test arrangement for measuring a semiconductor wafer, the test arrangement comprises a carrier for placing the semiconductor wafer . The carrier comprises a base body, which may be electrically insulating . In addition, the carrier may comprise a plurality of first conductive lines , which are arranged on the base body so as to face the semiconductor wafer . Moreover, the carrier may comprise a plurality of second conductive lines , which are arranged on the base body so as to face the semiconductor wafer . For example , the plurality of first and second conductive lines are arranged on a top side of the carrier, wherein the semiconductor wafer is arranged on the top side during testing especially in direct contact with the top side . In particular, the plurality of first and second conductive lines are electrically conductive lines . Moreover, the plurality of first conductive lines and the plurality of second conductive lines may cross each other at crossing points .

[0009] According to at least one embodiment , the first conductive lines are provided for supplying a driving current to the semiconductor wafer at the crossing points . Moreover, the second conductive lines may be provided for determining an electrical characteristic value of the semiconductor wafer at the crossing points . For example , the electrical characteristic value is a voltage like a forward voltage of the semiconductor wafer . The crossing points may serve in each case as points of entrance to the semiconductor wafer . Hence , the first conductive lines , which may be provided as driving or force lines , and the second conductive lines , which may be provided as voltage sensing lines , are separated from each other as far as they get into contact with the semiconductor wafer at the crossing points . Thus , when the semiconductor wafer is energi zed by means of the carrier, hori zontal current spreading over the whole carrier can be suppressed . Moreover, common conductive paths shared by both the first and second conductive lines are shortened . All this provides for an improved measurement accuracy or smaller measurement deviation of characteristic values of the semiconductor wafer like the forward voltage . According to at least one embodiment , the test arrangement comprises a test device , which is provided to be placed on the semiconductor wafer on a side facing away from the carrier . During testing the semiconductor wafer may be arranged on the carrier in such a way that a bottom side of the semiconductor wafer faces the top side of the carrier and a top side of the semiconductor wafer faces the test device . Especially, during testing the test device is arranged in such a way that it is in direct contact with the top side of the semiconductor wafer .

[0010] According to at least one embodiment , the test device comprises at least one pair of a first contact element and a second contact element , wherein the first contact element is assigned to the first conductive lines and the second contact element is assigned to the second conductive lines . For example , the first contact element and the second contact element are needles .

[0011] The at least one pair of the first contact element and the second contact element may define a test area on the semiconductor wafer comprising at least one , preferably more than one , crossing point . During testing, a driving current may be provided between every first conductive line of the test area and the first contact element and an electrical characteristic value may be determined between every second conductive line of the test area and the second contact element . For example , the test area may cover only a part of the semiconductor wafer . In this case , the test device may be moved in relation to the semiconductor wafer during testing to measure the entire semiconductor wafer, or the test device may comprise more than one test area defined by more than one pair of a first and second contact element in order to measure the entire semiconductor wafer .

[0012] Advantageously, the test arrangement allows for electrically contacting the semiconductor wafer on two di f ferent sides by means of the carrier and the test device and for separating the driving lines from the sensing lines up to the crossing points .

[0013] According to at least one embodiment of a test arrangement for measuring a semiconductor wafer, the test arrangement comprises :

[0014] - a carrier for placing the semiconductor wafer, wherein the carrier includes :

[0015] - an electrically insulating base body,

[0016] - a plurality of first conductive lines , which are arranged on the base body so as to face the semiconductor wafer, and

[0017] - a plurality of second conductive lines , which are arranged on the base body so as to face the semiconductor wafer, wherein the plurality of first conductive lines and the plurality of second conductive lines cross each other at crossing points ,

[0018] - a test device , which is provided to be placed on the semiconductor wafer on a side facing away from the carrier and which comprises at least one pair of a first contact element assigned to the first conductive lines and a second contact element assigned to the second conductive lines , wherein the at least one pair of the first contact element and the second contact element defines a test area on the semiconductor wafer comprising at least one crossing point , wherein the first conductive lines are provided for supplying a driving current to the semiconductor wafer at the crossing points , and the second conductive lines are provided for determining an electrical characteristic value of the semiconductor wafer at the crossing points .

[0019] It is an advantage of the test arrangement that current paths through the semiconductor wafer can be influenced by means of the carrier, which increases the measurement accuracy of the characteristic value that is determined .

[0020] According to at least one embodiment or configuration, the electrically insulating base body comprises or consists of a polymer . A suitable material is nylon, for example .

[0021] According to at least one embodiment or configuration, the plurality of first conductive lines run essentially parallel to each other . Moreover, the plurality of second conductive lines may run essentially parallel to each other . Here , "essentially" means that deviations are possible within common production tolerances . Moreover, the plurality of first conductive lines may cross the plurality of second conductive lines at angles greater than 0 ° and smaller than 180 ° . For example , the plurality of first conductive lines may cross the plurality of second conductive lines at essentially right angles . Hence , the plurality of first and second conductive lines may constitute a matrix-like arrangement or grid-like arrangement . The crossing points may form a rectangular point grid .

[0022] According to at least one embodiment or configuration, the test arrangement comprises a control unit for selecting pairs in each case of a first conductive line and a second conductive line crossing each other at one crossing point of the test area from the plurality of first and second conductive lines . For example , the control unit may comprise or consist of a high-density matrix or multiplexer module . Moreover, the control unit may be suited for determining the electrical characteristic value of the semiconductor wafer at the crossing points . Hence , it is possible to determine a pair of characteristic values , which are for example the driving current and the voltage , for every selected pair of a first conductive line and a second conductive line .

[0023] According to at least one embodiment or configuration, the test arrangement is provided for measuring a semiconductor wafer including an active area, which is suitable for emitting electromagnetic radiation, for example having a wavelength in the visible spectral range , when the semiconductor wafer is supplied with the driving current . For example , the semiconductor wafer may comprise a semiconductor layer sequence including a first semiconductor layer of a first conductivity type , for example a p-doped semiconductor layer, and a second semiconductor layer of a second conductivity type , for example an n-doped semiconductor layer . The active area may be arranged between the first and second semiconductor layers .

[0024] The semiconductor wafer may contain materials based on arsenide , phosphide or nitride compound semiconductors , for example . "Based on arsenide , phosphide or nitride compound semiconductors" means in the present context that the semiconductor wafer contains AlnGamIni-n-mAs , AlnGamIni-n-mP, InnGai-nAsmPi-mor AlnGamlnx-n-mN, where 0 < n < 1 , 0 < m < 1 and n+m < 1 . This material does not necessarily have to have a mathematically exact composition according to the above formula . Rather, it may have one or more dopants as well as additional constituents that do not substantially change the characteristic physical properties of the AlnGamlnx-n-mAs , AlnGamIni-n-mP, InnGai-nAsmPi-mor AlnGamIni-n-mN material . For simplicity, however, the above formula includes only the essential constituents of the crystal lattice (Al , Ga, In, As or P or N, respectively) , even though these may be partially replaced by small amounts of other substances . A quinternary semiconductor consisting of Al , Ga, In ( group I I I ) and P and As ( group V) is also conceivable .

[0025] According to at least one embodiment or configuration, the test arrangement comprises a detection unit for detecting the electromagnetic radiation . Especially, the detection unit allows for measuring the electromagnetic radiation emitted from the test area . The electromagnetic radiation may represent another characteristic value that can be determined by the test arrangement .

[0026] The test method described in the following can be executed with a test arrangement of the kind as mentioned above . Therefore , all features described in connection with the test arrangement apply to the test method as well , and vice versa .

[0027] According to at least one embodiment of a test method for measuring a semiconductor wafer, the test method comprises the following steps , preferably in the cited order :

[0028] - providing a test arrangement of the kind as mentioned above ,

[0029] - placing a semiconductor wafer on the carrier of the test arrangement in such a way that the plurality of first conductive lines and the plurality of second conductive lines face the semiconductor wafer,

[0030] - placing the test device of the test arrangement on the semiconductor wafer on a side facing away from the carrier,

[0031] - selecting at least one pair of a first conductive line and a second conductive line from the plurality of first and second conductive lines , wherein the first conductive line and the second conductive line cross each other at a crossing point of the test area,

[0032] - providing a driving current to the semiconductor wafer between the first contact element and the first conductive line of the at least one selected pair, and

[0033] - determining an electrical characteristic value of the semiconductor wafer between the second contact element and the second conductive line of the at least one selected pair .

[0034] According to at least one embodiment or configuration, the electrical characteristic value which is determined between the second contact element and the second conductive line is a voltage , for example a forward voltage .

[0035] The test method allows for determining a pair of characteristic values , which are for example the driving current and the voltage , for every selected pair of a first conductive line and a second conductive line .

[0036] For example , the driving current provided at the selected crossing point flows through the semiconductor wafer in an essentially vertical direction . In particular, the vertical direction runs oblique or perpendicular to a main extension plane of the semiconductor wafer . The main extension plane of the semiconductor wafer may be a hori zontal plane .

[0037] According to at least one embodiment or configuration, a high potential is applied to the first contact element , whereas the first conductive lines are provided with a low potential , which is switched below the high potential to provide the driving current .

[0038] According to at least one embodiment or configuration, all pairs of a first conductive line and a second conductive line crossing each other at one crossing point are selected . Hence , electrical characteristic values or pairs of characteristic values may be determined for all crossing points .

[0039] According to at least one embodiment or configuration, the pairs of a first conductive line and a second conductive line crossing each other at one crossing point are selected sequentially . In accordance therewith, the first conductive lines may be addressed one after another . And, the second conductive lines may be addressed one after another, too . Especially, the test method is a rasteri zing method, wherein the semiconductor wafer is measured by a raster of test areas .

[0040] According to at least one embodiment or configuration, the semiconductor wafer is embodied in such a way that it comprises bond pads where the at least one pair of a first contact element and a second contact element is placed . For example , the bond pads are regularly arranged on the top side of the semiconductor wafer . The bond pads may be arranged in a grid-like manner . According to at least one embodiment or configuration, the bond pads are embodied in such a way that they comprise an opening in each case . For example , the bond pads are embodied in a ring-like manner having circular openings .

[0041] According to at least one embodiment or configuration, the semiconductor wafer emits electromagnetic radiation when a driving current is supplied, and the electromagnetic radiation passes the opening of the bond pad of the test area . It is an advantage of the test method that a hori zontal spread of the driving current can be limited to the region of the bond pads so that a more accurate measurement of the brightness of the electromagnetic radiation is possible .

[0042] The test arrangement and the test method are suitable for quick test , waferprober, VCSEL-prober , laser and quality aging tester applications .

[0043] The test arrangement and the test method will be further explained in conj unction with the Figures described in the following .

[0044] Figure 1A shows a schematic cross sectional view of an exemplary embodiment of a test arrangement , and Figure IB shows a schematic plan view of a part of the test arrangement shown in Figure 1A,

[0045] Figure 2A shows a schematic plan view and Figure 2B a schematic cross sectional view of a method stage of an exemplary embodiment of a test method, and Figure 3 shows a schematic cross sectional view of a method stage of a comparative embodiment of a test method .

[0046] Identical , equivalent or equivalently acting elements may be indicated with the same reference numerals in the figures . The figures are schematic illustrations and thus not necessarily true to scale . Comparatively small elements and particularly layer thicknesses can rather be illustrated exaggeratedly large for the purpose of better clari fication .

[0047] In accordance with Figures 1A and IB, an exemplary embodiment of a test arrangement 100 is described . The test arrangement 100 can be used for measuring a semiconductor wafer 40 . For example , the semiconductor wafer 40 is suited for the production of a plurality of semiconductor components like LEDs , for example pLEDs , or VCSELs . A plurality of semiconductor bodies 44 may be singulated from the semiconductor wafer 40 after testing and further processed into semiconductor components like LEDs , for example pLEDs , or VCSELs . The semiconductor wafer 40 may be suitable for emitting electromagnetic radiation, for example having a wavelength in the visible spectral range . For example , the semiconductor wafer 40 comprises a semiconductor layer sequence including a first semiconductor layer 41 of a first conductivity type , for example an n-doped semiconductor layer, an active area 42 and a second semiconductor layer 43 of a second conductivity type , for example a p-doped semiconductor layer, wherein the active area 42 is arranged between the first and second semiconductor layers 41 , 43 . The semiconductor wafer 40 may contain materials based on arsenide , phosphide or nitride compound semiconductors as mentioned above . The test arrangement 100 comprises a carrier 1 , on which the semiconductor wafer 40 is placed during testing . For example , the semiconductor wafer 40 can be brought in direct contact with a top side 1A of the carrier 1 .

[0048] The carrier 1 includes an electrically insulating base body 2 comprising or consisting of a polymer like nylon, for example . Moreover, the carrier 1 comprises at its top side 1A a plurality of first electrically conductive lines 3 and a plurality of second electrically conductive lines 4 ( see Figure IB ) , which are arranged on the base body 2 so as to face the semiconductor wafer 40 . The plurality of first conductive lines 3 and the plurality of second conductive lines 4 cross each other at crossing points C ( see Figure IB ) . For example , the plurality of first conductive lines 3 are arranged essentially parallel to each other . The same may apply to the second conductive lines 4 . Moreover, every first conductive line 3 may intersect every second conductive line 4 at an essentially right angle . Hence , the crossing points C may constitute a rectangular point grid . Suitable materials for the conductive lines 3 , 4 are for example metals or TCOs ( transparent conductive oxides ) .

[0049] The test arrangement 100 further comprises a test device 10 , which during testing is placed on the semiconductor wafer 40 on a top side 40A facing away from the carrier 1 . The test device 10 comprises at least one pair of a first contact element 11 assigned to the first conductive lines 3 and a second contact element 12 assigned to the second conductive lines 4 . For example , the first contact element 11 and the second contact element 12 are needles . The first contact element 11 and the second contact element 12 may be brought in direct contact with the top side 40A during testing . They define a test area A on the semiconductor wafer 40 , which in this case may comprise more than one crossing point C and is smaller than the top side 40A of the semiconductor wafer 40 . During testing, the semiconductor wafer 40 is measured in the test area A. Generally, the first conductive lines 3 are provided for supplying a driving current to the semiconductor wafer 40 at the crossing points C . And the second conductive lines 4 are provided for determining an electrical characteristic value , for example a voltage like a forward voltage of the semiconductor wafer 40 at the crossing points C .

[0050] The test arrangement 100 may further comprise a control unit 20 . Generally, pairs in each case of a first conductive line 3 and a second conductive line 4 crossing each other at one crossing point C can be selected by the control unit 20 from the plurality of first and second conductive lines 3 , 4 . During testing, those pairs are selected whose crossing points C are in the test area A. The test area A may be moved in relation to the semiconductor wafer 40 to measure the entire semiconductor wafer 40 . For example , the control unit 20 comprises or consists of a high-density matrix or multiplexer module .

[0051] The test arrangement 100 may further comprise a detection unit 30 for detecting the electromagnetic radiation emitted by the semiconductor wafer 40 during testing . The electromagnetic radiation may be another characteristic value which can be determined by the test arrangement 100 in addition to the voltage . The test arrangement 100 has a compact design, wherein the semiconductor wafer 40 can be electrically contacted by the electrically conductive lines 3 , 4 on a bottom side 40B and by the contact elements 11 , 12 on the top side 40A. Moreover, the test arrangement 100 provides for an improved measurement accuracy due to the first and second conductive lines 3 , 4 , which allow for decoupling the driving current from the voltage measurement and shortening a common conductive path shared by both and suppressing hori zontal current spreading over the whole carrier 1 .

[0052] In accordance with Figures 2A and 2B, an exemplary embodiment of a test method is described .

[0053] The test method comprises a step of providing a test arrangement 100 , for example of the kind as described in connection with Figures 1A and IB . Thus , all features and advantages described in connection with the test arrangement 100 apply to the test method as well and vice versa .

[0054] Moreover, the test method comprises a step of placing a semiconductor wafer 40 on the carrier 1 of the test arrangement 100 in such a way that the plurality of first conductive lines 3 and the plurality of second conductive lines 4 face the semiconductor wafer 40 . Especially, the semiconductor wafer 40 is directly arranged on the top side 1A of the carrier 1 such that the conductive lines 3 , 4 touch the bottom side 40B of the semiconductor wafer 40 .

[0055] Furthermore , the test method comprises a step of placing the test device 10 of the test arrangement 100 on the semiconductor wafer 40 on the top side 40A facing away from the carrier 1 . Especially, the test device 10 is directly arranged on the semiconductor wafer 40 such that the contact elements 11 , 12 touch the top side 40A of the semiconductor wafer 40 .

[0056] In addition, the test method comprises a step of selecting pairs in each case of a first conductive line 3 and a second conductive line 4 from the plurality of first and second conductive lines 3 , 4 , wherein the first conductive line 3 and the second conductive line 4 of each pair cross each other at a crossing point C of the test area A. A driving current is provided to the semiconductor wafer 40 between the first contact element 11 and the first conductive line 3 of each pair, and an electrical characteristic value , for example a voltage like a forward voltage of the semiconductor wafer 40 is determined between the second contact element 12 and the second conductive line 4 for every selected pair of the test area A. Especially, a high potential is applied to the first contact element 11 , whereas the first conductive lines 3 are provided with a low potential , which is switched below the high potential to provide the driving current . The test method allows for determining a pair of characteristic values , which may be the driving current and the voltage , for every selected pair of a first conductive line 3 and a second conductive line 4 .

[0057] Preferably, the test method comprises selecting all pairs of a first conductive line 3 and a second conductive line 4 crossing each other at one crossing point C . Especially, the test method is a rasteri zing method, wherein the whole semiconductor wafer 40 is measured by a raster of test areas A. For example , the test area A may be moved in relation to the semiconductor wafer 40 , following a predetermined raster to select all pairs . The pairs may be selected sequentially . The semiconductor wafer 40 may be embodied in such a way that it comprises bond pads 45 ( Figures 2A and 2B show only a part of the semiconductor wafer 40 and thus only one bond pad 45 ) where the at least one pair of a first contact element 11 and a second contact element 12 is placed . Advantageously, the hori zontal current spread I only occurs in the test area A. In comparison thereto , the hori zontal current spread I takes place over the whole top side 1A of the carrier 1 i f the carrier 1 consists of an electrically conductive material like a metal material ( see Figure 3 ) .

[0058] The bond pads 45 are embodied in such a way that they comprise an opening 46 in each case . I f the semiconductor wafer 40 emits electromagnetic radiation R when a driving current is supplied, the electromagnetic radiation R passes the opening 46 of the bond pad 45 of the test area A. As the hori zontal spread of the driving current is limited to the test area A, side emissions of the radiation R outside the test area A can be suppressed so that the brightness can be measured with improved accuracy in comparison to the comparative example of Figure 3 .

[0059] The invention is not limited to these embodiments by the description based on the embodiments . Rather, the invention includes any new feature and any combination of features , which includes in particular any combination of features in the patent claims , even i f this feature or this combination itsel f is not explicitly indicated in the patent claims or embodiments . This patent application claims the priority of German patent application 102023126417.6, the disclosure content of which is hereby incorporated by reference.

[0060] References

[0061] 1 carrier

[0062] 1A top side

[0063] 2 base body

[0064] 3 first conductive line

[0065] 4 second conductive line

[0066] 10 test device

[0067] 11 first contact element

[0068] 12 second contact element

[0069] 20 control unit

[0070] 30 detection unit

[0071] 40 semiconductor wafer

[0072] 40A top side

[0073] 40B bottom side

[0074] 41 first semiconductor layer

[0075] 42 active area

[0076] 43 second semiconductor layer

[0077] 44 component

[0078] 45 bond pad

[0079] 46 opening

[0080] 100 test arrangement

[0081] A test area

[0082] C crossing point

[0083] I current spread

[0084] R electromagnetic radiation

Claims

Claims1. A test arrangement (100) for measuring a semiconductor wafer (40) , wherein the test arrangement (100) comprises:- a carrier (1) for placing the semiconductor wafer (40) , wherein the carrier (1) includes:- an electrically insulating base body (2) ,- a plurality of first conductive lines (3) , which are arranged on the base body (2) so as to face the semiconductor wafer (40) , and- a plurality of second conductive lines (4) , which are arranged on the base body (2) so as to face the semiconductor wafer (40) , wherein the plurality of first conductive lines (3) and the plurality of second conductive lines (4) cross each other at crossing points (C) ,- a test device (10) , which is provided to be placed on the semiconductor wafer (40) on a side facing away from the carrier (1) and which comprises at least one pair of a first contact element (11) assigned to the first conductive lines (3) and a second contact element (12) assigned to the second conductive lines (4) , wherein the at least one pair of the first contact element (11) and the second contact element (12) defines a test area (A) on the semiconductor wafer (40) comprising at least one crossing point (C) , wherein the first conductive lines (3) are provided for supplying a driving current to the semiconductor wafer (40) at the crossing points (C) , and the second conductive lines (4) are provided for determining an electrical characteristic value of the semiconductor wafer (40) at the crossing points (C) .

2. The test arrangement (100) according to the preceding claim, wherein the second conductive lines (4) are provided for determining a voltage of the semiconductor wafer (40) at the crossing points (C) .

3. The test arrangement (100) according to any of the preceding claims, wherein the electrically insulating base body (2) comprises or consists of a polymer.

4. The test arrangement (100) according to any of the preceding claims, wherein the plurality of first conductive lines (3) run essentially parallel to each other and the plurality of second conductive lines (4) run essentially parallel to each other, and the plurality of first conductive lines (3) cross the plurality of second conductive lines (4) at angles greater than 0° and smaller than 180°.

5. The test arrangement (100) according to any of the preceding claims, which comprises a control unit (20) for selecting pairs in each case of a first conductive line (3) and a second conductive line (4) crossing each other at one crossing point (C) of the test area (A) from the plurality of first and second conductive lines (3, 4) .

6. The test arrangement (100) according to any of the preceding claims, which is provided for measuring a semiconductor wafer (40) including an active area (42) , which is suitable for emitting electromagnetic radiation (R) when the semiconductor wafer (40) is supplied with the driving current .

7. The test arrangement (100) according to the preceding claim, which comprises a detection unit (3 ) for detecting the electromagnetic radiation (R) .

8. The test arrangement (100) according to any of the preceding claims, wherein the first contact element (11) and the second contact element (12) are needles.

9. A test method for measuring a semiconductor wafer (40) , wherein the test method comprises:- providing a test arrangement (100) according to any of the preceding claims,- placing a semiconductor wafer (40) on the carrier (1) of the test arrangement (100) in such a way that the plurality of first conductive lines (3) and the plurality of second conductive lines (4) face the semiconductor wafer (40) ,- placing the test device (10) of the test arrangement (100) on the semiconductor wafer (40) on a side facing away from the carrier ( 1 ) ,- selecting at least one pair of a first conductive line (3) and a second conductive line (4) from the plurality of first and second conductive lines (3, 4) , wherein the first conductive line (3) and the second conductive line (4) cross each other at a crossing point (C) of the test area (A) ,- providing a driving current to the semiconductor wafer (40) between the first contact element (11) and the first conductive line (3) of the at least one selected pair, and- determining an electrical characteristic value of the semiconductor wafer (40) between the second contact element (12) and the second conductive line (4) of the at least one selected pair.

10. The test method according to the preceding claim, wherein the electrical characteristic value which is determined between the second contact element (12) and the second conductive line (4) is a voltage.

11. The test method according to either of the two preceding claims, wherein all pairs of a first conductive line (3) and a second conductive line (4) crossing each other at one crossing point (C) are selected.

12. The test method according to the preceding claim, wherein the pairs of a first conductive line (3) and a second conductive line (4) crossing each other at one crossing point (C) are selected sequentially.

13. The test method according to any of claims 9 to 12, wherein the semiconductor wafer (40) is embodied in such a way that it comprises bond pads (45) where the at least one pair of a first contact element (11) and a second contact element (12) is placed.

14. The test method according to the preceding claim, wherein the bond pads (45) are embodied in such a way that they comprise an opening (46) in each case.

15. The test method according to the preceding claim, wherein the semiconductor wafer (40) emits electromagnetic radiation (R) when a driving current is supplied, and the electromagnetic radiation (R) passes the opening (46) of the bond pad (45) of the test area (A) .

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