Test device, test method, and program

Abstract

Provided is a test device comprising: a pattern generation unit that generates a protocol pattern that is for testing a device to be tested, and that has a plurality of cycles which each include a predetermined number of designated patterns; and a sequence control unit that controls the pattern generation unit in accordance with a first command having a plurality of steps and a second command having a plurality of steps. The pattern generation unit generates the protocol pattern such that at least one of the plurality of cycles includes a signal pattern corresponding to at least one of the steps of the first command and a signal pattern corresponding to at least one of the steps of the second command.

Description

Testing device, testing method and program

[0001] The present invention relates to a test device, a test method, and a program.

[0002] Patent Document 1 describes a "testing apparatus and testing method for testing a memory under test." [Prior art documents] [Patent documents] [Patent document 1] Japanese Patent Application Laid-Open No. 2007-200371 [Patent document 2] Japanese Patent Application Laid-Open No. 2010-165422 [Patent document 3] Japanese Patent Application Laid-Open No. 2009-93227 [Patent document 4] Japanese Patent Application Laid-Open No. 2012-103016 General disclosure

[0003] In a first aspect of the present invention, there is provided a test apparatus comprising: a pattern generation unit that generates a protocol pattern for testing a device under test, the protocol pattern having a plurality of cycles, each cycle consisting of a predetermined number of specified patterns; and a sequence control unit that controls the pattern generation unit in accordance with a first instruction having a plurality of steps and a second instruction having a plurality of steps, wherein the pattern generation unit generates the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction.

[0004] In the above test apparatus, the number of the steps included in the first command may be greater than the number of specified patterns.

[0005] In any of the above test apparatuses, the pattern generation unit may generate a first cycle including a signal pattern corresponding to at least one step of the plurality of steps included in the first instruction. The sequence control unit may determine whether or not there are any remaining steps among the plurality of steps included in the first instruction that have not been used to generate the first cycle. If there are no remaining steps, the sequence control unit may control the pattern generation unit to generate a second cycle, which is a cycle subsequent to the first cycle, with a signal pattern corresponding to at least one step of the second instruction. If there are remaining steps and the number of remaining steps is greater than the specified number of patterns, the sequence control unit may control the pattern generation unit to generate the second cycle with a signal pattern corresponding to the remaining steps. If there are remaining steps and the number of remaining steps is equal to or less than the specified number of patterns, the sequence control unit may control the pattern generation unit to generate the second cycle with a signal pattern corresponding to the remaining steps and a signal pattern corresponding to at least one step of the second instruction.

[0006] In any of the above test apparatuses, the sequence control section may update the remaining steps to include steps of the first instruction and / or the second instruction that were not used to generate the second cycle.

[0007] In any of the above test apparatuses, the pattern generating section may include a plurality of pattern generators, each of which generates a signal pattern corresponding to at least one step of the first instruction or the second instruction.

[0008] In any of the above test devices, the pattern generating section may include a first multiplexer that combines the signal patterns output by the plurality of pattern generators into one continuous signal pattern and outputs the combined signal pattern.

[0009] Any of the above test apparatuses may include a memory unit that stores signal patterns corresponding to each step of the first instruction and the second instruction. Each of the plurality of pattern generators may include a port for accessing the memory unit. Each of the plurality of pattern generators may include an output unit for outputting the signal pattern stored in the memory unit. Each of the plurality of pattern generators may include a second multiplexer provided between the port and the output unit that selects the signal pattern to be output by each of the plurality of pattern generators.

[0010] In any of the above test devices, each of the plurality of pattern generators may include a first reading unit that reads signal patterns corresponding to each step of the first instruction from the memory unit via the port when the number of remaining steps of the first instruction is equal to or greater than the specified number of patterns, and that reads signal patterns corresponding to each step of the second instruction from the memory unit via the port when the number of remaining steps of the first instruction is less than the specified number of patterns.

[0011] In any of the above test devices, each of the plurality of pattern generators may include a second reading unit that, when the number of remaining steps of the first instruction is equal to or greater than the specified number of patterns, reads from the memory unit via the port a signal pattern identical to the signal pattern read by the first reading unit, and, when the number of remaining steps of the first instruction is less than the specified number of patterns, reads from the memory unit via the port a signal pattern corresponding to the remaining steps of the first instruction.

[0012] In any of the above test devices, each of the plurality of pattern generators may include a third reading unit that reads from the memory unit via the port a signal pattern identical to the signal pattern read by the first reading unit in the previous cycle.

[0013] In any of the above test devices, the second multiplexer may select a signal pattern to be output by each of the plurality of pattern generators from the signal patterns read out by the first readout section, the second readout section, and the third readout section.

[0014] In any of the above test devices, the number of specified patterns may be equal to the number of the plurality of pattern generators.

[0015] In any of the above test devices, the number of specified patterns may be a power of two.

[0016] In a second aspect of the present invention, there is provided a testing method comprising: a step of generating, by a computer, a protocol pattern for testing a device under test, the protocol pattern having a plurality of cycles, each cycle consisting of a predetermined number of specified patterns; and a step of controlling, by the computer, the generation of the protocol pattern in accordance with a first instruction having a plurality of steps and a second instruction having a plurality of steps, wherein the step of generating the protocol pattern includes a step of generating the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction.

[0017] In a third aspect of the present invention, there is provided a program that, when executed by a computer, causes the computer to function as a pattern generation unit that generates a protocol pattern for testing a device under test, the protocol pattern having a plurality of cycles, each cycle consisting of a predetermined number of specified patterns, and a sequence control unit that controls the pattern generation unit in accordance with a first instruction having a plurality of steps and a second instruction having a plurality of steps, and that generates the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction.

[0018] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0019] 1 shows an example of the configuration of a test apparatus 100 together with a device under test 10. 1 shows an example of the configuration of an ALPG 20. 1 shows an example of generation of a protocol pattern PAT. 1 shows generation of a protocol pattern PAT according to a comparative example. 1 shows a modified example of generation of a protocol pattern PAT. 1 shows generation of a protocol pattern PAT according to a comparative example. 1 shows an example of a flowchart for generation of a protocol pattern PAT. 1 shows an example of the configuration of a pattern generator 240 together with a sequence control unit 22, a memory unit 26, and a first multiplexer 258. 1 shows a modified example of generation of a protocol pattern PAT. 1 shows an example of a computer 1000 in which multiple aspects of the present invention may be embodied in whole or in part.

[0020] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0021] 1 shows an example of the configuration of a test apparatus 100 together with a device under test 10. The test apparatus 100 includes an ALPG 20, an input section 30, an acquisition section 40, and a judgment section 50, and tests the device under test 10, such as an analog circuit, a digital circuit, a memory, or a system-on-chip (SOC). The test apparatus 100 inputs test signals based on a protocol pattern PAT for testing the device under test 10 to the device under test 10, and judges whether the device under test 10 is good or bad based on response signals output by the device under test 10 in response to the test signals.

[0022] The ALPG 20 generates a protocol pattern PAT for testing the device under test 10. The ALPG 20 also generates an expected value pattern that is expected as a response signal output by the device under test 10.

[0023] The input section 30 generates a test signal based on the protocol pattern PAT generated by the ALPG 20, and inputs the test signal to the device under test 10. The acquiring section 40 acquires a response signal output by the device under test 10.

[0024] The judging section 50 compares the response signal of the device under test 10 acquired by the acquiring section 40 with the expected value pattern generated by the ALPG 20. The judging section 50 judges whether the device under test 10 is good or bad based on the comparison result between the response signal and the expected value pattern.

[0025] 2 shows an example of the configuration of the ALPG 20. The ALPG 20 includes a sequence control unit 22 and a pattern generation unit 24. The ALPG 20 may also include a memory unit 26 and a timing generation unit 28.

[0026] The pattern generating section 24 generates a protocol pattern PAT for testing the device under test 10. The protocol pattern PAT has a plurality of cycles. Each cycle consists of a predetermined number of specified patterns. Details of the protocol pattern PAT will be described later.

[0027] The sequence control unit 22 controls the pattern generation unit 24 in response to a plurality of input instructions. Each of the plurality of instructions may include a plurality of steps. The sequence control unit 22 controls the pattern generation unit 24 in response to a first instruction having a plurality of steps and a second instruction having a plurality of steps. The first instruction and the second instruction may be two consecutive instructions among the plurality of instructions input to the sequence control unit 22. The sequence control unit 22 may control the pattern generation unit 24 to generate a signal pattern corresponding to each step of the first instruction and a signal pattern corresponding to each step of the second instruction. The pattern generation unit 24 may generate a protocol pattern PAT as a single consecutive pattern including a signal pattern corresponding to each step of the first instruction and a signal pattern corresponding to each step of the second instruction. Details of the first instruction and the second instruction will be described later.

[0028] The memory unit 26 may store signal patterns corresponding to each step of the first instruction and the second instruction. The memory unit 26 may store the signal patterns corresponding to each step of the first instruction and the second instruction at different addresses. For example, the memory unit 26 may store the signal patterns corresponding to each step of the first instruction at address 0 and the signal patterns corresponding to each step of the second instruction at address 1.

[0029] The pattern generating unit 24 may generate signal patterns corresponding to each step of the first instruction and the second instruction by accessing the memory unit 26. The sequence control unit 22 may control the pattern generating unit 24 to access the memory unit 26 in order to cause the pattern generating unit 24 to generate signal patterns corresponding to each step of the first instruction and the second instruction.

[0030] The timing generating section 28 may generate a clock signal CLK. The sequence control section 22 may control the pattern generating section 24 in synchronization with the clock signal CLK generated by the timing generating section 28. The period of the multiple cycles of the protocol pattern PAT may be the same as the period of the clock signal CLK. In other words, one period of the clock signal CLK may correspond to one cycle of the protocol pattern PAT.

[0031] The pattern generating section 24 may include a plurality of pattern generators 240 and a first multiplexer 258. In this example, the pattern generating section 24 includes four pattern generators 240. The number of pattern generators 240 included in the pattern generating section 24 is not limited to this. The pattern generating section 24 may include three or fewer pattern generators 240, or may include five or more pattern generators 240. As an example, the number of pattern generators 240 included in the pattern generating section 24 is a power of two.

[0032] Each of the plurality of pattern generators 240 may generate a signal pattern corresponding to at least one step of the first instruction or the second instruction. For example, if the first instruction has four steps, pattern generator 240a may generate a signal pattern corresponding to the first step, pattern generator 240b may generate a signal pattern corresponding to the second step, pattern generator 240c may generate a signal pattern corresponding to the third step, and pattern generator 240d may generate a signal pattern corresponding to the fourth step.

[0033] The first multiplexer 258 may combine the signal patterns output by each of the multiple pattern generators 240 into one continuous signal pattern and output the combined signal pattern. The first multiplexer 258 may output the combined signal pattern as the protocol pattern PAT. For example, if the first instruction has four steps and the pattern generators 240a to 240d generate signal patterns corresponding to the first to fourth steps, respectively, the first multiplexer 258 may combine the signal patterns corresponding to the first to fourth steps and output the signal patterns corresponding to each step of the first instruction as the protocol pattern PAT.

[0034] 3A shows an example of generating a protocol pattern PAT. The protocol pattern PAT in this example includes signal patterns corresponding to each step of command A and command B. Command A and command B are examples of a first command and a second command, respectively. Command A has nine steps (A-1) to (A-9). Command B has nine steps (B-1) to (B-9).

[0035] The protocol pattern PAT in this example has at least four cycles, and each cycle includes four signal patterns. That is, the number of designated patterns in this example is four. The number of designated patterns may be equal to the number of the multiple pattern generators 240. Each of the multiple pattern generators 240 may generate one signal pattern per cycle, so that the number of designated patterns in each cycle is equal to the number of the multiple pattern generators 240. Like the number of the multiple pattern generators 240, the number may be three or less, or five or more. As an example, the number of designated patterns is a power of two.

[0036] The number of steps in the first command may be greater than the number of designated patterns. In this example, command A has 9 steps, which is greater than the number of designated patterns (4 in this example). The number of steps in the second command may be the same as the number of designated patterns, or may be greater than the number of designated patterns. In this example, command B has 9 steps, which is greater than the number of designated patterns.

[0037] The pattern generation unit 24 generates the protocol pattern PAT so that at least one cycle of the multiple cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction. In this example, the pattern generation unit 24 generates the protocol pattern PAT so that cycle 3 includes a signal pattern corresponding to step (A-9) of instruction A and a signal pattern corresponding to steps (B-1) to (B-3) of instruction B.

[0038] In this way, the pattern generation unit 24 of the present example generates the protocol pattern PAT so that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions, thereby enabling efficient processing of instructions having a number of steps greater than the number of designated patterns.

[0039] Although cycles 1 to 4 are shown in this figure, the protocol pattern PAT may include cycles after cycle 4. For example, the protocol pattern PAT of this example includes at least cycle 5, which includes signal patterns corresponding to steps (B-8) and (B-9) of instruction B. Cycle 5 may further include signal patterns corresponding to steps of other instructions after the signal patterns corresponding to steps (B-8) and (B-9) of instruction B.

[0040] 3B shows the generation of a protocol pattern PAT according to a comparative example. In the protocol pattern PAT according to the comparative example, the number of steps in each instruction must match the number of designated patterns.

[0041] In the comparative example, instruction A, which has nine steps, is rewritten into instructions A1 to A3, each having four steps, so that the number of steps in each instruction matches the number of specified patterns. Similarly, instruction B, which has nine steps, is rewritten into instructions B1 to B3, each having four steps. Furthermore, dummy steps such as steps (A-10) to (A12) and steps (B-10) to (B-12) are added so that the number of steps in each instruction matches the number of specified patterns.

[0042] The pattern generation unit 24 according to the embodiment generates a protocol pattern PAT such that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions, and therefore can efficiently process instructions having a number of steps greater than the number of specified patterns without rewriting the instructions and / or adding dummy steps to the instructions.

[0043] 4A shows a modified example of generating a protocol pattern PAT. The protocol pattern PAT of this example includes signal patterns corresponding to each step of command A, command B, and command C. Command A and command B are an example of a first command and a second command, and command B and command C are another example of a first command and a second command. Command A has five steps (A-1) to (A-5), which is greater than the number of specified patterns (4 in this example). Command B has four steps (B-1) to (B-4), which is the same as the number of specified patterns. Command C has four steps (C-1) to (C-4), which is the same as the number of specified patterns.

[0044] In this example, the pattern generation unit 24 generates the protocol pattern PAT so that cycle 2 includes a signal pattern corresponding to step (A-5) of instruction A and a signal pattern corresponding to steps (B-1) to (B-3) of instruction B. In this case, instruction A corresponds to the first instruction, and instruction B corresponds to the second instruction. Furthermore, in this example, the pattern generation unit 24 generates the protocol pattern PAT so that cycle 3 includes a signal pattern corresponding to step (B-4) of instruction B and a signal pattern corresponding to steps (C-1) to (C-3) of instruction C. In this case, instruction B corresponds to the first instruction, and instruction C corresponds to the second instruction. In this way, by the pattern generation unit 24 generating the protocol pattern PAT so that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions, it is possible to efficiently process instructions having a number of steps greater than the specified number of patterns.

[0045] 4B shows the generation of a protocol pattern PAT according to a comparative example. In the comparative example, instructions A, B, and C are rewritten as instructions A1, A2+B1, B2+B1', and B2'+C' so that the number of steps in each instruction matches the number of specified patterns. In this way, if the number of steps in each instruction must match the number of specified patterns, more complex rewriting of instructions than in the comparative example of FIG. 3B may be required.

[0046] The pattern generation unit 24 according to the embodiment generates a protocol pattern PAT such that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions, and therefore can efficiently process instructions having a number of steps greater than the number of specified patterns without requiring complex rewriting of the instructions.

[0047] Increasing the number of pattern generators 240 included in the pattern generation section 24 to increase the speed of the test apparatus 100 also increases the number of specified patterns. In this case, when attempting to process an instruction with a number of steps greater than the number of specified patterns, the problem of dummy steps and / or complex rewriting of instructions becomes even more significant. The pattern generation section 24 of this example generates a protocol pattern PAT such that at least one cycle includes a signal pattern corresponding to at least one step of each of the multiple instructions, thereby enabling efficient processing of instructions with a number of steps greater than the number of specified patterns. This is effective even when the number of specified patterns increases. This allows the speed of the test apparatus 100 to be increased by increasing the number of pattern generators 240.

[0048] 5 shows an example of a flowchart for generating a protocol pattern PAT. However, the method for generating the protocol pattern PAT is not limited to this. The protocol pattern PAT may be generated so that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions.

[0049] In step S100, the pattern generation unit 24 generates a first cycle including a signal pattern corresponding to at least one step among the multiple steps included in the first instruction. For example, in the example of FIG. 3A, the pattern generation unit 24 generates cycle 1 including signal patterns corresponding to steps (A-1) to (A-4) among the nine steps included in instruction A. In this example, cycle 1 corresponds to the first cycle. Furthermore, the pattern generation unit 24 generates cycle 2 including signal patterns corresponding to steps (A-5) to (A-8) among the nine steps included in instruction A. In this example, cycle 2 corresponds to the first cycle.

[0050] In step S102, the sequence control unit 22 determines whether or not there are any remaining steps among the multiple steps of the first instruction that have not been used to generate the first cycle. For example, in the example of FIG. 3A , the sequence control unit 22 determines that there are remaining steps (yes) because, among the nine steps of instruction A, there are steps (A-5) to (A-9) that have not been used to generate cycle 1. In this example, cycle 1 corresponds to the first cycle. Furthermore, the sequence control unit 22 determines that there are remaining steps (yes) because, among the nine steps of instruction A, there is step (A-9) that has not been used to generate cycle 2. In this example, cycle 2 corresponds to the first cycle.

[0051] If it is determined in step S102 that there are no remaining steps (No), in step S104, the sequence control unit 22 controls the pattern generation unit 24 to generate a second cycle, which is the next cycle after the first cycle, with a signal pattern corresponding to at least one step of the second command. In other words, if there are no remaining steps, this means that the generation of signal patterns corresponding to each step of the first command has been completed, and therefore the pattern generation unit 24 may generate the second cycle with a signal pattern corresponding to at least one step of the second command.

[0052] If it is determined in step S102 that there are remaining steps (yes), then in step S106, the sequence control unit 22 determines whether the number of remaining steps is greater than the specified number of patterns. For example, in the example of FIG. 3A, the sequence control unit 22 determines that the number of remaining steps (A-5)-(A-9) not used in generating cycle 1 is greater than the specified number of patterns (4 in this example) (yes). In this example, cycle 1 corresponds to the first cycle. Furthermore, the sequence control unit 22 determines that the number of remaining steps (A-9) not used in generating cycle 2 is less than the specified number of patterns (4 in this example) (no). In this example, cycle 2 corresponds to the first cycle.

[0053] If it is determined in step S106 that the number of remaining steps is greater than the specified number of patterns (yes), in step S108, the sequence control unit 22 controls the pattern generation unit 24 to generate a second cycle with a signal pattern corresponding to the remaining steps. For example, in the example of FIG. 3A , the sequence control unit 22 controls the pattern generation unit 24 to generate cycle 2 with a signal pattern corresponding to steps (A-5) to (A-8) of the remaining steps (A-5) to (A-9) that were not used to generate cycle 1. In this example, cycle 1 corresponds to the first cycle, and cycle 2 corresponds to the second cycle.

[0054] If it is determined in step S106 that the number of remaining steps is equal to or less than the specified number of patterns (No), in step S110, the sequence control unit 22 controls the pattern generation unit 24 to generate a second cycle using a signal pattern corresponding to the remaining steps and a signal pattern corresponding to at least one step of the second instruction. For example, in the example of FIG. 3A , the sequence control unit 22 controls the pattern generation unit 24 to generate cycle 3 using a signal pattern corresponding to the remaining step (A-9) not used in generating cycle 2 and a signal pattern corresponding to steps (B-1) to (B-3) of instruction B. In this example, cycle 2 corresponds to the first cycle, and cycle 3 corresponds to the second cycle. Furthermore, instruction A corresponds to the first instruction, and instruction B corresponds to the second instruction.

[0055] In step S112, the sequence control unit 22 updates the remaining steps to the steps of the first instruction and / or the second instruction that were not used to generate the second cycle. For example, in the example of FIG. 3A , if cycle 1 corresponds to the first cycle and cycle 2 corresponds to the second cycle, the sequence control unit 22 updates step (A-9) of instruction A, which is the first instruction that was not used to generate cycle 2, to the remaining steps. Also, in the example of FIG. 3A , if cycle 2 corresponds to the first cycle and cycle 3 corresponds to the second cycle, the sequence control unit 22 updates steps (B-4) to (B-9) of instruction B, which is the second instruction that was not used to generate cycle 3, to the remaining steps.

[0056] In step S114, the sequence control unit 22 determines whether the generation of the protocol pattern PAT has been completed. If it is determined that the generation of the protocol pattern PAT has been completed (yes), the flow for generating the protocol pattern PAT ends. If it is determined that the generation of the protocol pattern PAT has not been completed (no), the flow returns to step S102, and the flow described above may be repeated.

[0057] According to the above flow, the pattern generation unit 24 generates the protocol pattern PAT so that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions, thereby enabling efficient processing of instructions having a number of steps greater than the number of designated patterns.

[0058] Note that, as the flow is repeated, the instructions corresponding to the first instruction and the second instruction, and the cycles corresponding to the first cycle and the second cycle may be changed as appropriate. In the above, it has been described that cycle 1 corresponds to the first cycle, cycle 2 corresponds to the second cycle, and cycle 2 corresponds to the first cycle, and cycle 3 corresponds to the second cycle. Similarly, it will be understood by those skilled in the art that there may be cases where cycle 3 corresponds to the first cycle, cycle 4 corresponds to the second cycle, cycle 4 corresponds to the first cycle, and the subsequent cycle corresponds to the second cycle, and instruction B corresponds to the first instruction, and the subsequent instruction corresponds to the second instruction, etc.

[0059] 6 shows an example of the configuration of the pattern generator 240, along with the sequence control unit 22, the memory unit 26, and the first multiplexer 258. While the configuration of the pattern generator 240a is shown as a representative of the multiple pattern generators 240, the other pattern generators 240b-240d may have a similar configuration. The pattern generator 240 may include a first switch unit 241, a second switch unit 242, a first port 243, a second port 244, a first readout unit 246, a second readout unit 248, a third readout unit 250, a flip-flop 249, a second multiplexer 252, and an output unit 254.

[0060] The first switch unit 241 may switch the pattern generation signal input from the sequence control unit 22. The sequence control unit 22 of this example inputs to the pattern generator 240 a pattern generation signal for generating a signal pattern corresponding to each step of a first command and a pattern generation signal for generating a signal pattern corresponding to each step of a second command. The sequence control unit 22 may select which pattern generation signal to input by controlling and switching the first switch unit 241. The sequence control unit 22 may control the first switch unit 241 based on the remaining steps.

[0061] The second switch unit 242 may switch whether to input the pattern generation signal input from the sequence control unit 22 to the second port 244. That is, the second switch unit 242 may switch whether to input the pattern generation signal input from the sequence control unit 22 to both the first port 243 and the second port 244, or to input only to the first port 243. The sequence control unit 22 may select the port to input the pattern generation signal to by controlling and switching the second switch unit 242. The sequence control unit 22 may control the second switch unit 242 based on the remaining steps.

[0062] The first port 243 and the second port 244 access the memory unit 26. The first port 243 and the second port 244 may access the memory unit 26 based on a pattern generation signal input from the sequence control unit 22. For example, when a pattern generation signal for generating a signal pattern corresponding to each step of a first command is input from the sequence control unit 22, the first port 243 and / or the second port 244 accesses an address in the memory unit 26 that stores a signal pattern corresponding to each step of the first command. Furthermore, when a pattern generation signal for generating a signal pattern corresponding to each step of a second command is input from the sequence control unit 22, the first port 243 and / or the second port 244 accesses an address in the memory unit 26 that stores a signal pattern corresponding to each step of the second command.

[0063] When the number of remaining steps of the first instruction is equal to or greater than the designated number of patterns, the first reading unit 246 may read signal patterns corresponding to each step of the first instruction from the memory unit 26 via the first port 243. When the number of remaining steps of the first instruction is less than the designated number of patterns, the first reading unit 246 may read signal patterns corresponding to each step of the second instruction from the memory unit 26 via the first port 243. The first reading unit 246 may input the read signal pattern PatA to the second multiplexer 252. The sequence control unit 22 may control the reading of the signal patterns by the first reading unit 246 by controlling the first switch unit 241.

[0064] When the number of remaining steps of the first instruction is equal to or greater than the specified number of patterns, the sequence control unit 22 controls the first switch unit 241 to connect to a terminal that inputs a pattern generation signal for generating a signal pattern corresponding to each step of the first instruction. As a result, the first port 243 accesses an address in the memory unit 26 that stores the signal pattern corresponding to each step of the first instruction. Then, the first reading unit 246 reads the signal pattern corresponding to each step of the first instruction from the memory unit 26 via the first port 243.

[0065] When the number of remaining steps of the first instruction is less than the specified number of patterns, the sequence control unit 22 controls the first switch unit 241 to connect to a terminal that inputs a pattern generation signal for generating signal patterns corresponding to each step of the second instruction. As a result, the first port 243 accesses an address in the memory unit 26 that stores the signal patterns corresponding to each step of the second instruction. The first reading unit 246 then reads the signal patterns corresponding to each step of the second instruction from the memory unit 26 via the first port 243.

[0066] When the number of remaining steps of the first instruction is equal to or greater than the designated pattern number, the second readout unit 248 may read the same signal pattern as the signal pattern read out by the first readout unit 246 from the memory unit 26 via the second port 244. When the number of remaining steps of the first instruction is less than the designated pattern number, the second readout unit 248 may read out a signal pattern corresponding to the remaining steps of the first instruction from the memory unit 26 via the second port 244. The second readout unit 248 may input the read signal pattern PatB to the second multiplexer 252. The sequence control unit 22 may control the reading of the signal pattern by the second readout unit 248 by controlling the second switch unit 242.

[0067] When the number of remaining steps of the first instruction is equal to or greater than the specified number of patterns, the sequence control unit 22 controls the second switch unit 242 to a connected state. As a result, a pattern generation signal for generating a signal pattern corresponding to each step of the first instruction is input to the second port 244, and the second port 244 accesses an address in the memory unit 26 that stores the signal pattern corresponding to each step of the first instruction. The second reading unit 248 then reads, via the second port 244, the signal pattern corresponding to each step of the first instruction, which is the same signal pattern as the signal pattern read by the first reading unit 246, from the memory unit 26.

[0068] When the number of remaining steps of the first instruction is less than the specified number of patterns, the sequence control unit 22 controls the second switch unit 242 to a disconnected state. As a result, a pattern generation signal for generating a signal pattern corresponding to each step of the second instruction is not input to the second port 244, and the second port 244 remains accessing the address of the memory unit 26 that stores the signal patterns corresponding to each step of the first instruction. The second reading unit 248 then reads the signal patterns corresponding to the remaining steps of the first instruction from the memory unit 26 via the second port 244.

[0069] The third readout unit 250 may read the same signal pattern as the signal pattern read out by the first readout unit 246 in the previous cycle from the memory unit 26 via the first port 243. The third readout unit 250 may read the signal pattern from the memory unit 26 via the first port 243 and the flip-flop 249. That is, the flip-flop 249 delays the signal pattern read out by the first readout unit 246 by one cycle, so that the third readout unit 250 may read out the same signal pattern as the signal pattern read out by the first readout unit 246 in the previous cycle. The third readout unit 250 may input the read signal pattern PrePatA to the second multiplexer 252.

[0070] The above describes the arrangement and control of ports and switch units for realizing the operations of first read unit 246, second read unit 248, and third read unit 250, but the present invention is not limited to this. As an example, the first port 243 may be set to access an address in memory unit 26 that stores a signal pattern corresponding to each step of a first command, and the second port 244 may be set to access an address in memory unit 26 that stores a signal pattern corresponding to each step of a second command, and a switch unit may be provided and controlled between each port and each read unit, thereby controlling the signal pattern read by each read unit.

[0071] The second multiplexer 252 is provided between the first port 243 and the second port 244 and the output unit 254. The second multiplexer 252 may select a signal pattern output by each of the plurality of pattern generators 240. The second multiplexer 252 may select a signal pattern output by each of the plurality of pattern generators 240 from the signal patterns read by the first readout unit 246, the second readout unit 248, and the third readout unit 250. The sequence control unit 22 may control the selection of the signal pattern by the second multiplexer 252 based on the remaining steps. The selection of the signal pattern by the second multiplexer 252 will be described in detail later.

[0072] The output section 254 outputs the signal pattern stored in the memory section 26. The output section 254 may output the signal pattern selected by the second multiplexer 252 to the first multiplexer 258.

[0073] The first multiplexer 258 may combine the signal patterns output by the plurality of pattern generators 240 into one continuous signal pattern and output the combined signal pattern.

[0074] In the above description, the second multiplexer 252 performs a 3-to-1 operation of selecting one signal pattern from three signal patterns PatA, PatB, and PrePatA, and the first multiplexer 258 performs a 4-to-1 operation of combining signal patterns from four pattern generators 240 into one signal pattern, but this is not limiting. As an example, the first multiplexer 258 and the second multiplexers 252 of each pattern generator 240 may be configured as a single multiplexer as a whole, and the multiplexer may perform a 12-to-1 operation of combining 12 signal patterns (PatA, PatB, PrePatA x 4) into one continuous signal pattern and outputting it.

[0075] 7 shows a modified example of generating a protocol pattern PAT. In this example, the remaining number of steps, the signal pattern PatA read by the first reading unit 246, the signal pattern PatB read by the second reading unit 248, and the protocol pattern PAT output by the first multiplexer 258 are shown, along with the cycle synchronized with the clock signal CLK generated by the timing generating unit 28. This example shows the case of generating a protocol pattern PAT corresponding to instructions A, B, C, and D, each of which has nine steps.

[0076] The pattern generating unit 24 generates a cycle 1 including a signal pattern corresponding to steps (A-1) to (A-4) among the multiple steps (A-1) to (A-9) included in the instruction A (S100 in FIG. 5).

[0077] At the start of cycle 1, the remaining steps are all steps of instruction A, which is 9. This corresponds to the case where the number of remaining steps of the first instruction (instruction A in this case) is equal to or greater than the specified pattern number (4 in this case). Therefore, the first readout unit 246 reads out a signal pattern corresponding to steps (A-1)-(A-4) of instruction A from the memory unit 26 (PatA). The second readout unit 248 reads out a signal pattern corresponding to steps (A-1)-(A-4) of instruction A, which is the same signal pattern as the signal pattern read out by the first readout unit 246 (PatB). Since there is no previous cycle in cycle 1, the third readout unit 250 does not read anything (PrePatA). These operations may be the same for each of the multiple pattern generators 240.

[0078] The second multiplexer 252 selects a signal pattern output by each of the plurality of pattern generators 240. The sequence control unit 22 may control the selection of the signal pattern by the second multiplexer 252 of each of the plurality of pattern generators 240 so as to generate a desired protocol pattern PAT. For example, in response to a control signal from the sequence control unit 22, the second multiplexer 252 of the pattern generator 240a selects the signal pattern corresponding to step (A-1) from the signal pattern PatA, the second multiplexer 252 of the pattern generator 240b selects the signal pattern corresponding to step (A-2) from the signal pattern PatA, the second multiplexer 252 of the pattern generator 240c selects the signal pattern corresponding to step (A-3) from the signal pattern PatA, and the second multiplexer 252 of the pattern generator 240d selects the signal pattern corresponding to step (A-4) from the signal pattern PatA.

[0079] In this example, the selected signal pattern is indicated by a bold frame. In this example, all signal patterns are selected from the signal pattern PatA read by the first readout unit 246, but this is not limiting. In other words, since the second readout unit 248 also reads the same signal pattern in cycle 1, the second multiplexer 252 may select from the signal pattern PatB read by the second readout unit 248.

[0080] The first multiplexer 258 combines the signal patterns output by each of the multiple pattern generators 240 into one continuous signal pattern and outputs the combined signal pattern. The first multiplexer 258 may combine the signal patterns output by each of the multiple pattern generators 240 in a predetermined order. In this example, the first multiplexer 258 combines the signal patterns output by the pattern generators 240a, 240b, 240c, and 240d in this order, and outputs the signal patterns corresponding to steps (A-1) to (A-4) as the protocol pattern PAT.

[0081] The sequence control unit 22 determines whether or not there are any remaining steps among the multiple steps included in the instruction A that have not been used to generate the cycle 1 (step S102 in FIG. 5). In this example, the sequence control unit 22 determines that there are remaining steps (A-5) to (A-9).

[0082] The sequence control unit 22 determines whether the number of remaining steps is greater than the number of designated patterns (step S106 in FIG. 5). In this example, it is determined that the number of remaining steps is 5, which is greater than the number of designated patterns (4).

[0083] The sequence control unit 22 controls the pattern generation unit 24 to generate cycle 2 with signal patterns corresponding to the remaining steps (A-5) to (A-8) (step S108 in FIG. 5).

[0084] At the start of generation of cycle 2, the number of remaining steps is 5, which corresponds to the case where the number of remaining steps of the first instruction (instruction A in this case) is equal to or greater than the number of specified patterns (4 in this case). Therefore, the operation of the read unit and multiplexer is the same as in cycle 1, so a repeated explanation will be omitted. In cycle 2, there is the previous cycle, so the third read unit 250 reads from the memory unit 26 the signal patterns (A-1)-(A-4) that are the same as the signal patterns read by the first read unit 246 in cycle 1 (PrePatA).

[0085] The sequence control unit 22 updates the step (A-9) of instruction A that was not used in generating cycle 2 as the remaining step (step S112 in FIG. 5). The sequence control unit 22 determines whether or not the generation of the protocol pattern PAT has been completed (step S114 in FIG. 5). Since the generation of the protocol pattern PAT has not been completed, the process returns to step S102 in FIG. 5 and the operation continues.

[0086] The sequence control unit 22 determines whether there are any remaining steps (step S102 in FIG. 5). Here, the sequence control unit 22 determines that there is a remaining step (A-9).

[0087] The sequence control unit 22 determines whether the number of remaining steps is greater than the number of designated patterns (step S106 in FIG. 5). In this example, it is determined that the number of remaining steps is 1, which is equal to or less than the number of designated patterns, 4.

[0088] The sequence control unit 22 controls the pattern generating unit 24 to generate cycle 3 with a signal pattern corresponding to the remaining step (A-9) and a signal pattern corresponding to at least one step of command B (step S110 in FIG. 5).

[0089] At the start of generation of cycle 3, the number of remaining steps is 1, which corresponds to a case where it is less than the specified number of patterns (here, 4). Therefore, the first reading unit 246 reads from the memory unit 26 the signal pattern corresponding to steps (B-1) to (B-4) of instruction B (PatA). The second reading unit 248 reads from the memory unit 26 the signal pattern (A-9) corresponding to the remaining steps of instruction A (PatB). The third reading unit 250 reads from the memory unit 26 the signal pattern (A-5) to (A-8) that is the same as the signal pattern read by the first reading unit 246 in cycle 2 (PrePatA).

[0090] The second multiplexer 252 of the pattern generator 240a may select a signal pattern corresponding to step (A-9) from the signal pattern PatB, the second multiplexer 252 of the pattern generator 240b may select a signal pattern corresponding to step (B-1) from the signal pattern PatA, the second multiplexer 252 of the pattern generator 240c may select a signal pattern corresponding to step (B-2) from the signal pattern PatA, and the second multiplexer 252 of the pattern generator 240d may select a signal pattern corresponding to step (B-3) from the signal pattern PatA. The first multiplexer 258 may output signal patterns corresponding to steps (A-9), (B-1) to (B-3) as the protocol pattern PAT by combining the signal patterns output by the pattern generator 240a, the pattern generator 240b, the pattern generator 240c, and the pattern generator 240d in this order.

[0091] In this way, the pattern generation unit 24 of this example generates the protocol pattern PAT so that at least one cycle includes a signal pattern corresponding to at least one step of each of a plurality of instructions, by the first reading unit 246 and the second reading unit 248 reading signal patterns corresponding to each step of different instructions by referring to different addresses in the memory unit 26. This makes it possible to efficiently process instructions having a number of steps greater than the number of designated patterns.

[0092] The sequence control unit 22 updates steps (B-4) to (B-9) of instruction B that were not used in generating cycle 3 as remaining steps (step S112 in FIG. 5). The sequence control unit 22 determines whether generation of the protocol pattern PAT is complete (step S114 in FIG. 5). Since generation of the protocol pattern PAT is not complete, the process returns to step S102 in FIG. 5 and the operation continues.

[0093] The sequence control unit 22 determines whether there are any remaining steps (step S102 in FIG. 5). Here, the sequence control unit 22 determines that there are remaining steps (B-4) to (B-9).

[0094] The sequence control unit 22 determines whether the number of remaining steps is greater than the number of designated patterns (step S106 in FIG. 5). In this example, it is determined that the number of remaining steps is 6, which is greater than the number of designated patterns (4).

[0095] The sequence control unit 22 controls the pattern generation unit 24 to generate cycle 4 with signal patterns corresponding to the remaining steps (B-4) to (B-7) (step S108 in FIG. 5).

[0096] At the start of generation of cycle 4, the number of remaining steps is 6, which corresponds to the case where the number of remaining steps of the first instruction (instruction B in this case) is equal to or greater than the specified number of patterns (4 in this case). The first reading unit 246 reads out a signal pattern corresponding to steps (B-5) to (B-8) of instruction B from the memory unit 26 (PatA). The second reading unit 248 reads out a signal pattern corresponding to steps (B-5) to (B-8) of instruction B, which is the same signal pattern as the signal pattern read out by the first reading unit 246 (PatB). The third reading unit 250 reads out a signal pattern (B-1) to (B-4) from the memory unit 26, which is the same signal pattern as the signal pattern read out by the first reading unit 246 in cycle 3 (PrePatA).

[0097] The second multiplexer 252 of the pattern generator 240a selects the signal pattern corresponding to step (B-5) from the signal pattern PatA, the second multiplexer 252 of the pattern generator 240b selects the signal pattern corresponding to step (B-6) from the signal pattern PatA, the second multiplexer 252 of the pattern generator 240c selects the signal pattern corresponding to step (B-7) from the signal pattern PatA, and the second multiplexer 252 of the pattern generator 240d selects the signal pattern corresponding to step (B-4) from the signal pattern PrePatA. The first multiplexer 258 combines the signal patterns output by the pattern generator 240d, the pattern generator 240a, the pattern generator 240b, and the pattern generator 240c in this order, and outputs the signal patterns corresponding to steps (B-4) to (B-7) as the protocol pattern PAT.

[0098] In this way, the pattern generation unit 24 of this example can refer to a signal pattern that was not used in the previous cycle by having the third read unit 250 read from the memory unit 26 the same signal pattern as the signal pattern that the first read unit 246 read in the previous cycle, thereby eliminating a reference mismatch caused by at least one cycle including a signal pattern that corresponds to at least one step of each of multiple instructions. As a result, by the pattern generation unit 24 generating the protocol pattern PAT such that at least one cycle includes a signal pattern that corresponds to at least one step of each of multiple instructions, it is possible to efficiently process instructions that have a number of steps greater than the specified number of patterns.

[0099] Furthermore, in the pattern generation unit 24 of this example, the first multiplexer 258 combines the signal patterns output by each of the multiple pattern generators 240 into a single continuous signal pattern and outputs the combined signal pattern, so even if the order of the patterns output by the multiple pattern generators 240 differs from the order of the steps included in the instructions, the pattern generation unit 24 can generate a protocol pattern PAT in which the signal patterns output by the multiple pattern generators 240 are appropriately rearranged. As a result, by the pattern generation unit 24 generating a protocol pattern PAT such that at least one cycle includes a signal pattern corresponding to at least one step of each of the multiple instructions, it is possible to efficiently process instructions having a number of steps greater than the specified number of patterns.

[0100] The sequence control unit 22 updates steps (B-8) and (B-9) of instruction B, which were not used in generating cycle 4, as remaining steps (step S112 in FIG. 5). The sequence control unit 22 determines whether generation of the protocol pattern PAT has been completed (step S114 in FIG. 5). Since generation of the protocol pattern PAT has not been completed, the process returns to step S102 in FIG. 5 and the operation continues. By repeating the above operations, the pattern generation unit 24 may generate a protocol pattern PAT having nine cycles, each cycle consisting of the predetermined specified number of patterns, four.

[0101] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, where the blocks may represent (1) stages of a process in which operations are performed or (2) sections of apparatus responsible for performing the operations. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer-readable instructions stored on a computer-readable medium, and / or a processor provided with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry, and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry including logical AND, OR, XOR, NAND, NOR, and other logic operations, flip-flops, registers, memory elements such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

[0102] A computer-readable medium may include any tangible device capable of storing instructions that are executed by an appropriate device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture containing instructions that can be executed to create means for performing the operations specified in the flowcharts or block diagrams. Examples of computer-readable media may include electronic, magnetic, optical, electromagnetic, and semiconductor storage media. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), compact disc read-only memories (CD-ROMs), digital versatile discs (DVDs), Blu-ray (RTM) discs, memory sticks, integrated circuit cards, and the like.

[0103] The computer readable instructions may include either assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0104] The computer-readable instructions may be provided to a processor or programmable circuit of a programmable data processing device, such as a computer, locally or via a wide area network (WAN) such as a local area network (LAN) or the Internet, and the computer-readable instructions may be executed to create means for performing the operations specified in the flowcharts or block diagrams. Here, the computer may be a personal computer (PC), a tablet computer, a smartphone, a workstation, a server computer, a general-purpose computer, a special-purpose computer, or the like, or may be a computer system in which multiple computers are connected. Such a computer system in which multiple computers are connected is also called a distributed computing system, and is a broad definition of computer. In a distributed computing system, the multiple computers collectively execute a program by each executing a portion of the program and passing data between the computers as needed during program execution.

[0105] Examples of processors include computer processors, central processing units (CPUs), processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc. A computer may have one processor or multiple processors. In a multiprocessor system with multiple processors, each processor executes a portion of a program and passes data between processors as needed during program execution, allowing the multiple processors to collectively execute the program. For example, in multitasking, each of the multiple processors may execute a portion of each task in small chunks by switching tasks at each time slice. In this case, which portion of a program each processor executes changes dynamically. Which portion of a program each of the multiple processors executes may also be statically determined by multiprocessor-aware programming.

[0106] 8 shows an example of a computer 1000 in which aspects of the present invention may be embodied, in whole or in part. Programs installed on the computer 1000 may cause the computer 1000 to function as or perform operations associated with an apparatus or one or more sections of the apparatus according to embodiments of the present invention, and / or to perform a process or steps of a process according to embodiments of the present invention. Such programs may be executed by the CPU 1012 to cause the computer 1000 to perform specific operations associated with some or all of the blocks of the flowcharts and block diagrams described herein.

[0107] A computer 1000 according to this embodiment includes a CPU 1012, a RAM 1014, a graphics controller 1016, and a display device 1018, which are interconnected by a host controller 1010. The computer 1000 also includes input / output units such as a communication interface 1022, a hard disk drive 1024, a DVD-ROM drive 1026, and an IC card drive, which are connected to the host controller 1010 via an input / output controller 1020. The computer also includes legacy input / output units such as a ROM 1030 and a keyboard 1042, which are connected to the input / output controller 1020 via an input / output chip 1040.

[0108] The CPU 1012 operates according to programs stored in the ROM 1030 and RAM 1014, thereby controlling each unit. The graphics controller 1016 acquires image data generated by the CPU 1012 into a frame buffer or the like provided in the RAM 1014 or into the graphics controller 1016 itself, and causes the image data to be displayed on the display device 1018.

[0109] The communication interface 1022 communicates with other electronic devices via a network. The hard disk drive 1024 stores programs and data used by the CPU 1012 in the computer 1000. The DVD-ROM drive 1026 reads programs or data from a DVD-ROM 1027 and provides the programs or data to the hard disk drive 1024 via the RAM 1014. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0110] The ROM 1030 stores therein a boot program or the like that is executed by the computer 1000 upon activation, and / or programs that depend on the hardware of the computer 1000. The input / output chip 1040 may also connect various input / output units to the input / output controller 1020 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0111] The programs are provided by a computer-readable medium such as a DVD-ROM 1027 or an IC card. The programs are read from the computer-readable medium, installed in the hard disk drive 1024, RAM 1014, or ROM 1030, which are also examples of computer-readable media, and executed by the CPU 1012. Information processing described in these programs is read by the computer 1000, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be configured by implementing information manipulation or processing in accordance with the use of the computer 1000.

[0112] For example, when communication is performed between computer 1000 and an external device, CPU 1012 may execute a communication program loaded into RAM 1014 and instruct communication interface 1022 to perform communication processing based on the processing described in the communication program. Under the control of CPU 1012, communication interface 1022 reads transmission data stored in a transmission buffer processing area provided in RAM 1014, hard disk drive 1024, DVD-ROM 1027, or a recording medium such as an IC card, and transmits the read transmission data to the network, or writes received data received from the network to a reception buffer processing area or the like provided on the recording medium.

[0113] The CPU 1012 may also read all or a necessary portion of a file or database stored on an external recording medium such as a hard disk drive 1024, a DVD-ROM drive 1026 (DVD-ROM 1027), an IC card, etc. into the RAM 1014, and perform various types of processing on the data on the RAM 1014. The CPU 1012 then writes back the processed data to the external recording medium.

[0114] Various types of information, such as various types of programs, data, tables, and databases, may be stored on the recording medium and may undergo information processing. The CPU 1012 may perform various types of processing on data read from the RAM 1014, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequences of the programs, and write the results back to the RAM 1014. The CPU 1012 may also search for information in a file, database, etc. on the recording medium. For example, if multiple entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored on the recording medium, the CPU 1012 may search for an entry that matches a condition specified by the attribute value of the first attribute from among the multiple entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0115] The above-described programs or software modules may be stored in a computer-readable medium on or near the computer 1000. A recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can also be used as a computer-readable medium, thereby providing the programs to the computer 1000 via the network.

[0116] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0117] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0118] 10 Device under test, 20 ALPG, 22 Sequence control section, 24 Pattern generation section, 26 Memory section, 28 Timing generation section, 30 Input section, 40 Acquisition section, 50 Judgment section, 100 Test equipment, 240 Pattern generator, 241 First switch section, 242 Second switch section, 243 First port, 244 Second port, 246 First read section, 248 Second read section, 249 Flip-flop, 250 Third read section, 252 Second multiplexer, 254 Output section, 258 First multiplexer, 1000 Computer, 1010 Host controller, 1012 CPU, 1014 RAM, 1016 Graphics controller, 1018 Display device, 1020 Input / output controller, 1022 Communication interface, 1024 Hard disk drive, 1026 DVD-ROM drive, 1027 DVD-ROM, 1030 ROM, 1040 I / O chip, 1042 keyboard

Claims

1. A testing apparatus comprising: a pattern generation unit that generates a protocol pattern for testing a device under test, the protocol pattern having a plurality of cycles, each cycle consisting of a predetermined number of specified patterns; and a sequence control unit that controls the pattern generation unit in response to a first instruction having a plurality of steps and a second instruction having a plurality of steps, wherein the pattern generation unit generates the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction.

2. The test device according to claim 1, wherein the number of the steps included in the first command is greater than the number of the designated patterns.

3. The test apparatus according to claim 1 or 2, wherein the pattern generation unit generates a first cycle including a signal pattern corresponding to at least one step among the plurality of steps of the first instruction, and the sequence control unit determines whether or not there are any remaining steps among the plurality of steps of the first instruction that have not been used in generating the first cycle, and if there are no remaining steps, controls the pattern generation unit to generate a second cycle, which is the next cycle after the first cycle, with a signal pattern corresponding to at least one step of the second instruction, and if there are remaining steps and the number of the remaining steps is greater than the specified number of patterns, controls the pattern generation unit to generate the second cycle with a signal pattern corresponding to the remaining steps, and if there are remaining steps and the number of the remaining steps is equal to or less than the specified number of patterns, controls the pattern generation unit to generate the second cycle with a signal pattern corresponding to the remaining steps and a signal pattern corresponding to at least one step of the second instruction.

4. The test apparatus according to claim 3, wherein the sequence control section updates the steps of the first instruction and / or the second instruction that were not used in generating the second cycle as the remaining steps.

5. A test apparatus according to any one of claims 1 to 4, wherein the pattern generating section has a plurality of pattern generators, each of which generates a signal pattern corresponding to at least one step of the first instruction or the second instruction.

6. The test device according to claim 5, wherein said pattern generating section has a first multiplexer that combines the signal patterns output by each of said plurality of pattern generators into one continuous signal pattern and outputs the same.

7. A test apparatus as described in claim 5 or 6, comprising a memory section for storing signal patterns corresponding to each step of the first instruction and the second instruction, each of the plurality of pattern generators including: a port for accessing the memory section; an output section for outputting the signal pattern stored in the memory section; and a second multiplexer provided between the port and the output section for selecting the signal pattern output by each of the plurality of pattern generators.

8. The test device according to claim 7, wherein each of the plurality of pattern generators includes a first reading unit that reads a signal pattern corresponding to each step of the first instruction from the memory unit via the port when the number of remaining steps of the first instruction is equal to or greater than the designated number of patterns, and that reads a signal pattern corresponding to each step of the second instruction from the memory unit via the port when the number of remaining steps of the first instruction is less than the designated number of patterns.

9. The test device described in claim 8, wherein each of the plurality of pattern generators includes a second readout unit that reads from the memory unit via the port a signal pattern identical to the signal pattern read out by the first readout unit when the number of remaining steps of the first instruction is equal to or greater than the designated number of patterns, and that reads from the memory unit via the port a signal pattern corresponding to the remaining steps of the first instruction when the number of remaining steps of the first instruction is less than the designated number of patterns.

10. The test apparatus according to claim 9, wherein each of the plurality of pattern generators includes a third readout section that reads from the memory section via the port a signal pattern identical to the signal pattern read out in the previous cycle by the first readout section.

11. The test apparatus according to claim 10, wherein the second multiplexer selects a signal pattern output by each of the plurality of pattern generators from the signal patterns read by the first readout section, the second readout section and the third readout section.

12. The test apparatus according to any one of claims 5 to 11, wherein the number of the designated patterns is equal to the number of the plurality of pattern generators.

13. The test device according to any one of claims 1 to 12, wherein the number of specified patterns is a power of two.

14. A testing method comprising: a step of: a computer generating a protocol pattern for testing a device under test, the protocol pattern having a plurality of cycles, each cycle consisting of a predetermined number of specified patterns; and a step of a computer controlling generation of the protocol pattern in accordance with a first instruction having a plurality of steps and a second instruction having a plurality of steps, wherein the step of generating the protocol pattern includes a step of generating the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction.

15. A program which, when executed by a computer, causes the computer to function as: a pattern generating unit which generates a protocol pattern for testing a device under test having a plurality of cycles, each cycle consisting of a predetermined number of designated patterns; and a sequence control unit which controls the pattern generating unit in response to a first instruction having a plurality of steps and a second instruction having a plurality of steps, wherein the pattern generating unit generates the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step of the first instruction and a signal pattern corresponding to at least one step of the second instruction.

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