µled arrangement and method for producing the same

Abstract

The invention concerns a µLED arrangement comprising a layer stack having a first layer of a first doping type and second layer of a second doping type and an active layer structure in between. A first contact covers a surface of the first layer, said surface facing away from the active layer structure. A semiconductor layer forms a µlens deposited on a surface of the second layer, said surface facing away from the active layer structure. The layer stack comprises first mesa etched sidewalls, extending from the first layer along the active layer structure towards the second layer and second mesa etched sidewalls, said sidewalls forming the µlens.

Description

[0001] pLED ARRANGEMENT AND METHOD FOR PRODUCING THE SAME

[0002] The present application claims priority from German application DE 10 2023 126 794 . 9 dated October 2 , 2023 , the disclosure of which is incorporated herein by reference in its entirety . The present invention concerns an arrangement of a pLED with an integrated plens having an improved performance , as well as a method for processing the pLED with the integrated plens .

[0003] BACKGROUND pLEDs are used for a variety of different applications , including but not limited to proj ector applications . In the case of VR or AR applications , the overall display size is relatively small , only a few cm2if at all , which is a challenge if high resolutions like HD r even larger shall be achieved .

[0004] As a result , pLEDs are used, as those provide a very small size of only a few pm2with sufficient brightness . Still , apart from achieving the brightness over all main colors red, blue and green, a high directionality and small or none optical crossover is required . Depending on the design, the pLEDs are either implemented as an integrated array of devices or separately placed on a surface of a circuit board wafer .

[0005] Usually, for high brightness and reduced optical crosstalk, the optoelectronic devices and pLEDs are usually mesa etched during processing to optically and electrically isolate the individual devices on a wafer . This process is suitable for separate devices as well as for integrated arrays . Mesa etching however causes non-radiative recombination (NRR) of charge carriers at the mesa edges , due to resulting defects ( dangling bonds which act as non-radiative recombination centres ) in the structure of the optoelectronic device along the mesa edges . Current spreading in the layers above and below the active region and also through the active region allows charge carriers to propagate in the direction of the pixel edges , which may then recombine non-radiatively at the defects , lowering the quantum efficiency of the pLED .

[0006] This effect is of lesser relevance for optoelectronic device based on nitride material systems due to the short diffusion length of charge carriers in this material system. However, for materials based on phosphide like in InGaP, InAlP or Indium Gallium Aluminum Phosphite ( InGaAlP ) -based p-LEDs , the diffusion length is significantly larger and may even be larger than the length of those devices . pLEDs based on such material systems are usually used for red color to yellow color emission, although the emission wavelength can be varied with composition .

[0007] In addition to the diffusion length, InGaAlP-based pLEDs ( red emission ) comprise a high refractive index, leading to high internal losses and low light extraction efficiencies .

[0008] It is therefore an obj ect of the present invention to address some of the above-mentioned issues to improve the overall efficiency and directionality of pLED intended to be used for AR and VR applications .

[0009] SUMMARY OF THE INVENTION

[0010] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0011] The inventors propose to combine a plens formation using a semiconductor material with the pixelation process to separate an individual light emitting layer stack . In this way, improved light out coupling and charge carrier confinement for enhanced internal quantum efficiency can be combined in one design . The proposed idea utilizes only two mesa etching steps from two opposite sides , with each step possible to optimize separately from the other one .

[0012] The proposed method is not limited to a specific material system or process technologies . Rather different material systems including phosphides , nitrides and arsenide are likewise possible to use . The design of the pLED can be chosen independently of the plens design and, for example , optimized for high internal quantum efficiency . The plens can provide various functionalities depending on the needs for the application . To this extent , the processing can be optimized and the overall structure post-processed to add further optical functionalities , like for example , but not limited to collimation, shaping of light using optical band gap, even light conversion and mixing .

[0013] The inventors therefore propose in some aspects a pLED arrangement comprising a layer stack having a first layer of a first doping type and a second layer of a second doping type and an active layer structure in between . The active layer structure can comprise a single pn- j unction a quantum well or a multiquantum well structure . Depending on the design, different material compositions for layers of the active layer structure are possible , i . e . using different Al concentration to provide barrier and quantum well layers in a multiquantum well structure .

[0014] Likewise , the first and second doped layers may comprise one or more sublayers facilitating various functionalities like , for example , charge carrier inj ection and charge carrier transport . The material composition may also vary, resulting in slightly different band gaps . Those different band gaps may improve the light emission facility with reduced internal absorption . The various techniques and optimization approaches are known in the art .

[0015] The pLED arrangement according to the proposed principle further comprises a first contact covering a surface of the first layer, said surface facing away from the active layer structure . The contact may also form a connection to a circuit wafer, that provides control and power signals to the pLED . In accordance with the proposed principle , a semiconductor layer forming a plens is deposited on a surface of the second layer , said surface facing away from the active layer structure . The layer stack now comprises first mesa etched sidewalls , extending from the first layer along the active layer structure towards the second layer . The semiconductor layer comprises second mesa etched sidewalls , said sidewalls forming the glens .

[0016] Hence , the arrangement comprises sidewalls extending in different directions . While the sidewalls of the layer stack, either inclined or not extend from a first contact towards the active layer structure , the second sidewalls provided by a second mesa etch form the glens in a semiconductor layer not part of the layer stack for the generation and emission of light . Still , both are monolithically integrated and have been processed from the same wafer . As a result of the proposed principle , no alignment of the glens material and the layer stack is required, reducing not only the complexity, but also enabling a better out coupling and shaping of light with less distortion . The lens shape can be obtained by a lithographic step via lithophoto resist shaping and adj ustment of plasma etching conditions during the second mesa etching process .

[0017] In some aspects , the second mesa etched sidewall each comprise an increasing periphery in a direction towards the active layer structure . The first mesa etch comprises one of an increasing periphery in a direction towards the active layer structure or a substantial equal periphery in a direction towards the active layer structure . Simply speaking , both sidewalls portions , the lower one of the layer stack and the upper of the glens are "opening up" towards the center of the structure .

[0018] In this regard, the two sidewall portions can comprise different sizes . For example , in some aspects according to the proposed principle , a periphery of the second mesa etched sidewalls closest to the active layer structure is larger than a periphery of the first mesa etched sidewalls closes to the active layer structure . Simply speaking, this means that the glens overlaps the active layer structure and extends beyond . This has the benefit that light emitted towards the side by the layer stack can still be collimated or otherwise processed by the glens . As an alternative , a periphery of the second mesa etched sidewalls comprises a maximum value larger than a maximum value of a periphery of the first mesa etched sidewalls . Likewise , the maximum periphery of the semiconductor layer is larger than a periphery of one of the active layer structure and the maximum periphery of the first mesa etched sidewalls .

[0019] In some aspects , the first mesa etched sidewalls extend into a portion of the second layer . It may optionally expose a planar surface portion of the second layer adj acent to the sidewalls . The planar surface can extend laterally to an adj acent device , such that a plurality of devices can be arranged in a pLED array . The planar surface portion is covered by either a regrowth layer or a dielectric material .

[0020] In some further aspects of the proposed principle , the second mesa etched sidewalls extend into a portion of the second layer, optionally through the second layer to a dielectric layer surrounding the layer stack . Consequently, the second mesa etch may cut in some aspects through the second doped layer and even through regrowth layers previously applied onto the layer stack . Such complete separation of the second doped layer may prevent or significantly reduce any optical crosstalk of light into adj acent pLEDs . The structure also comprises a significantly smaller artificial pn-interface between a regrown layer and the second doped layer . This parasitic diode is therefore smaller , and its effect becomes smaller .

[0021] Some further aspects concern the second contact , that is , the contact contacting the second doped layer . In some aspects , a conductive layer material , particular one of a reflective metal and ITO is deposited on a portion of the second mesa etched sidewalls of the plens forming a second contact . Reflective metal is used, for example , if the light is not yet collimated or a narrower beam shape is required . In some aspects , the metal covers a portion of the sidewalls of the second doped layer and a portion of the semiconductor layer forming the plens . Depending on the base material system and the material used for the semiconductor layer, a metal composition or alloy or even a conductive transparent oxide like ITO may be suitable .

[0022] To prevent short circuits or reduce any parasitic effect of an artificially created interface , a dielectric layer is deposited in some aspects on a portion of the second mesa etched sidewalls covering at least a portion of the second doped layer and optionally portions of regrown layers exposed by the second mesa etch .

[0023] Depending on the base material , the layer stack has to be postprocessed after the sidewalls of the layer stack are formed . This is for example , particularly relevant for pLEDs based on phosphides and arsenide due to the large diffusion length of a few pm. in some aspects of the proposed principle , the first mesa etched sidewalls are covered by one or more regrowth layers . The regrowth layers extend onto a surface of the first layer facing away from the active layer structure , onto the sidewalls and optionally onto planar surface portions of the second doped layer adj acent to the sidewalls . They are usually applied after the mesa etching process . The material is doped in some cases and its thickness varies from a few lO Onm to a few lO Onm. One or more of such regrowth layers can be applied, providing carrier inj ection and transportation functionality . In some aspects , the regrowth layer may also inj ect charge carrier from the sidewall into the active layer structure .

[0024] A passivation and dielectric layer may cover in some aspects the sidewalls and optionally the regrowth layer ( if any . ) the passivation layer extends from the sidewalls onto a planar portion of the second doped layer adj acent to the sidewalls . In some aspects , the passivation layer also acts as an etch stop during the second mesa etching process . Hence , the passivation forms a direct interface with another passivation layer used for the plens , the second layer or the semiconductor layer forming the plens .

[0025] In some further aspects of the proposed principle , the semiconductor layer comprises a doped contact layer deposited on the second doped layer and optionally in contact with a metal layer forming a second contact and a substantially undoped layer on the doped contact layer . The undoped layer may be made of a different material composition compared to the contact layer comprises a lower refractive index than the doped contact layer and / or optionally comprising a larger band gap than the doped contact layer . The first contact may comprise a reflective metal in some aspects , extending from the surface of the first layer onto the sidewalls of the layer stack .

[0026] The proposed pLED is suitable to emit light of various colors . Consequently, different material systems are usable for pLED or a pLED array in accordance with the proposed principle . For example , the layer stack may be based in some aspects on a phosphide material system, with the active layer structure comprising InGaAlP with different Al concentration in different sublayers thereof ; and wherein the semiconductor material comprises one of InGAlP and InAlP . Alternatively, a nitride material system can be used, including but not limited to one or more of GaN, AlGaN, InGaN and InGaAlN .

[0027] Another aspect concerns a method for processing a pLED with an integrated plens and / or an array of such devices . In a method for processing a pLED arrangement , a growth substrate with an optional buffer layer is provided . A semiconductor layer is epitaxially depositing on the growth substrate and a layer stack is epitaxially deposited on the semiconductor layer . The layer stack comprises a first layer of a first doping type and a second layer of a second doping type and an active layer structure in between, the second layer facing the semiconductor layer .

[0028] Then a first mesa etching process is conducted to expose sidewalls of the first layer, the active layer structure and optionally a portion of the second layer . The first mesa etching process generates an exposed surface of the second layer substantially parallel to the growth substrate . The exposed sidewalls can optionally annealed or otherwise processed, whereas the respective techniques may depend on the base material used for the layer stack .

[0029] Then a first contact material is deposited over a surface of the first layer and the exposed sidewalls of the layer stack, and optionally also on a planar surface adj acent to the sidewalls . The first contact material is electrically isolated from the sidewalls and the planar surface . Hence , the first contact material electrically connects the first layer directly, but not all other layers . The layer stack is then rebonded and the growth substrate subsequently removed . The rebonding provides access to the semiconductor layer . A second mesa etching process in the semiconductor layer to shape a plens arranged substantially centrally over the layer stack . A second contact is finally deposited on or along a periphery of mesa etched sidewalls of the semiconductor layer .

[0030] In some further aspects , the sidewalls exposed during the first mesa etching process may be annealed or otherwise processed to reduce the density of non-radiative recombination centers . For this purpose , one or more regrowth layers can be deposited on the exposed sidewall , the regrowth layers comprising an undoped or a slightly p-doped material , that comprises a larger band gap than the material of the active layer structure . The regrowth layer generates an electric barrier , repelling charge carriers from the surface of the sidewall . Furthermore or alternatively, a dielectric material is deposited on the one or more regrowth layers , optionally covering the exposed surface of the second layer substantially parallel to the growth substrate .

[0031] The proposed principle requires only two mesa etching steps , whereas the first mesa etchings step is referred to as a shallow mesa etching step . The second mesa etching step is conducted from a different direction and side . This is different to conventional techniques , that utilize two mesa steps from the same side to conduct a shallow and a deep mesa etching process . As a result of the proposed principle , the slope or inclination of the sidewalls of the layer stack in regard to the lateral dimension of the active layer structure is substantially constant . In other words , the inclined etched sidewall generated during the first mesa etching process does not have an edge .

[0032] The second mesa etching process is conducted such as to form inclined sidewalls , whereas a slope of the sidewalls of the semiconductor layer in regard to the lateral dimension of the active layer structure comprises at least two different values . More particular, the slope can be convex, parabolic or any other form. Furthermore , the surface of the semiconductor layer stack can further be processed with periodic recesses to generate a photonic crystal or roughened . The first and / or the second mesa etched sidewall each comprise an increasing periphery in a direction towards the active layer structure .

[0033] In some further aspects , a lateral dimension of the sidewalls generated during the first mesa etch is smaller than a lateral dimension of the sidewalls generated during the second mesa etch .

[0034] Some aspects define the step of conducting a second mesa etching process . For example , the semiconductor layer is etched down to a small portion of the doped semiconductor layer remaining on top of the second layer . In this embodiment , the second mesa etching process will therefore etch only a portion of the semiconductor layer . As an alternative , the semiconductor layer is etched until the second layer is reached . Further, at least a portion of the second layer can also be etched . In some instances , the second layer is therefore etched from both sides .

[0035] In some aspects , the second layer is etched completely through during the second mesa etching process . The second mesa etching may stop at the etchant stop layer . Such layer can, for example , be a passivation layer . In some instances , it is the passivation layer deposited after the first mesa etching process .

[0036] In some instances , a conductive layer material , particular one of a reflective metal and ITO is deposited on a portion of the second mesa etched sidewalls , particularly adj acent to a periphery of the semiconductor layer , forming a second contact ; forming a second contact . In the case of a reflective metal , light emitted in that direction is reflected into the layer stack . This may support collimation of light in connection with the plens .

[0037] Depending on the depth of the second mesa etching process and the design of the layer stack ( i . e . with regrowth layers ) , portions of the regrowth layer are exposed . Hence , it may be advisable to deposit a dielectric layer material on a planar surface exposed by the second mesa etching process that is adj acent to the sidewalls . The dielectric layer may also cover exposed portions of one of the second layer and the one or more regrowth layers .

[0038] Some more aspects concern the semiconductor layer and the material used for forming the plens . Depending on the material system, a high refractive index may pose a challenge . Hence , it is proposed in some aspects to provide several sublayers for the semiconductor layer with different band gaps and / or refractive indices . Generally, the material of the plens should have a band gap larger than the band gap of the active layer structure , to be substantially transparent for the generated light . At the same time , the material may act as a carrier inj ection layer and contacted to the second contact .

[0039] Consequently, in some aspects , the semiconductor layer is deposited on the growth substrate by first depositing a substantially undoped layer on the doped contact layer . Then a doped contact layer is deposited on the substantially undoped layer , wherein said doped layer optionally comprising a higher refractive index than the undoped layer and / or optionally comprises a smaller band gap than the undoped contact layer .

[0040] SHORT DESCRIPTION OF THE DRAWINGS

[0041] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings , in which

[0042] Figure 1 shows a first embodiment of a pLED with an integrated plens in accordance with some aspect of the proposed principle ;

[0043] Figure 2 illustrates a second embodiment of a pLED with an integrated plens in accordance with some aspect of the proposed principle ;

[0044] Figures 3A and 3B show two different embodiments of a pLED with an integrated plens having additional optical functionalities in accordance with some aspect of the proposed principle ; Figures 4A to 4E illustrate several method steps for processing a pLED with an integrated plens in accordance with some aspects of the proposed principle ;

[0045] Figures 5A to 5C show further steps of processing the emission side of a pLED with an integrated plens in accordance with some aspects of the proposed principle ;

[0046] Figures 6A and 6B illustrate other process steps to process the emission side of a pLED with an integrated plens in accordance with some aspects of the proposed principle .

[0047] DETAILED DESCRIPTION

[0048] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

[0049] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0050] Figure 1 illustrates the first embodiment of a pLED with a monolithic integrated plens formed on the main emission surface . For the purpose of simplification, the surface of the plens as well as the main emission surface of the combination of plens and pLED is referred to as the top surface , whereas the surface facing away from the main emission surface is referred to as the bottom surface . Likewise , a surface facing in the direction of the bottom surface is facing downwards .

[0051] The pLED illustrated in Figure 1 comprises a substrate 10 , on which the device is arranged upon . The substrate 10 can either be a temporary carrier to be used for further processing the device , but also any final wafer including circuitry for controlling or supplying the device with the necessary power . In this regard, the temporary substrate 10 can be made of a semiconductor material like SIO2 , or another material , that is different from the base material systems of the respective pLED .

[0052] The present embodiment concerns a pLED based on phosphide including but not limited to InGaAlP, InAlP and InGaP . The actual material composition may vary in the different layers to obtain different electrical properties or example . The phosphide material systems are suitable for an emission of light in the orange to red part of the visible spectrum . In accordance with the proposed principle , the pLED comprises a mesa-etched semiconductor layer stack based on such material system. More particular , pLED comprises a first mesa etched structure from bottom towards the top surface substantially forming the layer stack and a second mesa etch and contact layer from top towards the bottom corresponding to a region generating the plens 19 .

[0053] More particularly, pLED 1 comprises a contact metal 11 layer , which is arranged on the carrier substrate 10 . The contact layer 11 includes a metal acting also a mirror interface towards the plens 19 to reflect light being generated in active layer 17 . A p-doped contact layer 13 , for example of doped InGaAlP ( indium gallium aluminum phosphide ) , or other materials like the doped GaAs ( gallium arsenide ) or of doped GaP ( gallium phosphide ) is arranged on the contact metal layer 11 . The p- doped layer 13 on top of the contact layer 11 acts as a current distribution layer . Then an epitaxially grown p-doped layer 14 is arranged on top of layer 13 , for example , based on the same material system . Then, a thin p-doped barrier layer 15 made for example of InAlP ( indium aluminum phosphide ) is deposited on top . Except for contact layer 13 , layers 14 and 15 also extend on the sidewalls , as explained further down in greater detail . Instead of the material of layer 13 , the sidewalls are covered by a dielectric material 11 .

[0054] Layer 14 is followed by several other p-doped layers (part of layer depicted as 16 ) including an InGaAlP cladding layer, on which a multiquantum well structure 17 is arranged . The multi-quantum well structure 17 comprises a plurality of InGaAlP ( indium gallium aluminum phosphide ) layers in the present embodiment acting as barrier layers and quantum well layers , respectively . The layers of structure 17 are usually undoped ( or only with a small dopant concentration ) and contain alternating different aluminum concentrations . The different aluminum content in the respective layers of multi-quantumwell structure 17 cause a change in the band gap in the barrier and quantum well layers , with the barrier layers comprising a higher band gap caused by a higher content of aluminum. Following the multi-quantum well structure 17 , another cladding layer , not illustrated herein, is deposited on the multi-quantumwell structure and n-doped layer material 18 is deposited thereupon .

[0055] The layer stack of layers 16 , the cladding layers , the layer structure 17 as well as the n-doped layer 18 are usually mesa-etched during processing of the device to achieve separating between different devices . The mesa etch process , also referred to as shallow mesa etch process , generates inclined sidewalls based on the material system. In this case of a phosphide material system, the inclined sidewalls are subsequently annealed and, in this particular case , re- or overgrown by material of the p-doped barrier layer 15 . Likewise , deposition of p-doped layer 14 is done using a regrowth process . The bottom surface of layer 14 on the sidewalls is covered by a passivation and dielectric layer, and only the bottom surface is covered by the p-doped contact layer .

[0056] The mesa etched surfaces of the layer stack are inclined with a certain angle reaching from the bottom towards the n-doped layer 18 and then extend further outward substantially parallel along the main emission surface . Hence , the active layer structure 17 is arranged within the mesa etched sidewalls as illustrated in Figure 1 . The passivation and dielectric layer 12 are arranged on the sidewalls of the p-doped layer 14 and extends on the planar surface adj acent to the inclined sidewalls . It prevents current flow from the metal of p-contact layer 11 into n- doped layer 18 adj acent to the inclined sidewalls or from the side into the layer stack .

[0057] Another n-contact layer 19' ' , for example , made of n-doped InGaAlP material , is arranged upon layer 18 . On layer 19 ' ' the layer 19 ' forming the plens is arranged . Both layers , contact layer 19' ' and lens layer 19 ' are forming the plens 19 and are generated during a second mesa etching process . The plens layer 19' covers the periphery of the active layer structure 17 in the mesa etched layer stack . More particularly, as illustrated by the vertical dashed lines , the periphery of plens layer 19' follows the periphery of the mesa etched sidewalls of the layer stack . As a result , the active layer structure 17 comprises a size , that is equal ( in case of vertical sidewalls ) of is slightly smaller than the respective plens layer 19' being arranged on n-contact layer 19 ' ' and layer 18 . The periphery of plens layer 19 ' is now surrounded by a contact metal 20 arranged on the surface of contact layer 19 ' ' . Contact metal 20 is used to contact the n-side of the layer stack .

[0058] As presented herein, two mesa etching process steps are required to form the respective combination of the plens and the layer stack of pLED 1 . As a result , the inclined sidewalls of the layer stack comprise substantially a single angle from bottom towards top , wherein in conventional solutions using more mesa etched process steps various angles can occur . Moreover, the first mesa etch as illustrated herein will leave the small portion of the n-doped layer 18 on the outer periphery intact and does therefore not completely etch through the layer stack .

[0059] The additional material being the remaining portions of layer 18 and the n-contact layer 19 ' around the periphery of the pLED may cause an optical crosstalk in monolithically integrated pLEDs arrays , in which several pLEDs are arranged adj acent to each other . This will slightly reduce the overall efficiency . Partially, the situation can be eased by etching through both layers at a larger distance from the peripherys . However, such an approach requires more space between two adj acent pLEDs . On the other hand, the remaining material is substantially defect free and therefore does not have a significant amount of non- radiative recombination centers . Hence , the internal quantum efficiency is increased in this solution .

[0060] An alternative solution, in which the optical crosstalk is further reduced at the expense of potential additional non-radiative recombination centers , is given in Figure 2 . The structure and design of layer stack layers 16 , 17 and 18 is similar to the previous embodiment . Likewise , the layer stack is etched with a shallow mesa etch and subsequently overgrown with the barrier layer 15 , the epitaxially doped layer 14 as well as the contact and passivation layer 13 and 12 , respectively . To this extent , the structure is similar to the one illustrated in the embodiment of Figure 1 .

[0061] However, a second mesa etch is performed forming a plens using the contact material 19' and 19 ' ' in subsequent process steps , which are explained in greater detail below . The mesa etch does not stop on the n-doped contact layer material 19 ' but continues until the passivation layer 12 on the periphery deposited in the previous process step after the regrowth and passivation process is reached . As a result , an outer periphery portion of the n-doped material layer 18 is etched completely through . Likewise , the peripheral planar portions of the barrier layer 15 and the epitaxial layer 14 adj acent to the inclined sidewalls are also etched and completely removed until the passivation layer 12 is reached . Still , the active layer 17 is overgrown by the p-doped epitaxial layer . The overall pn- unction between the p-doped barrier layer 15 , and the material layer 18 is reduced due to the second etching process .

[0062] A dielectric layer 21 is applied on the surface of the exposed portions of layers 18 , 15 and 14 after annealing the exposed sidewalls to cover the exposed n-doped regions of layer 18 as well as the potentially p- doped regions of the barrier layer material 15 and the p-doped layer 14 . A metal contact layer 20 is arranged on top of the passivation layer 21 .

[0063] As illustrated in Figure 2 , the design and a periphery of plens can be adj usted such that only the contact material of layer 19' and 19 ' ' form a plens but also a portion of the n-doped layer 18 . To either prevent or at least reduce light emitting along the sidewalls of the pLED, the contact layer 20 is of a reflective metal or alternatively of ITO, if a desired collimation or emission characteristic is already achieved . Likewise , if the light emitted from the active layer towards the plens is different , for example , by a specific design of the contact metal layer 11 , the application of the metal contact can be replaced by ITO or vice versa .

[0064] The benefit of pLED in comparison to Figure 1 is the reduced carrier leakage through the p-doped regrown layers at the periphery and the avoidance or reduction of the artificial pn-j unction along the periphery by the additional deep mesa etch process from the top side . Using a metal as a contact layer may also suppress any optical crosstalk in any adj acent pLEDs . Similar to the previous embodiment , the active region that is layer structure 17 is located within the area of the plens . Further , the periphery of the active layer structure 17 comprises a smaller area size than the corresponding bottom size of the plens . This may improve the overall light extraction efficiency . Finally, the plens geometry size is adj usted such that it corresponds substantially to the pixel mesa structure , which provides a reduced far field distortion .

[0065] Continuing to Figure 3A and 3B, the plens etched or more generally layers 19 ' ' and 19 ' can provide additional optical functionalities . Starting from Figure 3A, which shows a similar structure as the embodiment , one may apply a structured mask layer and subsequently etch portions of the contact layer of the plens 19 ' ' . The resulting structure with periodic recesses causes an adj ustment of a photonic band gap , which results in a far field narrowing and shaping of the emitted light . By changing the geometry or applying a slightly different material in the respective recesses , one may adj ust the effective refractive index to improve the light extraction from a high index material to smaller or low index material . In addition, one can also fill the recesses with quantum dots or a converter material to provide a mixing of light generating mixed color light .

[0066] Figures 3A and 3B illustrate two possible embodiments for such additional processing of the plens after the deep mesa etch is conducted . While in Figures 2 and 3A, the mesa etching process itself causes , by setting appropriate parameters , an adj ustable curved surface having certain optical properties , the structure of Figure 3A is caused by a dedicated structured etching process after conducting a second mesa etching from the top towards the bottom . In Figure 3A, a photonic crystal supports the shaping of the emitted light . In Figure 3B, the structuring generates a plurality of periodically arranged pyramids and / or cones like , which provides an improved light extraction . Other shapes and arrangements are possible to add any required functionality .

[0067] Figures 4A to 4E illustrate some process steps of a method of producing a pLED or more generally a plurality of pLEDs in accordance with the proposed principle . While only the processing of a single pLED is illustrated herein, one may utilize this method to produce a plurality of monolithically integrated pLEDs on a respective wafer . Those can then be further processed by wafer-wafer bonding to apply the necessary power and control circuitry directly to an array of pLEDs .

[0068] It should also be noted that various method steps can be adj usted or slightly amended depending on the base material system chosen and several design choices . This particularly relates to the postprocessing after the first shallow etching process exposing the sidewall of the active layer structure , strongly affecting the overall quantum efficiency . For example , in phosphide or arsenide material systems one may specifically use overgrow techniques to reduce the non- radiative recombination centers . Such techniques are not required or can be implemented in a simpler way in nitride base material systems , because of the shorter diffusion length of charge carriers in such system . Figures 4A to 4E show several method steps of processing a pLED in accordance with the proposed principle . The method for processing utilizes similar steps as in conventional manufacturing techniques , starting with a growth substrate 50 on the wafer level , which comprises one or more of buffer layers 51 . The growth substrate as well as of the buffer layers 51 are selected depending on the base material system in subsequent processes steps . The buffer layer 51 is usually used to even and flattens the surface as well as cover any possible crystal defects from the growth substrate 50 to provide a smooth and defect free surface .

[0069] On top of the buffer layer' s surface , a plurality of differently doped layers are epitaxially deposited . The deposition process can be conducted by various means including for example , chemical vapor deposition CVD, derivatives thereof like MOCVD, PECVD, physical gas phase deposition, PVD and others . Various parameter settings like the dopant concentration or the base material system adj ustments can be used to provide the respective layer stack . Apart from phosphide material systems , which are used for the present embodiment , material systems like phosphide or nitride systems are suitable for the process in accordance with the proposed principle . Such material systems include for example gallium arsenide , GaAs or AlGaAs , GaP , AlGaP , InGaAlP, GaN, AlGaN, and InAlGaN, etc .

[0070] In the present embodiment , first and doped layer 19 is epitaxially deposited on the top surface of buffer layer 51 . The layer 19 also acts as a subsequent structure for the plens and may comprise a thickness of several pm . For this purpose , it may comprise various dopant concentration settings as well as slight changes in the material composition to adj ust the reflective index in order to improve the out coupling of light into the air interface . To this extent , layer 19 may comprise one or more sublayer, like 19' being undoped and 19 ' ' being n-doped with a different material composition for refractive index matching .

[0071] On top of layer 19 later forming the n-contact layer , an n-doped layer 18 is epitaxially deposited . The n-doped layer 18 may comprise a slightly different material composition compared to layer 19 and its sublayer and is used to current distribution as well as current inj ection of the charge carriers from layer 19 into the active layer structure 17 . Layer 18 may also comprise one or more barrier layers , for example , made of indium aluminum phosphide , InAlP or aluminum phosphide , A1P .

[0072] A first thin cladding layer 17 ' deposited on top of layer 18 , said cladding layer being an undoped indium gallium aluminum phosphide layer . The cladding layer 17 ' is used to prevent dopant diffusion from layers 19 or 18 into the active region of layer structure 17 . Layer structure 17 comprises a multi-quantum well structure in the present embodiment with a plurality of barrier layers and quantum well layers , respectively . The active layer structure 17 is made of a indium gallium aluminum phosphide composition, wherein the different layers that is the barrier layers and quantum well layers differentiate by different aluminum contents . More particularly, a higher aluminum content is usually used for the barrier layers because of the slightly increased bandwidth . The number of barrier layers and quantum well layers may vary and reach between 4 and 20 , but can include larger or smaller numbers as well . A second cladding layer 17 ' ' is provided on top of the multi-quantum well structure 17 and on top of said cladding layer , a p-doped layer structure 16 is arranged .

[0073] The layer stack illustrated in Figure 4A corresponds to conventional layer stacks and is subsequently mesa etched to provide a mesa etched layer stack . For this purpose , a hard mask 30 is applied on top surface of the p-doped layer 16 , which is subsequently structured to expose portions of the top surface in areas 31 . The hard mask material is resilient against the subsequent etching process , which is illustrated in figure 4B . The etching process removes various layers down to a small portion of the n-doped layer 18 as illustrated in Figure 4B . The etching process exposes sidewalls 32 of the p-doped layer 16 , both cladding layers 17 ' and 17 ' ' as well as the multi-quantum well structure 17 . The exposed planar surface of layer 18 is slightly recessed with respect to the first cladding layer 17 ' , hence a small portion of layer 18 is etched by this process . In this particular example , however, it is also possible to perform the etching process generating the recesses 31 only to about the level of cladding layer 17 ' .

[0074] Based on the respective material system, further steps have now to be performed to reduce the number of non-radiative recombination centers and clean the exposed sidewalls , for example of the cladding layers 17 ' , 17 ' ' and the multi-quantum well structure 17 . Particularly for phosphide material systems , various techniques have been developed including, for example , quantum well intermixing along the sidewalls prior to the etching process . Shown herein is a different technique , namely processing the stack with regrowth of several layers covering the sidewalls with a semiconductor material . Figure 4C illustrates this process , in which a slightly p-doped thin layer 15 is re-grown along the top surface of layer 16 as well as on the exposed sidewalls . Depending on the design technique , the thin layer 15 can comprise several sublayers . The layer 15 acts as a p-doped barrier layer comprising for example indium aluminum phosphide , InAlP , which provides a larger band gap than the active layer structure 17 . This will generate a band gap potential , preventing the charge carriers from reaching the non-radiative recombination centers along the sidewalls . Layer 15 extends over the surface of layer 16 , the sidewalls as well as a portion of the top surface of n-doped layer 18 . However, due to the small thickness , the resistance of layer 15 is relatively large , thereby providing only a small leakage current through the artificially created pn-j unction on the interface between layer 18 and layer 15 .

[0075] In subsequent steps , several more of the p-doped layers are deposited and re-grown on the respective top surface as well as on the sidewalls .

[0076] Figure 4D illustrates the results of the deposition processes , including an additional p-doped epitaxial layer 14 , deposited on the barrier layer 15 . In a subsequent step, a p-contact layer 13 (made of p-doped InGaAlP , p-doped GaAs , ITO or p-doped GaP ) is also deposited on the top surface as well as along the sidewalls . Then, a photo resist layer is applied, not shown herein, subsequently structured . The subsequent etching process removes material of the contact layer 13 on the sidewalls as well as on the planar portions above n-doped layer 18 . The material of layer 13 only covers the top of layer 14 . Finally, a dielectric insulating layer 12 is deposited on the top surface of layer 13 as well as on the side surfaces and the surrounding mesa etched portions . Dielectric layer 12 may comprise Si02 , A12O3 or any other dielectric material suited for the design of the pLED . It completely embeds the mesa etched layer stack and the re-grown layers . Then, another photoresist layer ( not shown herein ) is deposited and subsequently structured to cover the dielectric passivation layer 12 on the sidewalls and the mesa etched portions of layer 18 adj acent to the sidewalls . Hence , the top surface of the passivation layer 12 is exposed and subsequently removed to expose the surface of p-contact layer 13 beneath . A contact material 11 is then deposited on the top surface of layer 13 as well as on the side walls of the layer stack . Contact material 11 , for example a metal or a metal composition, provides a carrier inj ection into layer 13 and subsequently into the active structure 17 . In the passivation and dielectric layer 12 along the sidewalls and the mesa etched portions of layer 18 adj acent to the sidewalls , any current flow through the artificial pn-interface on the mesa etched portions is effectively suppressed .

[0077] The metal material of layer 12 may comprise reflective properties , for example , gold can be used in the case of phosphide material systems . The reflective properties enhance the efficiency in operation of the device .

[0078] The resulting structure shown in Figure 4E is substantially finished and can now be processed further by rebonding the pLED, or the array of pLEDs to a temporary or permanent substrate . For this purpose , any shallow Mesa etched recess can be filled up with some further dielectric material and the structure completely re-bonded to a temporary substrate using wafer to wafer bonding techniques , for example . Figure 5A illustrates the results of such rebonding process . For simplicity purposes , a dielectric material of a temporary substrate 10 fills opposite spaces in the shallow Mesa etched portions and the bottom surface 11 to provide an even surface . The dielectric material can comprise recesses , which are filled with conductive material forming contact areas thereon . A wafer to wafer bonding process is used ( not shown herein ) to connect the pLED array to a circuit wafer .

[0079] The rebonding process provides access to the growth substrate 50 as well as the buffer layer 51 . Growth substrate 50 and buffer layer 51 are subsequently removed to gain access to the top surface of layer 19 . Layer 19 comprises the material subsequently used to process the plens thereof . A number hard mas k layer 40 is deposited thereupon in a first step and subsequently structured as illustrated . The hard mas k layer 40 in the present embodiment basically covers a portion of the top surface of layer 19 directly above the active layer structure 17 . Depending on the design techniques and the subsequent etching process steps , the periphery of hard mask layer 40 can comprise a slightly larger diameter and size compared to the periphery of the active layer structure 17 . The hard mask layer may also comprise a certain shape or form, which supports etching along a certain angle . In the present example , the periphery of hard mas k layer 40 is slightly smaller than the edges of the mesa etched layer stack, but approximately the same size as the periphery of the multi-quantum well layer 17 .

[0080] Figure 5B illustrates the next processing step , in which a deep mesa etch is performed . Similar to the shallow mesa etch step , various techniques including dry etching process or wet etching processes are suitable . Depending on the material for layers 19 and 18 used as well as depending on the desired shape of the plens , different etching parameters as explained further below are used .

[0081] The deep mesa etch exposes sidewalls of the layer 19 forming the plens later on, and also access slightly into the top portion of layer 18 around the periphery . As a result , the resulting structure is slightly larger than the periphery of the active layer . The form and shape of the sidewalls as well as its curvature can be adj usted to the needs . For example , during the etching process , the etching parameters are varied like etchant concentration or temperature to change the curvature and the etching rate . Moreover, different etchants for example , suitable to selectively etch along certain crystal direction are suitable to form the desired shape . Furthermore , the etching process can be stopped and the mask layer 40 adj usted in shape or form and size to provide different etching profiles .

[0082] Although illustrated herein for simplicity purposes , the sidewalls of the mesa etch are usually not straight as indicated, but curved, resembling the shape of the desire plens and optical function . Still , a curvature is not always required, as long as the desired optical function of the plens is achievable .

[0083] Figure 5C illustrates the next step . After removal of the hard mas k layer, a photoresist layer 41 is applied and subsequently structured to expose again the sidewalls of layer 19 as well as the now exposed portions of layer 18 adj acent to the sidewalls of layer 19 . A conductive material 20 is applied to the sidewalls and to the upper portion of layer 18 , providing the contact for inj ecting the charge carriers . In some instances , instead of an additional photoresist layer 41 as illustrated in Figure 5C, the hard mas k 40 can be reused and the respective conductive material 20 applied thereupon . Depending on the deposition, the sidewalls are either fully covered as illustrated or only to a certain height , leaving some portion of the sidewall of layer 19 uncovered . The conductive material 20 deposited thereupon is either ITO or any other conductive material that can also comprise a reflective metal . This will result in a reflection of light being emitted towards the sidewalls back into the main pLED . Such light is subsequently again reflected from the contact metal layer 11 until it emits through the top surface . Consequently, the curvature of plens made of layer 19 as well as the material upon the sidewalls allow adj usting the optical functionality over a variety of different ranges and parameters .

[0084] Figures 6A and 6B illustrate an embodiment with the plens having a different shape generated by varying the deep mesa etching process . The hard mas k layer 40 applied on the top surface of layer 19 ' ' in this embodiment is slightly smaller than the periphery of the active layer structure 17 . As a result and adj ustable by the varying the parameters during the Mesa etching process , the sidewalls and surface of the material 19' ' and n-contact layer 19 ' comprise a round shape , following a conventional form of a plens . Additionally, the etching process stops at regrowth layer 15 , that is , it completely removes the portion of layers 19' ' , 19 ' and 18 around the periphery of the layer stack . In this regard, the material of layer 15 can be selected to act as the usual etch stop for the Mesa etching process . Furthermore , as indicated herein, the lens is slightly larger than the respective layer stack, with the bottom of the lens extending over the outer periphery of the layer stack itself . Hence , the plens in this particular embodiment is larger than the size of active layer structure 17 and the layer stack .

[0085] As a further alternative and not illustrated in Figure 6A, the deep mesa etch can continue until the passivation layer 12 is reached . Such a solution would produce a pLED as depicted in Figure 2 .

[0086] To prevent a short circuit to the p-doped regrowth layer 15 , a dielectric material 21 is applied on the exposed surface of layer 15 prior to depositing a conductive material 20 . Similar to the previous embodiment , the conductive element 20 can include a transparent conductive oxide ( ITO for example ) or a reflective layer of metal . The main emission surface is formed by the upper surface of the plens material 19' ' . Moreover, the additional n-contact layer 19 ' between the n-doped material 18 and lens material 19' ' as illustrated in Figure 6A comprises a lower band gap with a higher doping concentration than the undoped lens material 19' ' above . This provides a refractive index matching to the plens material 19' ' , which offers an improved functionality .

[0087] The proposed principle generated a pLED with a mesa etched layer stack as well as an integrated plens which are manufactured using two mesa etching steps from two different directions and sides , that is from the bottom as well as from the top . In contrast to conventional techniques , the combination of the plens formation after the mesa etching process for the semiconductor layer stack enables a process for separating individual emitters , which provides an improved light out coupling and charge carrier confinement for enhanced internal quantum efficiency . Those effects can be combined in a single design . In addition, the alignment of the plens is significantly simplified, as the lens and layer stack are not processed as separate devices but from the same semiconductor material . The various aspects illustrated herein can be combined in different ways and are not dependent or unique to a specific material system . As stated before , combined formation of the plens with the layer stack with a monolithic epitaxial layer structure provides a combination of high internal quantum efficiency and reduced optical crosstalk . pLEDs with the given structure are suitable for proj ect applications , like AR and VR, as they allow a high efficiency and a higher directionality of the out coupled light .

[0088] LIST OF REFERENCES

[0089] I LED

[0090] 10 substrate, temporary substrate

[0091] II contact metal layer

[0092] 12 passivation layer

[0093] 13 contact layer

[0094] 14 p-doped layer

[0095] 15 p-doped barrier layer

[0096] 16 p-doped layer

[0097] 17' , 17' ' cladding layer

[0098] 17 active layer structure

[0099] 18 n doped layer

[0100] 19' n-contact layer

[0101] 19' ' plens layer

[0102] 19 plens

[0103] 19a, 19b periodic structure

[0104] 20 contact metal

[0105] 21 dielectric layer

[0106] 30 hard mask

[0107] 40 hard mask

[0108] 41 photo resist layer

Claims

CLAIMS1 . pLED arrangement comprising :A layer stack having a first layer of a first doping type and a second layer of a second doping type and an active layer structure in between;A first contact covering a surface of the first layer, said surface facing away from the active layer structure ;A semiconductor layer forming a plens deposited on a surface of the second layer , said surface facing away from the active layer structure ;Wherein the layer stack comprises first mesa etched sidewalls , extending from the first layer along the active layer structure towards the second layer;Wherein the semiconductor layer comprises second mesa etched sidewalls , said sidewalls forming the plens .2 . The arrangement according to claim 1 , wherein the second mesa etched sidewall each comprise an increasing periphery in a direction towards the active layer structure and the first mesa etch comprises one of an increasing periphery in a direction towards the active layer structure or a substantial equal periphery in a direction towards the active layer structure .3 . The arrangement according to any of the preceding claims , wherein the first mesa etched sidewalls extend into a portion of the second layer , optionally exposing a planar surface portion of the second layer adj acent to the sidewalls .4 . The arrangement according to any of the preceding claims , wherein the second mesa etched sidewalls extend into a portion of the second layer , optionally through the second layer to a dielectric layer surrounding the layer stack .5 . The arrangement according to any of the preceding claims , whereina periphery of the second mesa etched sidewalls closest to the active layer structure is larger than a periphery of the first mesa etched sidewalls closes to the active layer structure ; or a periphery of the second mesa etched sidewalls comprises a maximum value larger than a maximum value of a periphery of the first mesa etched sidewalls ; or wherein the maximum periphery of the semiconductor layer is larger than a periphery of one of the active layer structure and the maximum periphery of the first mesa etched sidewalls .6 . The arrangement according to any of the preceding claims , wherein a conductive layer material , particular one of a reflective metal and ITO is deposited on a portion of the second mesa etched sidewalls of the plens forming a second contact ; and / or a dielectric layer is deposited on a portion of the second mesa etched sidewalls covering at least a portion of the second doped layer and optionally portions of regrown layers exposed by the second mesa etch .7 . The arrangement according to any of the preceding claims , wherein the first mesa etched sidewalls are covered by one or more regrown layer , which extend onto a surface of the first layer facing away from the active layer structure , onto the sidewalls and optionally onto planar surface portions of the second doped layer adj acent to the sidewalls .8 . The arrangement according to any of the preceding claims , wherein sidewalls are covered by a passivation layer extending from the sidewalls onto a planar portion of the second doped layer adj acent to the sidewalls .9 . The arrangement according to any of the preceding claims , wherein the semiconductor layer comprises :A doped contact layer deposited on the second layer having a second oping type and optionally in contact with a metal layer forming a second contact ;A substantially undoped layer on the doped contact layer , said undoped layer optionally comprising a lower refractive index than the doped contact layer and / or optionally comprising a larger bandgap than the doped contact layer .10 . The arrangement according to any of the preceding claims , wherein the first contact comprises a reflective metal extending from the surface of the first layer onto the sidewalls of the layer stack .11 . The arrangement according to any of the preceding claims , wherein the layer stack is based on a phosphide material system, with the active layer structure comprising InGaAlP with different Al concentration in different sublayers thereof ; and wherein the semiconductor material comprises one of InGAlP and InAlP .12 . The arrangement according to any of the preceding claims , wherein the semiconductor layer comprises on its shaped surface an optically active structure , in particularly one of :An antiref lective coating ;A roughened surface ; andA periodic structure generating an optical bandgap .13 . A method for processing a pLED arrangement comprising the steps of : Providing a growth substrate with an optional buffer layer Epitaxially depositing a semiconductor layer on the growth substrate ;Epitaxially depositing a layer stack on the semiconductor layer , the layer stack having a first layer of a first doping type and second layer of a second doping type and an active layer structure in between, the second layer facing the semiconductor layer;Conducting a first mesa etching process to expose sidewalls of the first layer, the active layer structure and optionally a portion of the second layer, wherein the first mesa etching process generates an exposed surface of the second layer substantially parallel to the growth substrate ;Optionally annealing the exposed sidewalls ;Depositing a first contact material over a surface of the first layer and the exposed sidewalls of the layer stack, the first contact material being electrically isolated from the exposed sidewalls ;Rebonding the layer stack and subsequently removing the growth substrate ;Conducting a second mesa etching process in the semiconductor layer to shape a plens arranged substantially centrally over the layer stack;Depositing a second contact on or along a periphery of mesa etched sidewalls of the semiconductor layer .14 . The method according to claim 13 , wherein optionally annealing the exposed sidewalls comprises the steps of :Depositing one or more regrowth layer on the exposed sidewall , the regrowth layers comprising an undoped or p-doped material , tat comprises a larger bandgap then material of the active layer structure ;Depositing a dielectric material on the one or more regrowth layers , optionally covering the exposed surface of the second layer substantially parallel to the growth substrate .15 . The method according to any of claims 13 to 14 , wherein the first and / or the second mesa etching process are conducted such as to form inclined sidewalls , whereas a slope of the sidewalls of the layer stack in regard to the lateral dimension of the active layer structure is substantially constant , while a slope of the sidewalls of the semiconductor layer in regard to the lateral dimension of the active layer structure comprises at least two different values .16 . The method according to any of claims 13 to 15 , wherein the first and / or the second mesa etched sidewall each comprise an increasing periphery in a direction towards the active layer structure .17 . The method according to any of claims 13 to 16 , wherein a lateral dimension of the sidewalls generated during the first mesa etch issmaller than a lateral dimension of the sidewalls generated during the second mesa etch .18 . The method according to any of claims 13 to 17 , wherein conducting a second mesa etching process comprises at least one of :Etching the semiconductor layer to a small portion of a doped semiconductor layer remains on top of the second layer;Etching the semiconductor layer till the second layer is reached; Optionally etching at least a portion of the second layer Optionally etching through the second layer till a passivation layer or an etch stop layer .19 . The method according to any of claims 13 to 18 , wherein conducting a second mesa etching process comprises :Depositing a conductive layer material , particular one of a reflective metal and ITO on a portion of the second mesa etched sidewalls , particularly adj acent to a periphery of the semiconductor layer forming a second contact ; forming a second contact .20 . The method according to any of claims 13 to 19 , wherein conducting a second mesa etching process comprises :Depositing a dielectric layer material on a planar surface exposed by the second mesa etching process that is adj acent to the sidewalls of the semiconductor layer; said dielectric layer optionally covering exposed portions of one of the second layer and the one or more regrowth layers .21 . The method according to any of claims 13 to 20 , wherein the step of epitaxially depositing a semiconductor layer on the growth substrate comprises :Depositing a substantially undoped layer on the doped contact layer ;Depositing a doped contact layer on the substantially undoped layer , wherein said doped layer optionally comprising a higher refractive index than the undoped layer and / or optionally comprises a smaller bandgap than the undoped contact layer .22 . The method according to any of claims 13 to 21 , wherein the layer stack is based on a phosphide material system, with the active layer structure comprising InGaAlP with different Al concentration in different sublayers thereof ; and wherein the semiconductor material comprises one of InGAlP and InAlP .

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