Semiconductor module

Abstract

This semiconductor module includes a substrate, an encapsulating resin, a filling part, and a metal layer. The substrate has a front surface and a back surface. The back surface is located on the reverse side from the front surface. The encapsulating resin is provided on the front surface. The metal layer covers the filling part in a plan view of the front surface. The substrate has a recess extending from the front surface to the back surface. The filling part is connected to the recess.

Description

Semiconductor Module

[0001] The present disclosure relates to a semiconductor module.

[0002] Japanese Patent Laid-Open Publication No. 2023-76696 (Patent Document 1) discloses a semiconductor module in which a light emitting element is mounted on a substrate having a through hole formed therein.

[0003] JP 2023-76696 A

[0004] [Summary] However, when forming the sealing resin that seals the light-emitting element, there is a risk that part of the sealing resin may enter the through-hole. If part of the sealing resin adheres to the inner surface of the through-hole, it becomes difficult to form a tin plating.

[0005] A semiconductor module according to one aspect of the present disclosure includes a substrate, a sealing resin, a filling portion, and a metal layer. The substrate has a front surface and a back surface. The back surface is located opposite the front surface. The sealing resin is disposed on the front surface. The metal layer covers the filling portion in a plan view of the front surface. The substrate has a recess formed therein that extends from the front surface to the back surface. The filling portion is connected to the recess.

[0006] FIG. 1 is a schematic plan view of a semiconductor module according to a first embodiment. FIG. 2 is a schematic side view of the semiconductor module according to the first embodiment. FIG. 3 is a schematic bottom view of the semiconductor module according to the first embodiment. FIG. 4 is a flowchart of a method for manufacturing a semiconductor module according to the first embodiment. FIG. 5 is a schematic plan view showing a step in the method for manufacturing a semiconductor module according to the first embodiment. FIG. 6 is a schematic plan view showing a step subsequent to the step shown in FIG. 5 in the method for manufacturing a semiconductor module according to the first embodiment. FIG. 7 is a schematic plan view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing a semiconductor module according to the first embodiment. FIG. 8 is a schematic plan view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing a semiconductor module according to the first embodiment. FIG. 9 is a schematic plan view of a semiconductor module according to a second embodiment. FIG. 10 is a schematic side view of a semiconductor module according to the second embodiment. FIG. 11 is a schematic bottom view of a semiconductor module according to the second embodiment. FIG. 12 is a schematic perspective view showing a state in which the semiconductor module according to the second embodiment is mounted on a mounting substrate. FIG. 13 is a schematic side view of a semiconductor module according to a third embodiment. FIG. 14 is a flowchart of a method for manufacturing a semiconductor module according to the third embodiment. Fig. 15 is a schematic plan view showing one step in the method for manufacturing a semiconductor module according to embodiment 3. Fig. 16 is a schematic plan view showing a step subsequent to the step shown in Fig. 15 in the method for manufacturing a semiconductor module according to embodiment 3. Fig. 17 is a schematic plan view showing a step subsequent to the step shown in Fig. 16 in the method for manufacturing a semiconductor module according to embodiment 3. Fig. 18 is a schematic side view of a semiconductor module according to embodiment 4.

[0007] [Detailed Description] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be combined in any manner.

[0008] First Embodiment <Configuration of Semiconductor Module> Fig. 1 is a schematic plan view of a semiconductor module 100a according to a first embodiment. Fig. 2 is a schematic side view of the semiconductor module 100a according to the first embodiment. Fig. 3 is a schematic bottom view of the semiconductor module 100a according to the first embodiment.

[0009] 1 to 3 is, for example, a semiconductor module 100a on which a light-emitting element 2 is mounted, and mainly includes a substrate 1, two light-emitting elements 20a and 20b, wires 3, a sealing resin 4, a conductive layer 5, a metal layer 6, a resist 7, and a filling portion 8. In FIGS. 1 and 2, a straight dotted line L1 indicates the outline of the sealing resin 4.

[0010] The substrate 1 has a front surface 10s1, a back surface 10s2, and a side surface 10s3. The front surface 10s1 is the surface on which the light-emitting element 2 and the sealing resin 4 are arranged. The back surface 10s2 is the surface located opposite the front surface 10s1. The side surface 10s3 is a surface connecting the front surface 10s1 and the back surface 10s2. The side surface 10s3 includes a first side surface 11s3 and a second side surface 12s3. The first side surface 11s3 is the surface opposite the second side surface 12s3. The substrate 1 is formed, for example, from a mixture of BT resin (bismaleimide-triazine resin) and glass cloth.

[0011] A recess Th is formed on the side surface 10s3 of the substrate 1. Specifically, as shown in Figures 1 and 3, recesses Tha, Thb, Thc, and Thd are formed at each of the four corners of the substrate 1 in a plan view of the front surface 10s1. Note that in Figures 1 and 3, fan-shaped dotted lines indicate the outline of the recess Th. The recess Th is formed so as to extend from the front surface 10s1 to the back surface 10s2.

[0012] As shown in Figure 1, the directions in which the front surface 10s1 and the back surface 10s2 extend are the x-direction and the y-direction. The y-direction is perpendicular to the x-direction. The direction perpendicular to the front surface 10s1 is the z-direction. In other words, the z-direction is perpendicular to the x-direction and the y-direction.

[0013] The conductive layer 5 includes front-side conductive portions 51a, 51b, 51c, and 51d, back-side conductive portions 52a, 52b, 52c, 52d, 52e, and 52f, and side-side conductive portions 53a, 53b, 53c, and 53d. As shown in FIG. 1 , the front-side conductive portions 51a, 51b, 51c, and 51d are arranged on the front surface 10s1. The back-side conductive portions 52a, 52b, 52c, 52d, 52e, and 52f are arranged on the back surface 10s2. The side-side conductive portions 53a, 53b, 53c, and 53d are arranged in the recesses Tha, Thb, Thc, and Thd, respectively.

[0014] As shown in FIG. 1 , the surface-side conductive portion 51a and the surface-side conductive portion 51b are spaced apart from each other in the x direction. The surface-side conductive portion 51c and the surface-side conductive portion 51d are spaced apart from each other in the x direction. The surface-side conductive portion 51a and the surface-side conductive portion 51c are spaced apart from each other in the y direction. The surface-side conductive portion 51b and the surface-side conductive portion 51d are spaced apart from each other in the y direction. In the x direction, the surface-side conductive portion 51a and the surface-side conductive portion 51c are located on the opposite side from the side where the surface-side conductive portion 51b and the surface-side conductive portion 51d are located. In the y direction, the surface-side conductive portion 51a and the surface-side conductive portion 51b are located on the opposite side from the side where the surface-side conductive portion 51c and the surface-side conductive portion 51d are located. Note that, since the surface-side conductive portions 51a, 51b, 51c, and 51d are partially covered with the metal layer 6 and the resist 7, the surface-side conductive portions 51a, 51b, 51c, and 51d are partially not shown in FIG.

[0015] 1, the surface-side conductive portions 51a and 51b are arranged on the first side surface 11s3 side in the y direction, and the surface-side conductive portions 51c and 51d are arranged on the second side surface 12s3 side in the y direction.

[0016] The back-side conductive portion 52a and the back-side conductive portion 52b are spaced apart from each other in the x-direction. As shown in FIG. 2 , the back-side conductive portion 52c and the back-side conductive portion 52d are spaced apart from each other in the x-direction. The back-side conductive portion 52a and the back-side conductive portion 52c are spaced apart from each other in the y-direction. The back-side conductive portion 52b and the back-side conductive portion 52d are spaced apart from each other in the y-direction. In the x-direction, the back-side conductive portion 52a and the back-side conductive portion 52c are located on the opposite side from the side where the back-side conductive portion 52b and the back-side conductive portion 52d are located. In the y-direction, the back-side conductive portion 52a and the back-side conductive portion 52b are located on the opposite side from the side where the back-side conductive portion 52c and the back-side conductive portion 52d are located.

[0017] In the y direction, the back-side conductive portions 52a, 52b, 52e, and 52f are arranged on the first side surface 11s3 side. In the y direction, the back-side conductive portions 52c and 52d are arranged on the second side surface 12s3 side. The back-side conductive portions 52e and 52f are arranged between the back-side conductive portion 52a and the back-side conductive portion 52b in the x direction. The back-side conductive portions 52a, 52e, 52f, and 52b are arranged at a distance from each other in the x direction. The back-side conductive portion 52e is electrically connected to the back-side conductive portion 52c. The back-side conductive portion 52f is electrically connected to the back-side conductive portion 52d.

[0018] The side-side conductive portion 53a is disposed on the recess Tha (not shown). The side-side conductive portion 53a electrically connects the front-side conductive portion 51a and the back-side conductive portion 52a. The side-side conductive portion 53b is disposed on the recess Thb (not shown). The side-side conductive portion 53b electrically connects the front-side conductive portion 51b and the back-side conductive portion 52b. As shown in FIG. 2, the side-side conductive portion 53c is disposed on the recess Thc. The side-side conductive portion 53c electrically connects the front-side conductive portion 51c and the back-side conductive portion 52c. As shown in FIG. 2, the side-side conductive portion 53d is disposed on the recess Thd. The side-side conductive portion 53d electrically connects the front-side conductive portion 51d and the back-side conductive portion 52d. The configurations of the side-side conductive portions 53a and 53b are substantially the same as the configurations of the side-side conductive portions 53c and 53d shown in FIG. 2.

[0019] The light-emitting element 20a is disposed on the surface-side conductive portion 51a. Specifically, as shown in FIG. 1, the surface-side conductive portion 51a is electrically connected to the light-emitting element 20a via a conductive adhesive such as solder. The light-emitting element 20a is electrically connected to the surface-side conductive portion 51b via a wire 30a. The light-emitting element 20b is disposed on the surface-side conductive portion 51c. Specifically, as shown in FIGS. 1 and 2, the surface-side conductive portion 51c is electrically connected to the light-emitting element 20b via a conductive adhesive such as solder. The light-emitting element 20b is electrically connected to the surface-side conductive portion 51d via a wire 30b. The wire 3 is formed, for example, by wire bonding.

[0020] 2, the sealing resin 4 seals the light-emitting element 2. Specifically, the light-emitting element 2 is disposed inside the sealing resin 4. As shown in FIGS. 1 and 2, the sealing resin 4 is disposed so as to be spaced apart in the x direction from the metal layer 6 and the filling portion 8. The material constituting the sealing resin 4 is, for example, a silicone resin.

[0021] The metal layer 6 includes front-side metal layers 61a, 61b, 61c, and 61d and back-side metal layers 62a, 62b, 62c, 62d, 62e, and 62f. As shown in FIG. 2, the metal layer 6 is formed on the filling portion 8 and the conductive layer 5. Specifically, as shown in FIG. 1, the front-side metal layers 61a, 61b, 61c, and 61d are each disposed at the four corners of the front surface 10s1. Each of the front-side metal layers 61a, 61b, 61c, and 61d has, for example, a rectangular shape. As shown in FIG. 3, the back-side metal layer 62a covers the back-side conductive portion 52a. The back-side metal layer 62b covers the back-side conductive portion 52b. The back-side metal layer 62c covers the back-side conductive portion 52c. The back-side metal layer 62d covers the back-side conductive portion 52d. The back-side metal layer 62e covers the back-side conductive portion 52e. The back-side metal layer 62f covers the back-side conductive portion 52f.

[0022] The metal layer 6 includes, for example, a gold plating layer. The metal layer 6 may include, for example, an underlayer of tin plating 9, which will be described later. The underlayer may be, for example, at least one of a copper plating layer and a nickel plating layer. The metal layer 6 may be formed by stacking, for example, a copper plating layer, a nickel plating layer, and a gold plating layer in this order in the z direction.

[0023] As will be described later, tin plating 9 may be formed on the conductive layer 5, the metal layer 6, and the filling portion 8 (see FIGS. 9 to 11).

[0024] The resist 7 includes front-side resists 71a, 71b, 71c, and 71d and back-side resists 72a and 72b. As shown in FIG. 2 , the front-side resists 71a, 71b, 71c, and 71d are disposed on the front surface 10s1 so as to cover portions of the conductive layer 5. Specifically, a portion of the front-side resist 71a covers a portion of the front-side conductive portion 51a so as to prevent the front-side conductive portion 51a from being connected to the sealing resin 4. A portion of the front-side resist 71b covers a portion of the front-side conductive portion 51b so as to prevent the front-side conductive portion 51b from being connected to the sealing resin 4. A portion of the front-side resist 71c covers a portion of the front-side conductive portion 51c so as to prevent the front-side conductive portion 51c from being connected to the sealing resin 4. A portion of the front-side resist 71d covers a portion of the front-side conductive portion 51d so as to prevent the front-side conductive portion 51d from being connected to the sealing resin 4.

[0025] 1, in a plan view of the front surface 10s1, each of the front surface-side resists 71a, 71b, 71c, and 71d is disposed so as to partially overlap the sealing resin 4. From a different perspective, as shown in Fig. 2, the resist 7 is sandwiched between the conductive layer 5 and the sealing resin 4 in the z direction. In this way, the conductive layer 5 and the sealing resin 4 are disposed so as to be spaced apart from each other in the z direction.

[0026] 3 , back-side resists 72a and 72b are connected to metal layer 6 and back surface 10s2. In a plan view of back surface 10s2, a portion of back-side resist 72a is arranged to cover a portion of back-side metal layer 62c and a portion of back-side metal layer 62e. In a plan view of back surface 10s2, a portion of back-side resist 72b is arranged to cover a portion of back-side metal layer 62d and a portion of back-side metal layer 62f.

[0027] Here, as shown in FIG. 2 , the semiconductor module 100a according to the first embodiment is characterized in that the semiconductor module 100a includes a filling portion 8. The filling portion 8 is connected to the recess Th. Specifically, the filling portion 8 is connected to the recess Th via the side-side conductive portions 53a, 53b, 53c, and 53d. Basically, the filling portion 8 extends in the z-direction so as to fill each recess Th. This prevents a portion of the sealing resin 4 from entering the recess Th when the sealing resin 4 is formed, as will be described later. As a result, the tin plating 9 can be formed on the filling portion 8. Furthermore, the arrangement of the filling portion 8 in the recess Th improves the design freedom for the semiconductor module 100a, as will be described later.

[0028] 2 , the filling portion 8 has a first surface 8s1 and a second surface 8s2. The first surface 8s1 faces the front-side metal layers 61a, 61b, 61c, and 61d. The second surface 8s2 is located on the opposite side of the first surface 8s1 in the z direction. The second surface 8s2 faces the back-side metal layers 62a, 62b, 62c, and 62d. In the first embodiment, the first surface 8s1 and the second surface 8s2 are connected to the metal layer 6.

[0029] As shown in FIG. 1 , in a plan view of the front surface 10s1, the metal layer 6 covers the filling portion 8. Specifically, in a plan view of the front surface 10s1, the front surface-side metal layer 61a covers a portion of the front surface-side conductive portion 51a and the filling portion 8a. In a plan view, the front surface-side metal layer 61b covers a portion of the front surface-side conductive portion 51b and the filling portion 8b. In a plan view, the front surface-side metal layer 61c covers a portion of the front surface-side conductive portion 51c and the filling portion 8c. In a plan view, the front surface-side metal layer 61d covers a portion of the front surface-side conductive portion 51d and the filling portion 8d. In this way, the metal layer 6 acts as a lid, and when the sealing resin 4 is formed, intrusion of a portion of the sealing resin 4 into the recess Th is suppressed.

[0030] In the z direction, filling portion 8a is arranged so as to be sandwiched between front-side metal layer 61a and back-side metal layer 62a. In the z direction, filling portion 8b is arranged so as to be sandwiched between front-side metal layer 61b and back-side metal layer 62b. As shown in Figure 2, in the z direction, filling portion 8c is arranged so as to be sandwiched between front-side metal layer 61c and back-side metal layer 62c. As shown in Figure 2, in the z direction, filling portion 8d is arranged so as to be sandwiched between front-side metal layer 61d and back-side metal layer 62d.

[0031] The material of the filling portion 8 may be any material that can be connected to the tin plating 9 or the solder fillet 90 (see FIG. 12), such as a conductive resin. An example of the conductive resin is a silver-coated copper powder epoxy resin.

[0032] The material forming the filling portion 8 may be metal. If the material forming the filling portion 8 is metal, the filling portion 8 is prevented from coming off the recess Th in the dicing step (S9a) described later.

[0033] The filling portion 8 does not have to be formed over the entire region in which the recess Th extends in the z direction. From a different perspective, the filling portion 8 may be formed in a portion of the recess Th, and the filling portion 8 may be disposed on the front surface 10s1 side in the z direction. Specifically, the distance t2 from the first surface 8s1 to the second surface 8s2 may be smaller than the distance t1 from the front surface 10s1 to the back surface 10s2 (see FIG. 13 ). The distance t2 from the first surface 8s1 to the second surface 8s2 may be 0.8 times or less, 0.5 times or less, or 0.3 times or less, the distance t1 from the front surface 10s1 to the back surface 10s2. This reduces the manufacturing cost of the semiconductor module 100a. In particular, when the material constituting the filling portion 8 is metal, the manufacturing cost of the semiconductor module 100a can be significantly reduced.

[0034] <Method of Manufacturing Semiconductor Module> A method of manufacturing the semiconductor module 100a will now be described. FIG. 4 is a flowchart of the method of manufacturing the semiconductor module 100a according to the first embodiment. FIG. 5 is a schematic plan view showing a step in the method of manufacturing the semiconductor module 100a according to the first embodiment. FIG. 6 is a schematic plan view showing a step subsequent to the step shown in FIG. 5 in the method of manufacturing the semiconductor module 100a according to the first embodiment. FIG. 7 is a schematic plan view showing a step subsequent to the step shown in FIG. 6 in the method of manufacturing the semiconductor module 100a according to the first embodiment. FIG. 8 is a schematic plan view showing a step subsequent to the step shown in FIG. 7 in the method of manufacturing the semiconductor module 100a according to the first embodiment. As shown in FIG. 4, the method of manufacturing the semiconductor module 100a first performs a step (S1a) of preparing a substrate 10a. In this step (S1a), a substrate 10a that will become a base material 1 is prepared as shown in FIG. 5. A copper foil 50a may be formed on the surface of the substrate 10a. 5 to 8, the straight dotted lines L2 indicate the locations along which the substrate 10a is cut into individual pieces in the dicing step (S9a) described below.

[0035] Next, a step (S2a) of forming through holes TH is performed. In this step (S2a), a plurality of through holes TH are formed in the substrate 10a using a drill, as shown in FIG. 6 . The through holes TH are formed so as to extend from the front surface to the back surface of the substrate 10a. In the first embodiment, the through holes TH are formed so as to penetrate the copper foil 50a.

[0036] Next, a step (S3a) of forming a conductive layer 5 is performed. In this step (S3a), the conductive layer 5 is formed on the copper foil 50a and the inner surfaces of the through holes TH. The conductive layer 5 is formed by electrolytic plating on the copper foil 50a and the inner surfaces of the through holes TH. Thereafter, the conductive layer 5 is patterned as shown in FIG. 7. Note that in FIGS. 7 and 8, the circular dotted lines indicate the outline of the through holes TH.

[0037] Next, a step (S4a) of forming a filling portion 8 is performed. In this step (S4a), as shown in FIG. 8 , a conductive resin, for example, a silver-coated copper powder epoxy resin, is formed in the through-hole TH so as to fill the through-hole TH. Metal may also be formed in the through-hole TH. In this manner, the filling portion 8 is connected to the side-side conductive portions 53a, 53b, 53c, and 53d. Forming the filling portion 8 in the through-hole TH improves the design freedom for the substrate 10a. For example, a step (S6a) of forming a resist 7, which will be described later, can be performed.

[0038] Next, a step (S5a) of forming resist 7 is performed. In this step (S5a), resist 7 is formed on the rear and front surfaces of substrate 10a. Resist 7 is formed so as to cover a portion of conductive layer 5 (see FIG. 1).

[0039] Next, a step (S6a) of forming metal layer 6 is performed. In this step (S6a), metal layer 6 is formed so as to cover through-hole TH and filling portion 8 in a plan view of substrate 10a (see FIG. 1).

[0040] Next, a step (S7a) of mounting the light-emitting element 2 is performed. In this step (S7a), as shown in FIG. 1 , the light-emitting element 20a is mounted by die bonding on the surface-side conductive portion 51a formed on the surface of the substrate 10a. The light-emitting element 20b is mounted by die bonding on the surface-side conductive portion 51c. Next, wires 30a and 30b are formed by wire bonding. Specifically, the light-emitting element 20a and the surface-side conductive portion 51b are electrically connected via the wire 30a formed by wire bonding. The light-emitting element 20b and the surface-side conductive portion 51d are electrically connected via the wire 30b formed by wire bonding.

[0041] Next, a step (S8a) of forming the sealing resin 4 is performed. In this step (S8a), the light-emitting element 2 mounted on the substrate 10a is sealed with the sealing resin 4. First, a predetermined mold having a cavity is prepared (not shown). Next, the mold is placed on the substrate 10a on which the light-emitting element 2 is mounted. In this state, the sealing resin 4 is injected into the cavity of the mold. Here, when the sealing resin 4 is injected into the cavity, if the surface pressure between the mold and the substrate 10a is insufficient, some of the sealing resin 4 may leak out of the mold. As a result, in a conventional configuration in which the filling portion 8 and the metal layer 6 are not formed, some of the sealing resin 4 penetrates into the through-hole TH. As described above, in the substrate 10a according to the first embodiment, the filling portion 8 is formed in the through-hole TH, and the metal layer 6 is disposed so as to cover the filling portion 8 and the through-hole TH. Therefore, the metal layer 6 acts as a lid, preventing some of the sealing resin 4 leaking out of the mold from penetrating into the through-hole TH.

[0042] Next, a dicing step (S9a) is performed. In this step (S9a), the substrate 10a is diced along the dotted lines L2 shown in FIGS. 5 to 8. In this manner, the substrate 10a on which the light-emitting elements 2 are mounted is singulated, thereby manufacturing the semiconductor module 100a shown in FIGS. 1 to 3. By singulating the substrate 10a by dicing, a portion of the through-hole TH becomes the recess Th. For example, if the material constituting the filling portion 8 is metal, the filling portion 8 is prevented from coming off the recess Th by dicing.

[0043] <Effects> The semiconductor module 100a according to the present disclosure includes a substrate 1, a sealing resin 4, a filling portion 8, and a metal layer 6. The substrate 1 has a front surface 10s1 and a back surface 10s2. The back surface 10s2 is located on the opposite side of the front surface 10s1. The sealing resin 4 is disposed on the front surface 10s1. The metal layer 6 covers the filling portion 8 in a plan view of the front surface 10s1. The substrate 1 is formed with a recess Th that extends from the front surface 10s1 to the back surface 10s2. The filling portion 8 is connected to the recess Th.

[0044] In this way, when the sealing resin 4 is formed, a portion of the sealing resin 4 is prevented from entering the region (recess Th) where the filling portion 8 is formed. As a result, the tin plating 9 can be formed on the filling portion 8. Furthermore, since the filling portion 8 is disposed in the recess Th, the design freedom for the semiconductor module 100a is improved. As a result, the resist 7 can be formed on the surface 10s1.

[0045] The semiconductor module 100a further includes a light emitting element 2. The sealing resin 4 seals the light emitting element 2. In this way, the semiconductor module 100a can be used as a light emitting device.

[0046] In the semiconductor module 100a, the material constituting the filling portion 8 is a conductive resin. In this way, the filling portion 8 can electrically connect the conductive layer 5 on the front surface 10s1 to the conductive layer 5 on the back surface 10s2. Furthermore, if the material constituting the conductive resin is, for example, a silver-coated copper powder epoxy resin, a tin plating 9 can be formed on the filling portion 8.

[0047] Second Embodiment <Configuration of Semiconductor Module> Fig. 9 is a schematic plan view of a semiconductor module 100b according to a second embodiment. Fig. 9 corresponds to Fig. 1. Fig. 10 is a schematic side view of the semiconductor module 100b according to the second embodiment. Fig. 10 corresponds to Fig. 2. Fig. 11 is a schematic bottom view of the semiconductor module 100b according to the second embodiment. Fig. 11 corresponds to Fig. 3. The semiconductor module 100b shown in Figs. 9 to 11 basically has the same configuration as the semiconductor module 100a shown in Figs. 1 to 3 and can achieve the same effects, but differs in that it has tin plating 9.

[0048] As described above, the surfaces of the conductive layer 5, the metal layer 6, and the filling portion 8 are made of materials on which tin plating can be formed. Therefore, the tin plating 9 may be formed on the conductive layer 5, the metal layer 6, and the filling portion 8 of the semiconductor module 100a according to the first embodiment. Specifically, after the dicing step (S9a), the tin plating 9 is formed on the semiconductor module 100a according to the first embodiment using a barrel plating process. The tin plating 9 is formed on the conductive layer 5, the metal layer 6, and the filling portion 8 that are not covered by the resist 7.

[0049] As described above, by arranging the filling portion 8 in the recess Th, front surface resists 71a, 71b, 71c, and 71d can be formed on the front surface 10s1 in the step (S6a) of forming the resist 7.

[0050] In a semiconductor module equipped with tin plating 9, when exposed to high temperatures during reflow or the like, the tin plating 9 formed on the conductive layer 5 and the metal layer 6 may melt. For example, if the conductive layer 5 and the metal layer 6 are connected to the sealing resin 4 without a resist, the melted tin plating 9 may penetrate into the sealing resin 4. If the tin plating 9 penetrates into the area where the sealing resin 4 is arranged, the wire 3 may peel off.

[0051] In the second embodiment, the sealing resin 4 is arranged to be spaced apart in the x-direction from the metal layer 6 and the filling portion 8 via the front-side resists 71a, 71b, 71c, and 71d. The front-side resists 71a, 71b, 71c, and 71d cover the conductive layer 5 so that the conductive layer 5 and the sealing resin 4 are spaced apart in the z-direction. In this way, in a plan view of the front surface 10s1, the resist 7 is arranged between the sealing resin 4 and the metal layer 6. Therefore, even if the tin plating 9 formed on the conductive layer 5, the metal layer 6, and the filling portion 8 melts, the tin plating 9 does not penetrate into the region where the sealing resin 4 is arranged.

[0052] FIG. 12 is a schematic perspective view showing a state in which the semiconductor module 100b of the second embodiment is mounted on a mounting substrate 200. The semiconductor module 100b is mounted on the mounting substrate 200 so that the first side surface 11s3 faces the mounting substrate 200. At this time, the semiconductor module 100b is mounted on the mounting substrate 200 so that each of the front surface 10s1 and the back surface 10s2 is perpendicular to the mounting substrate 200. In this manner, a side-view light-emitting device is manufactured. As shown in FIG. 12 , solder fillets 90 are formed on the front surface-side conductive portions 51a and 51b, the back surface-side conductive portions 52a, 52e, 52f, and 52b, and the filling portions 8a and 8b. The tin plating 9 formed on the back surface-side conductive portions 52a, 52e, 52f, and 52b is electrically connected to wiring (not shown) having a predetermined width formed on the mounting substrate 200 by the solder fillets 90.

[0053] 12 , solder fillets 90 can be formed on the conductive layer 5, the metal layer 6, and the filling portion 8. When exposed to high temperatures during reflow or the like, the solder fillets 90 formed on the conductive layer 5, the metal layer 6, and the filling portion 8 may melt. However, because the resist 7 is disposed between the sealing resin 4 and the metal layer 6, even if the solder fillets 90 formed on the conductive layer 5, the metal layer 6, and the filling portion 8 melt, the solder fillets 90 do not penetrate into the sealing resin 4.

[0054] It is preferable that the metal layer 6 contains a material that does not melt even when the temperature reaches a high enough level to melt the tin plating 9 or the solder fillet 90 during reflow, etc. Specifically, it is preferable that the metal layer 6 contains at least one of a copper plating layer and a nickel plating layer as a base layer for the tin plating 9.

[0055] <Effects> The semiconductor module 100b further includes a resist 7. The resist 7 is formed on the surface 10s1. In a plan view of the surface 10s1, the resist 7 is disposed between the sealing resin 4 and the metal layer 6. In this manner, even if the tin plating 9 formed on the conductive layer 5, the metal layer 6, and the filling portion 8 melts, the tin plating 9 does not penetrate into the sealing resin 4. As a result, peeling of the wire 3 sealed by the sealing resin 4 can be suppressed.

[0056] The semiconductor module 100b further includes a tin plating 9. The tin plating 9 is connected to the metal layer 6 or the filling portion 8. In this manner, the semiconductor module 100b can be electrically mounted on the mounting substrate 200 via the solder fillet 90.

[0057] In the semiconductor module 100b, the metal layer 6 includes at least one of a copper plating layer and a nickel plating layer, so that the metal layer 6 does not melt even when exposed to high temperatures during reflow or the like.

[0058] Third Embodiment <Configuration of Semiconductor Module> Figure 13 is a schematic side view of a semiconductor module 100c according to a third embodiment. Figure 13 corresponds to Figure 2. The semiconductor module 100c shown in Figure 13 basically has the same configuration as the semiconductor module 100a shown in Figures 1 to 3 and can achieve the same effects, but differs in that the filling portion 8 is not formed over the entire region in which the recess Th extends in the z direction. As shown in Figure 13, the filling portion 8 is connected to the metal layer 6 via the conductive layer 5. The material constituting the filling portion 8 is metal. This prevents the filling portion 8 from coming off the recess Th in the dicing step (S9b).

[0059] As described above, it is sufficient that the filling portion 8 is formed in a part of the recess Th, and that the filling portion 8 is disposed on the front surface 10s1 side in the z direction. Specifically, on the front surface 10s1 side of the substrate 1, the first surface 8s1 of the filling portion 8 is connected to the front surface-side conductive portions 51a, 51b, 51c, and 51d. The second surface 8s2 of the filling portion 8 is connected to a part of the side surface-side conductive portions 53a, 53b, 53c, and 53d.

[0060] The first surface 8s1 is flush with the surface 10s1 of the base material 1 in the z direction. The second surface 8s2 may be located between the surface 10s1 and the back surface 10s2 of the base material 1 in the z direction. That is, as shown in FIG. 13 , the distance t2 from the first surface 8s1 to the second surface 8s2 may be smaller than the distance t1 from the surface 10s1 to the back surface 10s2. The distance t2 from the first surface 8s1 to the second surface 8s2 may be 0.8 times or less, 0.5 times or less, or 0.3 times or less, of the distance t1 from the surface 10s1 to the back surface 10s2. This reduces the manufacturing cost of the semiconductor module 100c. In particular, when the material constituting the filling portion 8 is metal, the manufacturing cost of the semiconductor module 100c can be significantly reduced.

[0061] In a region in the z direction where the filling portion 8 is not formed, the side-side conductive portions 53 a, 53 b, 53 c, ​​and 53 d are connected to the inner circumferential surface of the recess Th. Parts of the side-side conductive portions 53 a, 53 b, 53 c, ​​and 53 d are connected to the second surface 8 s 2 of the filling portion 8.

[0062] <Method of Manufacturing Semiconductor Module> A method of manufacturing the semiconductor module 100c will now be described. FIG. 14 is a flowchart of the method of manufacturing the semiconductor module 100c according to the third embodiment. FIG. 15 is a schematic plan view showing one step in the method of manufacturing the semiconductor module 100c according to the third embodiment. FIG. 16 is a schematic plan view showing a step subsequent to the step shown in FIG. 15 in the method of manufacturing the semiconductor module 100c according to the third embodiment. FIG. 17 is a schematic plan view showing a step subsequent to the step shown in FIG. 16 in the method of manufacturing the semiconductor module 100c according to the third embodiment.

[0063] The method for manufacturing the semiconductor module 100c first performs the same steps as those shown in Fig. 5 in the method for manufacturing the semiconductor module 100a according to the first embodiment. That is, a step (S1b) of preparing the substrate 10a is first performed. In this step (S1b), the substrate 10a that will become the base material 1 is prepared, as shown in Fig. 5.

[0064] Next, a step (S2b) of forming through holes TH is performed. In this step (S2b), a plurality of through holes TH are formed in the substrate 10a, as shown in FIG. 15. The through holes TH are formed so as to extend from the rear surface of the substrate 10a to the front surface to which the copper foil 50a is connected. In other words, in the third embodiment, the through holes TH are formed so as not to penetrate the copper foil 50a. Note that in FIGS. 15 to 17, circular dotted lines indicate the outline of the through holes TH.

[0065] Next, a step (S3b) of forming a filling portion 8 is performed. In this step (S3b), a metal plating is formed so as to fill the through-hole TH from the back surface of the substrate 10a. In this manner, as shown in FIG. 16 , a filling portion 8 made of a metal material is formed. The filling portion 8 may be formed in a portion of the through-hole TH, and the filling portion 8 may be disposed on the front surface 10s1 side in the z direction. Specifically, the first surface 8s1 may be disposed on the same plane as the front surface 10s1 of the substrate 1 in the z direction. The second surface 8s2 may be disposed between the front surface 10s1 and the back surface 10s2 of the substrate 1 in the z direction. In other words, as shown in FIG. 13 , the distance t2 from the first surface 8s1 to the second surface 8s2 may be smaller than the distance t1 from the front surface 10s1 to the back surface 10s2.

[0066] Next, a step (S4b) of forming a conductive layer 5 is performed. In this step (S4b), the conductive layer 5 is formed on the copper foil 50a, the inner surface of the through hole TH, and the second surface 8s2 of the filling portion 8. The conductive layer 5 is formed by electrolytic plating on the copper foil 50a, the inner surface of the through hole TH, and the second surface 8s2 of the filling portion 8. Then, as shown in FIG. 17 , the conductive layer 5 is patterned. At this time, in areas where the filling portion 8 is not formed in the z direction, side-side conductive portions 53a, 53b, 53c, and 53d are formed on the inner surface of the through hole TH. Portions of the side-side conductive portions 53a, 53b, 53c, and 53d are connected to the second surface 8s2 of the filling portion 8.

[0067] Next, a step (S5b) of forming resist 7 is performed. In this step (S5b), resist 7 is formed on the rear and front surfaces of substrate 10a. Resist 7 is formed so as to cover a portion of conductive layer 5.

[0068] Next, a step (S6b) of forming a metal layer 6 is performed. In this step (S6b), as shown in Fig. 13 , the metal layer 6 is formed on the copper foil 50a, the inner circumferential surface of the through hole TH, and the conductive layer 5 formed on the second surface 8s2 of the filling portion 8. In a plan view of the substrate 10a, the metal layer 6 is formed so as to cover the through hole TH and the filling portion 8.

[0069] After the step (S6b) of forming the metal layer 6, the steps (S7b) of mounting the light-emitting element 2 to the step (S9b) of dicing are sequentially performed. The steps (S7b) of mounting the light-emitting element 2 to the step (S9b) of dicing are similar to the steps (S7a) of mounting the light-emitting element 2 to the step (S9a) of dicing in the manufacturing method of the semiconductor module 100a according to the first embodiment. In the step (S3b) of forming the filling portion 8, if the material constituting the filling portion 8 is metal, the step (S9b) of dicing prevents the filling portion 8 from coming off the recess Th due to dicing. In this manner, the semiconductor module 100c shown in FIG. 13 can be manufactured.

[0070] <Effects> In the semiconductor module 100c, the filling portion 8 has a first surface 8s1 and a second surface 8s2. The first surface 8s1 faces the metal layer 6. The second surface 8s2 is opposite the first surface 8s1. The distance t2 from the first surface 8s1 to the second surface 8s2 is smaller than the distance t1 from the front surface 10s1 to the back surface 10s2. In this way, when the material constituting the filling portion 8 is metal, the manufacturing cost of the semiconductor module 100a can be significantly reduced.

[0071] In the semiconductor module 100c, the material constituting the filling portion 8 is metal, which prevents the filling portion 8 from coming off the recess Th in the dicing step (S9b).

[0072] Fourth Embodiment <Configuration of Semiconductor Module> Fig. 18 is a schematic side view of a semiconductor module 100d according to a fourth embodiment. Fig. 18 corresponds to Fig. 13. The semiconductor module 100d shown in Fig. 18 basically has the same configuration as the semiconductor module 100c shown in Fig. 13 and can achieve the same effects, but differs in that it has tin plating 9.

[0073] As described above, the surfaces of the conductive layer 5, the metal layer 6, and the filling portion 8 are made of materials on which tin plating can be formed. Therefore, the tin plating 9 may be formed on the conductive layer 5, the metal layer 6, and the filling portion 8 of the semiconductor module 100c according to the third embodiment. In this way, the semiconductor module 100d can be electrically mounted on the mounting substrate 200 via the solder fillet 90.

[0074] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. Unless there is a contradiction, at least two of the embodiments disclosed herein may be combined. The basic scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0075] The present disclosure includes the following aspects. (Supplementary Note 1) A semiconductor module comprising: a substrate having a surface and a back surface opposite the surface; a sealing resin disposed on the surface; a filling portion; and a metal layer covering the filling portion in a plan view of the surface, wherein a recess extending from the surface to the back surface is formed in the substrate, and the filling portion is connected to the recess. (Supplementary Note 2) The semiconductor module according to Supplementary Note 1, wherein the filling portion has one surface facing the metal layer and a second surface opposite the first surface, and wherein the distance from the first surface to the second surface is shorter than the distance from the surface to the back surface. (Supplementary Note 3) The semiconductor module according to Supplementary Note 1 or Supplementary Note 2, further comprising a resist formed on the surface, wherein the resist is disposed between the sealing resin and the metal layer in a plan view of the surface. (Supplementary Note 4) The semiconductor module according to any one of Supplementary Notes 1 to 3, further comprising tin plating, wherein the tin plating is connected to the metal layer and the filling portion. (Supplementary Note 5) The semiconductor module according to any one of Supplementary Notes 1 to 4, further comprising a light-emitting element, wherein the sealing resin seals the light-emitting element. (Supplementary Note 6) The semiconductor module according to any one of Supplementary Notes 1 to 5, wherein the material constituting the filling section is a conductive resin. (Supplementary Note 7) The semiconductor module according to any one of Supplementary Notes 1 to 5, wherein the material constituting the filling section is a metal. (Supplementary Note 8) The semiconductor module according to any one of Supplementary Notes 1 to 7, wherein the metal layer includes at least one of a copper plating layer and a nickel plating layer.

[0076] DESCRIPTION OF SYMBOLS 1 Base material, 2, 20a, 20b Light emitting element, 3, 30a, 30b Wire, 4 Sealing resin, 5 Conductive layer, 6 Metal layer, 61a, 61b, 61c, 61d Surface side metal layer, 62a, 62b, 62c, 62d, 62e, 62f Back side metal layer, 7 Resist, 8, 8a, 8b, 8c, 8d Filling portion, 9 Tin plating, 10a Substrate, 10s1 Surface, 10s2 Back side, 10s3 Side, 11s3 First side, 12s3 Second side, 50a Copper foil, 51a, 51b, 51c, 51d Surface side conductive portion, 52a, 52b, 52c, 52d, 52e, 52f Back side conductive portion, 53a, 53b, 53c, 53d Side-side conductive portion, 61a, 61b, 61c, 61d: front-side metal layer, 62a, 62b, 62c, 62d, 62e, 62f: rear-side metal layer, 71a, 71b, 71c, 71d: front-side resist, 72a, 72b: rear-side resist, 90: solder fillet, 100a, 100b, 100c, 100d: semiconductor module, 200: mounting substrate, L: dotted line, TH: through-hole, Th, Tha, Thb, Thc, Thd: recess, t1, t2: distance.

Claims

1. A semiconductor module comprising: a substrate having a surface and a back surface opposite the surface; a sealing resin disposed on the surface; a filling portion; and a metal layer covering the filling portion in a planar view of the surface, wherein a recess is formed in the substrate extending from the surface to the back surface, and the filling portion is connected to the recess.

2. The semiconductor module described in claim 1, wherein the filling portion has a first surface facing the metal layer and a second surface opposite the first surface, and the distance from the first surface to the second surface is smaller than the distance from the front surface to the back surface.

3. A semiconductor module according to claim 1 or claim 2, further comprising a resist formed on said surface, said resist being disposed between said sealing resin and said metal layer in a plan view of said surface.

4. The semiconductor module according to any one of claims 1 to 3, further comprising a tin plating, said tin plating being connected to said metal layer and said filling portion.

5. A semiconductor module according to any one of claims 1 to 4, further comprising a light emitting element, the sealing resin sealing the light emitting element.

6. A semiconductor module according to any one of claims 1 to 5, wherein the material constituting the filling portion is a conductive resin.

7. A semiconductor module according to any one of claims 1 to 5, wherein the material constituting the filling portion is a metal.

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