Storage device and electronic apparatus

Abstract

A storage device according to one embodiment of the present disclosure comprises: a magnetoresistive element having a variable resistance value; a ferromagnetic bias layer that imparts a magnetic field to the magnetoresistive element; and a soft magnetic flux guide layer that absorbs magnetic flux.

Description

Storage devices and electronic equipment

[0001] The present disclosure relates to a storage device and an electronic device.

[0002] Magnetoresistive random access memory (MRAM) using a magnetoresistive element (magnetoresistive effect element) has a magnetic tunnel junction structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a storage layer and a reference layer). Resistance varies depending on the relative magnetization angle between the storage layer, whose magnetization direction is variable, and the reference layer, whose magnetization direction is invariable. Therefore, the binary resistance depending on whether the relative magnetization direction is parallel or antiparallel can be utilized for information storage. In the storage layer, perpendicular magnetic anisotropy (PMA) makes magnetic energy most stable in two directions, up and down, and an energy barrier exists at the angle between them, enabling nonvolatile data retention even when the voltage is turned off.

[0003] The write operation of a voltage-driven magnetic storage device (VC-MRAM: Voltage Controlled Magnetic Random Access Memory) involves removing energy barriers by applying an in-plane magnetic field and using voltage-controlled magnetic anisotropy (VCMA), causing the magnetization in the storage layer to begin precessing with the magnetic field direction as its precession axis. Writing is completed by cutting off the voltage when the magnetization reverses direction. In principle, this voltage-driven writing method allows for high-speed writing on the order of sub-ns, and has the advantage of low power consumption due to being voltage-driven.

[0004] The reversal time required for writing is determined by the precession period of the magnetization, and the stronger the in-plane magnetic field, the shorter the precession period. To control the precession period to a pulse width of approximately 10 ns, which allows for accurate drive of the write pulse, the bias magnetic field must be controlled accurately at less than 20 Oe. However, applying a uniform in-plane magnetic field to the entire memory element is difficult, and variations of several Oe are expected to occur for each bit. A change in the bias magnetic field of several Oe causes large variations in the reversal time, preventing a reduction in the write error rate (WER). One method for applying a bias magnetic field to a magnetoresistive element is to introduce a ferromagnetic bias layer (see, for example, Patent Document 1).

[0005] Japanese Patent Application Laid-Open No. 2016-225633

[0006] However, when the above-mentioned ferromagnetic bias layer is introduced, in order to reduce the bias magnetic field to, for example, less than 20 Oe, it is necessary to make the ferromagnetic bias layer smaller or thinner, but this increases the variation in the processed shape, the roughness of the film, the non-uniformity within the wafer surface, etc., and therefore increases the variation in the bias magnetic field.

[0007] Therefore, the present disclosure provides a memory device and an electronic device that can reduce the bias magnetic field applied to a magnetoresistive element and reduce the variation in the bias magnetic field.

[0008] A memory device according to one embodiment of the present disclosure includes a magnetoresistive element having a variable resistance value, a ferromagnetic bias layer that applies a magnetic field to the magnetoresistive element, and a soft magnetic flux guide layer that absorbs magnetic flux.

[0009] A memory device according to an embodiment of the present disclosure includes a magnetoresistive element having a variable resistance value, and a soft magnetic flux guide layer and an antiferromagnetic layer that apply a magnetic field to the magnetoresistive element.

[0010] An electronic device according to one embodiment of the present disclosure includes a memory device, the memory device having a magnetoresistive element with a variable resistance value, a ferromagnetic bias layer that applies a magnetic field to the magnetoresistive element, and a soft magnetic flux guide layer that absorbs magnetic flux.

[0011] An electronic device according to one embodiment of the present disclosure includes a memory device, the memory device having a magnetoresistive element with a variable resistance value, and a soft magnetic flux guide layer and an antiferromagnetic layer that apply a magnetic field to the magnetoresistive element.

[0012] 1 is a diagram showing an example of the configuration of a memory device according to the first embodiment. FIG. 2 is a diagram showing an example of the configuration of a memory cell according to the first embodiment. FIG. 3 is a diagram showing another example of the configuration of a memory cell according to the first embodiment. FIG. 4 is a cross-sectional view showing an example of the configuration of a memory cell array according to the first embodiment. FIG. 5 is a diagram for explaining an example of a write operation of a VC-MRAM according to the first embodiment. FIG. 6 is a diagram showing a formula for a precession period and a graph showing the relationship between an in-plane magnetic field and the precession period according to the first embodiment. FIG. 7 is a diagram showing a graph showing the relationship between an in-plane magnetic field and the precession period, and a parameter set according to the first embodiment. FIG. 8 is a diagram showing the pulse width dependency of a write error rate under each in-plane magnetic field application condition according to the first embodiment. FIG. 9 is a diagram showing an example of a flowchart of a write process according to the first embodiment. FIG. 10 is a diagram showing an example of a timing chart of a write process according to the first embodiment. FIG. 11 is a cross-sectional view showing an example of the configuration of a memory cell array according to the second embodiment. FIG. 12 is a cross-sectional view showing an example of the configuration of a memory cell array according to the third embodiment. FIG. 13 is a cross-sectional view showing an example of the configuration of a memory cell array according to the fourth embodiment. FIG. 14 is a plan view showing an example of the shape of a flux guide layer according to the fourth embodiment. FIG. 15 is a plan view showing another example of the shape of a flux guide layer according to the fourth embodiment. 10. A perspective view showing an example of the arrangement of memory cells according to the fourth embodiment. 11. A cross-sectional view showing an example of the configuration of a memory cell array according to the fifth embodiment. 12. A cross-sectional view showing an example of the configuration of a memory cell array according to the sixth embodiment. 13. A cross-sectional view showing an example of the configuration of a memory cell array according to the seventh embodiment. 14. A cross-sectional view showing an example of the configuration of a memory cell array according to the eighth embodiment. 15. A cross-sectional view showing an example of the configuration of a memory cell array according to the ninth embodiment. 16. A cross-sectional view showing an example of the configuration of a memory cell array according to the tenth embodiment. 17. A perspective view showing an example of the arrangement of memory cells according to the tenth embodiment. 18. A cross-sectional view showing an example of the configuration of a memory cell array according to the eleventh embodiment. 19. A cross-sectional view showing an example of the configuration of a memory cell array according to the twelfth embodiment. 20. A cross-sectional view showing an example of the configuration of a memory cell array according to the thirteenth embodiment. 21. A cross-sectional view showing an example of the configuration of a memory cell array according to the fourteenth embodiment.Fig. 23 is a cross-sectional view showing a configuration example of a memory cell array according to a fifteenth embodiment; Fig. 24 is a diagram showing an application example using a memory device according to any of the above-mentioned embodiments; Fig. 25 is a diagram showing a configuration example of an imaging device according to an application example; Fig. 26 is a diagram showing a configuration example of a distance measuring device according to an application example.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modified examples. Note that the embodiments of the present disclosure do not limit the devices, equipment, methods, etc. related to the present disclosure. Furthermore, in the following embodiments, essentially identical components are designated by the same reference numerals, and redundant explanations will be omitted.

[0014] One or more of the following embodiments can be implemented independently. However, at least a portion of the following embodiments may be implemented in appropriate combination with at least a portion of another embodiment. These embodiments may include novel features that are different from one another. Therefore, each embodiment may contribute to solving different objectives or problems, and may achieve different effects. The effects of each embodiment are merely examples and are not intended to be limiting, and other effects may also be achieved.

[0015] The present disclosure will be described in the following order: 1. First Embodiment 1-1. Configuration Example of Memory Device 1-2. Configuration Example of Memory Cell 1-3. Configuration Example of Memory Cell Array 1-4. Write Operation Example of VC-MRAM 1-5. Control Example of In-Plane Magnetic Field 1-6. Write Processing Example 1-7. Example of Timing Chart of Write Processing 2. Second Embodiment 2-1. Configuration Example of Memory Cell Array 3. Third Embodiment 3-1. Configuration Example of Memory Cell Array 4. Fourth Embodiment 4-1. Configuration Example of Memory Cell Array 4-2. Shape Example of Flux Guide Layer 4-3. Arrangement Example of Memory Cell 5. Fifth Embodiment 5-1. Configuration Example of Memory Cell Array 6. Sixth Embodiment 6-1. Configuration Example of Memory Cell Array 7. Seventh Embodiment 7-1. Configuration Example of Memory Cell Array 8. Eighth Embodiment 8-1. Configuration Example of Memory Cell Array 9. Ninth Embodiment 9-1. Configuration Example of Memory Cell Array 10. Tenth Embodiment 10-1. Configuration Example of Memory Cell Array 10-2. Arrangement Example of Memory Cell 11. Eleventh Embodiment 11-1. Configuration Example of Memory Cell Array 12. Twelfth Embodiment 12-1. Configuration Example of Memory Cell Array 13. Thirteenth Embodiment 13-1. Configuration Example of Memory Cell Array 14. Fourteenth Embodiment 14-1. Configuration Example of Memory Cell Array 15. Fifteenth Embodiment 15-1. Configuration Example of Memory Cell Array 16. Functions and Effects of Each Embodiment 17. Other Embodiments 18. Application Examples 18-1. Various Devices 18-2. Imaging Device 18-3. Distance Measuring Device 19. Supplementary Notes

[0016] 1. First Embodiment 1-1. Configuration Example of Storage Device An example of the configuration of a storage device 10 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing an example of the configuration of a storage device 10 according to this embodiment.

[0017] 1, a memory device 10 includes a memory cell array 11. The memory device 10 is an example of a memory device that stores data based on the magnetization direction of a magnetic material.

[0018] The memory cell array 11 includes a plurality of memory cells 100 arranged in a matrix. These memory cells 100 are connected to bit lines BL, source lines SL, and word lines WL, respectively. For example, the plurality of word lines WL are wired to extend in the row direction, and the plurality of bit lines BL and the plurality of source lines SL are wired to extend in the column direction. The bit lines BL, source lines SL, and word lines WL each function as control lines.

[0019] Each memory cell 100 has a magnetoresistive element (magnetoresistive effect element) 110 and a selection element 120. The magnetoresistive element 110 is, for example, a magnetoresistive element such as an MTJ (Magnetic Tunnel Junction). The selection element 120 is connected to one end of the magnetoresistive element 110 and controls the application of voltage, current, etc. to the magnetoresistive element 110. For example, various transistors can be used as this selection element 120. For example, a VC-MRAM cell can be used as the memory cell 100.

[0020] 1, the memory cells 100 share one source line SL for every two columns in the column direction, i.e., the memory cells 100 arranged in two columns are connected to two bit lines BL and one source line SL (2BL / 1SL).

[0021] In addition to the memory cell array 11, the memory device 10 includes peripheral circuits 20. In the example of Figure 1, the peripheral circuits 20 include an I / O (input / output circuit) 21, a control circuit 22, a voltage generation circuit 23, a write circuit 24, a read circuit 25, a bit line address decoder 26, a bit line control circuit 27, a word line address decoder 28, a word line control circuit 29, and a sense amplifier 30. The bit line control circuit 27 is connected to the bit line BL, the word line control circuit 29 is connected to the word line WL, and the sense amplifier 30 is connected to the source line SL. The basic configuration of such a memory is well known, so the basic configuration will be briefly described.

[0022] The I / O 21 enables the exchange of commands related to reading and writing data, addresses of memory cells 100 to be accessed, data, etc. between an external circuit (e.g., an arithmetic circuit) of the memory device 10 and the control circuit 22 of the memory device 10.

[0023] In response to a command, the control circuit 22 controls the writing and reading of data to and from the memory cell 100. For example, the control circuit 22 receives a command (such as a write or read command) from an external circuit, and controls the writing and reading of data based on the received command.

[0024] The voltage generation circuit 23 generates a voltage (e.g., a pulse voltage) used to write and read data to the memory cell 100, and supplies the generated voltage to the write circuit 24 and the read circuit 25. Note that voltages required for circuit operation are provided separately.

[0025] The write circuit 24 controls the voltage and current (for example, pulse voltage and pulse current) used to write data to the memory cell 100. The write circuit 24 functions as a write unit.

[0026] The read circuit 25 controls the reading of data from the memory cell 100. Specifically, the read circuit 25 controls a voltage (for example, a pulse voltage) used to detect the resistance value of the magnetoresistive element 110. The read circuit 25 functions as a read unit.

[0027] The bit line address decoder 26 obtains the address of the bit line BL corresponding to the address received at the I / O 21 described above.

[0028] The bit line control circuit 27 selects and controls the bit line BL corresponding to the address of the bit line address decoder 26. For example, writing data to the memory cell 100 by the write circuit 24 and reading data from the memory cell 100 by the read circuit 25 are performed via the bit line control circuit 27 etc.

[0029] The word line address decoder 28 obtains the address of the word line WL corresponding to the address received at the I / O 21 described above.

[0030] The word line control circuit 29 selects and controls the word line WL corresponding to the address of the word line address decoder 28 .

[0031] The sense amplifier 30 detects the data read from the memory cell 100 by the read circuit 25 , specifically the resistance value of the magnetoresistive element 110 .

[0032] <1-2. Configuration Example of Memory Cell> A configuration example of the memory cell 100 according to this embodiment will be described with reference to Fig. 2 and Fig. 3. Fig. 2 and Fig. 3 are diagrams each showing a configuration example of the memory cell 100 according to this embodiment. Each of these figures is a schematic diagram showing a configuration example of the memory cell 100.

[0033] 2 and 3, the magnetoresistive element 110 and the selection element 120 of the memory cell 100 are connected in series, and the selection element 120 has a drain (drain terminal), a source (source terminal), and a gate (gate terminal). The contact layers 103 and 104 correspond to, for example, electrode layers or connection layers.

[0034] 2, the magnetoresistive element 110 of the memory cell 100 is connected to the wiring 101 via the contact layer 103, and is connected to the selection element 120 via the contact layer 104. The drain of the selection element 120 is connected to the contact layer 104, and the source is connected to the source line SL. The gate of the selection element 120 is connected to the word line WL. The contact layer 103 is connected to the wiring 101 that constitutes the bit line BL. By applying an on-voltage to the word line WL, the selection element 120 becomes conductive, allowing a voltage to be applied to the magnetoresistive element 110.

[0035] 3, the magnetoresistive element 110 of the memory cell 100 is connected to the wiring 102 via the contact layer 104, for example, and to the selection element 120 via the contact layer 103. The drain of the selection element 120 is connected to the bit line BL, and its source is connected to the contact layer 103. The gate of the selection element 120 is connected to the word line WL. The contact layer 104 is connected to the wiring 102 that constitutes the source line SL. By applying an on-voltage to the word line WL, the selection element 120 becomes conductive, allowing a voltage to be applied to the magnetoresistive element 110.

[0036] As described above, the bit line BL is connected to the bit line control circuit 27 (see FIG. 1). The word line WL is connected to the word line control circuit 29 (see FIG. 1). The source line SL is connected to the sense amplifier 30 (see FIG. 1). By applying a voltage between the bit line BL and the source line SL and also applying an on-voltage to the word line WL to make the selection element 120 conductive, a voltage for writing or reading can be applied to the magnetoresistive element 110.

[0037] <1-3. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view showing a configuration example of the memory cell array 11 according to this embodiment. This figure is a schematic diagram showing a configuration example of a part of the memory cell array 11.

[0038] As shown in FIG. 4, the memory cell array 11 is provided with a plurality of magnetoresistive elements 110 and a plurality of bias layers 200 .

[0039] Each of the magnetoresistive elements 110 has a reference layer 111, a tunnel barrier layer 112, a memory layer 113, a spacer layer 114, and a flux guide layer 115. In the example of Fig. 4, the reference layer 111, the tunnel barrier layer 112, the memory layer 113, the spacer layer 114, and the flux guide layer 115 are stacked in this order to form the magnetoresistive element 110. In the example of Fig. 4, the contact layer 103 may be referred to as an upper via, and the contact layer 104 may be referred to as a lower via.

[0040] Each bias layer 200 is provided between adjacent magnetoresistive elements 110, for example, between adjacent memory layers 113. The bias layer 200 is a ferromagnetic bias layer (hard bias layer) that applies a bias magnetic field to the magnetoresistive element 110. The bias layer 200 applies a bias magnetic field, for example, in an in-plane direction (horizontal direction). The bias layer 200 is made of a ferromagnetic body (ferromagnetic material). For example, a hard magnetic body can be used as the ferromagnetic body. The hard magnetic body includes, for example, Co, Fe, Pt, Pd, Cr, Ir, Sm, Nd, etc.

[0041] The reference layer 111 is a layer that has magnetic anisotropy and an invariable magnetization direction. This reference layer 111 is also referred to as, for example, a pinned layer or a magnetization pinned layer. The reference layer 111 may be composed of, for example, CoFeB, a CoFeC alloy, a NiFeB alloy, or a NiFeC alloy. The reference layer 111 may also be composed of, for example, a laminated ferri-pinned structure in which multiple ferromagnetic layers are stacked with a nonmagnetic layer interposed therebetween. Materials for the ferromagnetic layers that constitute the reference layer 111 of this laminated ferri-pinned structure can include, for example, Co, CoFe, CoFeB, Ni, Pd, and Pt. Materials for the nonmagnetic layers can include, for example, Ru, Re, Ir, and Os.

[0042] Furthermore, the reference layer 111 may have a fixed magnetization direction by utilizing antiferromagnetic coupling between an antiferromagnetic layer and a ferromagnetic layer. Examples of materials that can be used for the antiferromagnetic layer include magnetic materials such as FeMn alloys, PtMn alloys, PtCrMn alloys, NiMn alloys, IrMn alloys, NiO, and Fe2O3. Nonmagnetic elements such as Ag, Cu, Au, Al, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Hf, Ir, W, Mo, and Nb can also be added to these magnetic materials.

[0043] The tunnel barrier layer 112 is an insulating layer disposed adjacent to the memory layer 113. This tunnel barrier layer 112 imparts a voltage-controlled magnetic anisotropy effect, for example, by applying an electric field to the memory layer 113. The tunnel barrier layer 112 may be composed of, for example, an oxide of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba, or a nitride of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. The tunnel barrier layer 112 may also be composed of an insulator, dielectric, or semiconductor, such as MgF2, CaF, SrTiO2, AlLaO3, or AlNO. A stacked structure of these layers may also be used.

[0044] The memory layer 113 is a layer that has magnetic anisotropy and a variable magnetization direction. This memory layer 113 is also referred to as a free layer, for example. The states in which the magnetization direction of the memory layer 113 is the same as and different from the magnetization direction of the reference layer 111 are called a parallel state and an antiparallel state, respectively. The magnetoresistive element 110 is in a low resistance state when in the parallel state, and in a high resistance state when in the antiparallel state. As described above, the magnetization direction of the memory layer 113 can be changed by applying a voltage to the magnetoresistive element 110. The memory layer 113 is, for example, a layer that has a VCMA effect.

[0045] The memory layer 113 may also be composed of, for example, cobalt iron (CoFe), cobalt iron boron (CoFeB), Fe, iron boride (FeB), or the like. The memory layer 113 may also be composed of, for example, transition metals (Hf, Ta, W, Re, Ir, Pt, Au, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Ti, V, Cr, Mn, Ni, Cu), or the like. The memory layer 113 may also include, for example, nitrides or oxides. Materials that induce proximity magnetic moments in magnetic materials include, for example, iridium (Ir) and osmium (Os). The voltage-controlled magnetic anisotropy effect can also be improved by adding heavy metals to the memory layer 113.

[0046] The storage layer 113 may also have a laminated structure in which multiple ferromagnetic layers are stacked with a nonmagnetic layer interposed therebetween. In this case, two adjacent ferromagnetic layers may be exchange-coupled via the nonmagnetic layer. The nonmagnetic layer may be composed of, for example, Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, Ba, W, Re, Ir, Pt, Au, Nb, Mo, Ru, Rh, Pd, Ag, V, Mn, Ni, or Cu.

[0047] The spacer layer 114 is a layer that prevents magnetic coupling between the memory layer 113 and the flux guide layer 115. This spacer layer 114 is formed of, for example, a non-magnetic material. Note that, as the material of the spacer layer 114, various materials that can prevent magnetic coupling between the memory layer 113 and the flux guide layer 115 can be used in addition to non-magnetic materials.

[0048] The flux guide layer 115 is a soft magnetic layer that absorbs magnetic flux. The flux guide layer 115 is formed of a soft magnetic body (soft magnetic material). Examples of soft magnetic bodies include Ni, Fe, Co, Mn, Al, Si, Mo, V, and B. The flux guide layer 115 is easily magnetized when a magnetic field is applied and easily returns to its original state when the magnetic field is removed, i.e., it is a layer with high magnetic permeability. The flux guide layer 115 absorbs the magnetic flux generated from the ferromagnetic bias layer 200, thereby reducing the bias magnetic field applied to the magnetoresistive element 110. This eliminates the need to reduce the magnetic field itself generated by the ferromagnetic bias layer 200.

[0049] The various layers described above can be fabricated by, for example, a physical vapor deposition (PVD) method such as sputtering, ion beam deposition, or vacuum evaporation, or a chemical vapor deposition (CVD) method such as atomic layer deposition (ALD). These layers can be patterned by reactive ion etching (RIE) or ion milling. It is preferable to form the various layers consecutively in a vacuum chamber, followed by patterning.

[0050] Data (e.g., 0 or 1) is written to the memory cell 100 by switching the resistance state (resistance value) of the magnetoresistive element 110 between a low resistance state (low resistance value) and a high resistance state (high resistance value). The low resistance state is a state in which the magnetization of the reference layer 111 and the magnetization of the storage layer 113 are parallel to each other, and the high resistance state is a state in which the magnetization of the reference layer 111 and the magnetization of the storage layer 113 are antiparallel to each other. For example, by reversing the magnetization direction of the storage layer 113 between the positive direction of the Z-axis and the negative direction of the Z-axis, the resistance state of the magnetoresistive element 110 can be switched between a low resistance state and a high resistance state. For example, data corresponding to the low resistance state is 0, and data corresponding to the high resistance state is 1. The magnetoresistive element 110 is an MTJ element that can reverse the magnetization of the storage layer 113 by utilizing, for example, the VCMA effect.

[0051] As mentioned above, the basic structure of the magnetoresistive element 110 is a sandwich structure in which a non-magnetic insulating thin film is sandwiched between two magnetic thin films. This structure is called a magnetic tunnel junction (MTJ). Because the non-magnetic thin film is very thin, only a few nanometers thick, a tunnel current flows when a voltage is applied to both ends of the element. The magnitude of this tunnel current is characterized by its dependence on the relative angle between the magnetizations of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect. In MRAM, the magnetization of one of the two magnetic layers (reference layer 111) is fixed, and the magnetization of the other magnetic layer (storage layer 113) is controlled by an external field. Examples of external fields used to control the magnetization direction include methods that utilize magnetic anisotropy control using voltage. The TMR effect is used to read the state.

[0052] <1-4. Write Operation Example of VC-MRAM> A write operation example of the VC-MRAM according to this embodiment will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining a write operation example of the VC-MRAM according to this embodiment.

[0053] The storage layer 113 has perpendicular magnetic anisotropy. As shown in FIG. 5, (a) in the standby state (timing T1 with respect to the applied voltage), magnetic energy A1 is most stable in two directions (initial direction S and reverse direction E) for the magnetization. Because an energy barrier A2 exists at the angle between these two directions, nonvolatile data retention is possible even when the voltage is turned off. (b) When a write voltage is applied (timing T2 with respect to the applied voltage), the energy barrier A2 is removed by voltage modulation of magnetic anisotropy (VCMA) under the application of an in-plane magnetic field Hext, causing the magnetization of the storage layer 113 to begin precessing with the applied magnetic field direction as the precession axis. (c) After writing (timing T3 with respect to the applied voltage), the write is completed by turning off the voltage when the magnetization faces the reverse direction E. The in-plane magnetic field Hext is applied to the magnetoresistive element 110 by the bias layer 200.

[0054] In the example of Figure 5, for convenience of explanation, an XYZ coordinate system (with the Y axis perpendicular to the paper surface) is shown. The X-axis direction and Y-axis direction correspond to the plane directions of the layers of the magnetoresistive element 110 having the aforementioned stacked structure. The X-axis direction, Y-axis direction, and XY plane direction may also be referred to as the horizontal direction. The Z-axis direction corresponds to the direction perpendicular to the plane directions of the layers of the magnetoresistive element 110 (stacking direction). The Z-axis direction may also be referred to as the vertical direction.

[0055] <1-5. Control Example of In-Plane Magnetic Field> A control example of the in-plane magnetic field Hext according to this embodiment will be described with reference to Figs. 6 to 8. Fig. 6 is a diagram showing a formula for the precession period and a graph showing the relationship between the in-plane magnetic field Hext and the precession period according to this embodiment. Fig. 7 is a diagram showing a graph showing the relationship between the in-plane magnetic field Hext and the precession period and a parameter set according to this embodiment. In the example of Fig. 7, α = 0.01.

[0056] The reversal time required for writing is determined by the precession period of the magnetization. Therefore, the precession period τ is expressed by the mathematical formula B1 as shown in FIG. 6. In the example of FIG. 6, α, γ, μ ０are the damping constant, gyromagnetic ratio, and magnetic permeability, respectively. The relationship between the in-plane magnetic field Hext and the precession period τ using this formula B1 is shown in graph B2, as shown in Figure 6. This graph B2 shows the results for three different damping constant values ​​(α = 0.1, 0.05, 0.01). It can be seen that within a realistic range of damping constants, the reversal time is almost independent of the damping constant and overlaps under all conditions. Therefore, the reversal time is determined only by the magnitude of the in-plane magnetic field Hext.

[0057] However, it is difficult to apply a uniform in-plane magnetic field Hext to the entire magnetoresistive element 110, and variations of several Oe are expected to occur for each bit. For this reason, considering a region of about 10 ns where the pulse width can be controlled with precision, as shown in Figure 7, the precession period τ (reversal time) varies greatly with a change of several Oe in the in-plane magnetic field Hext. In this case, the write error rate (WER) does not decrease.

[0058] 8 is a diagram showing the pulse width dependency of the write error rate under each application condition of the in-plane magnetic field Hext according to this embodiment. In the example of FIG. 8, the calculation result when the in-plane magnetic field Hext is set to 100 Oe, which is relatively easy to control accurately, is plotted by white triangles. The calculation result when the in-plane magnetic field Hext is reduced to 60 Oe is plotted by black triangles. The calculation result when the in-plane magnetic field Hext is reduced to 35 Oe is plotted by white squares. The calculation result when the in-plane magnetic field Hext is reduced to 22 Oe is plotted by white circles. The calculation result when the in-plane magnetic field Hext is reduced to 17 Oe is plotted by black circles.

[0059] 8, in the results plotted by the white triangles when the in-plane magnetic field Hext=100 Oe, the precession period becomes shorter, and the window C1 where the write error rate decreases becomes narrower around 1 to 2 ns on the horizontal axis. Furthermore, it can be seen that the second and third successful write periods occur around 5 to 6 ns and 9 ns on the horizontal axis, but the window C1 where the write error rate decreases becomes gradually narrower, making it difficult to ensure a margin.

[0060] The results of the plot of the white circles for an in-plane magnetic field Hext = 22 Oe show that the window C2 in which the write error rate decreases is wide in the region of 6 to 10 ns on the horizontal axis. The window width at WER = 1e-4 is about 4 ns, four times wider than the approximately 1 ns at an in-plane magnetic field Hext = 100 Oe. However, as shown in the results of the plot of the black circles for an in-plane magnetic field Hext = 17 Oe, the WER curve shifts by about 2 ns when the in-plane magnetic field Hext is reduced by just 5 Oe from 22 Oe to 17 Oe (see arrow C3), so a method for accurately controlling the small in-plane magnetic field Hext is required.

[0061] Here, one possible method for applying an in-plane bias magnetic field is to introduce a ferromagnetic bias layer 200. When introducing this ferromagnetic bias layer 200, in order to reduce the bias magnetic field to, for example, less than 20 Oe, it is necessary to make the ferromagnetic bias layer 200 (e.g., a magnet for generating the bias magnetic field) small or thin. However, this increases the variation in the bias magnetic field due to variations in the processed shape, film roughness, nonuniformity within the wafer surface, etc., and therefore increases the number of write error bits under a single write condition.

[0062] Therefore, according to the present embodiment, a technology is provided for precisely applying a small external magnetic field to the storage layer 113 while suppressing its variation in order to ensure a write window (write window) for the voltage-anisotropy modulation-type magnetoresistive element 110. It is difficult to precisely control a small external magnetic field while suppressing its variation by simply applying a magnetic field using the ferromagnetic bias layer 200. Therefore, instead of reducing the magnetic field generated by the ferromagnetic bias layer 200 itself, a soft magnetic material with high magnetic permeability is placed near the storage layer 113 as a flux guide layer 115. This allows the flux guide layer 115 to absorb most of the magnetic flux generated by the ferromagnetic bias layer 200, thereby reducing the magnetic field applied to the storage layer 113 and its variation. Furthermore, the flux guide layer 115 also serves as a magnetic shield, thereby improving resistance to magnetic noise sources such as geomagnetism and electromagnetic waves and increasing reliability.

[0063] As described above, according to this embodiment, by introducing the flux guide layer 115 with high magnetic permeability and having this flux guide layer 115 absorb the magnetic flux generated from the ferromagnetic bias layer 200, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110. Furthermore, since it is not necessary to reduce the magnetic field itself generated from the ferromagnetic bias layer 200, it is possible to increase the size of the ferromagnetic bias layer 200, thereby reducing the variation in the bias magnetic field. Furthermore, by adding the flux guide layer 115 to the stacked structure of the magnetoresistive element 110, it is possible to integrate the fabrication process and eliminate the need for an additional step.

[0064] <1-6. Example of Write Processing> An example of the write processing according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a diagram showing an example of a flowchart of the write processing according to this embodiment.

[0065] The control circuit 22 (for example, a state machine included in the control circuit 22) controls the write process. The flowchart starts when a write command and write data are input from the I / O 21 to the control circuit 22. For convenience, data corresponding to a low resistance state is 0, and data corresponding to a high resistance state is 1.

[0066] 9, in step S11, an initial read is performed. In step S12, the read data is compared with the write data. In step S13, it is determined whether the read data matches the write data. If it is determined that the read data matches the write data (Yes in step S13), the process ends.

[0067] On the other hand, if it is determined in step S13 that the read data does not match the write data (No in step S13), a write voltage is applied to the selected cell (selected memory cell 100) in step S14. A verify read is performed in step S15, and the process returns to step S12. Thereafter, the processes from step S12 onward are executed again.

[0068] 9, the number of times the verify read is repeated is not set, but it is also possible to set a maximum number of times it is repeated in advance. Also, the process may be terminated without performing the verify read.

[0069] <1-7. Example of Timing Chart of Write Process> An example of a timing chart of the write process according to this embodiment will be described with reference to Fig. 10. Fig. 10 is a diagram showing an example of a timing chart of the write process according to this embodiment.

[0070] 10, the read start signal and the write start signal are generated by the control circuit 22. The bit line control signal is generated by the bit line control circuit 27, and the word line control signal is generated by the word line control circuit 29. The bit line BL and the word line WL are selected by the bit line address decoder 26 and the word line address decoder 28.

[0071] The applied voltage is generated by the voltage generation circuit 23 and becomes the input voltage to the sense amplifier 30 during readout. Note that the example in Fig. 10 schematically shows the difference between the high resistance state (High) and the low resistance state (Low) when a voltage is applied to the magnetoresistive element 110, and the actual signal response is not limited to the example in Fig. 10.

[0072] The sense amplifier control signal is generated by the control circuit 22 as a signal for controlling the timing of determining read data. The sense amplifier 30 determines whether the resistance state of the magnetoresistive element 110 was a high resistance state (High) or a low resistance state (Low), and outputs the result to the control circuit 22. The control circuit 22 compares the result to determine whether it matches the write data.

[0073] Next, the operation will be described in chronological order.

[0074] When the control circuit 22 outputs a read start signal and an address to the bit line address decoder 26 and the word line address decoder 28, the bit line address decoder 26 and the word line address decoder 28 decode the address and turn on the bit line control signal and word line control signal corresponding to the corresponding bit line BL and word line WL.

[0075] Next, the voltage generation circuit 23 generates a read voltage, and the read circuit 25 applies the read voltage to the target bit line BL. The read voltage changes to High or Low depending on whether the magnetoresistive element 110 is in a high resistance state or a low resistance state. After the read voltage is determined, the sense amplifier control signal is turned on, and the read result is output from the sense amplifier 30.

[0076] The control circuit 22 compares the write data with the read data, and if the data match, ends the process. If the data do not match, it turns on the write signal. The example in Figure 10 shows a case where the data do not match. With the corresponding bit line control signal and word line control signal turned on, the write circuit 24 applies a write voltage to the target bit line BL. The control circuit 22 then performs a verify read, and if the read data matches the write data, it ends the process.

[0077] Note that the control of the verify read and the control of the initial read may be the same, and the read voltage may be different between the control of the verify read and the control of the initial read. The example of Fig. 10 shows an example in which writing is successful with one voltage application, but if it fails, the write voltage may be applied again. Furthermore, the write control is not limited to the example of Fig. 10. Various start signals may not be necessary depending on the circuit design, and the timing of controlling the bit line BL and the word line WL is arbitrary.

[0078] 9 and 10 show examples of writing, but any reading method can be applied to reading. The flowchart and timing chart for reading are part of FIGS. 9 and 10, and therefore will not be described here.

[0079] <2. Second Embodiment> <2-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 4), but differences therebetween will be described.

[0080] 11 , in this embodiment, the stacking order of the magnetoresistive element 110 is different from that of the first embodiment. In the example of Fig. 11 , the flux guide layer 115, the spacer layer 114, the memory layer 113, the tunnel barrier layer 112, and the reference layer 111 are stacked in this order to form the magnetoresistive element 110.

[0081] In this embodiment, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and to reduce variations in the bias magnetic field. Furthermore, as in the first embodiment, by adding a flux guide layer 115 to the stacked structure of the magnetoresistive element 110, it is possible to integrate the fabrication process and eliminate the need for an additional step.

[0082] <3. Third Embodiment> <3-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 12. Fig. 12 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 4), but differences therebetween will be described.

[0083] 12 , in this embodiment, a bias layer 200 is incorporated into the magnetoresistive element 110. That is, the magnetoresistive element 110 has the bias layer 200. This bias layer 200 is provided on the flux guide layer 115 via a spacer layer 116. In the example of FIG. 12 , the planar area (horizontal area) of the contact layer 103 is larger than the planar area of ​​the magnetoresistive element 110.

[0084] The spacer layer 116 is a layer that does not magnetically couple the flux guide layer 115 and the bias layer 200. The spacer layer 116 is formed of, for example, a non-magnetic material. Note that, as the material of the spacer layer 116, various materials that can prevent the flux guide layer 115 and the bias layer 200 from being magnetically coupled, other than the non-magnetic material, can be used.

[0085] According to this embodiment, by adding the bias layer 200 to the stacked structure of the magnetoresistive element 110, the processing process can be integrated, eliminating the need for additional steps. For example, it is no longer necessary to embed the bias layer 200 between the magnetoresistive elements 110. Note that, in this embodiment as well, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce the variation in the bias magnetic field.

[0086] <4. Fourth Embodiment> <4-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 13. Fig. 13 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 4), but differences therebetween will be described.

[0087] As shown in Fig. 13, in this embodiment, the contact layer 103 has a flux guide layer 115. This makes it possible to arbitrarily determine the planar shape of the contact layer 103, i.e., the flux guide layer 115, independently of the magnetoresistive element 110, thereby enhancing the magnetic flux absorption effect. Examples of the shape of this flux guide layer 115 will be described later. In the example of Fig. 13, the planar area (horizontal area) of the contact layer 103 is larger than the planar area of ​​the magnetoresistive element 110.

[0088] In the example of Figure 13, a part of the contact layer 103 is made of a soft magnetic material, and a flux guide layer 115 is provided on the contact layer 103, but for example, the entire contact layer 103 may be made of a soft magnetic material, and the contact layer 103 may serve as the flux guide layer 115.

[0089] <4-2. Shape Examples of Flux Guide Layer> Shape examples of the flux guide layer 115 according to this embodiment will be described with reference to Fig. 14 to Fig. 17. Each of Fig. 14 to Fig. 17 is a plan view showing an example of the shape of the flux guide layer 115 according to this embodiment.

[0090] 14 to 17 show the planar shape (shape in plan view) of the flux guide layer 115, but the planar shape of the contact layer 103 is also the same as the planar shape of the flux guide layer 115.

[0091] As shown in Fig. 14, the planar shape of the flux guide layer 115 is formed into a rectangular shape. The rectangular flux guide layer 115 extends in the direction in which the bias layers 200 are arranged. As shown in Fig. 15, the planar shape of the flux guide layer 115 is formed into an elliptical shape. The elliptical flux guide layer 115 extends in the direction in which the bias layers 200 are arranged. As shown in Fig. 16, the planar shape of the flux guide layer 115 is formed into a circular shape. Furthermore, as shown in Fig. 17, the planar shape of the flux guide layer 115 is formed into a triangular shape.

[0092] According to such an example of the shape of the flux guide layer 115, it is possible to form the planar shape of the flux guide layer 115 into various shapes. Therefore, the flux guide layer 115 can be processed into various shapes that allow the magnetic field applied to the memory layer 113 to be controlled with higher precision.

[0093] The relative arrangement of the flux guide layer 115 and the bias layer 200 is not limited to that shown in the figure. For example, the flux guide layer 115 and the bias layer 200 do not necessarily need to be electrically connected, and the arrangement of the flux guide layer 115 and the bias layer 200 may be shifted in the in-plane direction or the perpendicular direction (direction perpendicular to the in-plane direction). In other words, the arrangement of the flux guide layer 115 and the bias layer 200 has a degree of freedom in the in-plane direction and the perpendicular direction. This allows for an arrangement that allows for more accurate control of the magnetic field applied to the memory layer 113.

[0094] 4-3. Example of Memory Cell Layout An example of the layout of the memory cells 100 according to this embodiment will be described with reference to Fig. 18. Fig. 18 is a perspective view showing an example of the layout of the memory cells 100 according to this embodiment.

[0095] 18, in this embodiment, as in the first embodiment, the memory cells 100 are arranged in a matrix. Each of these memory cells 100 is connected to a bit line BL, a source line SL, and a word line WL. Each of the magnetoresistive elements 110 is connected to the bit line BL via a contact layer 103. This contact layer 103 has the flux guide layer 115 as described above.

[0096] As described above, the relative arrangement of the flux guide layer 115 and the bias layer 200 is not limited to that shown in the figure. For example, the flux guide layer 115 and the bias layer 200 do not necessarily need to be electrically connected, and the arrangement of the flux guide layer 115 and the bias layer 200 may be shifted in the in-plane direction or the perpendicular direction. In other words, as described above, the arrangement of the flux guide layer 115 and the bias layer 200 has a degree of freedom in the in-plane direction and the perpendicular direction. This allows for an arrangement that allows for more accurate control of the magnetic field applied to the memory layer 113.

[0097] According to this embodiment, by providing the flux guide layer 115 as part of the contact layer 103, the planar shape of the flux guide layer 115 can be determined arbitrarily, independently of the magnetoresistive element 110. This makes it possible to process the flux guide layer 115 into various shapes that can more accurately control the magnetic field applied to the memory layer 113, thereby enhancing the effect of absorbing magnetic flux. Note that, in this embodiment as well, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce variations in the bias magnetic field.

[0098] <5. Fifth Embodiment> <5-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 19. Fig. 19 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the fourth embodiment (see Fig. 13), but differences therebetween will be described.

[0099] 19 , in this embodiment, the cross-sectional shape of the flux guide layer 115 is formed, for example, in a U-shape. This flux guide layer 115 is laminated on the spacer layer 114 so as to cover the entire outer circumferential surface of the spacer layer 114 and a part of the outer circumferential surface of the memory layer 113 without contacting the spacer layer 114. More specifically, the flux guide layer 115 extends along the outer circumferential surfaces of the spacer layer 114 and the memory layer 113 while being spaced apart from the outer circumferential surfaces of the spacer layer 114 and the memory layer 113. As a result, the flux guide layer 115 covers the entire outer circumferential surface of the spacer layer 114 and a part of the outer circumferential surface of the memory layer 113 without contacting the spacer layer 114.

[0100] According to this embodiment, the flux guide layer 115 is formed so as to cover a part of the outer peripheral surface of the memory layer 113 in a non-contact manner. This makes it possible to increase the absorption of magnetic flux by the flux guide layer 115, thereby enabling precise control of the minute magnetic field. Note that, in this embodiment as well, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce the variation in the bias magnetic field.

[0101] <6. Sixth Embodiment> <6-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 20. Fig. 20 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the fifth embodiment (see Fig. 19), but differences therebetween will be described.

[0102] 20 , in this embodiment, the cross-sectional shape of the flux guide layer 115 is formed, for example, in a C-shape. This flux guide layer 115 is laminated on the spacer layer 114 so as to cover the entire outer circumferential surface of the spacer layer 114 and the entire outer circumferential surface of the memory layer 113 without contacting them. More specifically, the flux guide layer 115 extends along the outer circumferential surfaces of the spacer layer 114 and the memory layer 113 while being spaced apart from the outer circumferential surfaces of the spacer layer 114 and the memory layer 113, and protrudes toward the outer circumferential surface of the memory layer 113. As a result, the flux guide layer 115 covers the entire outer circumferential surface of the spacer layer 114 and the entire outer circumferential surface of the memory layer 113 without contacting them.

[0103] According to this embodiment, it is possible to control the minute magnetic field with high precision, as in the fifth embodiment. Note that, also in this embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce the variation in the bias magnetic field, as in the first embodiment.

[0104] <7. Seventh Embodiment> <7-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 21. Fig. 21 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the third embodiment (see Fig. 12), but differences therebetween will be described.

[0105] 21 , in this embodiment, the contact layer 103 has a flux guide layer 115, a spacer layer 116, and a bias layer 200. This makes it possible to arbitrarily determine the planar shape of the contact layer 103, i.e., the flux guide layer 115, independently of the magnetoresistive element 110, thereby enhancing the effect of absorbing magnetic flux.

[0106] According to this embodiment, similar to the fourth embodiment, it is possible to enhance the magnetic flux absorption effect by arbitrarily determining the planar shape of the flux guide layer 115. Note that, similar to the first embodiment, this embodiment also makes it possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and to reduce variations in the bias magnetic field.

[0107] <8. Eighth Embodiment> <8-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 22. Fig. 22 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the fourth embodiment (see Fig. 13), but differences therebetween will be described.

[0108] As shown in Figure 22, in this embodiment, the contact layer 103 is composed of a flux guide layer 115 and an antiferromagnetic layer 210. The antiferromagnetic layer 210 is stacked on the flux guide layer 115. This antiferromagnetic layer 210 is made of an antiferromagnetic material. The flux guide layer 115 and the antiferromagnetic layer 210 apply a magnetic field to the magnetoresistive element 110. Therefore, the bias layer 200 is not required. In the example of Figure 22, the bias layer 200 is not present.

[0109] According to this embodiment, the contact layer 103 has a flux guide layer 115 and an antiferromagnetic layer 210. As a result, an exchange bias is applied to the flux guide layer 115 from the antiferromagnetic layer 210, so that the magnetization direction is fixed and a bias magnetic field is applied to the memory layer 113. Therefore, the bias layer 200 is not necessary, and the magnetic field applied to the magnetoresistive element 110 can be reduced. Furthermore, by adjusting the flux guide layer 115 and the antiferromagnetic layer 210, it is possible to reduce variations in the bias magnetic field. Note that in this embodiment as well, as in the fourth embodiment, the planar shapes of the flux guide layer 115 and the antiferromagnetic layer 210 can be arbitrarily determined, thereby enhancing the effect of absorbing magnetic flux.

[0110] <9. Ninth Embodiment> <9-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 23. Fig. 23 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the eighth embodiment (see Fig. 22), but differences therebetween will be described.

[0111] 23 , in this embodiment, the cross-sectional shape of the flux guide layer 115 is formed, for example, in a C-shape. As in the sixth embodiment (see FIG. 20 ), this flux guide layer 115 is provided so as to cover the entire outer circumferential surface of the spacer layer 114 and the entire outer circumferential surface of the memory layer 113 in a non-contact manner (see the sixth embodiment for details).

[0112] According to this embodiment, as in the eighth embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce the variation in the bias magnetic field. Also, as in the fourth embodiment, it is possible to arbitrarily determine the planar shapes of the flux guide layer 115 and the antiferromagnetic layer 210, thereby enhancing the effect of absorbing magnetic flux. Also, as in the sixth embodiment, it is possible to precisely control the minute magnetic field.

[0113] <10. Tenth Embodiment> <10-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 4), but differences therebetween will be described.

[0114] 24, the flux guide layer 115 functions as a wiring (for example, the wiring 101). That is, the flux guide layer 115 is provided in place of the wiring 101 according to the first embodiment. In this case, the flux guide layer 115 can be implemented simply by replacing the electrode material of the wiring 101 with a soft magnetic material.

[0115] 10-2. Example of Memory Cell Layout An example of the layout of the memory cells 100 according to this embodiment will be described with reference to Fig. 25. Fig. 25 is a perspective view showing an example of the layout of the memory cells 100 according to this embodiment.

[0116] 18 , in this embodiment, as in the first embodiment, the memory cells 100 are arranged in a matrix. Each of these memory cells 100 is connected to a bit line BL, a source line SL, and a word line WL. The bit line BL is formed by a flux guide layer 115. Each of the magnetoresistive elements 110 is connected to the bit line BL via a contact layer 103.

[0117] Here, it is desirable that the contact layer 103 be made of a non-magnetic material to avoid magnetic coupling. In this case, it is particularly desirable that the direction of the bias magnetic field generated by the bias layer 200 is parallel to the longitudinal direction of the bit line BL.

[0118] According to this embodiment, the flux guide layer 115 is provided with a wiring function, thereby facilitating the mounting of the flux guide layer 115. Note that, in this embodiment, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and the variation in the bias magnetic field.

[0119] <11. Eleventh Embodiment> <11-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 26. Fig. 26 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the fourth embodiment (see Fig. 13), but differences therebetween will be described.

[0120] 26, in this embodiment, a bias layer 200 is laminated on each contact layer 103. This bias layer 200 is provided in common to each magnetoresistive element 110. This eliminates the need for additional processing steps, and makes it possible to implement the bias layer 200 simply by changing the film formation material.

[0121] According to this embodiment, the bias layer 200 is shared by each magnetoresistive element 110, thereby facilitating the implementation of the bias layer 200. Note that, in this embodiment, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and to reduce variations in the bias magnetic field.

[0122] <12. Twelfth Embodiment> <12-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 27. Fig. 27 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 4), but differences therebetween will be described.

[0123] 27, in this embodiment, the contact layer 104 has a flux guide layer 115. In this case, too, the contact layer 104, that is, the flux guide layer 115, can be deformed, similarly to the fourth embodiment (see FIG. 13).

[0124] According to this embodiment, similar to the fourth embodiment, it is possible to enhance the magnetic flux absorption effect by arbitrarily determining the planar shape of the flux guide layer 115. Note that, similar to the first embodiment, this embodiment also makes it possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and to reduce variations in the bias magnetic field.

[0125] <13. Thirteenth Embodiment> <13-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 28. Fig. 28 is a cross-sectional view showing the configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the first embodiment (see Fig. 4), but differences therebetween will be described.

[0126] 28 , in this embodiment, an encapsulation layer 220 is provided. That is, the memory system D1 including the magnetoresistive elements 110, the wirings 101 and 102, and the bias layers 200 is sealed by the encapsulation layer 220. For example, an insulating material can be used as the encapsulation layer 220. A flux guide layer 115 is laminated on the encapsulation layer 220.

[0127] According to this embodiment, by providing the flux guide layer 115 outside the memory system D1, not only is the process for forming the flux guide layer 115 easier to perform, but the influence of its formation on existing processes can be minimized. Note that, in this embodiment as well, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce variations in the bias magnetic field.

[0128] <14. Fourteenth Embodiment> <14-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to Fig. 29. Fig. 29 is a cross-sectional view showing a configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the thirteenth embodiment (see Fig. 28), but differences therebetween will be described.

[0129] 29 , in this embodiment, the bias layer 200 is also provided outside the memory system D1 together with the flux guide layer 115. The bias layer 200 is formed in common for each magnetoresistive element 110. The flux guide layer 115 is provided above the wiring 101, and the bias layer 200 is provided above the flux guide layer 115.

[0130] According to this embodiment, by providing the flux guide layer 115 and the bias layer 200 outside the memory system D1, not only is the process for forming the flux guide layer 115 and the bias layer 200 easier to perform, but the influence of their formation on existing processes can be minimized. Note that, in this embodiment as well, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce variations in the bias magnetic field.

[0131] <15. Fifteenth Embodiment> <15-1. Configuration Example of Memory Cell Array> A configuration example of the memory cell array 11 according to this embodiment will be described with reference to FIG. 30. FIG. 30 is a cross-sectional view showing a configuration example of the memory cell array 11 according to this embodiment. This embodiment is basically the same as the fourteenth embodiment (see FIG. 29), but differences therebetween will be described.

[0132] 30 , in this embodiment, a flux guide layer 117 is provided in addition to the flux guide layer 115. The flux guide layer 115 is provided above the memory system D1, and the flux guide layer 117 is provided below the memory system D1. In other words, the flux guide layers 115 and 117 are arranged to sandwich the memory system D1 without contacting each other.

[0133] According to this embodiment, by forming the flux guide layers 115 and 117 on the top and bottom of the outside of the memory system D1 and sandwiching the memory system D1, it is possible to weaken the bias magnetic field between the flux guide layers 115 and 117 and make the spatial distribution of the bias magnetic field uniform. Note that, in this embodiment as well, as in the first embodiment, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and reduce the variation in the bias magnetic field.

[0134] <16. Actions and Effects of Each Embodiment> As described above, according to each embodiment, the storage device 10 includes a magnetoresistive element 110 with a variable resistance value, a ferromagnetic bias layer 200 that applies a magnetic field to the magnetoresistive element 110, and a soft magnetic flux guide layer 115 that absorbs magnetic flux (see, for example, FIGS. 4 and 11 ). As a result, the flux guide layer 115 absorbs the magnetic flux generated from the ferromagnetic bias layer 200, thereby reducing the magnetic field applied to the magnetoresistive element 110. Furthermore, because there is no need to reduce the magnetic field itself generated from the ferromagnetic bias layer 200, it is possible to increase the size of the ferromagnetic bias layer 200, thereby reducing variations in the bias magnetic field.

[0135] Furthermore, the magnetoresistive element 110 may have a flux guide layer 115 (see, for example, FIGS. 4 and 11). This adds the flux guide layer 115 to the stacked structure of the magnetoresistive element 110, making it possible to integrate the fabrication process and eliminate the need for an additional step.

[0136] Moreover, the magnetoresistive element 110 has the flux guide layer 115, and may further have a memory layer 113 whose magnetization direction is variable, and a spacer layer 114 provided between the memory layer 113 and the flux guide layer 115 to prevent magnetic coupling between the memory layer 113 and the flux guide layer 115 (see FIGS. 4 and 11 , etc.). This makes it possible to provide the flux guide layer 115 close to the memory layer 113, thereby reliably reducing the magnetic field applied to the memory layer 113.

[0137] Furthermore, a plurality of magnetoresistive elements 110 and bias layers 200 may be provided, and each of the plurality of bias layers 200 may be provided between adjacent magnetoresistive elements 110 (see, for example, FIGS. 4 and 11 ). This makes it possible to realize a uniform in-plane magnetic field.

[0138] The magnetoresistive element 110 may also have a bias layer 200 (see FIG. 12). This adds the bias layer 200 to the stacked structure of the magnetoresistive element 110, making it possible to integrate the fabrication process and eliminate the need for an additional step.

[0139] Furthermore, the magnetoresistive element 110 has the bias layer 200, and may further have a spacer layer 114 provided between the flux guide layer 115 and the bias layer 200 to prevent magnetic coupling between the flux guide layer 115 and the bias layer 200 (see FIG. 12 ). This makes it possible to provide the flux guide layer 115 close to the bias layer 200, thereby reliably reducing the magnetic field applied to the memory layer 113.

[0140] The memory device 10 further includes a contact layer 103 (or contact layer 104) provided on the magnetoresistive element 110, and the contact layer 103 (or contact layer 104) may have a flux guide layer 115 (see FIGS. 13 and 27). This makes it possible to arbitrarily determine the planar shape of the flux guide layer 115 independently of the magnetoresistive element 110, thereby enhancing the effect of absorbing magnetic flux.

[0141] Furthermore, the flux guide layer 115 in the contact layer 103 may be formed so as to cover part or all of the outer peripheral surface of the magnetoresistive element 110 (e.g., the memory layer 113) without contact (see FIGS. 19 and 20). This allows the flux guide layer 115 to enhance its absorption of magnetic flux.

[0142] Furthermore, the contact layer 103 has a flux guide layer 115, and may further have a bias layer 200 and a spacer layer 116 provided between the flux guide layer 115 and the bias layer 200 to prevent magnetic coupling between the flux guide layer 115 and the bias layer 200 (see FIG. 21). This makes it possible to arbitrarily determine the planar shape of the flux guide layer 115 independently of the magnetoresistive element 110, thereby enhancing the effect of absorbing magnetic flux.

[0143] Furthermore, a plurality of magnetoresistive elements 110 may be provided, and the flux guide layer 115 may be provided in common to the plurality of magnetoresistive elements 110 (see FIG. 24 ). This makes it possible to easily mount the flux guide layer 115.

[0144] Furthermore, the flux guide layer 115 may be wiring (e.g., wiring 101, bit line BL) connected to a plurality of magnetoresistive elements 110 (see FIG. 24 ). This makes it possible to form the flux guide layer 115 in the process of forming the wiring, thereby facilitating the mounting of the flux guide layer 115.

[0145] Moreover, the memory device 10 may further include an encapsulation layer 220 that seals the plurality of magnetoresistive elements 110, and the flux guide layer 115 may be laminated on the encapsulation layer 220 (see FIG. 28 ). This allows the flux guide layer 115 to be provided outside the memory system D1 that includes the magnetoresistive elements 110, etc., which not only reduces the process difficulty of forming the flux guide layer 115 but also minimizes the influence of its formation on existing processes.

[0146] Furthermore, a plurality of magnetoresistive elements 110 may be provided, and the bias layer 200 may be provided in common to the plurality of magnetoresistive elements 110 (see FIG. 26 ). This allows the bias layer 200 to be shared by each of the magnetoresistive elements 110, making it easier to implement the bias layer 200.

[0147] Furthermore, the flux guide layer 115 is provided in common to the plurality of magnetoresistive elements 110, and the storage device 10 may further include an encapsulation layer 220 that encapsulates the plurality of magnetoresistive elements 110, the flux guide layer 115, and the bias layer 200 (see FIGS. 29 and 30 ). As a result, the flux guide layer 115 is provided in common to each of the magnetoresistive elements 110, which not only reduces the process difficulty of forming the flux guide layer 115 but also minimizes the impact of its formation on existing processes.

[0148] Furthermore, the storage device 10 may further include a soft magnetic flux guide layer (second flux guide layer) 117 that absorbs magnetic flux, in addition to the flux guide layer (first flux guide layer) 115 (see FIG. 30 ). This makes it possible to reliably reduce the magnetic field applied to the magnetoresistive element 110.

[0149] Furthermore, the flux guide layers 115 and 117 may be provided so as to sandwich the magnetoresistive element 110 without contacting each other (see FIG. 30 ), thereby weakening the bias magnetic field between the flux guide layers 115 and 117 and making the spatial distribution of the bias magnetic field uniform.

[0150] The bias layer 200 may contain Co, Fe, Pt, Pd, Cr, Ir, Sm, or Nd, and the flux guide layer 115 may contain Ni, Fe, Co, Mn, Al, Si, Mo, V, or B (see FIG. 4, etc.). This makes it possible to reliably reduce the bias magnetic field applied to the magnetoresistive element 110 and the variation in the bias magnetic field.

[0151] The storage device 10 may also include a magnetoresistive element 110 with a variable resistance value, and a soft magnetic flux guide layer 115 and an antiferromagnetic layer 210 that apply a magnetic field to the magnetoresistive element 110 (see FIGS. 22 and 23). As a result, the flux guide layer 115 and the antiferromagnetic layer 210 apply a magnetic field to the magnetoresistive element 110, eliminating the need for the ferromagnetic bias layer 200 and enabling the magnetic field applied to the magnetoresistive element 110 to be reduced. Furthermore, by adjusting the flux guide layer 115 and the antiferromagnetic layer 210, variations in the bias magnetic field can be reduced.

[0152] Furthermore, the planar shape of the flux guide layer 115 in the contact layer 103 may be formed into a rectangular, elliptical, circular, or triangular shape (see FIGS. 14 to 17). This makes it possible to process the flux guide layer 115 into various shapes that can more accurately control the magnetic field applied to the memory layer 113, thereby improving the absorption of magnetic flux by the flux guide layer 115.

[0153] 17. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0154] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific form of distribution and integration of the components and processes is not limited to that shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0155] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0156] For example, the above-described embodiments can be combined to control a small bias magnetic field. The ferromagnetic bias layer 200 is one means for generating a bias magnetic field, and the structure including the flux guide layer 115 is also effective when an external magnetic field is supplied by other means.

[0157] <18. Application Examples> <18-1. Various Devices> An application example of the storage device 10 according to any one of the first to fifteenth embodiments will be described with reference to Fig. 31. Fig. 31 is a diagram showing an application example using the storage device 10 according to any one of the first to fifteenth embodiments.

[0158] The memory device 10 according to any one of the first to fifteenth embodiments described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. For example, as shown in FIG. 31 , the storage device 10 according to any one of the first to fifteenth embodiments described above can be used in, for example, "devices for capturing images for viewing, such as digital cameras and mobile devices with camera functions," "devices for traffic use, such as in-vehicle sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras for monitoring moving vehicles and roads, and distance measuring sensors for measuring distances between vehicles," "devices for home appliances such as TVs, refrigerators, and air conditioners for capturing images of user gestures and operating the device in accordance with the gestures," "devices for medical and healthcare use, such as endoscopes and devices for capturing blood vessel images by receiving infrared light," "devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication," "devices for beauty use, such as skin measuring devices for capturing images of the skin and microscopes for capturing images of the scalp," "devices for sports use, such as action cameras and wearable cameras for sports use," and "devices for agricultural use, such as cameras for monitoring the condition of fields and crops."

[0159] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as an electronic device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). Furthermore, for example, the technology according to the present disclosure may be realized as an electronic device mounted on an endoscopic surgery system, a microsurgery system, or the like.

[0160] <18-2. Imaging Device> An imaging device 300 according to an application example will be described with reference to Fig. 32. Fig. 32 is a diagram showing an example of the configuration of the imaging device 300 according to an application example. This imaging device 300 is an example of an electronic device to which the storage device 10 according to any one of the first to fifteenth embodiments described above is applied. Examples of the imaging device 300 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0161] 32, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 is capable of capturing still images and moving images.

[0162] The optical system 301 includes one or more lenses. The optical system 301 guides light from a subject (incident light) to the image sensor 303, and forms an image on the light receiving surface of the image sensor 303.

[0163] The shutter device 302 is disposed between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light blocking period for the image sensor 303 under the control of the control circuit 304.

[0164] The image sensor 303 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the image sensor 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304. The image sensor 303 may be, for example, a solid-state image sensor.

[0165] The control circuit 304 outputs a drive signal that controls the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302 , thereby driving the image sensor 303 and the shutter device 302 .

[0166] The signal processing circuit 305 performs various signal processing on the signal charges output from the image sensor 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to a monitor 306 and also to a memory 307.

[0167] The monitor 306 displays moving or still images captured by the image sensor 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

[0168] The memory 307 stores image data supplied from the signal processing circuit 305, i.e., image data of moving images or still images captured by the image sensor 303. As the memory 307, for example, the storage device 10 according to any one of the first to fifteenth embodiments described above is used.

[0169] Even in an imaging device 300 configured in this manner, by applying a memory device 10 according to any one of the first to fifteenth embodiments described above as the memory 307, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and to reduce the variation in the bias magnetic field.

[0170] <18-3. Distance Measuring Device> A distance measuring device 400 according to an application example will be described with reference to Fig. 33. Fig. 33 is a diagram showing an example of the configuration of the distance measuring device 400 according to an application example. This distance measuring device 400 is an example of an electronic device to which the storage device 10 according to any one of the first to fifteenth embodiments described above is applied.

[0171] 33, distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an image sensor (solid-state image sensor) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. Distance measuring device 400 projects light from light source unit 401 toward an object and receives light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0172] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0173] The optical system 402 includes one or more lenses. The optical system 402 guides light from a subject (incident light) to the image sensor 403, and forms an image on the light receiving surface (sensor portion) of the image sensor 403.

[0174] The image sensor 403 accumulates signal charges in response to light that is imaged on the light receiving surface via the optical system 402. A distance signal indicating a distance determined from a light receiving signal (APD OUT) output from the image sensor 403 is supplied to a signal processing circuit 405. As the image sensor 403, for example, a solid-state image sensor such as an image sensor is used.

[0175] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the image sensor 403, and the like, thereby driving the light source unit 401, the image sensor 403, and the like.

[0176] The signal processing circuit 405 performs various signal processing on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and also to a memory 407.

[0177] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. The monitor 406 may be, for example, a panel display device such as a liquid crystal panel or an organic EL panel.

[0178] The memory 407 stores image data supplied from the signal processing circuit 405, i.e., image data of the distance image captured by the image sensor 403. As the memory 407, for example, the storage device 10 according to any one of the first to fifteenth embodiments described above is used.

[0179] Even in a distance measuring device 400 configured in this manner, by applying a memory device 10 according to any one of the first to fifteenth embodiments described above as memory 407, it is possible to reduce the bias magnetic field applied to the magnetoresistive element 110 and to reduce the variation in the bias magnetic field.

[0180] As described above, the storage device 10 according to any one of the first to fifteenth embodiments can be implemented in various electronic devices. For example, the storage device 10 according to any one of the first to fifteenth embodiments may be installed in various electronic devices, such as an HDD (hard disk drive), a notebook PC (personal computer), a mobile device (e.g., a smartphone or tablet PC), a PDA (personal digital assistant), a wearable device, a game device, or a music device, in addition to the imaging device 300 or the distance measuring device 400. For example, the storage device 10 may be used as various types of memory, such as storage.

[0181] <19. Supplementary Note> The present technology may also have the following configurations. (1) A storage device comprising: a magnetoresistive element having a variable resistance; a ferromagnetic bias layer that applies a magnetic field to the magnetoresistive element; and a soft magnetic flux guide layer that absorbs magnetic flux. (2) The storage device according to (1), wherein the magnetoresistive element includes the flux guide layer. (3) The storage device according to (2), wherein the magnetoresistive element includes: a memory layer having a variable magnetization direction; and a spacer layer that is provided between the memory layer and the flux guide layer and prevents magnetic coupling between the memory layer and the flux guide layer. (4) The storage device according to any one of (1) to (3), wherein a plurality of the magnetoresistive elements and the bias layers are provided, and each of the plurality of bias layers is provided between adjacent plurality of the magnetoresistive elements. (5) The storage device according to any one of (1) to (4), wherein the magnetoresistive element includes the bias layer. (6) The storage device according to (5), wherein the magnetoresistive element has a spacer layer provided between the flux guide layer and the bias layer, preventing magnetic coupling between the flux guide layer and the bias layer. (7) The storage device according to (1), further comprising a contact layer provided on the magnetoresistive element, the contact layer having the flux guide layer. (8) The storage device according to (7), wherein the flux guide layer is formed so as to cover part or all of the outer circumferential surface of the magnetoresistive element in a non-contact manner. (9) The storage device according to (7) or (8), wherein the contact layer has the bias layer and a spacer layer provided between the flux guide layer and the bias layer, preventing magnetic coupling between the flux guide layer and the bias layer. (10) The storage device according to (1), wherein a plurality of the magnetoresistive elements are provided, and the flux guide layer is provided in common to a plurality of the magnetoresistive elements. (11) The storage device according to (10), wherein the flux guide layer is wiring connected to a plurality of the magnetoresistive elements.(12) The storage device according to (10) or (11), further comprising an encapsulation layer that encapsulates the plurality of magnetoresistive elements, and the flux guide layer is stacked on the encapsulation layer. (13) The storage device according to (1), further comprising a plurality of the magnetoresistive elements, and the bias layer being provided in common to the plurality of magnetoresistive elements. (14) The storage device according to (1), further comprising an encapsulation layer that encapsulates the plurality of magnetoresistive elements, the flux guide layer, and the bias layer being provided in common to the plurality of magnetoresistive elements. (15) The storage device according to (1), further comprising a soft magnetic second flux guide layer that absorbs magnetic flux, the flux guide layer being a first flux guide layer. (16) The storage device according to (15), further comprising a soft magnetic second flux guide layer that absorbs magnetic flux, the first flux guide layer and the second flux guide layer being provided to sandwich the magnetoresistive element in a non-contact manner. (17) The storage device according to any one of (1) to (16), wherein the bias layer contains Co, Fe, Pt, Pd, Cr, Ir, Sm, or Nd, and the flux guide layer contains Ni, Fe, Co, Mn, Al, Si, Mo, V, or B. (18) A storage device comprising: a magnetoresistive element having a variable resistance value; and a soft magnetic flux guide layer and an antiferromagnetic layer that apply a magnetic field to the magnetoresistive element. (19) An electronic device comprising: a storage device having: a magnetoresistive element having a variable resistance value; a ferromagnetic bias layer that applies a magnetic field to the magnetoresistive element; and a soft magnetic flux guide layer that absorbs magnetic flux. (20) An electronic device comprising: a storage device having: a magnetoresistive element having a variable resistance value; and a soft magnetic flux guide layer and an antiferromagnetic layer that apply a magnetic field to the magnetoresistive element. (21) An electronic device comprising the storage device according to any one of (1) to (18).

[0182] 10 Memory device 11 Memory cell array 20 Peripheral circuit 21 I / O 22 Control circuit 23 Voltage generation circuit 24 Write circuit 25 Read circuit 26 Bit line address decoder 27 Bit line control circuit 28 Word line address decoder 29 Word line control circuit 30 Sense amplifier 100 Memory cell 101 Wiring 102 Wiring 103 Contact layer 104 Contact layer 110 Magnetoresistive element 111 Reference layer 112 Tunnel barrier layer 113 Storage layer 114 Spacer layer 115 Flux guide layer 116 Spacer layer 117 Flux guide layer 120 Selection element 200 Bias layer 210 Antiferromagnetic layer 220 Encapsulating layer 300 Imaging device 307 Memory 400 Rangefinder 407 Memory D1 Memory system SL Source line WL Word line

Claims

1. A memory device comprising: a magnetoresistive element having a variable resistance; a ferromagnetic bias layer that applies a magnetic field to the magnetoresistive element; and a soft magnetic flux guide layer that absorbs magnetic flux.

2. The memory device according to claim 1, wherein the magnetoresistive element comprises the flux guide layer.

3. The memory device according to claim 2, wherein the magnetoresistive element has: a memory layer whose magnetization direction is variable; and a spacer layer provided between the memory layer and the flux guide layer for preventing magnetic coupling between the memory layer and the flux guide layer.

4. The memory device according to claim 1, wherein a plurality of said magnetoresistive elements and said bias layers are provided, and each of said plurality of bias layers is provided between adjacent ones of said magnetoresistive elements.

5. The memory device according to claim 1, wherein the magnetoresistive element has the bias layer.

6. The storage device according to claim 5, wherein the magnetoresistance element has a spacer layer provided between the flux guide layer and the bias layer for preventing magnetic coupling between the flux guide layer and the bias layer.

7. The memory device according to claim 1, further comprising a contact layer provided on said magnetoresistive element, said contact layer having said flux guide layer.

8. The storage device according to claim 7, wherein the flux guide layer is formed so as to cover a part or the whole of the outer circumferential surface of the magnetoresistive element in a non-contact manner.

9. The memory device according to claim 7, wherein the contact layer comprises: the bias layer; and a spacer layer provided between the flux guide layer and the bias layer for preventing magnetic coupling between the flux guide layer and the bias layer.

10. The memory device according to claim 1, wherein a plurality of said magnetoresistance elements are provided, and said flux guide layer is provided in common to the plurality of said magnetoresistance elements.

11. The memory device according to claim 10, wherein the flux guide layer is a wiring connected to a plurality of the magnetoresistance elements.

12. The storage device according to claim 10, further comprising an encapsulation layer that encapsulates a plurality of said magnetoresistive elements, said flux guide layer being laminated on said encapsulation layer.

13. The memory device according to claim 1, wherein a plurality of said magnetoresistance elements are provided, and said bias layer is provided in common to the plurality of said magnetoresistance elements.

14. The memory device according to claim 1, further comprising an encapsulation layer that encapsulates the plurality of magnetoresistance elements, the flux guide layer and the bias layer, the flux guide layer being provided in common to a plurality of the magnetoresistance elements.

15. The storage device according to claim 1, wherein the flux guide layer is a first flux guide layer, and further comprising a soft magnetic second flux guide layer that absorbs magnetic flux.

16. The storage device according to claim 15, wherein the first flux guide layer and the second flux guide layer are provided so as to sandwich the magnetoresistance element in a non-contact manner.

17. The memory device according to claim 1, wherein the bias layer includes Co, Fe, Pt, Pd, Cr, Ir, Sm or Nd, and the flux guide layer includes Ni, Fe, Co, Mn, Al, Si, Mo, V or B.

18. A memory device comprising: a magnetoresistive element having a variable resistance; and a soft magnetic flux guide layer and an antiferromagnetic layer that apply a magnetic field to the magnetoresistive element.

19. An electronic device comprising: a memory device having a magnetoresistive element having a variable resistance value; a ferromagnetic bias layer that applies a magnetic field to the magnetoresistive element; and a soft magnetic flux guide layer that absorbs magnetic flux.

20. An electronic device comprising: a memory device, the memory device having: a magnetoresistive element having a variable resistance value; and a soft magnetic flux guide layer and an antiferromagnetic layer that apply a magnetic field to the magnetoresistive element.

Images