Noise shaping SAR-based delta-sigma modulator for wide input signal range and input impedance amplification for bio-signal recording

Abstract

Presented are a noise shaping SAR-based delta-sigma modulator for a wide input signal range and input impedance amplification for bio-signal recording, and an operating method thereof. The noise shaping SAR-based delta-sigma modulator for a wide input signal range and input impedance amplification for bio-signal recording proposed in the present invention comprises: a correlated double sampling integrator that increases CMRR and reduces noise; an input sampling capacitor that samples in advance a previous output of the delta-sigma modulator when reflecting an output of the delta-sigma modulator to an input stage in order to amplify input impedance without additional amplifiers; an inverter-based amplifier that amplifies an input signal in order to acquire the wide input signal range; a noise shaping SAR for increasing the resolution; and a truncation logic that, when reducing bits output from the delta-sigma modulator to predetermined bits, feeding the predetermined bits back, and reflecting the fed bits to an input digital-analog converter, performs noise shaping via the noise shaping SAR in order to reduce a truncation error, and then performs truncation and feeds the truncated result back to the input digital-analog converter.

Description

A delta-sigma modulator based on noise-shaping SAR for wide input signal range and input impedance amplification for biosignal recording.

[0001] The present invention relates to a delta-sigma modulator based on noise-shaping SAR for wide input signal range and input impedance amplification for biosignal recording, and an operating method thereof.

[0002] Recently, interest in implantable and wearable devices for monitoring biosignals has been growing. A number of implantable neural interface devices have been developed to treat patients suffering from incurable diseases. Furthermore, wearable devices are rapidly gaining popularity and are being utilized in various healthcare applications, such as drowsiness and stress detection, using biosignals from wearable in-ear devices. Monitoring representative biosignals, such as the electroencephalogram (EEG), electrocardiogram (ECG), electromyogram (EMG), and local field potential (LFP), can yield the following therapeutic effects and benefits.

[0003] EEG monitoring can help analyze epileptic seizures and brain disorders, and ECG signal monitoring has been proven to provide valuable information on cardiovascular disease. Similarly, EMG signals can be used to detect muscle abnormalities. LFP signals can be effectively used to treat neurological disorders such as Parkinson's disease and epilepsy.

[0004] To properly capture these biosignals, the recording front-end circuit must possess the following characteristics: 1) low noise, 2) low power, 3) high input impedance, and 4) wide dynamic range (DR). Above all, the recording integrated circuit (IC) must have sufficiently low noise, as the signal amplitude is very small, from a few microvolts to tens of millivolts, over a signal frequency range of less than 1 Hz to 500 Hz. At the same time, the recording IC must have low power consumption to ensure long-term operation in implantable and wearable devices, as most devices are powered by small batteries.

[0005] Furthermore, sufficiently high input impedance is essential for stable biosignal recording. Since electrodes are typically required to measure biosignals, electrode impedance must be considered. Electrode impedance is approximately 50kJ-1M at a frequency of 1kHz. Furthermore, if there is a mismatch between electrode impedances, common-mode interference is converted to differential-mode interference, disrupting biosignal recording. To minimize input signal attenuation and common-mode to differential-mode conversion of interference occurring at the electrode-tissue interface, the input impedance of the biosignal acquisition IC must be sufficiently high.

[0006] Finally, DR is also a critical factor in biosignal acquisition circuits, as common-mode artifacts are a significant issue in wearable and implantable devices. Common sources of common-mode artifacts include the wearer's motion and the electrical stimulation of neural implants. These common-mode artifacts can easily couple to the recording channel, saturating it and preventing it from continuously recording biosignals. For example, in closed-loop implantable systems, unwanted simulation artifacts can interfere with and saturate the recording channel. In wearable devices, motions such as head movement and hand waving can generate artifacts in the common-mode voltage of the signal, interfering with signal acquisition in the recording channel. These artifacts can be as large as 100 mVPP and can easily distort the signal in the amplification stage, which typically requires a large amplifier gain. This artifact can saturate the entire recording channel, resulting in a latency of 100 ms or more before it returns to normal operation. To avoid these issues, wide dynamic range (DR) and high common-mode rejection ratio (CMRR) are also required. This ensures stable and continuous recording in wearable and implantable devices, even in the presence of large common-mode artifacts caused by user movement or simultaneous electrical stimulation.

[0007] The technical problem to be achieved by the present invention is to provide a Delta-Sigma Modulator (DSM) with Noise-Shaping (NS)-Successive Approximation (SAR) for high power efficiency and high resolution of an integrated circuit (IC). The first stage integrator of the DSM according to an embodiment of the present invention provides an integrator that supports not only a wide input swing but also high input impedance at low power consumption, an input sampling capacitor for improving the input impedance through a pre-sampling-based charge transfer reduction technique that does not require an additional amplifier, and a technique for implementing fourth-order noise shaping by effectively turning the truncation error into noise form without using an additional loop by feeding the truncation error back to the local NS-SAR loop.

[0008] In one aspect, the delta-sigma modulator based on noise-shaping SAR for amplifying a wide input signal range and input impedance for recording biosignals proposed in the present invention includes a correlated double sampling integrator for increasing CMRR (Common Mode Rejection Ratio) and reducing noise, an input sampling capacitor for pre-sampling a previous output of the delta-sigma modulator when reflecting the output of the delta-sigma modulator to an input terminal to amplify the input impedance without an additional amplifier, an inverter-based amplifier for amplifying the input signal to obtain a wide input signal range, a noise-shaping SAR (Successive Approximation) for increasing resolution, and a truncation logic for performing noise shaping through the noise-shaping SAR to reduce a truncation error when reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter.

[0009] The above input sampling capacitor is integrated in the integration stage, the previous output of the delta-sigma modulator is integrated in the input sampling capacitor, the charge difference between the current input voltage and the previous output is integrated in the feedback capacitor, and in the pre-sampling stage, the input sampling capacitor is pre-sampled by the asynchronous SAR ADC, and in the input sampling stage, the next input voltage is newly charged in the input sampling capacitor.

[0010] The above amplifier uses a current reuse inverter based amplifier that increases the linear input range of the amplifier by not using a cascade stack for improved transconductance (GM) and low power and wide bandwidth.

[0011] The above truncation logic reduces the output bits of the delta-sigma modulator to a predetermined number of bits and feeds them back to the input digital-to-analog converter, thereby feeding back the truncation error and reusing the input digital-to-analog converter to re-perform noise shaping with low power consumption.

[0012] The above noise shaping SAR uses a second-order noise shaping SAR, and the truncation error fed back to the input digital-to-analog converter through the truncation logic is additionally passed through a second-order noise shaping SAR NTF (Noise Transfer Function) to additionally generate second-order noise shaping, thereby performing a total of fourth-order noise shaping.

[0013] In another aspect, the operating method of the delta-sigma modulator based on noise-shaping SAR for a wide input signal range and input impedance amplification for bio-signal recording proposed in the present invention includes the steps of increasing the common mode rejection ratio (CMRR) and reducing noise through a correlated double sampling integrator, pre-sampling the previous output of the delta-sigma modulator to an input sampling capacitor when reflecting the output of the delta-sigma modulator to an input terminal to amplify the input impedance without an additional amplifier, a step of amplifying the input signal using an inverter-based amplifier to obtain a wide input signal range, a step of increasing the resolution through noise-shaping SAR, and a step of performing noise shaping through noise-shaping SAR to reduce a truncation error when reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to an input digital-to-analog converter, and then performing truncation through truncation logic to feed them back to the input digital-to-analog converter.

[0014] According to embodiments of the present invention, a wide input signal range for biosignal recording and an integrator of a noise-shaping SAR-based delta-sigma modulator for input impedance amplification are provided to support not only a wide input swing but also high input impedance at low power consumption, and the input impedance can be further improved through a pre-sampling-based charge transfer reduction technique that does not require an additional amplifier, and the charge transfer can be reduced and the input impedance can be increased by pre-charging the sampling capacitor only with the previously sampled signal. In addition, a novel truncation error forming method according to embodiments of the present invention can effectively form noise in the form of truncation errors without using an additional loop by feeding the truncation errors back to the local NS-SAR loop, so that fourth-order noise shaping can be generated.

[0015] FIG. 1 is a diagram illustrating a wide input signal range for biosignal recording and a noise-shaping SAR-based delta-sigma modulator for input impedance amplification according to one embodiment of the present invention.

[0016] FIG. 2 is a flowchart illustrating an operation method of a delta-sigma modulator based on noise shaping SAR for wide input signal range and input impedance amplification for biosignal recording according to one embodiment of the present invention.

[0017] FIG. 3 is a diagram illustrating an input sampling capacitor according to one embodiment of the present invention.

[0018] FIG. 4 is a diagram for explaining a process of pre-sampling a previous output of a delta-sigma modulator according to one embodiment of the present invention to an input sampling capacitor.

[0019] FIG. 5 is a drawing showing an amplifier according to one embodiment of the present invention.

[0020] FIG. 6 is a diagram for explaining an amplifier error according to one embodiment of the present invention.

[0021] Figure 7 is a drawing for explaining the noise level according to one embodiment of the present invention.

[0022] FIG. 8 is a drawing for explaining a cutting error of a digital-to-analog converter according to one embodiment of the present invention.

[0023] FIG. 9 is a graph showing measured SNDR and DR performance according to one embodiment of the present invention.

[0024] Fig. 10 is a graph showing the results of cutting errors depending on the presence or absence of noise shaping according to one embodiment of the present invention.

[0025] Figure 11 is a graph showing IRN performance according to one embodiment of the present invention.

[0026] FIG. 12 is a diagram showing measured CMRR and input impedance according to one embodiment of the present invention.

[0027] FIG. 13 is a diagram showing a chip micrograph and ECG recording results according to one embodiment of the present invention.

[0028] The present invention proposes a delta-sigma modulator based on noise-shaping SAR for wide input signal range and input impedance amplification for biosignal recording.

[0029] An integrated circuit (IC) according to an embodiment of the present invention directly converts a small input signal into digital data based on a first-order Delta-Sigma Modulator (DSM) with second-order Noise-Shaping (NS)-Successive Approximation (SAR) for high power efficiency and high resolution.

[0030] The first-stage integrator of the DSM according to an embodiment of the present invention can be designed to support not only a wide input swing but also high input impedance while consuming low power. Furthermore, the proposed pre-sampling-based charge transfer reduction technique, which does not require an additional amplifier, can further improve input impedance. Furthermore, charge transfer can be reduced and input impedance can be increased by pre-charging the sampling capacitor with only previously sampled signals.

[0031] A novel truncation error generation method according to an embodiment of the present invention is proposed. By feeding the truncation error back into the local NS-SAR loop, the truncation error can be effectively converted into noise, generating a fourth-order NS without using an additional loop. Hereinafter, an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0032]

[0033] FIG. 1 is a diagram illustrating a wide input signal range for biosignal recording and a noise-shaping SAR-based delta-sigma modulator for input impedance amplification according to one embodiment of the present invention.

[0034] A delta-sigma modulator according to an embodiment of the present invention includes a correlated double sampling (CDS) integrator (110), an input sampling capacitor (111), an amplifier (112), a noise shaping SAR (120), and truncation logic (130).

[0035] A correlated double sampling integrator (110) according to an embodiment of the present invention can increase CMRR (Common Mode Rejection Ratio) and reduce noise.

[0036] The input sampling capacitor (111) according to an embodiment of the present invention samples the previous output of the delta-sigma modulator in advance when reflecting the output of the delta-sigma modulator to the input terminal to amplify the input impedance without an additional amplifier.

[0037] An amplifier (112) according to an embodiment of the present invention amplifies a signal based on an inverter to obtain a wide input signal range.

[0038] The noise shaping SAR (120) according to an embodiment of the present invention can increase resolution.

[0039] The truncation logic (130) according to an embodiment of the present invention reduces the output bits of a delta-sigma modulator to a predetermined number of bits and feeds them back to an input digital-to-analog converter, performs noise shaping through a noise shaping SAR to reduce a truncation error, and then performs truncation and feeds it back to the input digital-to-analog converter.

[0040] There is a tradeoff between 1 / f noise reduction and input impedance, primarily due to the use of chopper stabilization. To overcome this tradeoff, the present invention proposes an NS-SAR nested DSM structure that simultaneously reduces 1 / f noise and increases input impedance without the use of an additional amplifier.

[0041] Referring to Fig. 1, a block diagram of the proposed DSM is shown, which consists of a first-order DSM and a second-order NS-SAR. High resolution with low power consumption is achieved by using an energy-efficient NS-SAR ADC rather than a structure that uses an amplifier-based multi-stage integrator. In addition, an input impedance boosting method is proposed to minimize charge transfer at the input of the CDS integrator (110), thereby reducing 1 / f noise and achieving boosted input impedance. For input impedance boosting, a proposed presampling-based charge transfer induction technique is used to minimize charge transfer from the Discrete-Time Delta-Sigma Modulator (DT-DSM) to the input capacitor (111). The proposed method eliminates the need for an additional amplifier for input impedance boosting. The CDS integrator (110) is also optimized to achieve a wide linear input range with high power efficiency. Finally, a novel truncation error shaping technique that reuses the NS-SAR is proposed.

[0042]

[0043] FIG. 2 is a flowchart illustrating an operation method of a delta-sigma modulator based on noise shaping SAR for wide input signal range and input impedance amplification for biosignal recording according to one embodiment of the present invention.

[0044] The method of operating a delta-sigma modulator based on noise-shaping SAR for a wide input signal range and input impedance amplification for recording a biosignal according to an embodiment of the present invention comprises the steps of increasing the common mode rejection ratio (CMRR) and reducing noise through a correlated double sampling integrator (210), pre-sampling the previous output of the delta-sigma modulator to an input sampling capacitor when reflecting the output of the delta-sigma modulator to an input terminal to amplify the input impedance without an additional amplifier (220), amplifying the input signal using an inverter-based amplifier to obtain a wide input signal range (230), increasing the resolution through noise-shaping SAR (240), and when reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to an input digital-to-analog converter, performing noise shaping through noise-shaping SAR to reduce a truncation error, and then performing truncation through truncation logic to convert the input digital-to-analog converter into an input digital-to-analog converter. It includes a step (250) of providing feedback to the converter.

[0045] In step (210), the Common Mode Rejection Ratio (CMRR) is increased and noise is reduced through a correlated double sampling integrator.

[0046] In step (220), when the output of the delta-sigma modulator is reflected to the input terminal to amplify the input impedance without an additional amplifier, the previous output of the delta-sigma modulator is pre-sampled to the input sampling capacitor.

[0047] In the integration step according to an embodiment of the present invention, the previous output of the delta-sigma modulator is integrated on the input sampling capacitor, and the charge difference between the current input voltage and the previous output is integrated on the feedback capacitor.

[0048] In the pre-sampling step according to an embodiment of the present invention, the input sampling capacitor is pre-sampled by an asynchronous SAR ADC.

[0049] In the input sampling step according to an embodiment of the present invention, the next input voltage is newly charged to the input sampling capacitor.

[0050] In step (230), the input signal is amplified using an inverter-based amplifier to obtain the wide input signal range.

[0051] According to an embodiment of the present invention, a current reuse inverter based amplifier is used to increase the linear input range of the amplifier by not using a cascade stack for improved GM (transconductance) and low power and wide bandwidth.

[0052] At step (240), the resolution is increased through noise shaping SAR.

[0053] In step (250), when the output bits of the delta-sigma modulator are reduced to a predetermined number of bits and fed back to the input digital-to-analog converter, noise shaping is performed through noise shaping SAR to reduce the truncation error, and then truncation is performed through truncation logic and fed back to the input digital-to-analog converter.

[0054] According to an embodiment of the present invention, by reducing the output bits of a delta-sigma modulator to a predetermined number of bits and feeding them back to an input digital-to-analog converter, a truncation error is fed back and the input digital-to-analog converter is reused to re-perform noise shaping with low power consumption.

[0055] According to an embodiment of the present invention, a second-order noise shaping SAR is used, and the truncation error fed back to the input digital-to-analog converter through the truncation logic is additionally passed through a second-order noise shaping SAR NTF (Noise Transfer Function) to additionally generate second-order noise shaping, thereby performing a total of fourth-order noise shaping. Hereinafter, the operation process of a delta-sigma modulator based on noise shaping SAR for a wide input signal range and input impedance amplification for recording a biosignal according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 8.

[0056]

[0057] FIG. 3 is a diagram showing an input sampling capacitor according to one embodiment of the present invention.

[0058] FIG. 3(a) is a diagram showing a case where an independent capacitor is used when reflecting the output of a delta-sigma modulator to an input terminal in a delta-sigma modulator according to the prior art, and FIG. 3(b) is a diagram showing an input sampling capacitor according to one embodiment of the present invention.

[0059] Input sampling capacitor according to an embodiment of the present invention (Fig. 3(b) C IN ) pre-samples the previous output of the delta-sigma modulator when reflecting the output of the delta-sigma modulator to the input stage to amplify the input impedance without an additional amplifier. By pre-sampling the previous output of the delta-sigma modulator to the capacitor that sampled the current input and then sampling the new input, charge transfer at the input is minimized. This becomes more advantageous as the sampling frequency increases.

[0060]

[0061] FIG. 4 is a diagram for explaining a process of pre-sampling a previous output of a delta-sigma modulator according to one embodiment of the present invention to an input sampling capacitor.

[0062] High input impedance characteristics are essential for biosignal acquisition, regardless of electrode impedance or mismatch. Figure 4 illustrates the detailed principles of the proposed input impedance boosting technique implemented in a CDS integrator to reduce 1 / f noise and offset. Figure 4(a) illustrates the integration phase, Figure 4(b) illustrates the pre-sampling phase, and Figure 4(c) illustrates the phase of the input sampling phase, respectively.

[0063] In the proposed structure, input signal sampling and D OUT The feedback is all the same C of the CDS integrator. IN is performed in . Therefore, during input sampling, C from the input IN The charge transferred to C can be greatly reduced. IN To obtain a higher input impedance by further reducing the amount of charge transferred to the input sampling and D OUT The delay between feedbacks must be minimized. As the oversampling ratio (OSR) increases, charge transfer decreases and input impedance increases.

[0064] In the present invention, a pre-sampling-based charge transfer reduction technique is proposed to further enhance the input impedance boosting effect. The operation of the integration stage circuit according to the embodiment of the present invention is the same as the previous technique, as shown in Fig. 4(a). In the integration stage, D OUT [n-1] result is C IN is applied to the lower terminal of the D. At high OSR, OUT [n-1] is close to Vin[n-1]. Then, C of the input capacitor IN Vin[n] and C IN D OUT The charge difference between [n-1] is transferred to the feedback capacitor and integrated. After the integration step, unlike the previous operation, D OUT A new step called the presampling step follows. Figure 4(b) shows the operation of the presampling step. During this step, DOUT [n] is generated within 100 ns by the asynchronous SAR ADC. Then the updated D OUT [n] is C IN is pre-sampled. Finally, in the input sampling step (Fig. 4 (c)), Vin [n + 1] is C IN is newly charged. Therefore, C IN Vin[n + 1] and C IN The charge difference between Vin[n] is C at the input IN As a result, the pre-sampling based charge transfer reduction technique proposed in the present invention is transmitted to the input and C IN D for OUT While the feedback delay is only 1 sample, the conventional technique introduces a 2-sample delay. This improvement can double the boosting effect at the same OSR. Therefore, the overall structure of the proposed DT-DSM, which incorporates this CDS integrator, reduces 1 / f noise while improving CMRR and input impedance.

[0065] However, there are some challenges in implementing the proposed circuit structure. The new D OUTAdditional power is consumed to pre-charge the input capacitive digital-to-analog converter (C-DAC), and no additional amplifier is required for input impedance boosting. To mitigate DT-DSM noise, the C-DAC size must be set relatively large. This characteristic may increase power and area consumption to some extent. In addition, utilizing the DT-DSM structure requires a strong reference buffer to quickly set the reference voltage for the C-DAC and prevent input-dependent loading effects. Since the number of bits fed back to the input C-DAC affects the input impedance, there is a limit to truncating the number of feedback bits. In addition, the introduction of a presampling time shortens the time to sample a new input. Since it becomes more difficult to increase the OSR, the DSM structure is designed in three stages to achieve the target resolution.

[0066]

[0067] FIG. 5 is a drawing showing an amplifier according to one embodiment of the present invention.

[0068] A discrete delta-sigma modulator according to one embodiment of the present invention has the advantage of utilizing a correlated double sampling integrator, but suffers from poor power efficiency. This is because increasing the amplifier gain requires increasing bandwidth. Therefore, to reduce power consumption, a small gain is used while maintaining a high bandwidth.

[0069] According to one embodiment of the present invention, an inverter-based amplifier (510) is used in this process. The internal structure (520) of the inverter-based amplifier according to one embodiment of the present invention can have a wide input signal range of 600 mVPP as a result of eliminating the need to stack MOSFETs in cascade if implemented with a low gain.

[0070] According to one embodiment of the present invention, the DSM quantization noise is formed by a third-order characteristic, so it can be reduced to a level below the DSM's Input-Referred Noise (IRN). However, the DSM's Noise Transfer Function (NTF) can easily degrade depending on the amplifier's characteristics. Therefore, the amplifier must be optimized for superior noise performance.

[0071] Referring to FIG. 5, an amplifier structure (520) according to one embodiment of the present invention is illustrated. A current-reuse inverter-based amplifier is used for enhanced GM. However, the amplifier bandwidth used in the integrator must be much wider than the sampling frequency, which typically results in higher power consumption. Therefore, the present invention optimally designs the amplifier to have a reasonable gain of 36 dB to achieve a wide bandwidth while consuming low power. This design achieves a unity-gain bandwidth of 480 kHz while consuming only 2.2 μA of current.

[0072] Furthermore, the linear input range of the amplifier is achieved by not using a cascade stack for the unnecessary high output resistance of the present invention. For low IRN, the input transistors must be sufficiently large to avoid gate leakage issues. Therefore, thick-gate oxide transistors are used as input transistors in the amplifier to reduce transistor gate leakage.

[0073]

[0074] FIG. 6 is a diagram for explaining an amplifier error according to one embodiment of the present invention.

[0075] However, a moderate amplifier gain can affect the NTF of the DSM. This is because the overall DSM loop gain decreases as the amplifier gain decreases. Furthermore, parasitic capacitance caused by the amplifier's large input transistors can degrade integrator performance. The amplifier's finite gain and parasitic capacitance can lead to gain and phase errors, as shown in Figure 6.

[0076] According to one embodiment of the present invention, phase error and gain error occur as the gain of the integrator decreases due to the inverter-based amplifier. The gain error is adjustable using the SAR ADC reference voltage and therefore does not significantly affect the delta-sigma modulator. However, the phase error affects the overall operation of the delta-sigma modulator.

[0077]

[0078] Figure 7 is a drawing for explaining the noise level according to one embodiment of the present invention.

[0079] Figure 7(a) shows the PSD for normalized frequency, and Figure 7(b) shows the PSD for frequency.

[0080] By using a small gain in the integrator, the characteristics deteriorate (712, 722) as if the noise level has increased compared to the existing noise transformation formula (711, 721). However, this is not a problem because the target noise level (731, 732) is higher.

[0081] Figure 7 compares the proposed DSM with the IRN, demonstrating the degradation caused by DSM noise and phase error. The ideal NTF of the proposed DSM is depicted by the black lines (711, 721). The combination of the first-order DSM and the second-order NS SAR significantly reduces quantization noise. However, in the present embodiment, the gain of the amplifier used in the integrator is limited to 36 dB, resulting in a phase error of 1.84%. Furthermore, process variations can degrade the performance of the amplifier GM. In the worst case, where the gain is further reduced by 6 dB, a phase error of approximately 3% is assumed. As shown in the red lines (712, 722) of Figure 7, the NTF degradation due to this phase error occurs because the loop gain decreases at low frequencies. Although the integrator performance degrades due to the low amplifier gain and parasitic capacitance, the noise level degraded by the integrator phase error is still significantly lower than the target noise level depicted by the blue lines (731, 732) of Figure 7.

[0082]

[0083] FIG. 8 is a drawing for explaining a cutting error of a digital-to-analog converter according to one embodiment of the present invention.

[0084] Fig. 8(a) is a diagram showing a truncation (TRNC) logic, Fig. 8(b) is a diagram showing a phase that reflects the truncation result back to the capacitor digital-to-analog converter of the SAR, and Fig. 8(c) is a diagram showing a phase that removes a truncation error using a noise shaping loop.

[0085] Increasing the output bit count in a delta-sigma modulator improves performance. However, as the bit count increases, the linearity of the input digital-to-analog converter becomes a problem.

[0086] Therefore, in the embodiment of the present invention, the 7-bit output is reduced to 5 bits and fed back to the input digital-to-analog converter. This process of discarding bits is called truncation, and a truncation error occurs during this process. This error is typically eliminated through additional noise shaping, which consumes power. In the embodiment of the present invention, a noise shaping loop is used to eliminate the truncation error.

[0087] When the output of the noise shaping SAR (820) is output from the circuit, the truncation result through the truncation logic (810) is reflected back to the capacitor digital-to-analog converter (830) of the SAR, thereby storing the truncation error back in the CDAC (capacitor DAC). Thereafter, by performing noise shaping again, both the truncation error and the quantization error are noise-shaped simultaneously.

[0088] More specifically, according to an embodiment of the present invention, an asynchronous 7-bit NS-SAR ADC structure is used to obtain a second-order NS without using an active amplifier structure, and the integrator output is quantized in the proposed DSM. As shown in Fig. 8(a), a passive second-order NS is utilized to achieve high resolution and low power consumption. Since the total capacitor size of the C-DAC is 1 pF, the passive integration capacitor can be determined as 3 pF for the passive integration coefficient 1 / (1-0.75z-1).

[0089] Typically, NS-SAR ADCs are vulnerable to low-frequency applications due to switch leakage current. As the process shrinks, leakage becomes more severe. Therefore, the number of switches can significantly impact NS-SAR performance. In low-frequency applications, even if NS-SAR achieves NS of two or more orders of magnitude, using a large number of switches in the 65nm process does not achieve NS of two or more orders of magnitude. Consequently, the NS-SAR method with the lowest number of switches is used, and thick oxide transistors are used for the NS switches due to leakage issues.

[0090] Additionally, according to an embodiment of the present invention, a C-DAC can be implemented using a custom-designed Metal-Oxide Metal (MOM) capacitor to minimize C-DAC mismatch. In an embodiment of the present invention, an 8-bit asynchronous SAR ADC with top plate sampling is proposed.

[0091] Furthermore, we propose a novel fourth-order truncation error shaping architecture by reusing NS-SAR ADCs. NS-SAR ADCs can generally produce high resolution with low power consumption. Therefore, passive second-order NS-SAR ADCs were selected as the quantizers of DSMs. However, linearity issues arise when the high-resolution ADC output is fed back to the DSM's input C-DAC. In this case, the multi-bit ADC output is typically truncated, and the resulting truncation error is in the form of noise in the digital domain. Existing truncation error shaping techniques typically choose second-order shaping due to the complexity and power consumption of digital logic. As the number of truncation bits increases beyond second order, filtering the truncation error becomes significantly more difficult, requiring more complex circuitry and higher power consumption. In this invention, we propose a novel truncation error shaping method that reuses NS-SAR ADCs to further sculpt noise with low power consumption.

[0092] According to an embodiment of the present invention, the truncation error is fed back to the C-DAC (830) of the NS-SAR ADC. Therefore, the truncation error additionally passes through the NS SAR NTF. This results in an additional second NS due to the truncation error, resulting in a total of four NSs.

[0093] Here, the first-order DSM and second-order NS-SAR characteristics result in a third-order NTF. However, to mitigate C-DAC complexity and linearity issues, the 7-bit output is truncated to 5 bits before being fed back to the input C-DAC. This truncation error significantly degrades noise performance. Applying the proposed technique yields a fourth-order NTF with the same in-band characteristics as the 7-bit feedback case.

[0094] Referring to Fig. 8(a), the circuit implementation of the proposed truncation error shaping is shown. After the asynchronous SAR (810) conversion, the truncation bits are fed to the SAR C-DAC (830), and the two LSBs are reset. Then, an active secondary NS is performed. As a result, the truncation error and quantization noise are formed simultaneously. The truncated 5-bit output is the result of truncation of the two LSBs by adding the 7-bit NS-SAR output and the two previously truncated LSBs. The truncation error is fed back to the C-DAC in the form of first-order noise in the digital domain. The processed 5-MSB result is applied to the logic circuit that switches the bottom plate of the C-DAC through an additional multiplexer, as shown in Fig. 8(b). Applying each bit conversion result to the C-DAC results in Φ TRN It rises from 0 to 1. After obtaining the truncated 5-bit result in the truncation logic of Fig. 8(a), Φ TRN The signal becomes high and the truncated 5-bit result is applied to the C-DAC. The proposed truncation error shape can affect the entire input swing range. However, this only leads to a slight reduction in the output swing.

[0095]

[0096] FIG. 9 is a graph showing measured SNDR and DR performance according to one embodiment of the present invention.

[0097] An IC fabricated in 65 nm CMOS according to one embodiment of the present invention consumes 5.2 μW and 0.1292 mm2. When a 600 mVPP sine wave input is applied, the measured peak SNDR is 94.5 dB and 80.7 dB for 500 Hz and 10 kHz BW, respectively, while the measured DR is 95.8 dB.

[0098] Figure 10 is a graph showing the results of a cutting error depending on the presence or absence of cutting logic according to one embodiment of the present invention.

[0099] Two-tone test results demonstrating TRNC error and artifact tolerance with and without the proposed truncation logic are presented.

[0100] Figure 11 is a graph showing IRN performance according to one embodiment of the present invention.

[0101] The measured IRN is 174 nV / √Hz, and the IRN does not change significantly even when the input DC offset changes.

[0102] FIG. 12 is a diagram showing measured CMRR and input impedance according to one embodiment of the present invention.

[0103] The measured CMRR is higher than 83 dB and the ZIN is measured as 208 MΩ at DC and 31.5 MΩ at 500 Hz.

[0104] FIG. 13 is a diagram showing a chip micrograph and ECG recording results according to one embodiment of the present invention.

[0105] Figure 13 shows a micrograph of the chip and an ECG signal recorded using the fabricated IC, showing that the ECG waveform is well separated despite motion artifacts. The design according to the embodiment of the present invention achieves a wider linear input range and excellent SNDR and DR performance. High CMRR and low 1 / f noise can be achieved thanks to the CDS. In addition, Z can be obtained without using a separate amplifier. IN can boost. The proposed IC achieves 174.3 dB FOMSNDR and 175.6 dB FOMDR, which are close to the state-of-the-art.

[0106]

[0107] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0108] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Correlated double sampling integrator that increases CMRR (Common Mode Rejection Ratio) and reduces noise; An input sampling capacitor that pre-samples the previous output of the delta-sigma modulator when reflecting the output of the delta-sigma modulator to the input stage to amplify the input impedance without an additional amplifier; An inverter-based amplifier that amplifies an input signal to obtain a wide input signal range; Successive Approximation (SAR) noise shaping to increase resolution; When reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter, the truncation logic performs noise shaping through noise shaping SAR to reduce the truncation error, and then performs truncation and feeds it back to the input digital-to-analog converter. Delta-sigma modulator including .

2. In paragraph 1, The above input sampling capacitor is, In the integration stage, the previous output of the delta-sigma modulator is integrated over the input sampling capacitor, and the charge difference between the current input voltage and the previous output is integrated over the feedback capacitor. In the pre-sampling stage, the input sampling capacitor is pre-sampled by the asynchronous SAR ADC, In the input sampling stage, the next input voltage is newly charged to the input sampling capacitor. Delta-sigma modulator.

3. In paragraph 1, The above amplifier, It uses a current reuse inverter-based amplifier that increases the linear input range of the amplifier by not using a cascade stack for improved GM (transconductance) and low power and wide bandwidth. Delta-sigma modulator.

4. In paragraph 1, The above cutting logic is, By reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter, the truncation error is fed back and the input digital-to-analog converter is reused to re-perform noise shaping with low power consumption. Delta-sigma modulator.

5. In paragraph 4, The above noise shaping SAR is, Using the second noise shaping SAR, the truncation error fed back to the input digital-to-analog converter through the above truncation logic is additionally passed through the second noise shaping SAR NTF (Noise Transfer Function), so that the second noise shaping is additionally generated, and thus a total of 4th noise shaping is performed. Delta-sigma modulator.

6. A step of increasing the Common Mode Rejection Ratio (CMRR) and reducing noise through a correlated double sampling integrator; When reflecting the output of a delta-sigma modulator to an input terminal to amplify the input impedance without an additional amplifier, a step of pre-sampling the previous output of the delta-sigma modulator to an input sampling capacitor; A step of amplifying an input signal using an inverter-based amplifier to obtain a wide input signal range; Step of increasing resolution through noise shaping SAR; and When reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter, a step of performing noise shaping through noise shaping SAR to reduce truncation error, and then performing truncation through truncation logic and feeding them back to the input digital-to-analog converter. A method of operating a delta-sigma modulator including:

7. In paragraph 6, When reflecting the output of the delta-sigma modulator to the input terminal to amplify the input impedance without the above-mentioned additional amplifier, the step of pre-sampling the previous output of the delta-sigma modulator to the input sampling capacitor is, In the integration stage, the previous output of the delta-sigma modulator is integrated over the input sampling capacitor, and the charge difference between the current input voltage and the previous output is integrated over the feedback capacitor. In the pre-sampling stage, the input sampling capacitor is pre-sampled by the asynchronous SAR ADC, In the input sampling stage, the next input voltage is newly charged to the input sampling capacitor. How the delta-sigma modulator works.

8. In paragraph 6, The step of amplifying the input signal using an inverter-based amplifier to obtain the above wide input signal range is as follows: It uses a current reuse inverter-based amplifier that increases the linear input range of the amplifier by not using a cascade stack for improved GM (transconductance) and low power and wide bandwidth. How the delta-sigma modulator works.

9. In paragraph 6, When reducing the output bits of the above delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter, the step of performing noise shaping through noise shaping SAR to reduce the truncation error and then performing truncation through truncation logic and feeding them back to the input digital-to-analog converter is as follows. By reducing the output bits of the delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter, the truncation error is fed back and the input digital-to-analog converter is reused to re-perform noise shaping with low power consumption. How the delta-sigma modulator works.

10. In paragraph 9, When reducing the output bits of the above delta-sigma modulator to a predetermined number of bits and feeding them back to the input digital-to-analog converter, the step of performing noise shaping through noise shaping SAR to reduce the truncation error and then performing truncation through truncation logic and feeding them back to the input digital-to-analog converter is as follows. Using the second noise shaping SAR, the truncation error fed back to the input digital-to-analog converter through the above truncation logic is additionally passed through the second noise shaping SAR NTF (Noise Transfer Function), so that the second noise shaping is additionally generated, and thus a total of 4th noise shaping is performed. How the delta-sigma modulator works.

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