Electro-optical modulation chip capable of monolithically integrating active optical device, and preparation method

Abstract

An electro-optical modulation chip (100) capable of monolithically integrating an active optical device, and a preparation method. The electro-optical modulation chip (100) comprises, from top to bottom, a compound semiconductor active layer (103), a germanium thin film layer (104) and an electro-optical material waveguide layer (105), wherein the electro-optical material waveguide layer (105) forms corresponding waveguide structures (12) by means of photoetching and etching; the germanium thin film layer (104) forms a germanium absorption layer (104-2) and a germanium substrate growth layer (104-1) by means of photoetching and etching; and the germanium thin film layer (104) is prepared by the ion scissors technology. On the one hand, high-speed and high-responsivity O / C waveband optical detection can be achieved, and on the other hand, a growth substrate matching the lattice of a compound semiconductor is provided for the compound semiconductor, achieving simultaneous integration of an optical gain semiconductor device.

Description

An electro-optical modulation chip capable of monolithically integrating active optical devices and a preparation method thereof Technical Field

[0001] The present invention belongs to the field of semiconductor optoelectronic chips, and in particular relates to an electro-optical modulation chip capable of monolithically integrating active optical devices and a preparation method thereof. Background Art

[0002] Electro-optical material crystals, such as lithium niobate, exhibit large nonlinear optical coefficients, along with excellent photorefractive, piezoelectric, and acoustic properties, and can be used as frequency doubling and difference frequency crystal materials. They possess excellent physical and mechanical properties, including a high damage threshold, a broad transparency spectrum, and very low transmission loss. Furthermore, their relatively low cost makes them highly suitable for the fabrication of optical modulators. Compared to traditional electro-optical modulation chips based on silicon (Si) fabricated using CMOS (complementary metal oxide semiconductor) processes, the nonlinear properties of electro-optical crystals offer promising applications in the recently emerging research and applications of optical frequency combs. With technological advancements, these electro-optical crystals can be integrated in thin-film form onto 6-inch and larger wafers. For example, lithium niobate-on-insulator (LNOI) thin films address the low integration density and polarization crosstalk challenges of traditional electro-optical waveguides, further simplifying the conditions for generating nonlinear effects within them. However, existing lithium niobate thin film technology is difficult to incorporate into the fabrication of active devices beyond modulation. Erbium-doped lithium niobate thin films have been developed to some extent, addressing the challenge of integrating optical gain into lithium niobate thin film systems, but their inherent modulation capabilities are limited, and therefore still have significant limitations. Overall, there is an urgent need for an electro-optical material system on an insulating layer that can simultaneously integrate optical gain, modulation, and detection functions into a single chip.

[0003] Summary of the Invention

[0004] The object of the present invention is to address the deficiencies of the prior art and to provide an electro-optical modulation chip capable of monolithically integrating active optical devices and a preparation method thereof.

[0005] According to the first aspect of the present invention, an electro-optic modulation chip capable of monolithically integrating active optical devices is provided, comprising, from top to bottom, a compound semiconductor active layer, a germanium thin film layer, and an electro-optical material waveguide layer; the electro-optical material waveguide layer is formed into a corresponding waveguide structure by photolithography and etching; the germanium thin film layer is formed into a germanium absorption layer and a germanium substrate growth layer by photolithography and etching;

[0006] The electro-optical material waveguide layer serves as a coupling medium for optical signals and together with the compound semiconductor active layer grown on the germanium substrate growth layer constitutes a waveguide, forming the optical gain portion of the electro-optical modulation chip;

[0007] The electro-optical material waveguide layer serves as a coupling medium for optical signals and together with the germanium absorption layer forms a waveguide, constituting the light detection part of the electro-optical modulation chip;

[0008] The electro-optical material waveguide layer serves as a propagation medium for optical signals and constitutes the optical modulation part of the electro-optical modulation chip.

[0009] According to the second aspect of the present invention, there is provided a method for preparing an electro-optical modulation chip capable of monolithically integrating active optical devices, comprising the following steps:

[0010] preparing an electro-optic material wafer having an electro-optic material waveguide layer, etching the electro-optic material waveguide layer to form a waveguide structure, depositing an insulating substrate layer and flattening the surface;

[0011] A germanium wafer is prepared. After hydrogen ion implantation, a germanium thin film layer, a germanium defect-enriched layer, a germanium cracked layer, and a residual germanium substrate are formed on the surface of the germanium wafer.

[0012] Bonding a germanium wafer to the surface of the upper insulating substrate layer, and retaining only the germanium thin film layer of the germanium wafer by annealing and grinding;

[0013] Etching the germanium thin film layer to form a germanium substrate growth layer for the optical gain portion and a germanium absorption layer for the optical detection portion; then depositing an insulating substrate layer, and opening a growth window in the optical gain portion for growing a compound semiconductor active layer on the germanium substrate growth layer;

[0014] Then, an insulating substrate layer is deposited, and a via electrode and a contact electrode are formed.

[0015] Furthermore, the impurity doping concentration of the germanium wafer should be between 10 16 cm -3 ~5×10 16 cm -3 The doping type is n-type or p-type, and the surface roughness should be within 0.5nm / 100μm. 2 the following.

[0016] Furthermore, the germanium wafer preparation process is specifically as follows:

[0017] Cleaning and drying the germanium wafer; depositing an oxide film on the germanium wafer to form a protective layer;

[0018] The germanium wafer was implanted with hydrogen ions at room temperature with an implantation angle of 7° and an implantation dose of 4×10 16 cm -3 ~1×10 17 cm -3 , injection energy is 60keV~250keV, injection beam current is less than or equal to 1000μA / cm 2 ;

[0019] After the implantation is completed, the germanium wafer is cleaned and dried again to obtain a finished germanium wafer.

[0020] Furthermore, the cleaning and drying are specifically as follows: using a buffered hydrofluoric acid solution or a diluted hydrofluoric acid solution to clean the oxide layer on the surface of the germanium wafer for 3 to 5 minutes; after the acid cleaning is completed, cleaning in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface; after the water washing is completed, nitrogen blowing or vacuum back adsorption and drying are used to remove the surface ultrapure water.

[0021] Furthermore, the bonding process of the germanium wafer is specifically as follows:

[0022] The surface of the germanium wafer and the upper insulating substrate layer are treated, specifically: a thin oxide film several nanometers thick is deposited on the surface of the germanium wafer and the upper insulating substrate layer, or the surface of the germanium wafer and the upper insulating substrate layer is activated by plasma, with the gas atmosphere being nitrogen or oxygen with argon as the carrier;

[0023] After surface treatment, the germanium wafer and the upper insulating substrate layer are pre-bonded;

[0024] Enhance the bond energy of the electro-optical modulation chip formed by pre-bonding;

[0025] In a vacuum environment, the germanium wafer is uniformly heated until the temperature rises to 300°C to 400°C for annealing, and the temperature is maintained long enough until the germanium cracking layer and the residual germanium substrate are peeled off;

[0026] The germanium defect-rich layer on the surface is removed by grinding, leaving the germanium thin film layer;

[0027] Annealing is performed again in a vacuum environment at a temperature of 500 to 550° C. for 10 to 60 minutes to further repair the remaining defects in the germanium thin film layer.

[0028] Furthermore, the bond energy enhancement is specifically: applying 5 to 20 N / cm2 of force to the electro-optical modulation chip in the longitudinal direction. 2 The uniform pressure is less than 10 -5 mbar vacuum atmosphere and ambient temperature of 150℃~250℃, slowly heating and maintaining for 0.5~2 hours and then slowly cooling down, so that the bond energy is enhanced to more than 2J / m 2 .

[0029] Furthermore, the annealing method for stripping the germanium cracking layer and the residual germanium substrate is as follows: when the size of the electro-optical modulation chip is less than or equal to 6 inches, furnace tube heating annealing is adopted; when the size of the electro-optical modulation chip is greater than 6 inches, laser annealing is adopted.

[0030] Furthermore, the etching of the germanium thin film layer is specifically as follows:

[0031] For the optical gain part, the thickness of the germanium thin film layer is reduced, and a germanium substrate growth layer is formed by photolithography and etching to facilitate the growth of the compound semiconductor active layer;

[0032] For the light modulation part, the germanium thin film layer needs to be completely etched;

[0033] For the light detection part, the germanium thin film layer serves as the light absorption layer. First, the germanium absorption layer is formed by photolithography and etching, and then a pn junction is formed by doping or a photodetector is formed by forming interdigitated electrodes.

[0034] Furthermore, in the optical gain part, a growth window is opened by etching the upper insulating substrate layer on the germanium substrate growth layer. It is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and a compound semiconductor active layer is grown.

[0035] The present invention provides an electro-optical modulation chip structure and fabrication method capable of simultaneously integrating optical gain, optical modulation, and optical detection. By integrating a single-crystal germanium thin film layer onto an electro-optical waveguide using ion scissor technology, this allows for the fabrication of high-speed, high-response germanium detectors in the communications band. Furthermore, the germanium used as a growth substrate matches the lattice of compound semiconductors, enabling high-quality crystal growth and the realization of high-performance optical gain devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 is a schematic structural diagram of an electro-optical modulation chip capable of monolithically integrating active optical devices provided by the present disclosure;

[0037] FIG2 is a flow chart of the preparation of an electro-optical modulation chip capable of monolithically integrating active optical devices provided by the present disclosure;

[0038] FIG3 is a schematic structural diagram of the preparation step S1 provided in the present disclosure;

[0039] FIG4 is a schematic structural diagram of the preparation step S2 provided in the present disclosure;

[0040] FIG5 is a schematic diagram of the germanium wafer structure in the preparation step S4 provided by the present disclosure;

[0041] FIG6 is a schematic diagram of the structure after pre-bonding in the preparation step S5 provided in the present disclosure;

[0042] FIG7 is a schematic diagram of forming a germanium thin film layer in the preparation step S5 provided by the present disclosure;

[0043] FIG8 is a schematic diagram of the final structure in the preparation step S5 provided in the present disclosure;

[0044] FIG9 is a schematic structural diagram of the preparation step S6 provided in the present disclosure;

[0045] FIG10 is a schematic structural diagram of the preparation steps S7-S8 provided in the present disclosure;

[0046] FIG11 is a schematic structural diagram of the preparation step S9 provided in the present disclosure;

[0047] FIG12 is a schematic structural diagram of the preparation steps S10-S11 provided in the present disclosure;

[0048] FIG13 is a schematic structural diagram of the preparation step S12 provided in the present disclosure;

[0049] In the figure, 100 is an electro-optical modulation chip, 10 is an electro-optical material wafer, 101 is a contact electrode, 102 is a via electrode, 103 is a compound semiconductor active layer, 11 is a germanium wafer, 104 is a germanium thin film layer, 104-a is a germanium cracking layer, 104-b is a germanium defect enriched layer, 104-c is a residual germanium substrate, 104-1 is a germanium substrate growth layer, 104-2 is a germanium absorption layer, 105 is an electro-optical material waveguide layer, 12 is a waveguide structure, 106a is an upper insulating substrate layer, 106b is a lower insulating substrate layer, 107 is a chip substrate layer, 200 is an optical gain part, 300 is an optical modulation part, and 400 is an optical detection part. DETAILED DESCRIPTION

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0052] For clarity, the following description of embodiments of the present invention and related structures primarily features single-chip structures formed on a semiconductor substrate and their fabrication steps. However, for efficiency reasons, various embodiments can be implemented at the wafer level.

[0053] It should be noted that references to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc., in the application documents indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to implement that feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0054] In general, terminology is understood at least in part based on usage in context. For example, the term "one or more," as used herein, may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a combination of features, structures, or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may again be understood to convey singular usage or plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but rather may allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0055] It will be readily understood that the meaning of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on” (something), but also encompasses “on” (something) with intervening features or layers therebetween, and “above” or “over” means not only “above” or “on” (something), but also can encompass “above” or “over” (something) with no intervening features or layers therebetween (i.e., directly on something).

[0056] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used for ease of description to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0057] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added atop the substrate can be patterned, or the material added atop the substrate can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be composed of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0058] As used herein, the term "layer" refers to a portion of a material comprising an area having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a width smaller than the width of an underlying or overlying structure. In addition, a layer can be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers thereon, above, and / or below. A layer can comprise multiple layers. For example, an interconnect layer can comprise one or more conductors and contact layers (wherein interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0059] As used herein, the term "front side" of a structure refers to the surface of the structure that is used to form a device or that will subsequently be used to form a device.

[0060] As used herein, the term "semiconductor" of a structure refers to, but is not limited to, a material having a conductivity value that falls between the conductivity values ​​of a conductor and an insulator. The material can be a single substance material or a compound material. Semiconductors can include, but are not limited to, single substances, binary alloys, ternary alloys, and quaternary alloys. Structures formed using one or more semiconductors can include a single semiconductor material, two or more semiconductor materials, a single-composition semiconductor alloy, two or more discrete-composition semiconductor alloys, and a semiconductor alloy that is graded from a first semiconductor alloy to a second semiconductor alloy. The semiconductor can be one of undoped (intrinsic), hole-doped, electron-doped, doped from a first doping level of one type to a third doping level of the same type, and doped from a first doping level of one type to a third doping level of a different type.

[0061] Further, the semiconductor may include, but is not limited to, Group IV semiconductors such as those between carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0062] Further, the semiconductor may include, but is not limited to, Group III-V semiconductors such as those between aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), and tin (Sb).

[0063] Further, the semiconductor may include, but is not limited to, Group II-VI semiconductors, such as those between zinc (Zn), cadmium (Cd), mercury (Hg), sulfur (S), selenium (Se), tellurium (Te), and oxygen (O).

[0064] As used herein, the term "metal" of a structure refers to, but is not limited to, materials (elemental, compound, and alloy) that have good electrical and thermal conductivity as a result of readily losing outer shell electrons. This may include, but is not limited to, gold, chromium, aluminum, silver, platinum, nickel, copper, rhodium, palladium, tungsten, and combinations of such materials.

[0065] As used herein, the terms "optical waveguide," "dielectric waveguide," or "waveguide" of a structure refer to, but are not limited to, a dielectric medium or combination of media that supports the propagation of optical signals within a predetermined wavelength range and is invariant along the propagation direction. An optical waveguide can be at least one of: an isolation structure comprising at least a core and a cladding (e.g., an optical fiber); an isolation structure formed as part of a carrier; an optical waveguide formed within a substrate (e.g., a planar lightwave circuit, a photonic integrated circuit, an integrated optical device); and an optical waveguide. This includes, but is not limited to, flexible optical waveguides formed from extruded glass, extruded doped silica, extruded chalcogenide glass, and polymers. This further includes, but is not limited to, optical waveguides formed within: quartz-on-insulator, quartz-on-silicon, silicon oxynitride-on-silicon, polymer-on-silicon, polymer-on-polymer, and the like.

[0066] As used herein, the term "waveguide layer" refers to a material portion having a thickness. More specifically, it may be formed of one or more layers of waveguide material to confine and guide light waves after subsequent processing.

[0067] As used herein, the term "dielectric layer" refers to a material portion having a thickness, more specifically, a dielectric layer having the function of achieving electrical connection or transporting carriers, including but not limited to one or more layers of metal or other conductive materials.

[0068] As used herein, the term "optical-electrical via structure" refers to a via structure connecting a dielectric layer and an electrical absorption layer. This structure facilitates electrical connections between the dielectric layer and the electrical absorption layer, enabling light, converted into electrons in the electrical absorption layer, to be transferred to the dielectric layer for further signal processing. Materials for this structure include, but are not limited to, the aforementioned metal materials or conductive polymer materials.

[0069] As shown in FIG1 , a cross-sectional structural diagram of an electro-optic modulation chip 100 capable of monolithically integrating active optical devices mentioned in the present invention is shown.

[0070] Specifically, the electro-optic modulation chip 100 capable of monolithically integrating active optical devices comprises, from top to bottom, a compound semiconductor active layer 103, a germanium thin film layer 104, and an electro-optical material waveguide layer 105. The electro-optical material waveguide layer 105 is formed into a corresponding waveguide structure 12 through photolithography and etching, enabling light propagation within the electro-optical material waveguide layer 105. The germanium thin film layer 104 is formed into a germanium absorption layer 104-2 and a germanium substrate growth layer 104-1 through photolithography and etching.

[0071] The electro-optical material waveguide layer 105 serves as a coupling medium for optical signals and together with the compound semiconductor active layer 103 grown on the germanium substrate growth layer 104-1, forms a waveguide. By means of electrical injection, the optical signal is amplified through the compound semiconductor active layer 103, thereby forming the optical gain portion 200 of the electro-optical modulation chip 100 capable of monolithically integrating active optical devices.

[0072] The electro-optical material waveguide layer 105 serves as a coupling medium for optical signals and together with the germanium absorption layer 104-2 forms a waveguide. Since germanium has strong absorption of light below 1600nm, the germanium absorption layer 104-2 can serve as a light detection medium. The electro-optical material waveguide layer 105 and the germanium absorption layer 104-2 together constitute the light detection part 400 of the electro-optical modulation chip 100 that can be monolithically integrated with active optical devices.

[0073] The electro-optical material waveguide layer 105 serves as a propagation medium for optical signals and constitutes the optical modulation part 300 of the electro-optical modulation chip 100 capable of monolithically integrating active optical devices.

[0074] FIG2 shows the manufacturing process of the electro-optic modulation chip 100 capable of monolithically integrating active optical devices. The following describes each process in detail:

[0075] S1: preparing an electro-optical material wafer 10;

[0076] Specifically, as shown in FIG3 , the electro-optic material wafer 10 includes a wafer having an electro-optic material waveguide layer 105 made of lithium niobate, lithium tantalate or other materials having a linear electro-optic effect, a lower insulating substrate layer 106 b and a chip substrate layer 107 .

[0077] In particular, such wafers can be provided by wafer manufacturers, and their specific preparation process is beyond the scope of discussion of the patent of this invention.

[0078] Preferably, the thickness of the electro-optic material waveguide layer 105 in the electro-optic material wafer 10 is 400 nm, and more generally, the thickness ranges from 300 nm to 500 nm.

[0079] S2: etching the waveguide structure 12;

[0080] As shown in FIG4 , a waveguide structure 12 needs to be formed on the electro-optical material waveguide layer 105 . The specific design of the waveguide structure is beyond the scope of the present invention, but its types should include common strip waveguides, ridge waveguides, gap waveguides, and sub-wavelength grating waveguides.

[0081] Preferably, the waveguide structure shown in FIG4 is a ridge waveguide, the purpose of which is to move the localized light mode of the optical waveguide upward to an area near the top of the waveguide structure 12 to facilitate coupling with subsequent structures, while having lower propagation loss than a strip waveguide.

[0082] S3: depositing an insulating substrate layer 106a and leveling the surface;

[0083] After the waveguide etching is completed, an oxide layer needs to be deposited to form an upper insulating substrate layer 106a. During the oxide layer deposition process, the geometric structure of the waveguide structure 12 will gradually transfer to the surface of the upper insulating substrate layer 106a as the deposition process proceeds. Therefore, the surface of the upper insulating substrate layer 106a needs to be polished and leveled.

[0084] In particular, in order to ensure that the waveguide structure 12 can support its upper structure when subsequently forming the optical gain part 200, the optical modulation part 300 and the optical detection part 400, it is necessary to limit the distance between the top surface of the upper insulating substrate layer 106a and the top surface of the waveguide structure 12.

[0085] Preferably, the spacing should be less than 100 nm, and the optimal spacing should be maintained at 50 nm.

[0086] S4: preparing germanium wafer;

[0087] Traditional Group IV semiconductor materials often do not have a linear electro-optic effect. Although compound semiconductor materials have a linear electro-optic effect, their production and processing costs are too high. Therefore, they are not suitable for the preparation of a low-cost and high-performance electro-optic modulation chip 100.

[0088] Common electro-optical materials such as lithium niobate and lithium tantalate are well-suited for fabricating the optical modulation section 300 in the electro-optic modulation chip 100. However, since these materials are generally insulating, it is not possible to simultaneously integrate the optical gain section 200 and the optical detection section 400 through simple doping and implantation. Although some scientists have developed an integrated optical chip that uses erbium-doped lithium niobate for optical amplification, the manufacturing process is complex and global, making it unsuitable for monolithic integration.

[0089] The present invention uses a germanium wafer 11 as the medium for integrating the optical gain section 200 and the optical detection section 400 into the electro-optic modulation chip 100. Ion shearing technology is used to integrate a germanium thin film layer 104 fabricated from the germanium wafer 11 onto an electro-optical waveguide layer 105. To achieve this, the germanium wafer 11 requires special processing.

[0090] Specifically, a germanium wafer 11 needs to be prepared in advance, and its impurity doping concentration should be between 10 16 cm -3 ~5×10 16 cm -3 The doping type can be n-type or p-type, and the surface roughness (RMS) should be guaranteed to be 0.5nm / 100μm 2 the following.

[0091] Subsequently, the germanium wafer 11 is cleaned. First, a 25% buffered hydrofluoric acid solution (BHF) or a diluted hydrofluoric acid solution (DHF) is used to clean the oxide layer on the surface of the germanium wafer 11 for 3 to 5 minutes. After the acid cleaning is completed, it is cleaned in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface. After the water washing is completed, it is necessary to ensure that the ultrapure water film on the surface of the germanium wafer 11 is evenly and flatly covered on the surface of the germanium wafer 11. The purpose of this step is to confirm that the dangling bond structure on the surface of the germanium wafer 11 is a hydrophilic structure. Afterwards, the surface ultrapure water is removed by blowing with nitrogen or vacuum back adsorption and drying.

[0092] Next, a dense oxide film is deposited on the germanium wafer 11 by vapor deposition to serve as a protective layer for subsequent processes. Preferably, the oxide film thickness should be 100nm and the material should be silicon dioxide. A wider range includes 50nm to 200nm.

[0093] Then, the germanium wafer 11 is subjected to hydrogen ion (H + ) injection, the injection angle is 7°, and the injection dose is 4×10 16 cm -3 ~1×10 17 cm -3 , injection energy is 60keV~250keV, injection beam current is less than or equal to 1000μA / cm 2 .

[0094] Preferably, in order to prevent the occurrence of self-heating effect and ensure that the germanium thin film layer 104 of sufficient thickness can be transferred to the surface of the electro-optical material waveguide layer 105 in the subsequent process, the injection conditions should be: injection angle of 7°, injection dose of 4×10 16 cm -3 , injection energy is 80keV, injection beam current is 100μA / cm 2 .

[0095] After the injection is completed, use BHF or DHF solution to clean the surface oxide layer again for 3 to 5 minutes. After the acid cleaning is completed, clean it in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface. After the water washing is completed, it is necessary to ensure that the ultrapure water film on the surface of the germanium wafer 11 is evenly and flatly covered on the surface of the germanium wafer 11. The purpose of this step is to confirm that the dangling bond structure on the surface of the germanium wafer 11 is still a hydrophilic structure. Afterwards, the surface ultrapure water is removed by nitrogen blowing or vacuum back adsorption and drying, and finally the prepared germanium wafer 11 is obtained.

[0096] As shown in Figure 5, the surface of the germanium wafer 11 has a germanium thin film layer 104. Because this layer is close to the surface of the germanium wafer 11, it has a low defect density and residual hydrogen ion concentration after ion implantation. As depth increases, a germanium defect-rich layer 104-b forms deeper within the surface of the germanium wafer 11. The location and thickness of this layer vary with implantation conditions. More specifically, the depth and thickness of the germanium defect-rich layer 104-b can be varied by adjusting the implantation energy and implantation dosage. Furthermore, under certain implantation conditions, the germanium defect enrichment process results in the formation of a germanium cleavage layer 104-a of a certain thickness at a specific depth. This layer contains numerous germanium lattice defects, and hydrogen ions passivate dangling bonds on the defects, concentrating as hydrogen molecules at the defect cores. Because the deeper residual germanium substrate 104-c is much deeper than the depth that hydrogen ions can penetrate after acceleration, its basic properties are similar to those of the germanium thin film layer 104, and both can be considered single crystal germanium.

[0097] S5: bonding germanium wafer;

[0098] To transfer the germanium thin film layer 104 onto the electro-optical waveguide layer 105, the germanium wafer 11 must first be wafer-bonded so that the upper surface of the germanium wafer 11 is tightly bonded to the upper surface of the upper insulating substrate layer 106a formed on the electro-optical modulation chip 100 through intermolecular forces. To achieve this, the germanium wafer 11 and the electro-optical modulation chip 100 must undergo surface treatment.

[0099] Specifically, a thin oxide film several nanometers thick is deposited on the surface of the germanium wafer 11. The material can be silicon oxide, aluminum oxide, or the like. Deposition methods include plasma-enhanced vapor deposition (PECVD), conventional vapor deposition, or atomic layer deposition (ALD). Similarly, a thin oxide film several nanometers thick is also deposited on the electro-optical modulation chip 100. Preferably, the oxide film is 5 nanometers thick and is deposited by ALD.

[0100] Another option is to use plasma surface activation, which uses a radio frequency power source of hundreds of watts to activate dangling bonds on the surface. The gas atmosphere can be nitrogen, oxygen, or other common semiconductor process gases with argon as the carrier.

[0101] After surface treatment, the two need to be pre-bonded. This pre-bonding operation does not require fine alignment. Figure 6 shows the structure of the electro-optical modulation chip 100 after pre-bonding with the germanium wafer 11. At this point, the germanium thin film layer 104 has been pre-transferred onto the upper insulating substrate layer 106a, but the intermolecular bonding strength is still weak, and the germanium defect-rich layer 104-b, the germanium cracked layer 104-a, and the residual germanium substrate 104-c have not yet been removed.

[0102] Next, we use bonding equipment to enhance the bonding energy of the pre-bonded electro-optical modulation chip 100. Specifically, a 5-20 N / cm 2 The uniform pressure is less than 10 - 5 mbar vacuum atmosphere and ambient temperature of 150℃~250℃, slowly heating and maintaining for 0.5~2 hours and then slowly cooling down, so that the bond energy is enhanced to more than 2J / m 2 .

[0103] In particular, the pressure and temperature must be adjusted based on the actual size of the electro-optical modulation chip 100 to prevent wafer cracking. In the present invention, the electro-optical modulation chip 100 can range in size from a single chip (<1-inch wafer) to a 12-inch wafer. The corresponding germanium wafer 11 should also be sized to match the electro-optical modulation chip 100.

[0104] Next, we need to peel off the germanium thin film layer 104. This step is called ion scissor technology. By raising the temperature and maintaining it for a long enough time, the residual hydrogen ions in the germanium cracked layer 104-a are induced to cluster and apply microscopic stress to the defects where they are located, so that the germanium cracked layer 104-a undergoes large-scale fracture parallel to the wafer direction, thereby peeling off the germanium cracked layer 104-a and the residual germanium substrate 104-c together, leaving only the germanium thin film layer 104 and the germanium defect-enriched layer 104-b, as shown in Figure 7.

[0105] In particular, the heating process should ensure that the temperature changes slowly and is evenly distributed across the wafer to avoid wafer breakage due to stress differences.

[0106] Preferably, it should be less than 10 -5In a vacuum environment of mbar, the wafer is uniformly heated at a rate of 1°C per minute until the temperature reaches 300°C to 400°C for annealing, and the temperature is maintained long enough until the germanium cracking layer 104-a breaks.

[0107] Because the fracture process is so rapid, the resulting stress transmission can inevitably cause wafer fragmentation. Another improved fracture method is to use high-energy laser-induced fracture. In this method, the laser focus is set near the germanium cleavage layer 104-a. Through continuous single-point scanning, annealing is performed, gradually inducing fractures in the germanium cleavage layer 104-a across the chip. Eventually, small fracture points spontaneously connect to form a large-scale fracture effect.

[0108] Preferably, when the size of the electro-optic modulation chip 100 is less than or equal to 6 inches, furnace heating annealing can be used; when the size of the electro-optic modulation chip 100 is greater than 6 inches, laser annealing should be used.

[0109] Subsequently, the germanium defect-rich layer 104-b on the surface is removed by chemical mechanical polishing, leaving the germanium thin film layer 104, as shown in FIG8. Finally, in a temperature less than 10 -5 Annealing is performed again in a vacuum environment of 100 mbar at a temperature of 500-550° C. for 10-60 minutes to further repair the remaining defects in the germanium thin film layer 104 .

[0110] S6: etching the germanium thin film layer;

[0111] The germanium thin film layer 104, as a precursor of the germanium substrate growth layer 104-1 and the germanium absorption layer 104-2, has been transferred to the surface of the upper insulating substrate layer 106a as described above. Next, the optical gain section 200, optical modulation section 300 and optical detection section 400 of the present invention will be discussed separately.

[0112] For optical gain section 200, the germanium thin film layer 104 has a light absorption effect in the target wavelength band, so its thickness needs to be reduced to minimize the absorption area. Since germanium itself matches the lattice constant of compound semiconductors, especially gallium arsenide (GaAs), it is very suitable as a precursor substrate for compound semiconductor growth. Therefore, its thickness should ensure that it provides a sufficient seed crystal area for the growth of compound semiconductor active layer 103. This invention does not discuss its specific growth mode. In contrast, the present invention emphasizes that during this step of processing the germanium thin film layer 104, it needs to be kept relatively thin, with a typical thickness of 50 nanometers, to form the germanium substrate growth layer 104-1, as shown in Figure 9. In addition, by forming a grid-like structure array on the germanium substrate growth layer 104-1, it can also serve as a precursor for compound semiconductor growth.

[0113] For the light modulation part 300, the germanium thin film layer 104 needs to be completely etched to ensure that it does not affect the electro-optical material waveguide layer 105 and introduce excessive insertion loss during light modulation.

[0114] For the light detection part 400, the germanium thin film layer 104 can be used as a light absorption layer. First, a germanium absorption layer 104-2 is formed by photolithography and etching, as shown in Figure 9, and then a pn structure is formed by doping to form a PIN type photodetector, or an MSM type photodetector is formed by forming interdigitated electrodes. Its typical thickness should be 200 nanometers.

[0115] S7: Continue depositing the upper insulating substrate layer 106a;

[0116] After the germanium substrate growth layer 104-1 and the germanium absorption layer 104-2 are formed, an upper insulating substrate layer 106a is deposited to ensure passivation of the germanium material, as shown in Figure 10. Because the growth window must be opened to allow compound semiconductor growth, the thickness of the upper insulating substrate layer 106a deposited in this step should not exceed 200 nanometers.

[0117] S8: Open the growth window;

[0118] A growth window is opened by etching the upper insulating substrate layer 106a on the germanium substrate growth layer 104-1, as shown in FIG10. This step needs to ensure that no natural oxide is generated on the germanium substrate growth layer 104-1 after the growth window is opened. Therefore, the sample needs to be stored in a vacuum after the etching is completed.

[0119] S9: growing compound semiconductors;

[0120] A compound semiconductor active layer 103 is grown on a germanium substrate growth layer 104-1 in a vapor phase epitaxial device, as shown in FIG11 . The present invention does not protect the compound semiconductor growth environment and layer structure, but only protects the compound semiconductor growth method using the germanium substrate growth layer 104-1 as a seed layer.

[0121] S10: Continue depositing the upper insulating substrate layer 106a;

[0122] As shown in FIG. 12 , the upper insulating substrate layer 106 a is continuously deposited to ensure airtight protection of the grown compound semiconductor.

[0123] S11: forming a via electrode 102;

[0124] Via structures are formed in the optical gain part 200 , the optical modulation part 300 and the optical detection part 400 by etching, and are filled with conductive materials (such as metal, transparent conductive oxide, etc.) to form via electrodes 102 , as shown in FIG12 .

[0125] S12: forming a contact electrode 101;

[0126] Finally, as shown in FIG13 , a contact electrode 101 is formed on the via electrode 102 by etching, electroplating or stripping. The contact electrode 101 is generally made of metal.

[0127] The above description is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. An electro-optic modulation chip capable of monolithically integrating active optical devices, characterized in that: From top to bottom, it includes a compound semiconductor active layer, a germanium thin film layer, and an electro-optical material waveguide layer; The electro-optical material waveguide layer is formed into a corresponding waveguide structure by photolithography and etching; the germanium thin film layer is formed into a germanium absorption layer and a germanium substrate growth layer by photolithography and etching; The electro-optic material waveguide layer serves as a coupling medium for optical signals, and together with the compound semiconductor active layer grown on the germanium substrate growth layer, forms a waveguide, which constitutes the optical gain part of the electro-optic modulation chip; The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the germanium absorption layer forms a waveguide, which constitutes the optical detection part of the electro-optic modulation chip; The electro-optic material waveguide layer serves as a propagation medium for optical signals and constitutes the optical modulation part of the electro-optic modulation chip.

2. A method for preparing an electro-optic modulation chip capable of monolithically integrating active optical devices, characterized in that: The following steps are involved: preparing an electro-optic material wafer having an electro-optic material waveguide layer, etching the electro-optic material waveguide layer to form a waveguide structure, depositing an insulating substrate layer and flattening the surface; A germanium wafer is prepared, and after hydrogen ion implantation, a germanium thin film layer, a germanium defect-enriched layer, a germanium cracked layer and a residual germanium substrate are formed on the surface of the germanium wafer; Bonding a germanium wafer to the surface of the upper insulating substrate layer, and retaining only the germanium thin film layer of the germanium wafer by annealing and grinding; Etching the germanium thin film layer to form a germanium substrate growth layer of the light gain part and a germanium absorption layer of the light detection part; Continue to deposit an upper insulating substrate layer, and open a growth window in the optical gain portion for growing a compound semiconductor active layer on the germanium substrate growth layer; The insulating substrate layer is continuously deposited, and a via electrode and a contact electrode are formed.

3. The preparation method according to claim 2, characterized in that: The impurity doping concentration of the germanium wafer should be 10 16 cm -3 ~5×10 16 cm -3 The doping type is n-type or p-type, and the surface roughness should be within 0.5nm / 100μm 2 the following.

4. The preparation method according to claim 2, characterized in that: The preparation process of the germanium wafer is specifically as follows: Cleaning and drying the germanium wafer; depositing an oxide layer film on the germanium wafer to form a protective layer; Hydrogen ion implantation was performed on the germanium wafer at room temperature with an implantation angle of 7° and an implantation dose of 4×10 16 cm -3 ~1×10 17 cm -3 , injection energy is 60keV~250keV, injection beam current is less than or equal to 1000μA / cm 2 ; After the implantation is completed, the germanium wafer is cleaned and dried again to obtain a finished germanium wafer.

5. The preparation method according to claim 4, characterized in that: The cleaning and drying are specifically as follows: using a buffered hydrofluoric acid solution or a diluted hydrofluoric acid solution to clean the oxide layer on the surface of the germanium wafer for 3 to 5 minutes; after the acid cleaning is completed, cleaning is performed in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface; after the water washing is completed, nitrogen blowing or vacuum back adsorption and drying are used to remove the surface ultrapure water.

6. The preparation method according to claim 2, characterized in that: The bonding process of the germanium wafer is specifically as follows: The surface of the germanium wafer and the surface of the upper insulating substrate layer are processed, specifically: a thin film of an oxide layer having a thickness of several nanometers is deposited on the surface of the germanium wafer and the upper insulating substrate layer, or the surface of the germanium wafer and the upper insulating substrate layer is activated by plasma, and the gas atmosphere is nitrogen or oxygen with argon as a carrier; After surface treatment, the germanium wafer and the upper insulating substrate layer are pre-bonded; Strengthen the bond energy of the electro-optical modulation chip formed by pre-bonding; In a vacuum environment, the germanium wafer is uniformly heated until the temperature rises to 300°C to 400°C for annealing, and is maintained for a sufficiently long time until the germanium cracked layer and the residual germanium substrate are peeled off; The germanium defect-rich layer on the surface is removed by grinding, and the germanium thin film layer is retained; Annealing is performed again in a vacuum environment at a temperature of 500 to 550° C. for 10 to 60 minutes to further repair the remaining defects in the germanium thin film layer.

7. The preparation method according to claim 6, characterized in that: The bond energy enhancement is specifically: applying 5-20N / cm to the electro-optic modulation chip longitudinally 2 The uniform pressure is less than 10 -5 mbar vacuum atmosphere and ambient temperature of 150℃~250℃, slowly heating up and maintaining for 0.5~2 hours and then slowly cooling down, so that the bond energy is enhanced to more than 2J / m 2 .

8. The preparation method according to claim 6, characterized in that: The annealing method for stripping the germanium cracking layer and the residual germanium substrate is as follows: when the size of the electro-optic modulation chip is less than or equal to 6 inches, a furnace tube heating annealing method is adopted; when the size of the electro-optic modulation chip is greater than 6 inches, a laser annealing method is adopted.

9. The preparation method according to claim 2, characterized in that: The etching of the germanium thin film layer is specifically as follows: For the optical gain part, the thickness of the germanium thin film layer is reduced, and a germanium substrate growth layer is formed by photolithography and etching to facilitate the growth of the compound semiconductor active layer; For the light modulation part, the germanium thin film layer needs to be completely etched; For the light detection part, the germanium thin film layer is used as the light absorption layer. First, the germanium absorption layer is formed by photolithography and etching, and then a pn junction is formed by doping or a photodetector is formed by forming interdigitated electrodes.

10. The preparation method according to claim 2, characterized in that: In the optical gain part, a growth window is opened by etching the upper insulating substrate layer on the germanium substrate growth layer. It is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and a compound semiconductor active layer is grown.

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