Data processing method, apparatus and device, and storage medium and distributed cluster

Abstract

The present application relates to the technical field of computers. Specifically, disclosed are a data processing method, apparatus and device, and a storage medium and a distributed cluster. On the basis of a compute express link protocol, the memory of a first accelerator installed on a host becomes a shared memory; after a host controller receives a calculation task, the control right of the shared memory is first switched to a sender device, such that the sender device writes into the shared memory data to be processed of the calculation task, and the control right is then switched to a second accelerator installed on the host, such that the second accelerator reads said data from the shared memory to complete the calculation task; and the control right of the shared memory is then switched to the sender device or the host controller, such that the sender device or the host controller reads a calculation result of the calculation task from the shared memory. Therefore, in an accelerator solution, data input and data output are both directly performed on the basis of a shared memory, and there is no need to move between a host memory and an accelerator memory, thereby shortening data import and export paths, and improving the data processing efficiency of the accelerator solution.

Description

Data processing method, device, equipment, storage medium and distributed cluster

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 25, 2023, with application number 202311386368.1, and application name “A data processing method, device, equipment, storage medium and distributed cluster”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a data processing method, apparatus, device, storage medium, and distributed cluster. Background Art

[0004] With the development of artificial intelligence, large-scale computing scenarios are increasing, and the computing power requirements of devices are becoming increasingly higher. Therefore, the solution of installing accelerators on host devices as coprocessors for the central processing unit (CPU) has become a widely used technology. For example, the powerful graphics processing unit (GPU) can process multiple data sets simultaneously, significantly improving the computing efficiency of the device.

[0005] However, the current solution of using coprocessors to enhance the computing power of the host requires importing or exporting through the host memory, whether the sending device writes the data to be processed locally or feeds back the calculation results of the computing task to the sending device of the computing task. That is, the solution of coprocessors accelerating the calculation of host devices adds a data transmission path, which has become the current bottleneck of this coprocessor acceleration solution.

[0006] How to further improve the computing efficiency of the host's solution of utilizing a coprocessor for acceleration is a technical problem that those skilled in the art need to solve.

[0007] Summary of the Invention

[0008] The present application provides a data processing method, applied to a host controller, comprising:

[0009] In response to receiving the computing task, switching control of the shared memory of the first accelerator installed in the host to the sender device of the computing task based on the computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on the remote direct data access protocol;

[0010] Switching control of the shared memory to a second accelerator installed in the host based on a computer fast interconnection protocol, so that the second accelerator reads data to be processed from the shared memory to perform a computing task, and writes the computing result to the shared memory;

[0011] In response to the second accelerator completing the computing task, the control of the shared memory is switched to the sending device based on the computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, or the control of the shared memory is switched to the host controller based on the computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory.

[0012] In some implementations, switching control of a shared memory to a sending device based on a computer express interconnect protocol includes:

[0013] enabling a remote direct data access channel of the first accelerator based on a computer rapid interconnection protocol, so as to connect the sending device to the shared memory based on the remote direct data access channel;

[0014] Switching the control of the shared memory to the second accelerator based on a computer fast interconnection protocol includes:

[0015] Enabling a channel from the first accelerator to the second accelerator based on a computer rapid interconnection protocol, so as to connect the second accelerator to the shared memory based on the channel to the second accelerator;

[0016] Switching the control of shared memory to the host controller based on the computer's fast interconnect protocol includes:

[0017] A channel from the first accelerator to the host controller is enabled based on a computer rapid interconnection protocol, so as to connect the host controller to the shared memory based on the channel to the host controller.

[0018] In some other implementations, switching control of the shared memory to the sending device based on a computer rapid interconnect protocol includes:

[0019] The remote direct data access module of the host is enabled, and the first accelerator is controlled based on the computer rapid interconnection protocol to connect the shared memory to the remote direct data access module, so as to connect the sending device to the shared memory based on the remote direct data access module.

[0020] In some implementations, switching control of a shared memory to a sending device based on a computer express interconnect protocol includes:

[0021] Configuring parameters of a channel selection register of a shared memory in the first accelerator based on a computer rapid interconnection protocol to switch control of the shared memory to a sending device;

[0022] Switching the control of the shared memory to the second accelerator based on a computer fast interconnection protocol includes:

[0023] Based on a computer rapid interconnection protocol, configuring parameters of a channel selection register of a shared memory in the first accelerator to switch control of the shared memory to the second accelerator;

[0024] Switching the control of shared memory to the host controller based on the computer's fast interconnect protocol includes:

[0025] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch control of the shared memory to the host controller.

[0026] In some implementations, configuring parameters of a channel select register of a shared memory in the first accelerator based on a computer rapid interconnect protocol to switch control of the shared memory to the sending device includes:

[0027] Based on a computer rapid interconnection protocol, configuring parameters of a channel selection register of a shared memory in the first accelerator to enable a first data input / output channel corresponding to the sending device, and disable a second data input / output channel corresponding to the second accelerator and a third data input / output channel corresponding to the host controller;

[0028] Configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnection protocol to switch control of the shared memory to a second accelerator includes:

[0029] Based on a computer rapid interconnection protocol, configuring parameters of a channel selection register of a shared memory in the first accelerator to enable a second data input / output channel corresponding to the second accelerator, and to disable a first data input / output channel corresponding to the sending device and a third data input / output channel corresponding to the host controller;

[0030] Configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnection protocol to switch control of the shared memory to a host controller includes:

[0031] Based on the computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to open the third data input and output channel corresponding to the host controller, and close the first data input and output channel corresponding to the sending device and the second data input and output channel corresponding to the second accelerator.

[0032] In some other implementations, configuring parameters of a channel selection register of a shared memory in the first accelerator based on a computer rapid interconnect protocol to switch control of the shared memory to a sending device includes:

[0033] Based on a computer rapid interconnection protocol, a parameter of a channel selection register of a shared memory in the first accelerator is configured to switch a three-select-one channel switching switch in the first accelerator to connect the sending device to the shared memory;

[0034] Configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnection protocol to switch control of the shared memory to a second accelerator includes:

[0035] Based on a computer fast interconnection protocol, a parameter of a channel selection register of a shared memory in the first accelerator is configured to switch a three-to-one channel switching switch in the first accelerator to connect the second accelerator to the shared memory;

[0036] Configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnection protocol to switch control of the shared memory to a host controller includes:

[0037] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch a three-to-one channel switch in the first accelerator to connect the host controller to the shared memory.

[0038] In some implementations, the shared memory is provided with a command buffer, so that the sending device, the host controller, and the second accelerator write read and write commands to the shared memory into the command buffer when they do not have control over the shared memory.

[0039] In some implementations, the command buffer includes a first command buffer corresponding to the sending device, a second command buffer corresponding to the second accelerator, and a third command buffer corresponding to the host controller;

[0040] When the sending device, the host controller, and the second accelerator do not have control over the shared memory, they write the read and write commands for the shared memory into the command buffer, including:

[0041] When the sending device, host controller and second accelerator do not have control over the shared memory, they will write the read and write commands of the shared memory into the corresponding command buffer. If the corresponding command buffer is full, the read and write commands will be overwritten with the read and write commands with the earliest writing time in the corresponding command buffer.

[0042] In some implementations, the method further includes:

[0043] The size of the first command buffer area, the size of the second command buffer area, and the size of the third command buffer area are configured according to the operating environment of the host.

[0044] In some implementations, after the sending device, the host controller, and the second accelerator obtain control of the shared memory, they check the command buffer. If the command buffer stores unexecuted read and write commands sent locally, they execute new read and write commands after executing the unexecuted read and write commands.

[0045] In some implementations, when the sending device, the host controller, and the second accelerator do not have control over the shared memory, they write the read and write commands to the shared memory into a local command buffer.

[0046] In some implementations, the second accelerator reads the to-be-processed data from the shared memory to perform the computing task, and writes the computing result to the shared memory, including:

[0047] The second accelerator reads the data to be processed from the shared memory into the local cache, inputs the data to be processed into the pre-deployed kernel model, obtains the calculation result, and writes the calculation result into the shared memory;

[0048] The kernel model is that the host controller writes to the shared memory after the host controller switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol.

[0049] In some implementations, in response to receiving a computing task, switching control of a shared memory of a first accelerator installed in a host to a sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes to-be-processed data of the computing task to the shared memory based on a remote direct data access protocol, includes:

[0050] In response to receiving a processing request for a computing task, configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a first data input / output channel corresponding to the remote direct data access network port, and configuring the remote direct data access network port based on the computer rapid interconnection protocol to enable the remote direct data access network port to receive and write data to be processed into the shared memory;

[0051] Switching control of the shared memory to a second accelerator installed in the host based on a computer fast interconnection protocol, so that the second accelerator reads data to be processed from the shared memory to perform a computing task, and writes the computing result to the shared memory, including:

[0052] Configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a third data input / output channel of the corresponding host controller, so as to write a kernel model corresponding to the computing task into the shared memory based on the third data input / output channel;

[0053] configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a second data input / output channel corresponding to the second accelerator, so that the second accelerator reads the kernel model and the data to be processed from the shared memory into a local cache through the second data input / output channel to perform a computing task, and writes the computing result to the shared memory based on the second data input / output channel after obtaining the computing result;

[0054] In response to the second accelerator completing the computing task, switching control of the shared memory to the sending device based on the computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, including:

[0055] In response to receiving information feedback from the second accelerator indicating that the computing task has been completed, configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable the first data input and output channel, and configuring a remote direct data access network port based on the computer rapid interconnection protocol to enable the sending device to read the computing result from the shared memory based on the remote direct data access protocol;

[0056] Switching the control of the shared memory to the host controller based on a computer fast interconnection protocol so that the host controller reads the calculation results from the shared memory, including:

[0057] In response to receiving information that the second accelerator has completed the computing task, the channel selection register of the shared memory is configured based on the computer rapid interconnection protocol to enable the third data input and output channel, so as to read the computing result from the shared memory to the host controller based on the third data input and output channel.

[0058] In some implementations, the first accelerator is a field programmable gate array that supports the Computer Express Interconnect protocol and has extended memory, or an application-specific integrated circuit device that supports the Computer Express Interconnect protocol and has extended memory, and the second accelerator is a graphics processor, with the extended memory serving as the shared memory of the first accelerator.

[0059] In some implementations, multiple graphics processors share the same shared memory of the first accelerator.

[0060] The present application also provides a data processing method, applied to a first accelerator of a host, comprising:

[0061] In response to receiving a first switching command sent by a host controller of the host based on a computer rapid interconnection protocol, switching control of the shared memory of the first accelerator to a sender device of the computing task, so that the sender device writes to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol;

[0062] In response to receiving a second switching command sent by the host controller based on the computer rapid interconnection protocol, switching control of the shared memory to a second accelerator installed in the host, so that the second accelerator reads the data to be processed from the shared memory to perform the computing task, and writes the computing result to the shared memory;

[0063] In response to receiving a first switching command sent by the host controller based on a computer rapid interconnection protocol when the second accelerator completes a computing task, the control of the shared memory of the first accelerator is switched to the sending device, so that the sending device reads the computing result from the shared memory based on a remote direct data access protocol; or, in response to receiving a third switching command sent by the host controller based on a computer rapid interconnection protocol when the second accelerator completes a computing task, the control of the shared memory of the first accelerator is switched to the host controller, so that the host controller reads the computing result from the shared memory.

[0064] In some implementations, the shared memory is provided with a command buffer, so that the sending device, the host controller, and the second accelerator write read and write commands to the shared memory into the command buffer when they do not have control over the shared memory.

[0065] The present application also provides a data processing method, which is applied to a second accelerator of a host, comprising:

[0066] In response to receiving a computing task start signal and obtaining control of a shared memory of a first accelerator installed in the host, reading to-be-processed data of the computing task from the shared memory to execute the computing task and write computing results to the shared memory;

[0067] In response to the completion of the computing task, notifying the host controller of information that the computing task is completed, so that the host controller switches the control right of the shared memory to the sender device of the computing task based on the computer rapid interconnection protocol so that the sender device reads the computing result from the shared memory based on the remote direct data access protocol, or switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory;

[0068] The data to be processed is data written to the shared memory by the sending device based on the remote direct data access protocol after the host controller switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol.

[0069] The present application also provides a data processing device, comprising a host controller, a first accelerator, and a second accelerator;

[0070] The first accelerator establishes a computer fast interconnection channel with the host controller based on a computer fast interconnection protocol to realize a shared memory of the first accelerator;

[0071] The host controller is used to, upon receiving a computing task, switch control of the shared memory to a sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol; switch control of the shared memory to the second accelerator based on the computer rapid interconnection protocol, so that the second accelerator reads the to-be-processed data from the shared memory to perform the computing task and writes the computing result into the shared memory; in response to the second accelerator completing the computing task, switch control of the shared memory to the sender device based on the computer rapid interconnection protocol, so that the sender device reads the computing result from the shared memory based on the remote direct data access protocol, or switch control of the shared memory to the host controller based on the computer rapid interconnection protocol, so that the host controller reads the computing result from the shared memory.

[0072] The present application also provides a distributed cluster, comprising a plurality of data processing devices as described above.

[0073] The present application also provides a data processing device, applied to a host controller, comprising:

[0074] a task receiving control unit, configured to, in response to receiving a computing task, switch control of a shared memory of a first accelerator installed in the host to a sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol;

[0075] a computing control unit, configured to switch control of the shared memory to a second accelerator installed in the host based on a computer rapid interconnection protocol, so that the second accelerator reads data to be processed from the shared memory to perform computing tasks, and writes computing results to the shared memory;

[0076] The result acquisition control unit is used to switch the control of the shared memory to the sending device based on the computer rapid interconnection protocol in response to the second accelerator completing the computing task, so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, or switch the control of the shared memory to the host controller based on the computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory.

[0077] The present application also provides a data processing device, comprising:

[0078] a memory for storing computer-readable instructions;

[0079] The processor is used to execute computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps of any of the above-mentioned data processing methods are implemented.

[0080] The present application also provides one or more non-volatile computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, enable the one or more processors to perform the steps of any one of the above-mentioned data processing methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0082] FIG1 is a schematic diagram of a scenario in which host computing is accelerated based on a graphics processor;

[0083] FIG2 is a schematic diagram of the structure of a data processing device provided by one or more embodiments of the present application;

[0084] FIG3 is a schematic diagram of a data processing scenario based on a data processing device provided by one or more embodiments of the present application;

[0085] FIG4 is a flow chart of a data processing method provided by one or more embodiments of the present application;

[0086] FIG5 is a flowchart of another data processing method provided by one or more embodiments of the present application;

[0087] FIG6 is a flowchart of another data processing method provided by one or more embodiments of the present application;

[0088] FIG7 is a schematic structural diagram of a data processing device provided by one or more embodiments of the present application;

[0089] FIG8 is a schematic structural diagram of another data processing device provided by one or more embodiments of the present application. DETAILED DESCRIPTION

[0090] The core of this application is to provide a data processing method, device, equipment, storage medium and distributed cluster for improving the computing efficiency of the host using a coprocessor acceleration solution.

[0091] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0092] The following describes the first embodiment of the present application.

[0093] Figure 1 is a schematic diagram of a scenario for host computing acceleration based on a graphics processor; Figure 2 is a structural schematic diagram of a data processing device provided in an embodiment of the present application; Figure 3 is a schematic diagram of a data processing scenario based on a data processing device provided in an embodiment of the present application.

[0094] To facilitate understanding, the data processing device provided in the embodiments of the present application is first introduced.

[0095] As shown in Figure 1, a graphics processing unit (GPU) is used as a coprocessor for a host controller. In traditional coprocessor acceleration solutions, the host controller is typically a central processing unit (CPU), which serves as the center for controlling computing tasks. The coprocessor is installed on the host's high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe) interface, connecting the host controller and the GPU via the high-speed serial computer expansion bus. The complete process of executing a computing task mainly includes:

[0096] S101: The host controller receives the data to be processed provided by the sender device (data acquisition server) through the Remote Direct Memory Access (RDMA) network port and stores it into the host memory;

[0097] S102: The host controller controls the copying of the data to be processed in the host memory to the graphics processor memory;

[0098] S103: The host controller deploys a kernel program (kernel model) corresponding to the computing task in the application computing logic core of the graphics processor; this step has no sequential relationship with S102;

[0099] S104: The application computing logic core of the graphics processor reads the data to be processed from the graphics processor memory and inputs it into the kernel program for calculation to obtain a calculation result;

[0100] S105: The application computing logic core of the graphics processor stores the computing result into the graphics processor memory;

[0101] S106: The host controller copies the calculation result from the graphics processor memory to the host memory.

[0102] It can be seen that although remote direct data access technology is used to achieve rapid data transmission between the sending device and the host, when executing computing tasks in the host, the input and output data need to be moved between the host memory and the coprocessor memory, and the data transmission path is long, which is a bottleneck affecting the efficiency of the coprocessor accelerated computing solution.

[0103] To further improve the computing efficiency of a host computer utilizing a coprocessor for acceleration, as shown in FIG2 , an embodiment of the present application provides a data processing device including a host controller, a first accelerator, and a second accelerator;

[0104] The first accelerator establishes a computer fast interconnection channel with the host controller based on a computer fast interconnection protocol to realize a shared memory of the first accelerator;

[0105] The host controller is used to, upon receiving a computing task, switch control of the shared memory to a sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol; switch control of the shared memory to the second accelerator based on the computer rapid interconnection protocol, so that the second accelerator reads the to-be-processed data from the shared memory to perform the computing task and writes the computing result into the shared memory; in response to the second accelerator completing the computing task, switch control of the shared memory to the sender device based on the computer rapid interconnection protocol, so that the sender device reads the computing result from the shared memory based on the remote direct data access protocol, or switch control of the shared memory to the host controller based on the computer rapid interconnection protocol, so that the host controller reads the computing result from the shared memory.

[0106] It should be noted that, in each embodiment of the present application, the first accelerator is defined as an accelerator device that supports a computer rapid interconnection protocol and has a memory storage device that can be used as a shared memory. The second accelerator is an accelerator device for actually performing a computing task. In practical applications, the first accelerator and the second accelerator on the host can be the same accelerator or different accelerators. The first accelerator can adopt one or more of a field programmable gate array (FPGA), an application specific integrated circuit device (ASIC), and the second accelerator can adopt one or more of a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit device (ASIC), and a processor distributed processing unit device (Data Processing Unit, DPU). In each embodiment of the present application, the host controller can refer to a central processing unit (CPU), or it can be other types of controllers for controlling the entire computing process.

[0107] In order to realize the memory of the first accelerator as the shared memory of the sending device, the host controller and the second accelerator, it is necessary not only to establish a computer fast interconnection channel between the first accelerator and the host controller based on the computer fast interconnection protocol, but also to establish a remote direct data access channel between the host and the sending device based on the remote direct data access protocol. In this way, the sending device can write data directly into the shared memory of the host without going through the main line memory, and the host controller and the second accelerator can both directly access the shared memory to obtain data without moving it between the host memory and the memory of the second accelerator.

[0108] Compute Express Link (CXL) is a high-speed interconnect technology designed to provide high-performance, low-latency, and high-concurrency connectivity and data transfer capabilities. The CXL specification defines three types of devices suitable for the CXL protocol: (1) devices that want to cache data in the CPU's main memory locally. In this case, the device only needs to use the CXL.I / O protocol and the CXL.cache protocol; (2) devices that have memory on an accelerator and want to interact between the CPU and the accelerator. Therefore, the CXL.I / O protocol is used to allow the CPU to discover and configure the device, and then the CXL.cache protocol is used to allow the device to access the CPU's memory and the CXL.mem protocol is used to allow the CPU to access the device's memory; (3) memory buffers. In this case, the CXL.I / O protocol is needed to discover and configure the device, and the CXL.mem protocol is used to allow the CPU and other processors to access the memory connected to the memory buffer. Among them, the third type of computer rapid interconnect device (Type 3) can expand the memory under the computer rapid interconnect protocol, allowing the host controller to use the device's memory without distinction. In the embodiment of the present application, the remote sending device is also required to use the shared memory of the first accelerator. Therefore, the host controls the remote direct data access network port and the shared memory of the first accelerator through the computer rapid interconnect bus, so that these two modules can operate under the control of the host controller.

[0109] As shown in Figure 2, the host 201 and the sending device 202 for providing the data to be processed for the computing task are connected based on remote direct data access. Specifically, they communicate through the remote direct data access network ports of both parties to realize direct memory-to-memory data transmission between the host 201 and the sending device 202.

[0110] In the host 201, a first accelerator that supports a computer rapid interconnection protocol and can provide shared memory is used, and its core is logically divided to obtain a computer rapid interconnection module for controlling the shared memory and a remote direct data access module for connecting to the remote direct data access network port of the host. Based on the computer rapid interconnection module, a computer rapid interconnection channel is established from the host controller to the first accelerator, so that the host controller can realize switching control of the control right of the shared memory based on the computer rapid interconnection channel. The control right of the shared memory mainly determines the read operation, write operation and other parameter configuration of the shared memory (such as dividing the storage area size to perform specific data storage operations). In order to maintain memory consistency, it should be set that only one subject (sender device, second accelerator or host controller) can write to the data storage area of ​​the shared memory at the same time. In the first accelerator, the computer rapid interconnection module and the remote direct data access module can be connected to the shared memory through a memory mapped bus (AVMM bus) respectively.

[0111] The host controller and the second accelerator are connected via a high-speed serial computer expansion bus, and the second accelerator and the shared memory of the first accelerator are connected via a memory storage interface (such as a double-data-rate synchronous dynamic random access memory (DDR) interface). The second accelerator performs a computing task, and it is necessary to deploy a kernel program (kernel model) corresponding to the computing task in the application computing kernel of the second accelerator, so as to perform calculations based on the pending data of the computing task provided by the sending device. In actual applications, the kernel program is usually provided by the host controller, and the pending data of the computing task is provided by the remote sending device. After deploying the kernel model with configured kernel parameters, the second accelerator inputs the pending data into the kernel model to perform the computing task and obtain the calculation results.

[0112] As shown in FIG3 , the complete process of executing a computing task using the data processing device provided in the embodiment of the present application mainly includes:

[0113] S301: The host switches the control right of the shared memory to the first data input / output channel connecting the remote direct data access channel and the shared memory through the computer fast interconnection module;

[0114] S302: The remote sender device writes the to-be-processed data of the computing task into the shared memory of the host based on the remote direct data access protocol;

[0115] S303: The host switches control of the shared memory to the third data input / output channel between the host controller and the shared memory through the computer fast interconnection channel, and writes the kernel program (kernel model) corresponding to the computing task into the shared memory based on the second data input / output channel.

[0116] Alternatively, S304: the host controller deploys a kernel program (kernel model) corresponding to the computing task in the application computing logic core of the second accelerator; either this step or S304 is selected;

[0117] S305: The host switches the control right of the shared memory to the second data input / output channel between the second accelerator and the shared memory through the computer fast interconnection channel;

[0118] S306: The second accelerator reads the data to be processed (and the kernel program) from the shared memory, and after deploying the kernel program with configured kernel parameters, inputs the data to be processed into the kernel program to execute the computing task and obtain a computing result;

[0119] S307: The second accelerator writes the calculation result into the shared memory.

[0120] The host controller interacts with the second accelerator to monitor the second accelerator's performance of the computing task. For example, the second accelerator can be designed to send an interrupt signal to the host controller after completing the computing task. After receiving the interrupt signal from the second accelerator, the host controller determines that the second accelerator has completed the computing task. The host controller can then control the shared memory by switching control back to the first data input / output channel via the computer's fast interconnect channel and notify the sending device to read the computing results in the shared memory via the first data input / output channel. Alternatively, the host controller can control the shared memory by switching control back to the host controller based on the computer's fast interconnect channel, thereby connecting a third data input / output channel between the host controller and the shared memory, allowing the host controller to read the computing results from the shared memory.

[0121] By using the data processing device provided in the embodiments of the present application, during the transmission of input data and input / output data related to the computing task, there is no need to move data between the host memory and the memory of the second accelerator used to execute the computing task. That is, data input and output in the accelerator solution are directly based on shared memory, which significantly shortens the path of data import and export, thereby improving the data processing efficiency of the accelerator solution.

[0122] On this basis, to prevent the sending device, host controller, or second accelerator from generating read and write requests to the shared memory when it has not yet obtained control of the shared memory, a command buffer area can be divided in the shared memory to cache the read and write commands of the sending device, host controller, and second accelerator to the shared memory when it does not have control of the shared memory. For balanced management, the command buffer area can be divided into a first command buffer area corresponding to the sending device, a second command buffer area corresponding to the second accelerator, and a third command buffer area corresponding to the host controller. The overall size of the command buffer area or the size of each command buffer area can be configured according to the control environment of the host. When the sending device, host controller, and second accelerator obtain control of the shared memory, they can first check whether the corresponding command buffer area stores any locally sent unexecuted read and write commands. If so, they will execute the unexecuted read and write commands before executing new read and write commands.

[0123] The second embodiment of the present application is described below.

[0124] On the basis of the above embodiments, the embodiments of the present application further provide a distributed cluster, which includes multiple data processing devices as described in the above embodiments. Remote direct data access channels can be established between each data processing device to achieve mutual data forwarding and load balancing. Furthermore, computer fast interconnection channels can be established between each data processing device based on a computer fast interconnection protocol to further improve the data forwarding efficiency and load balancing efficiency between data processing devices. When facing large-scale computing scenarios, a remote sending device distributes multiple computing tasks to each host in the distributed cluster. When each host is executing a planned task, it can offload the computing task to other hosts through load balancing when the load is heavy.

[0125] Based on the architecture of the above-mentioned data processing device, the data processing method provided in the embodiment of the present application is described below with reference to the accompanying drawings.

[0126] The third embodiment of the present application is described below.

[0127] FIG4 is a flow chart of a data processing method provided in an embodiment of the present application; FIG5 is a flow chart of another data processing method provided in an embodiment of the present application.

[0128] As shown in FIG4 , the data processing method provided by the embodiment of the present application, applied to a host controller, includes:

[0129] S401: When a computing task is received, control of a shared memory of a first accelerator installed in a host computer is switched to a sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol;

[0130] S402: Switching control of the shared memory to a second accelerator installed in the host based on a computer rapid interconnection protocol, so that the second accelerator reads data to be processed from the shared memory to perform a computing task, and writes the computing result to the shared memory;

[0131] S403: When the second accelerator completes the computing task, the control of the shared memory is switched to the sending device based on the computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, or the control of the shared memory is switched to the host controller based on the computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory. In an embodiment of the present application, as described in the above embodiment of the present application, the first accelerator is an accelerator device that supports the computer rapid interconnection protocol and has a memory storage device that can be used as a shared memory, and can adopt one or more of a field programmable gate array (FPGA) and an application specific integrated circuit device (ASIC). The second accelerator is an accelerator device for actually performing computing tasks, and can adopt one or more of a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit device (ASIC), and a processor distributed processing unit device (DPU). The host controller may refer to a central processing unit (CPU) or other types of controllers for controlling the entire computing process. In practical applications, the first accelerator and the second accelerator may be the same accelerator or different accelerators.

[0132] In practical applications, the first accelerator can be a field programmable gate array that supports the Computer Rapid Interconnect Protocol and has extended memory, or a dedicated integrated circuit device that supports the Computer Rapid Interconnect Protocol and has extended memory, the second accelerator is a graphics processor, and the extended memory is used as the shared memory of the first accelerator.

[0133] In various embodiments of the present application, in combination with the size of the shared memory that can be provided by the first accelerator and the computing requirements of the second accelerator, multiple graphics processors can be configured to share the shared memory of the same first accelerator.

[0134] The above embodiment describes how to implement the first accelerator's memory as shared memory for the sending device, the host controller, and the second accelerator. This requires not only a fast computer interconnection channel based on a fast computer interconnection protocol between the first accelerator and the host controller, but also a remote direct data access channel based on a remote direct data access protocol between the host and the sending device. To implement remote direct data access, a connection can be established between the first accelerator's built-in remote direct data access module and the host's remote direct data access network port, or between the first accelerator and an external remote direct data access module, which in turn connects to the remote direct data access network port.

[0135] The data processing method provided in the above embodiment realizes that the memory of the first accelerator installed on the host becomes a shared memory based on the computer rapid interconnection protocol, so that when the host controller receives a computing task, the control of the shared memory is first switched to the sending device, so that the sending device writes the to-be-processed data of the computing task into the shared memory, and then the control is switched to the second accelerator installed on the host, so that the second accelerator reads the to-be-processed data from the shared memory to complete the computing task, and then the control of the shared memory is switched to the sending device or the host controller to read the calculation result of the computing task from the shared memory, so that the data input and output in the accelerator scheme are directly based on the shared memory, without the need to move between the host memory and the accelerator memory, thereby shortening the data import and export path, thereby improving the data processing efficiency of the accelerator scheme.

[0136] In conjunction with the data processing device provided in FIG2 , as shown in FIG5 , based on the host controller, the first accelerator, and the second accelerator, the data processing method provided in the embodiment of the present application includes:

[0137] S501: When receiving a computing task, the host controller switches the control right of the shared memory of the first accelerator to the sending device based on the computer rapid interconnection protocol;

[0138] S502: The sending device writes the to-be-processed data of the computing task to the shared memory based on the remote direct data access protocol;

[0139] S503: The host controller switches the control right of the shared memory of the first accelerator to the second accelerator based on the computer rapid interconnection protocol;

[0140] S504: The second accelerator reads the data to be processed from the shared memory, performs the computing task, and writes the computing result into the shared memory;

[0141] S505: When the second accelerator completes the computing task, the host controller switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol;

[0142] S506: The sending device reads the calculation result from the shared memory based on the remote direct data access protocol;

[0143] S507: When the second accelerator completes the computing task, the host controller switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol;

[0144] S508: The host controller reads the calculation result from the shared memory.

[0145] It should be noted that S505, S506 and S507, S508 are executed in a selective manner.

[0146] If the first accelerator has a remote direct data access module, then in S401, the control of the shared memory is switched to the sending device based on the computer rapid interconnection protocol, including: enabling the remote direct data access channel of the first accelerator based on the computer rapid interconnection protocol, so as to connect the sending device to the shared memory based on the remote direct data access channel. In S402, the control of the shared memory is switched to the second accelerator based on the computer rapid interconnection protocol, including: enabling the channel of the first accelerator to the second accelerator based on the computer rapid interconnection protocol, so as to connect the second accelerator to the shared memory based on the channel to the second accelerator. In S403, the control of the shared memory is switched to the host controller based on the computer rapid interconnection protocol, including: enabling the channel of the first accelerator to the host controller based on the computer rapid interconnection protocol, so as to connect the host controller to the shared memory based on the channel to the host controller.

[0147] If the remote direct data access module is based on the host, then in S401, the control of the shared memory is switched to the sending device based on the computer rapid interconnection protocol, including: enabling the remote direct data access network port of the host, and controlling the first accelerator based on the computer rapid interconnection protocol to connect the shared memory to the remote direct data access network port, so as to connect the sending device to the shared memory based on the remote direct data access network port.

[0148] For S401, when the host controller receives information about the computing task sent by the remote sending device, the computer fast interconnection channel composed of the computer fast interconnection module switches the control of the shared memory of the first accelerator to the sending device, so that the sending device writes the to-be-processed data of the computing task into the shared memory based on the remote direct data access protocol.

[0149] For S402, after determining that the sending device has completed writing the data to be processed, the host controller switches control of the shared memory to the second accelerator based on the computer's fast interconnect channel, allowing the second accelerator's application computing logic core to read the data to be processed from the shared memory, execute the computing task, and obtain the computing result. To be able to execute the computing task, the second accelerator must have pre-deployed a kernel program corresponding to the computing task. The host controller can then write the kernel program to the second accelerator's memory via a high-speed serial computer expansion bus for the second accelerator's application computing logic core to read. Alternatively, the host controller switches control of the shared memory to the host controller based on the computer's fast interconnect channel, and then the host controller writes the kernel program to the shared memory, allowing the second accelerator to read both the kernel program and the data to be processed from the shared memory.

[0150] In S402, the second accelerator reads the data to be processed from the shared memory to perform the computing task, and writes the computing result into the shared memory, which may include: the second accelerator reads the data to be processed from the shared memory to the local cache, inputs the data to be processed into a pre-deployed kernel model, obtains the computing result, and writes the computing result into the shared memory; wherein, the kernel model is written to the shared memory by the host controller after the host controller switches the control of the shared memory to the host controller based on the computer rapid interconnection protocol.

[0151] In S403, the host controller interacts with the second accelerator to monitor the second accelerator's performance of the computing task. For example, the second accelerator can be designed to send an interrupt signal to the host controller after completing the computing task. After receiving the interrupt signal from the second accelerator, the host controller determines that the second accelerator has completed the computing task. The host controller can then control the shared memory by switching control back to the first data input / output channel via the computer's fast interconnect channel and notify the sending device to read the computing results in the shared memory via the first data input / output channel. Alternatively, the host controller can control the shared memory by switching control back to the host controller based on the computer's fast interconnect channel, thereby connecting a third data input / output channel between the host controller and the shared memory, allowing the host controller to read the computing results from the shared memory.

[0152] It should be noted that in addition to configuring the control of the shared memory through the computer's fast interconnection channel, the host controller can also read and write the shared memory based on the computer's fast interconnection channel after obtaining control of the shared memory. That is, when the host controller does not have control of the shared memory, the host controller still controls the switching of control of the shared memory.

[0153] The data processing method provided in the embodiment of the present application realizes that the memory of the first accelerator installed in the host becomes a shared memory based on the computer rapid interconnection protocol, so that when the host controller receives a computing task, the control of the shared memory is first switched to the sending device, so that the sending device writes the to-be-processed data of the computing task into the shared memory, and then the control is switched to the second accelerator installed in the host, so that the second accelerator reads the to-be-processed data from the shared memory to complete the computing task, and then the control of the shared memory is switched to the sending device or the host controller to read the computing result of the computing task from the shared memory, so that the data input and output in the accelerator scheme are directly based on the shared memory, without the need to move between the host memory and the accelerator memory, thereby shortening the path of data import and export, thereby improving the data processing efficiency of the accelerator scheme.

[0154] The fourth embodiment of the present application is described below.

[0155] Based on the above embodiments, the embodiments of the present application further provide a solution for a host controller to control switching of the control right of the shared memory.

[0156] In the data processing method provided in the embodiment of the present application, switching the control of the shared memory to the sending device based on the computer rapid interconnection protocol in S401 may include:

[0157] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch control of the shared memory to a sending device.

[0158] In step S402, switching the control right of the shared memory to the second accelerator based on the computer rapid interconnection protocol may include:

[0159] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch control of the shared memory to the second accelerator.

[0160] In step S403, the control right of the shared memory is switched to the host controller based on the computer rapid interconnection protocol, which may include:

[0161] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch control of the shared memory to the host controller.

[0162] In a specific implementation, please refer to FIG2 . To implement the three-channel selection function for the shared memory, a channel selection register (channel selector) can be deployed in the shared memory to implement the control switching logic of the shared memory.

[0163] The implementation logic of the channel selection register may be to configure a switch of a corresponding data input and output channel. Configuring the parameters of the channel selection register of the shared memory in the first accelerator based on the computer rapid interconnection protocol to switch control of the shared memory to the sending device may include:

[0164] Based on the computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to open the first data input and output channel corresponding to the sending device, and close the second data input and output channel corresponding to the second accelerator and the third data input and output channel corresponding to the host controller.

[0165] Configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnect protocol to switch control of the shared memory to a second accelerator may include:

[0166] Based on the computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to open the second data input and output channel corresponding to the second accelerator, and close the first data input and output channel corresponding to the sending device and the third data input and output channel corresponding to the host controller.

[0167] Configuring parameters of a channel selection register of a shared memory in the first accelerator based on a computer rapid interconnect protocol to switch control of the shared memory to the host controller may include:

[0168] Based on the computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to open the third data input and output channel corresponding to the host controller, and close the first data input and output channel corresponding to the sending device and the second data input and output channel corresponding to the second accelerator.

[0169] That is, the channel selection register internally includes a channel selection register corresponding to each data input / output channel (including the first data input / output channel, the second data input / output channel, and the third data input / output channel). The host controller configures the parameters of the channel selection register corresponding to each data input / output channel (including the first data input / output channel, the second data input / output channel, and the third data input / output channel) to enable only one data input / output channel at a time, thereby allowing the corresponding control entity to obtain read and write rights to the shared memory. The channel selection register is deployed in the shared memory of the first accelerator to configure the on / off state of each data input / output channel, and the host controller controls the on / off state of each data input / output channel by configuring the parameters of the channel selection register.

[0170] The fifth embodiment of the present application is described below.

[0171] Based on the above embodiment, an embodiment of the present application provides another solution for a host controller to control switching of the control right of a shared memory.

[0172] In the data processing method provided in an embodiment of the present application, configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnection protocol to switch control of the shared memory to a sending device may include:

[0173] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch a three-to-one channel switching switch in the first accelerator to connect a sending device to the shared memory.

[0174] Configuring parameters of a channel selection register of a shared memory in a first accelerator based on a computer rapid interconnect protocol to switch control of the shared memory to a second accelerator may include:

[0175] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch a three-to-one channel switching switch in the first accelerator to connect the second accelerator to the shared memory.

[0176] Configuring parameters of a channel selection register of a shared memory in the first accelerator based on a computer rapid interconnect protocol to switch control of the shared memory to the host controller may include:

[0177] Based on a computer rapid interconnection protocol, parameters of a channel selection register of a shared memory in the first accelerator are configured to switch a three-to-one channel switch in the first accelerator to connect the host controller to the shared memory.

[0178] In addition to the above-mentioned embodiment described in which the host controller controls the switching state of each data input and output channel by configuring the parameters of the channel selection register, and the host controller controls the logic of only opening one data input and output channel at the same time, please refer to Figure 2. As described in the embodiment of the present application, a channel selection register (channel selector) can be deployed in the shared memory, and the channel selection register internally includes a channel selection register and a three-to-one channel switching switch. The three first ends of the three-to-one channel switching switch are respectively connected to the sending device, the second accelerator and the host controller, and a second end of the three-to-one channel switching switch is connected to the write interface of the shared memory. Therefore, the host controller only needs to configure the parameters of the channel selection register to set the current on-state of the three-to-one channel switching switch to realize the logic of only opening one data input and output channel at the same time.

[0179] The sixth embodiment of the present application is described below.

[0180] On the basis of the above embodiments, in order to prevent the sending device, host controller or second accelerator from generating read and write requirements for the shared memory when it does not obtain control of the shared memory, and the generated read and write commands cannot be executed and are lost, resulting in data loss, in the data processing method provided in the embodiments of the present application, a command cache area can be set in the shared memory, so that the sending device, host controller and second accelerator will write the read and write commands to the shared memory into the command cache area when they do not have control of the shared memory.

[0181] In a specific implementation, a centralized command buffer can be allocated in the shared memory to cache read and write commands to the shared memory generated by the sending device, host controller, or second accelerator when it does not have control over the shared memory. Because the number of read and write commands generated by each control entity may vary, to prevent some control entities from occupying a large amount of command buffer, a separate command buffer can be set for each control entity, as shown in Figure 2.

[0182] The command buffer may include a first command buffer corresponding to the sending device, a second command buffer corresponding to the second accelerator, and a third command buffer corresponding to the host controller. When the sending device, the host controller, and the second accelerator do not have control over the shared memory, writing the read and write commands of the shared memory into the command buffer may include: when the sending device, the host controller, and the second accelerator do not have control over the shared memory, writing the read and write commands of the shared memory into the corresponding command buffer, and if the corresponding command buffer is full, overwriting the read and write commands with the earliest writing time in the corresponding command buffer.

[0183] In addition, the size of the entire command buffer or the size of the command buffer corresponding to each control entity can be adjusted according to needs. The data processing method provided in the embodiment of the present application can also include: configuring the size of the first command buffer, the size of the second command buffer, and the size of the third command buffer according to the operating environment of the host.

[0184] Furthermore, by executing a delete operation on the read and write commands in the command buffer, expired read and write commands are promptly deleted. Specifically, the channel cache size register in the shared memory can be configured to define the duration for which the first command buffer caches read and write commands, the second command buffer caches read and write commands, and the third command buffer caches read and write commands. For example, the third command buffer can be configured to only cache read and write commands generated by the host controller within the last three days, deleting expired read and write commands.

[0185] Based on this, after the sending device, host controller and second accelerator obtain control of the shared memory, they can first check the command buffer. If the command buffer stores unexecuted read and write commands sent locally, they will execute new read and write commands after executing the unexecuted read and write commands.

[0186] The data processing method provided in the embodiment of the present application, by setting a command buffer area in the shared memory of the first accelerator, can not only enable the sending device, the host controller, and the second accelerator to write the read and write commands to the shared memory to the command buffer area when they do not have control over the shared memory, but also enable the sending device, the host controller, and the second accelerator to have a certain buffering effect at the moment when they lose control of the shared memory, thereby avoiding the loss of read and write commands sent to the shared memory by the sending device, the host controller, or the second accelerator at this time.

[0187] The seventh embodiment of the present application is described below.

[0188] In addition to the aforementioned embodiment of dividing command buffers corresponding to the sender device, host controller, and second accelerator in shared memory, command buffers can also be divided in the local memory of each control entity. In some implementations, when the sender device, host controller, and second accelerator do not have control over the shared memory, they can write read and write commands to the shared memory into the local command buffer. After executing the read and write commands to the shared memory, the corresponding read and write commands in the local command buffer can be deleted.

[0189] When the sending device, the second accelerator, and the control host send read and write commands to the shared memory, they also cache the read and write commands in a pre-allocated command buffer in the local memory to avoid data loss when the control right to the shared memory is not currently in place. When the sending device, the host controller, and the second accelerator do not have control right to the shared memory, they can write the read and write commands to the shared memory to the corresponding command buffer. If the corresponding command buffer is full, the read and write commands will be overwritten with the oldest read and write commands in the corresponding command buffer.

[0190] In addition, the size of the entire command buffer area or the size of the command buffer area corresponding to each control subject can be adjusted according to needs.

[0191] Based on this, after the sending device, host controller and second accelerator obtain control of the shared memory, they can first check the command buffer in the local memory. If the command buffer stores unexecuted read and write commands sent locally, they will execute new read and write commands after executing the unexecuted read and write commands.

[0192] The data processing method provided by the embodiment of the present application sets a command buffer area in the local memory of the sending device, the host controller and the second accelerator.

[0193] Setting a command buffer area in the host memory can not only enable the sending device, the host controller and the second accelerator to write the read and write commands of the shared memory to the command buffer area in the local memory when they do not have control over the shared memory, but also enable the sending device, the host controller and the second accelerator to have a certain buffering effect at the moment when they lose control of the shared memory, thereby avoiding the loss of the read and write commands sent to the shared memory by the sending device, the host controller or the second accelerator at this time.

[0194] The eighth embodiment of the present application is described below.

[0195] Based on the above embodiments, embodiments of the present application provide a data processing method that is easy to implement. In actual applications, the host controller can start a thread corresponding to the computing task being performed by the second accelerator. If the host is equipped with multiple second accelerators that simultaneously perform computing tasks, the host controller can start multiple threads to simultaneously execute the data processing method provided in embodiments of the present application.

[0196] Taking the example of a computing task executed by a second accelerator and executed by a host controller running a first thread, in the data processing method provided in an embodiment of the present application, S401: upon receiving a computing task, switching control of the shared memory of the first accelerator installed in the host to the sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task to the shared memory based on a remote direct data access protocol, may include:

[0197] When a processing request for a computing task is received, a channel selection register of the shared memory is configured based on a computer rapid interconnection protocol to enable a first data input / output channel corresponding to the remote direct data access network port, and the remote direct data access network port is configured based on the computer rapid interconnection protocol to start the remote direct data access network port to receive and write data to be processed into the shared memory;

[0198] Specifically, the host controller runs a first thread to configure parameters of a channel selection register in the shared memory through a computer fast interconnection channel constructed with the first accelerator computer fast interconnection module, so as to enable a remote direct data storage channel (i.e., a first data input and output channel) for the shared memory: Set_channel_reg(1);

[0199] The host controller runs the first thread to configure the remote direct data storage module and starts receiving the pending data of the computing task from the remote sender device:

[0200] First apply for buff according to the size of the data to be processed:

[0201] buff = malloc_recv(length);

[0202] Then start receiving data to be processed:

[0203] Rdma_start_recv(buff).

[0204] S402: Switching the control of the shared memory to the second accelerator installed in the host based on the computer rapid interconnection protocol, so that the second accelerator reads the to-be-processed data from the shared memory to perform the computing task and writes the computing result to the shared memory, may include:

[0205] Configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a third data input / output channel of the corresponding host controller, so as to write a kernel model corresponding to the computing task into the shared memory based on the third data input / output channel;

[0206] Specifically, the host controller runs a first thread to configure parameters of a channel selection register in the shared memory through the computer fast interconnection channel, enabling the computer fast interconnection channel (i.e., the third data input and output channel) of the shared memory:

[0207] Set_channel_reg(3);

[0208] The host controller runs the first thread to download the kernel program to the shared memory, and also downloads the model parameters of the kernel program to the shared memory:

[0209] Download the kernel program to shared memory:

[0210] Gpu_Down_load(kernel);

[0211] Download model parameters args to shared memory:

[0212] Gpu_set_kernel_args(args);

[0213] configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a second data input / output channel corresponding to the second accelerator, so that the second accelerator reads the kernel model and the data to be processed from the shared memory into a local cache through the second data input / output channel to perform a computing task, and writes the computing result to the shared memory based on the second data input / output channel after obtaining the computing result;

[0214] Specifically, the host controller runs a first thread to configure parameters of a channel selection register in the shared memory through a computer fast interconnect channel, enabling the second accelerator channel (i.e., the second data input and output channel) of the shared memory:

[0215] Set_channel_reg(2);

[0216] The second accelerator is notified via a high-speed PCIe bus channel that it can perform computations:

[0217] The kernel program and the data to be processed are stored in the shared memory at in_buff, and the calculation result is stored in the shared memory at out_buff, which is passed to the second accelerator:

[0218] Gpu_kernel_start(kernel,in_buff,out_buff).

[0219] In step S403, when the second accelerator completes the computing task, switching the control of the shared memory to the sending device based on the computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol may include:

[0220] When information of completing the computing task is received from the second accelerator, the channel selection register of the shared memory is configured based on the computer rapid interconnection protocol to enable the first data input and output channel, and the remote direct data access network port is configured based on the computer rapid interconnection protocol, so that the sending device can read the computing result from the shared memory based on the remote direct data access protocol.

[0221] Alternatively, the host controller receives the calculation result, and in step S403, based on the computer rapid interconnection protocol, the control right of the shared memory is switched to the host controller so that the host controller reads the calculation result from the shared memory, which may include:

[0222] When receiving information that the computing task is completed fed back by the second accelerator, configuring the channel selection register of the shared memory based on the computer rapid interconnection protocol to enable the third data input and output channel, so as to read the computing result from the shared memory to the host controller based on the third data input and output channel;

[0223] Specifically, the host controller runs the first thread and waits for the second accelerator to complete the calculation:

[0224] Wait_sem();

[0225] Upon receiving information that the second accelerator triggers an interrupt feedback indicating that the computing task is completed, the host controller runs the first thread to configure parameters of the channel selection register in the shared memory through the computer fast interconnection channel, thereby enabling the computer fast interconnection channel (i.e., the third data input and output channel) of the shared memory:

[0226] Set_channel_reg(3);

[0227] The host controller runs the first thread to obtain the calculation results from the shared memory:

[0228] out_buff=Get_gpu_result().

[0229] The ninth embodiment of the present application is described below.

[0230] The above embodiment describes the data processing method provided by the present application with the host controller of the host as the execution subject. For ease of understanding, the embodiment of the present application further provides a data processing method based on the first accelerator.

[0231] The first accelerator applied to the host, the data processing method provided by the embodiment of the present application includes:

[0232] When a first switching command is received from a host controller of the host based on a computer rapid interconnection protocol, control of the shared memory of the first accelerator is switched to a sender device of the computing task, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol;

[0233] When a second switching command sent by the host controller is received based on the computer rapid interconnection protocol, control of the shared memory is switched to the second accelerator installed in the host, so that the second accelerator reads the data to be processed from the shared memory to perform the computing task and writes the computing result to the shared memory;

[0234] When a first switching command is received based on the computer rapid interconnection protocol and sent by the host controller when the second accelerator completes the computing task, the control of the shared memory of the first accelerator is switched to the sending device, so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol; or, when a third switching command is received based on the computer rapid interconnection protocol and sent by the host controller when the second accelerator completes the computing task, the control of the shared memory of the first accelerator is switched to the host controller, so that the host controller reads the computing result from the shared memory.

[0235] The first accelerator is a device that supports the computer rapid interconnection protocol and is used to provide shared memory to the sending device, the second accelerator, and the host controller. In actual application, please refer to the description of Example 1 of this application. The first accelerator establishes a computer rapid interconnection channel with the host controller based on the computer rapid interconnection protocol, so that the host controller can configure the remote direct data access module of the first accelerator and the shared memory of the first accelerator based on the computer rapid interconnection channel.

[0236] Furthermore, the shared memory may be provided with a command buffer area, so that the sending device, the host controller and the second accelerator write the read and write commands of the shared memory into the command buffer area when they do not have the control right of the shared memory.

[0237] It should be noted that the data processing method provided in the embodiment of the present application corresponds to the data processing device and data processing method provided in the above-mentioned embodiment. The specific implementation method of the data processing method provided in the embodiment of the present application can refer to the description of the above-mentioned embodiment, and the above-mentioned embodiment can also refer to the description of the embodiment of the present application when implementing it.

[0238] The following describes the tenth embodiment of the present application.

[0239] The above embodiment describes the data processing method provided by the present application with the host controller of the host as the execution subject. For ease of understanding, the embodiment of the present application further provides a data processing method based on a second accelerator.

[0240] The second accelerator applied to the host, the data processing method provided by the embodiment of the present application includes:

[0241] When a computing task start signal is received and control of a shared memory of a first accelerator installed in the host is obtained, the processing data of the computing task is read from the shared memory to execute the computing task and write the computing result into the shared memory;

[0242] When the computing task is completed, the host controller is notified of the completion of the computing task, so that the host controller switches the control right of the shared memory to the sender device of the computing task based on the computer rapid interconnection protocol so that the sender device reads the computing result from the shared memory based on the remote direct data access protocol, or switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory;

[0243] The data to be processed is data written to the shared memory by the sending device based on the remote direct data access protocol after the host controller switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol.

[0244] The second accelerator is an accelerator on the host computer that performs computing tasks. It accesses the shared memory provided by the first accelerator on the host computer through a memory storage interface (such as a double-data-rate synchronous dynamic random access memory (DDR) interface). The second accelerator receives a kernel program provided by the host controller or the sending device and deploys a kernel model for performing computing tasks in the local application computing logic core. The kernel program can also be pre-burned into the second accelerator to implement proprietary computing functions, eliminating the need to wait for the host controller to send the kernel program during the execution of the computing task.

[0245] It should be noted that the data processing method provided in the embodiment of the present application corresponds to the data processing device and data processing method provided in the above-mentioned embodiment. The specific implementation method of the data processing method provided in the embodiment of the present application can refer to the description of the above-mentioned embodiment, and the above-mentioned embodiment can also refer to the description of the embodiment of the present application when implementing it.

[0246] The following describes the eleventh embodiment of the present application.

[0247] FIG6 is a flowchart of another data processing method provided in an embodiment of the present application.

[0248] On the basis of the above embodiment, for ease of understanding, the embodiment of the present application further provides a data processing method, as shown in FIG6 , including:

[0249] S601: When the host controller receives a computing task data input signal sent by a sending device, it configures a channel selection register to enable a first data input and output channel;

[0250] S602: The first accelerator connects the remote direct data access channel to the shared memory;

[0251] S603: The host controller configures the remote direct data access module and starts the remote direct data access module to receive data;

[0252] S604: The first accelerator runs a remote direct data access module to receive the to-be-processed data of the computing task sent by the sending device and copies the data to the shared memory;

[0253] S605: The host controller configures the channel selection register to enable the third data input and output channel;

[0254] S606: The first accelerator connects the channel through which the host controller accesses the shared memory;

[0255] S607: The host controller downloads the kernel program and kernel model parameters to the shared memory;

[0256] S608: The host controller configures the channel selection register to enable the second data input and output channel;

[0257] S609: The first accelerator connects the second accelerator and the shared memory;

[0258] S610: The host controller notifies the second accelerator to start executing the computing task via the high-speed serial computer expansion bus;

[0259] S611: The second accelerator obtains a kernel program start signal from the host controller;

[0260] S612: The second accelerator imports the kernel program and the data to be processed from the shared memory into the local cache to perform the computing task;

[0261] S613: The second accelerator stores the calculation result in the shared memory;

[0262] S614: After the second accelerator completes the computing task, it interrupts and notifies the host controller of the completion of the computing task;

[0263] S615: After the host controller waits for the second accelerator to complete the calculation, it configures the channel selection register to enable the third data input and output channel;

[0264] S616: The first accelerator connects the channel through which the host controller accesses the shared memory;

[0265] S617: The host controller obtains the calculation result from the shared memory.

[0266] It should be noted that the data processing method provided in the embodiment of the present application corresponds to the data processing device and data processing method provided in the above-mentioned embodiment. The specific implementation method of the data processing method provided in the embodiment of the present application can refer to the description of the above-mentioned embodiment, and the above-mentioned embodiment can also refer to the description of the embodiment of the present application when implementing it.

[0267] The above describes in detail various embodiments corresponding to the data processing method. On this basis, the present application also discloses a data processing device, equipment and storage medium corresponding to the above method.

[0268] The following describes the twelfth embodiment of the present application.

[0269] FIG7 is a schematic structural diagram of a data processing device provided in an embodiment of the present application.

[0270] As shown in FIG7 , the data processing device provided in the embodiment of the present application, applied to a host controller, includes:

[0271] The task receiving control unit 701 is configured to, upon receiving a computing task, switch control of the shared memory of the first accelerator installed in the host to the sender device of the computing task based on the computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on the remote direct data access protocol;

[0272] A computing control unit 702 is configured to switch control of the shared memory to a second accelerator installed in the host based on a computer rapid interconnection protocol, so that the second accelerator reads data to be processed from the shared memory to perform computing tasks and writes computing results to the shared memory;

[0273] The result acquisition control unit 703 is used to switch the control of the shared memory to the sending device based on the computer rapid interconnection protocol when the second accelerator completes the computing task, so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, or to switch the control of the shared memory to the host controller based on the computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory.

[0274] In some implementations, the task receiving control unit 701 switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol, including:

[0275] enabling a remote direct data access channel of the first accelerator based on a computer rapid interconnection protocol, so as to connect the sending device to the shared memory based on the remote direct data access channel;

[0276] The computing control unit 702 switches the control right of the shared memory to the second accelerator based on the computer rapid interconnection protocol, including:

[0277] Enabling a channel from the first accelerator to the second accelerator based on a computer rapid interconnection protocol, so as to connect the second accelerator to the shared memory based on the channel to the second accelerator;

[0278] The result acquisition control unit 703 switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol, including:

[0279] A channel from the first accelerator to the host controller is enabled based on a computer rapid interconnection protocol, so as to connect the host controller to the shared memory based on the channel to the host controller.

[0280] In some implementations, the task receiving control unit 701 switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol, including:

[0281] The remote direct data access module of the host is enabled, and the first accelerator is controlled based on the computer rapid interconnection protocol to connect the shared memory to the remote direct data access module, so as to connect the sending device to the shared memory based on the remote direct data access module.

[0282] In some implementations, the task receiving control unit 701 switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol, including:

[0283] Configuring a channel selection register of a shared memory in the first accelerator based on a computer rapid interconnection protocol, configuring parameters of the channel selection register to enable a first data input / output channel corresponding to the sending device, and disable a second data input / output channel corresponding to the second accelerator and a third data input / output channel corresponding to the host controller;

[0284] The computing control unit 702 switches the control right of the shared memory to the second accelerator based on the computer rapid interconnection protocol, including:

[0285] Configuring a channel selection register in the first accelerator based on a computer rapid interconnection protocol, configuring parameters of the channel selection register to enable a second data input / output channel corresponding to the second accelerator, and disable a first data input / output channel corresponding to the sending device and a third data input / output channel corresponding to the host controller;

[0286] The result acquisition control unit 703 switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol, including:

[0287] A channel selection register in the first accelerator is configured based on a computer rapid interconnection protocol, and parameters of the channel selection register are configured to enable a third data input / output channel corresponding to the host controller, and to disable a first data input / output channel corresponding to the sending device and a second data input / output channel corresponding to the second accelerator.

[0288] In some implementations, the task receiving control unit 701 switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol, including:

[0289] Configuring a channel selection register of a shared memory in the first accelerator based on a computer rapid interconnection protocol, and configuring a parameter of the channel selection register to switch a three-select-one channel switching switch in the first accelerator to connect the sending device to the shared memory;

[0290] The computing control unit 702 switches the control right of the shared memory to the second accelerator based on the computer rapid interconnection protocol, including:

[0291] Configuring a channel selection register in the first accelerator based on a computer rapid interconnection protocol, configuring a parameter of the channel selection register to switch a three-to-one channel switching switch in the first accelerator to connect the second accelerator to the shared memory;

[0292] The result acquisition control unit 703 switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol, including:

[0293] A channel selection register in the first accelerator is configured based on a computer rapid interconnection protocol, and a parameter of the channel selection register is configured to switch a three-to-one channel switching switch in the first accelerator to connect the host controller and the shared memory.

[0294] In some implementations, the shared memory is provided with a command buffer, so that the sending device, the host controller, and the second accelerator write read and write commands to the shared memory into the command buffer when they do not have control over the shared memory.

[0295] In some implementations, the command buffer includes a first command buffer corresponding to the sending device, a second command buffer corresponding to the second accelerator, and a third command buffer corresponding to the host controller;

[0296] When the sending device, the host controller, and the second accelerator do not have control over the shared memory, they write the read and write commands for the shared memory into the command buffer, including:

[0297] When the sending device, host controller and second accelerator do not have control over the shared memory, they will write the read and write commands of the shared memory into the corresponding command buffer. If the corresponding command buffer is full, the read and write commands will be overwritten with the read and write commands with the earliest writing time in the corresponding command buffer.

[0298] In some implementations, the data processing device provided in the embodiments of the present application further includes:

[0299] The buffer area configuration unit is used to configure the size of the first command buffer area, the size of the second command buffer area, and the size of the third command buffer area according to the operating environment of the host.

[0300] In some implementations, after the sending device, the host controller, and the second accelerator obtain control of the shared memory, they check the command buffer. If the command buffer stores unexecuted read and write commands sent locally, they execute new read and write commands after executing the unexecuted read and write commands.

[0301] In some implementations, when the sending device, the host controller, and the second accelerator do not have control over the shared memory, they write the read and write commands to the shared memory into a local command buffer.

[0302] In some implementations, the second accelerator reads the to-be-processed data from the shared memory to perform the computing task, and writes the computing result to the shared memory, including:

[0303] The second accelerator reads the data to be processed from the shared memory into the local cache, inputs the data to be processed into the pre-deployed kernel model, obtains the calculation result, and writes the calculation result into the shared memory;

[0304] The kernel model is that the host controller writes to the shared memory after the host controller switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol.

[0305] In some implementations, when receiving a computing task, the task receiving control unit 701 switches control of the shared memory of the first accelerator installed in the host to the sender device of the computing task based on the computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on the remote direct data access protocol, including:

[0306] When a processing request for a computing task is received, a channel selection register of the shared memory is configured based on a computer rapid interconnection protocol to enable a first data input / output channel corresponding to the remote direct data access network port, and the remote direct data access network port is configured based on the computer rapid interconnection protocol to start the remote direct data access network port to receive and write data to be processed into the shared memory;

[0307] The computing control unit 702 switches the control of the shared memory to the second accelerator installed in the host based on the computer rapid interconnection protocol, so that the second accelerator reads the data to be processed from the shared memory to perform the computing task and writes the computing result to the shared memory, including:

[0308] Configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a third data input / output channel of the corresponding host controller, so as to write a kernel model corresponding to the computing task into the shared memory based on the third data input / output channel;

[0309] Configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a second data input / output channel corresponding to the second accelerator, and notifying the second accelerator to execute a computing task based on a high-speed serial computer expansion bus, so that the second accelerator reads a kernel model and data to be processed from the shared memory through the second data input / output channel to a local cache to execute the computing task, and writes the computing result to the shared memory based on the second data input / output channel after obtaining the computing result;

[0310] When the second accelerator completes the computing task, the result acquisition control unit 703 switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, including:

[0311] Upon receiving information that the second accelerator has completed the computing task based on the high-speed serial computer expansion bus, configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable the first data input and output channel, and configuring a remote direct data access network port based on the computer rapid interconnection protocol to enable the sending device to read the computing result from the shared memory based on the remote direct data access protocol;

[0312] Switching the control of the shared memory to the host controller based on a computer fast interconnection protocol so that the host controller reads the calculation results from the shared memory, including:

[0313] When information of completing the computing task fed back by the second accelerator based on the high-speed serial computer expansion bus is received, the channel selection register of the shared memory is configured based on the computer rapid interconnection protocol to enable the third data input and output channel, so as to read the computing result from the shared memory to the host controller based on the third data input and output channel.

[0314] In some implementations, the first accelerator is a field programmable gate array that supports the Computer Express Interconnect protocol and has extended memory, or an application-specific integrated circuit device that supports the Computer Express Interconnect protocol and has extended memory, and the second accelerator is a graphics processor, with the extended memory serving as the shared memory of the first accelerator.

[0315] In some implementations, multiple graphics processors share the same shared memory of the first accelerator.

[0316] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0317] The following describes the thirteenth embodiment of the present application.

[0318] Based on the above embodiments, an embodiment of the present application provides a data processing device.

[0319] A first accelerator applied to a host, a data processing device provided in an embodiment of the present application includes:

[0320] a data import unit, configured to, upon receiving a first switching command sent by a host controller of a host based on a computer rapid interconnection protocol, switch control of the shared memory of the first accelerator to a sender device of the computing task, so that the sender device writes to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol;

[0321] a computing auxiliary unit, configured to, upon receiving a second switching command sent by the host controller based on a computer rapid interconnection protocol, switch control of the shared memory to a second accelerator installed in the host, so that the second accelerator reads data to be processed from the shared memory to perform a computing task, and writes a computing result into the shared memory;

[0322] The calculation result export unit is used to switch the control of the shared memory of the first accelerator to the sending device when a first switching command is received based on the computer rapid interconnection protocol from the host controller when the second accelerator completes the calculation task, so that the sending device reads the calculation result from the shared memory based on the remote direct data access protocol; or, when a third switching command is received based on the computer rapid interconnection protocol from the host controller when the second accelerator completes the calculation task, switch the control of the shared memory of the first accelerator to the host controller, so that the host controller reads the calculation result from the shared memory.

[0323] In some implementations, the shared memory is provided with a command buffer, so that the sending device, the host controller, and the second accelerator write read and write commands to the shared memory into the command buffer when they do not have control over the shared memory.

[0324] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0325] The following describes the fourteenth embodiment of the present application.

[0326] Based on the above embodiments, an embodiment of the present application provides a data processing device.

[0327] The second accelerator applied to the host, the data processing device provided by the embodiment of the present application includes:

[0328] a computing unit configured to, upon receiving a computing task start signal and obtaining control of a shared memory of a first accelerator installed in the host, read to-be-processed data of the computing task from the shared memory, execute the computing task, and write a computing result into the shared memory;

[0329] a calculation result feedback unit, configured to notify the host controller of the completion of the calculation task upon completion of the calculation task, so that the host controller switches the control right of the shared memory to the sender device of the calculation task based on the computer rapid interconnection protocol so that the sender device reads the calculation result from the shared memory based on the remote direct data access protocol, or switches the control right of the shared memory to the host controller based on the computer rapid interconnection protocol so that the host controller reads the calculation result from the shared memory;

[0330] The data to be processed is data written to the shared memory by the sending device based on the remote direct data access protocol after the host controller switches the control of the shared memory to the sending device based on the computer rapid interconnection protocol.

[0331] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0332] The fifteenth embodiment of the present application is described below.

[0333] FIG8 is a schematic structural diagram of another data processing device provided in an embodiment of the present application.

[0334] Different from the data processing device provided in the first embodiment of the present application, the embodiment of the present application provides another data processing device for executing the data processing method provided in the embodiment of the present application.

[0335] As shown in FIG8 , the data processing device provided in the embodiment of the present application includes:

[0336] Memory 810 for storing computer-readable instructions 811;

[0337] The processor 820 is configured to execute the computer-readable instructions 811 . When the computer-readable instructions 811 are executed by the processor 820 , the steps of the data processing method according to any one of the above embodiments are implemented.

[0338] Among them, the processor 820 may include one or more processing cores, such as a 3-core processor, an 8-core processor, etc. The processor 820 can be implemented in at least one hardware form of digital signal processing DSP (Digital Signal Processing), field programmable gate array FPGA (Field-Programmable Gate Array), and programmable logic array PLA (Programmable Logic Array). The processor 820 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as the central processing unit CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 820 may be integrated with a graphics processing unit GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 820 may also include an artificial intelligence AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0339] The memory 810 may include one or more storage media, which may be non-transitory. The memory 810 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 810 is at least used to store the following computer-readable instructions 811, wherein the computer-readable instructions 811, after being loaded and executed by the processor 820, can implement the relevant steps in the data processing method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 810 may also include an operating system 812 and data 813, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 812 may be Windows. The data 813 may include but is not limited to the data involved in the above method.

[0340] In some embodiments, the data processing device may further include a display screen 830 , a power supply 840 , a communication interface 850 , an input / output interface 860 , a sensor 870 , and a communication bus 880 .

[0341] Those skilled in the art will appreciate that the structure shown in FIG8 does not limit the data processing device, and may include more or fewer components than shown in the figure.

[0342] The data processing device provided in the embodiment of the present application includes a memory and a processor. When the processor executes the computer-readable instructions stored in the memory, it can implement the above data processing method and the effect is the same as above.

[0343] The following describes the sixteenth embodiment of the present application.

[0344] It should be noted that the above-described embodiments of the apparatus and equipment are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection of the apparatus or module, which may be electrical, mechanical or other forms. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0345] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0346] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the various embodiments of the present application.

[0347] To this end, the embodiments of the present application also provide one or more non-volatile computer-readable storage media storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the steps of the data processing method are implemented when the processors execute them.

[0348] The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., which can store program codes.

[0349] The computer-readable instructions contained in the storage medium provided in this embodiment can implement the steps of the above data processing method when executed by the processor, and the effect is the same as above.

[0350] The above is a detailed introduction to a data processing method, device, equipment, storage medium and distributed cluster provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the devices, equipment, storage media and distributed clusters disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0351] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A data processing method, characterized in that: Applicable to host controllers, including: In response to receiving a computing task, switching control of a shared memory of a first accelerator installed in the host to a sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol; Switching the control of the shared memory to a second accelerator installed on the host based on a computer rapid interconnection protocol, so that the second accelerator reads the to-be-processed data from the shared memory to perform the computing task, and writes the computing result into the shared memory; and In response to the second accelerator completing the computing task, the control of the shared memory is switched to the sending device based on a computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on a remote direct data access protocol, or the control of the shared memory is switched to the host controller based on a computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory.

2. The data processing method according to claim 1, characterized in that: Switching the control right of the shared memory to the sending device based on a computer fast interconnection protocol includes: enabling a remote direct data access channel of the first accelerator based on a computer rapid interconnection protocol, so as to connect the sending device to the shared memory based on the remote direct data access channel; Switching the control right of the shared memory to the second accelerator based on a computer fast interconnection protocol includes: Enabling the first accelerator to access the second accelerator based on a computer rapid interconnection protocol, so as to connect the second accelerator to the shared memory based on the access to the second accelerator; Switching the control right of the shared memory to the host controller based on a computer fast interconnection protocol includes: The first accelerator is enabled to have a channel to the host controller based on a computer rapid interconnection protocol, so as to connect the host controller to the shared memory based on the channel to the host controller.

3. The data processing method according to claim 1, characterized in that: Switching the control right of the shared memory to the sending device based on a computer fast interconnection protocol includes: The remote direct data access module of the host is enabled, and the first accelerator is controlled based on a computer rapid interconnection protocol to connect the shared memory to the remote direct data access module, so as to connect the sender device to the shared memory based on the remote direct data access module.

4. The data processing method according to claim 1, characterized in that: Switching the control right of the shared memory to the sending device based on a computer fast interconnection protocol includes: Based on a computer fast interconnection protocol, configuring a parameter of a channel selection register of the shared memory in the first accelerator to switch control of the shared memory to the sending device; Switching the control right of the shared memory to the second accelerator based on a computer fast interconnection protocol includes: Based on a computer fast interconnection protocol, configuring a parameter of the channel selection register of the shared memory in the first accelerator to switch the control right of the shared memory to the second accelerator; Switching the control right of the shared memory to the host controller based on a computer fast interconnection protocol includes: Based on a computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to switch the control right of the shared memory to the host controller.

5. The data processing method according to claim 4, characterized in that: The method of configuring the parameters of the channel selection register of the shared memory in the first accelerator based on the computer rapid interconnection protocol to switch the control right of the shared memory to the sending device includes: Based on a computer rapid interconnection protocol, configuring the parameters of the channel selection register of the shared memory in the first accelerator to open a first data input / output channel corresponding to the sending device, and closing a second data input / output channel corresponding to the second accelerator and a third data input / output channel corresponding to the host controller; The method of configuring the parameters of the channel selection register of the shared memory in the first accelerator based on a computer rapid interconnection protocol to switch the control right of the shared memory to the second accelerator includes: Based on a computer rapid interconnection protocol, configuring parameters of a channel selection register of the shared memory in the first accelerator to enable the second data input / output channel corresponding to the second accelerator, and to disable the first data input / output channel corresponding to the sender device and the third data input / output channel corresponding to the host controller; The method of configuring the parameters of the channel selection register of the shared memory in the first accelerator based on the computer rapid interconnection protocol to switch the control right of the shared memory to the host controller includes: Based on the computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to open the third data input and output channel corresponding to the host controller, and close the first data input and output channel corresponding to the sending device and the second data input and output channel corresponding to the second accelerator.

6. The data processing method according to claim 4, characterized in that: The method of configuring the parameters of the channel selection register of the shared memory in the first accelerator based on the computer rapid interconnection protocol to switch the control right of the shared memory to the sending device includes: Based on a computer fast interconnection protocol, configuring a parameter of the channel selection register of the shared memory in the first accelerator to switch a three-to-one channel switching switch in the first accelerator to connect the sending device to the shared memory; The method of configuring the parameters of the channel selection register of the shared memory in the first accelerator based on a computer rapid interconnection protocol to switch the control right of the shared memory to the second accelerator includes: Based on a computer fast interconnection protocol, configuring a parameter of the channel selection register of the shared memory in the first accelerator to switch the three-to-one channel switching switch in the first accelerator to connect the second accelerator to the shared memory; The method of configuring the parameters of the channel selection register of the shared memory in the first accelerator based on the computer rapid interconnection protocol to switch the control right of the shared memory to the host controller includes: Based on a computer rapid interconnection protocol, the parameters of the channel selection register of the shared memory in the first accelerator are configured to switch the three-to-one channel switching switch in the first accelerator to connect the host controller and the shared memory.

7. The data processing method according to claim 1, characterized in that: The shared memory is provided with a command buffer area, so that the sending device, the host controller and the second accelerator write the read and write commands of the shared memory into the command buffer area when they do not have the control right of the shared memory.

8. The data processing method according to claim 7, characterized in that: The command buffer includes a first command buffer corresponding to the sending device, a second command buffer corresponding to the second accelerator, and a third command buffer corresponding to the host controller; The sending device, the host controller, and the second accelerator write the read and write commands of the shared memory into the command buffer area when they do not have the control right of the shared memory, including: When the sending device, the host controller and the second accelerator do not have control over the shared memory, they write the read and write commands of the shared memory into the corresponding command buffer area. If the corresponding command buffer area is full, the read and write commands are written over the read and write commands with the earliest writing time in the corresponding command buffer area.

9. The data processing method according to claim 8, characterized in that: Also includes: The size of the first command buffer area, the size of the second command buffer area, and the size of the third command buffer area are configured according to the operating environment of the host.

10. The data processing method according to claim 7, characterized in that: After obtaining control of the shared memory, the sending device, the host controller and the second accelerator check the command buffer. If the command buffer stores unexecuted read and write commands sent locally, new read and write commands are executed after the unexecuted read and write commands are executed.

11. The data processing method according to claim 1, characterized in that: When the sending device, the host controller and the second accelerator do not have the control right of the shared memory, the reading and writing commands of the shared memory are written into the local command buffer area.

12. The data processing method according to claim 1, characterized in that: The second accelerator reads the to-be-processed data from the shared memory to execute the computing task, and writes the computing result into the shared memory, including: The second accelerator reads the data to be processed from the shared memory to a local cache, inputs the data to be processed into a pre-deployed kernel model, obtains the calculation result, and writes the calculation result into the shared memory; The kernel model is what the host controller writes to the shared memory after the host controller switches the control right of the shared memory to the host controller based on the Computer Rapid Interconnection Protocol.

13. The data processing method according to claim 1, characterized in that: In response to receiving the computing task, switching the control of the shared memory of the first accelerator installed in the host to the sender device of the computing task based on the computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task to the shared memory based on the remote direct data access protocol, including: In response to receiving a processing request for the computing task, configuring a channel selection register of the shared memory based on a computer rapid interconnection protocol to enable a first data input / output channel corresponding to a remote direct data access network port, and configuring the remote direct data access network port based on a computer rapid interconnection protocol to start the remote direct data access network port to receive and write the to-be-processed data into the shared memory; The method of switching the control of the shared memory to the second accelerator installed in the host based on the computer rapid interconnection protocol, so that the second accelerator reads the to-be-processed data from the shared memory to perform the computing task, and writes the computing result into the shared memory, comprises: Configuring the channel selection register of the shared memory based on a computer rapid interconnect protocol to enable a third data input / output channel corresponding to the host controller, so as to write a kernel model corresponding to the computing task into the shared memory based on the third data input / output channel; and Based on a computer fast interconnection protocol, the channel selection register of the shared memory is configured to enable a second data input and output channel corresponding to the second accelerator, so that the second accelerator reads the kernel model and the data to be processed from the shared memory to a local cache through the second data input and output channel to perform the computing task, and writes the computing result to the shared memory based on the second data input and output channel after obtaining the computing result; In response to the second accelerator completing the computing task, switching the control of the shared memory to the sending device based on a computer rapid interconnection protocol so that the sending device reads the computing result from the shared memory based on a remote direct data access protocol, including: In response to receiving the information of completing the computing task fed back by the second accelerator, configuring the channel selection register of the shared memory based on a computer rapid interconnection protocol to enable the first data input and output channel, and configuring the remote direct data access network port based on a computer rapid interconnection protocol, so that the sending device reads the computing result from the shared memory based on a remote direct data access protocol; The method of switching the control right of the shared memory to the host controller based on a computer rapid interconnection protocol so that the host controller reads the calculation result from the shared memory includes: In response to receiving the information of completing the computing task fed back by the second accelerator, the channel selection register of the shared memory is configured based on a computer rapid interconnection protocol to enable the third data input and output channel, so as to read the computing result from the shared memory to the host controller based on the third data input and output channel.

14. The data processing method according to any one of claims 1 to 13, characterized in that: The first accelerator is a field programmable gate array that supports a computer rapid interconnection protocol and has an extended memory, or a dedicated integrated circuit device that supports a computer rapid interconnection protocol and has an extended memory. The second accelerator is a graphics processor, and the extended memory is used as the shared memory of the first accelerator.

15. The data processing method according to any one of claims 1 to 13, characterized in that: A plurality of the graphics processors share the same shared memory of the first accelerator.

16. A data processing method, characterized in that: The first accelerator applied to the host includes: In response to receiving a first switching command sent by a host controller of the host based on a computer rapid interconnection protocol, switching the control right of the shared memory of the first accelerator to a sender device of the computing task, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on a remote direct data access protocol; In response to receiving a second switching command sent by the host controller based on a computer rapid interconnection protocol, switching the control of the shared memory to a second accelerator installed in the host, so that the second accelerator reads the data to be processed from the shared memory to perform the computing task, and writes the computing result to the shared memory; and In response to receiving the first switching command sent by the host controller when the second accelerator completes the computing task based on a computer rapid interconnection protocol, the control of the shared memory of the first accelerator is switched to the sending device, so that the sending device reads the computing result from the shared memory based on a remote direct data access protocol; or, in response to receiving a third switching command sent by the host controller when the second accelerator completes the computing task based on a computer rapid interconnection protocol, the control of the shared memory of the first accelerator is switched to the host controller, so that the host controller reads the computing result from the shared memory.

17. The data processing method according to claim 16, characterized in that: The shared memory is provided with a command buffer area, so that the sending device, the host controller and the second accelerator write the read and write commands of the shared memory into the command buffer area when they do not have the control right of the shared memory.

18. A data processing method, characterized in that: A second accelerator applied to the host includes: In response to receiving a computing task start signal and obtaining control of a shared memory of a first accelerator installed on the host, reading to-be-processed data of the computing task from the shared memory to execute the computing task and write a computing result to the shared memory; and In response to completing the computing task, notifying the host controller of information that the computing task is completed, so that the host controller switches the control right of the shared memory to the sender device of the computing task based on a computer rapid interconnection protocol so that the sender device reads the computing result from the shared memory based on a remote direct data access protocol, or switches the control right of the shared memory to the host controller based on a computer rapid interconnection protocol so that the host controller reads the computing result from the shared memory; The data to be processed is written to the shared memory by the sender device based on the remote direct data access protocol after the host controller switches the control of the shared memory to the sender device based on the computer rapid interconnection protocol.

19. A data processing device, characterized in that: comprising a host controller, a first accelerator and a second accelerator; Wherein, the first accelerator establishes a computer fast interconnection channel with the host controller based on a computer fast interconnection protocol to realize a shared memory of the first accelerator; The host controller is used to, in response to receiving a computing task, switch the control of the shared memory to the sender device of the computing task based on a computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task to the shared memory based on a remote direct data access protocol; switch the control of the shared memory to the second accelerator based on a computer rapid interconnection protocol, so that the second accelerator reads the to-be-processed data from the shared memory to perform the computing task and writes the computing result to the shared memory; in response to the second accelerator completing the computing task, switch the control of the shared memory to the sender device based on a computer rapid interconnection protocol, so that the sender device reads the computing result from the shared memory based on a remote direct data access protocol, or switch the control of the shared memory to the host controller based on a computer rapid interconnection protocol, so that the host controller reads the computing result from the shared memory.

20. A distributed cluster, characterized in that: Comprising a plurality of data processing devices as claimed in claim 19.

21. A data processing device, characterized in that: Applicable to host controllers, including: A task receiving control unit, configured to, in response to receiving a computing task, switch the control right of the shared memory of the first accelerator installed in the host to the sender device of the computing task based on the computer rapid interconnection protocol, so that the sender device writes the to-be-processed data of the computing task into the shared memory based on the remote direct data access protocol; a computing control unit, configured to switch control of the shared memory to a second accelerator installed on the host based on a computer rapid interconnection protocol, so that the second accelerator reads the data to be processed from the shared memory to perform the computing task, and writes the computing result to the shared memory; and The result acquisition control unit is used for switching the control right of the shared memory to the sending device based on the computer rapid interconnection protocol in response to the second accelerator completing the computing task, so that the sending device reads the computing result from the shared memory based on the remote direct data access protocol, or based on The computer rapid interconnection protocol switches the control right of the shared memory to the host controller so that the host controller reads the calculation result from the shared memory.

22. A data processing device, characterized in that: include: a memory for storing computer readable instructions; A processor is used to execute the computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps of the data processing method according to any one of claims 1 to 17 are implemented.

23. One or more non-volatile computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of the method according to any one of claims 1 to 17.

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