Silicon wafer polishing method

Abstract

[Problem] To provide a silicon wafer having a small number of PIDs, and a silicon wafer polishing method that makes it possible to produce the silicon wafer. [Solution] A silicon wafer polishing method according to the present invention comprises: an F / T value calculation step S11 for calculating an F / T value by measuring a load current value F of a motor for rotationally driving a rotary surface plate and a surface temperature T of a polishing pad, during a silicon wafer polishing step; a PID evaluation step S12 for counting the number of polishing induced defects (PIDs) by observing the surface of the silicon wafer after the silicon wafer polishing step; and a polishing condition adjustment step S13 in which data on correlation between the F / T value prepared in advance and the number of PIDs is referenced to determine a polishing condition for obtaining a target F / T value such that the number of PIDs of the silicon wafer is equal to or less than a threshold value. The polishing condition obtained in the polishing condition adjustment step S13 is applied in the polishing step for the next batch and subsequent batches.

Description

Silicon wafer polishing method

[0001] The present invention relates to a method for polishing a silicon wafer.

[0002] Silicon wafers are widely used as substrate materials for semiconductor devices. Silicon wafers are manufactured by sequentially performing processes on silicon single crystal ingots, including slicing, beveling, lapping, etching, double-sided polishing, single-sided polishing, and cleaning. Among these processes, the single-sided polishing process is necessary to remove irregularities and waviness from the wafer surface and increase flatness, and mirror finishing is performed using the CMP (Chemical Mechanical Polishing) method.

[0003] Typically, a single-side polishing process for silicon wafers uses a single-wafer polishing machine (CMP machine). This wafer polishing machine is equipped with a rotating platen with an abrasive cloth attached and a polishing head that holds the wafer on the rotating platen while pressing it. One side of the wafer is polished by rotating the rotating platen and the polishing head while supplying slurry.

[0004] Regarding wafer polishing technology, for example, Patent Document 1 describes that, in order to obtain silicon single crystal wafers with few PIDs (Polishing Induced Defects), a polishing process is performed in multiple stages in which a wafer is polished by interposing a polishing slurry between the wafer and a polishing cloth, and in the final stage, a finish polishing process, the polishing rate is initially set to exceed 10 nm / min, and the polishing rate at the end is set to 5 nm / min or less, and the polishing stock removal in the finish polishing is set to 5 nm or more.

[0005] Patent Document 2 also describes the use of HEC (hydroxyethyl cellulose) in the CMP slurry used in the CMP finish polishing of silicon wafers, and the filtration of the slurry immediately before chemical mechanical polishing using a CMP apparatus. By using a filter to remove aggregates, impurities, etc. present in the polishing composition, the occurrence of PID can be reduced.

[0006] Japanese Patent No. 4696086 Japanese Patent Application Laid-Open No. 2021-095431

[0007] As mentioned above, the occurrence of PIDs has become a problem in the polishing process of silicon wafers. PIDs are linear convex defects with a height of a few nanometers and a length of approximately 100 nanometers that are introduced into wafers during the polishing process and can cause device failures. Until now, the surface of silicon wafers was covered with a larger number of particles and impurities than PIDs, making the presence of PIDs less noticeable. However, recent improvements in cleaning technology have allowed particles and other impurities to be removed, making the presence of PIDs more noticeable. In recent years, there has been a strong demand for silicon wafers with as few PIDs as possible.

[0008] PIDs are thought to be formed by residues from the slurry used in the polishing process. During the polishing process, aggregates of undissolved components of the water-soluble polymer (HEC) in the CMP slurry combine with abrasive grains and other foreign matter, coarsening and adsorbing to the silicon wafer surface. Convex defects are thought to form due to the difference in etching rate between the adsorption site of the aggregates and the surrounding area. As mentioned above, the number of PIDs can be reduced by removing aggregates and impurities from the slurry using a filter or other method, but further improvements are needed.

[0009] Therefore, an object of the present invention is to provide a silicon wafer having a small number of PIDs and a method for polishing a silicon wafer that can produce such a silicon wafer.

[0010] As a result of extensive research, the inventors of the present application have found that there is a certain correlation between the F / T value measured during the polishing process of a silicon wafer and the number of PIDs generated on the silicon wafer, and that PIDs can be reduced by controlling the F / T value. The F / T value is the ratio of the mechanical action to the chemical action of CMP, and increasing the F / T value increases the mechanical action. Under polishing conditions where the contribution of chemical action is large, such as etching, aggregates of undissolved HEC components that cause PIDs tend to remain, but under polishing conditions where the contribution of mechanical action is large, the aggregates are easily removed. Therefore, evaluation using the F / T value allows for more accurate determination of polishing conditions than evaluation using removal stock or polishing rate.

[0011] The present invention is based on such technical findings, and a method for polishing silicon wafers according to the present invention is a method for polishing silicon wafers, in which a silicon wafer held by a polishing head is pressed against a polishing pad attached to a rotary platen, and one side of the silicon wafer is polished by rotating the polishing pad and the rotary platen while supplying a slurry to the surface of the polishing pad, the method comprising: an F / T value calculation step of measuring a load current value F of a motor that rotationally drives the rotary platen and a surface temperature T of the polishing pad to calculate an F / T value during the polishing process of the silicon wafer; a PID evaluation step of observing the surface of the silicon wafer and counting the number of PIDs after the polishing process of the silicon wafer; and a polishing condition adjustment step of determining polishing conditions that will result in a target F / T value such that the number of PIDs on the silicon wafer is equal to or less than a threshold value, with reference to correlation data between the F / T value and the number of PIDs prepared in advance; and applying the polishing conditions obtained in the polishing condition adjustment step to the polishing process of the next batch and thereafter.

[0012] According to the present invention, it is possible to increase the production yield of silicon wafers with reduced PID while suppressing wear of the polishing pad and deterioration of the flatness quality of the wafer.

[0013] The method for polishing silicon wafers according to the present invention comprises a first polishing step of polishing a first silicon wafer and a second polishing step of polishing a second silicon wafer under polishing conditions determined in consideration of the evaluation results of the PID evaluation step, wherein the first polishing step includes the F / T value calculation step, the polishing condition adjustment step determines polishing conditions that result in a target F / T value that makes the number of PIDs of the first silicon wafer equal to or less than the threshold value with reference to the correlation data, and the second polishing step preferably polishes the second silicon wafer under the polishing conditions determined in the polishing condition adjustment step. In this way, the F / T value of the next batch can be changed in consideration of the F / T value of the previous batch, thereby reducing PIDs of the second silicon wafer.

[0014] In the second polishing step, it is preferable to adjust the F / T value by adjusting at least one of the rotation speed of the rotary platen and the pressure applied by the polishing head, thereby making it possible to easily adjust the F / T value.

[0015] In the second polishing step, if the F / T value determined in the first polishing step is smaller than the target F / T value, it is preferable to increase the F / T value by making the rotation speed of the rotating platen in the second polishing step slower than the rotation speed of the rotating platen in the first polishing step, or by making the applied pressure of the polishing head in the first polishing step greater than the applied pressure of the polishing head in the second polishing step.

[0016] In the second polishing step, the second silicon wafer is preferably polished under polishing conditions in which the F / T value is 0.2 (A / °C) or more and 0.6 (A / °C) or less. By controlling the polishing conditions so that the F / T value is 0.2 to 0.6 (A / °C), it is possible to produce a silicon wafer with reduced PID while suppressing wear of the polishing pad and deterioration of the flatness quality of the wafer.

[0017] In the F / T value calculation step, the F / T value is preferably calculated using data acquired within a certain period (e.g., within 10 seconds) immediately before the end of the first polishing step, which allows for control of polishing conditions based on a highly reliable F / T value.

[0018] The threshold value of the number of PIDs is preferably equal to or less than 30. The diameter of the silicon wafer is preferably 300 mm. This makes it possible to manufacture silicon wafers with high PID quality.

[0019] The silicon wafer polishing method according to the present invention preferably comprises a rough polishing step of rough polishing a silicon wafer and a finish polishing step of finish polishing the silicon wafer after the rough polishing step, and the F / T value calculation step, the PID evaluation step, and the polishing condition adjustment step are performed in the finish polishing step. In this case, the finish polishing step is preferably performed using a wafer polishing apparatus separate from that used in the rough polishing step. The silicon wafer polishing method according to the present invention may comprise two or more rough polishing steps before the finish polishing step, or may comprise an intermediate polishing step between the rough polishing step and the finish polishing step. By applying polishing conditions that result in a desired number of PIDs or less in the finish polishing (final polishing) in the multiple polishing steps, it is possible to produce silicon wafers with reduced PIDs while suppressing polishing pad wear and deterioration of wafer flatness quality.

[0020] According to the present invention, it is possible to provide a silicon wafer having a small number of PIDs and a method for polishing a silicon wafer that can produce such a silicon wafer.

[0021] FIG. 1 is a flowchart schematically illustrating a method for manufacturing a silicon wafer according to an embodiment of the present invention. FIG. 2 is a schematic side view showing the configuration of a wafer polishing apparatus used in a single-side polishing process. FIG. 3 is a flowchart showing a method for polishing a silicon wafer according to an embodiment of the present invention. FIG. 4 is a graph showing the change in F / T value over time during the polishing process of a wafer sample. FIG. 5 is a graph showing the measurement results of the number of PIDs for a wafer sample polished under the conditions of FIG. 4. FIG. 6 is a graph showing the change in F / T value over time during the polishing process of a wafer sample. FIG. 7 is a graph showing the measurement results of the number of PIDs for a wafer sample polished under the conditions of FIG. 6.

[0022] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0023] FIG. 1 is a flow chart that schematically shows a method for manufacturing a silicon wafer according to an embodiment of the present invention.

[0024] As shown in FIG. 1, the method for manufacturing a silicon wafer includes, in order, a slicing step S1 in which a single crystal ingot is sliced ​​to cut out wafers, a beveling step S2 in which the outer periphery of the wafer is chamfered, a lapping step S3 in which processing distortion on the wafer surface is reduced and the wafer is finished to a predetermined thickness, an etching step S4 in which fine distortions and scratches on the wafer surface are removed, a double-side polishing step S5 in which both sides of the wafer are polished simultaneously, a single-side polishing step S6 in which one side of the wafer is polished, and a cleaning step S7 in which foreign matter and dirt adhering to the wafer surface are removed.

[0025] The single-side polishing step S6 is composed of multiple polishing steps with different polishing conditions, including at least one rough polishing step S6a for removing deep scratches on the wafer surface and flattening it, and a finish polishing step S6b for removing small scratches remaining after rough polishing and achieving a mirror finish. Two or more rough polishing steps S6a may be performed before the finish polishing step S6b. The rough polishing step S6a and the finish polishing step S6b are performed using separate wafer polishing machines.

[0026] FIG. 2 is a schematic side view showing the configuration of the wafer polishing apparatus used in the single-side polishing step S6.

[0027] 2, the wafer polishing apparatus 1 includes a rotary platen 10, a rotation mechanism 11 for the rotary platen 10, a polishing pad 12 such as a nonwoven fabric attached to the upper surface of the rotary platen 10, a polishing head 13 disposed above the rotary platen 10, a pressure and rotation mechanism 14 for the polishing head 13, and a slurry supply mechanism 15 for supplying slurry 2 onto the rotary platen 10. The wafer polishing apparatus 1 also includes a radiation thermometer 16 for non-contactly measuring the surface temperature T of the polishing pad 12 during wafer polishing, a current measurement circuit 11b for measuring a load current value F of a motor 11a in the rotation mechanism 11 that rotates the rotary platen 10, and a control unit 17 for controlling each component.

[0028] In the wafer polishing process using the wafer polishing apparatus 1, a slurry 2 containing abrasive grains is supplied onto a rotating platen 10 to which a polishing pad 12 is attached, and while the wafer W on the rotating platen 10 is held under pressure by a polishing head 13, the rotating platen 10 and the polishing head 13 are rotated in the same direction to polish one side of the wafer that is in contact with the polishing pad 12. Since the finish polishing step S6b of the single-side polishing process S6 is a finishing step performed after the preceding rough polishing step S6a, the amount of polishing (removal stock) of the wafer W is several nm to 1 μm, and the processing time is very short, on the order of a few minutes. If the polishing time is too long, the amount of edge roll-off of the wafer increases, deteriorating the shape of the removal stock on the periphery.

[0029] The edge roll-off amount (ROA) refers to the amount of sagging of the wafer surface at the boundary between the edge exclusion area, which is outside the scope of flatness standards, and the area inside it. The edge roll-off amount is measured using the Edge Site Front least square deviation (ESFQD), a flatness index specified in the SEMI standard.

[0030] During wafer polishing, the control unit 17 takes in the surface temperature T of the polishing pad 12 measured by the radiation thermometer 16, and also takes in the load current value F of the motor 11a that rotates the rotating platen 10 from the current measurement circuit 11b, and constantly monitors these to calculate the F / T value.

[0031] The load current value F of the motor 11a is defined as an index representing the magnitude of friction, i.e., the strength of the mechanical removal action, and the larger the load current value F, the larger the F / T value. Under conditions where the rotation speed of the rotating surface plate 10 is constant, an increase in the load current value F means an increase in the friction force on the rotating surface plate 10.

[0032] The surface temperature T of the polishing pad 12 is equivalent to the temperature of the slurry flowing on the surface of the polishing pad 12 and is defined as an index showing the strength of the chemical removal action, and the F / T value decreases as the surface temperature T increases. An increase in the surface temperature T means that the chemical reaction of the slurry 2 is promoted.

[0033] In the single-side polishing step S6 (particularly the finish polishing step S6b), the F / T value is measured during the polishing step, and the polishing step is carried out under conditions under which the F / T value becomes a predetermined value. Furthermore, the correlation between the F / T value and the number of PIDs is calculated in advance, and the wafer is polished under polishing conditions under which the F / T value becomes equal to or less than the desired number of PIDs (threshold value). This will be explained in detail below.

[0034] FIG. 3 is a flowchart showing a method for polishing a silicon wafer according to an embodiment of the present invention.

[0035] As shown in FIG. 3, the method for polishing silicon wafers according to this embodiment includes an F / T value calculation step S11 in which the load current value F of the motor 11a that rotates the rotary platen 10 and the surface temperature T of the polishing pad 12 are measured during the polishing process of the silicon wafer to calculate the F / T value; a PID evaluation step S12 in which the surface of the silicon wafer after the polishing process is completed is observed to determine the number of PIDs; and a polishing condition adjustment step S13 in which the polishing conditions for the polishing processes of the next batch and thereafter are determined in consideration of the evaluation results of the PID evaluation step S12.

[0036] During the polishing process of a silicon wafer, the load current value F of the motor 11a and the surface temperature T of the polishing pad 12 are collected and recorded at a predetermined sampling period from the start to the end of polishing. In the F / T value calculation step S11, it is desirable to use the average value of multiple F / T values ​​(instantaneous values) collected within a certain period immediately before the end of the polishing process as the representative value. Specifically, data from the 10 seconds immediately before the end of the polishing process is used. The F / T value in the first half of the polishing process (especially immediately after the start) is unstable, and the reliability of the F / T value measurement results can be improved by adopting a measurement value when the F / T value is as stable as possible.

[0037] In the PID evaluation process S12, first, a laser surface inspection device (particle counter) is used to measure LPDs (Light Point Defects) on the wafer surface, and then the detected positions of the LPDs are observed with a SEM (Scanning Electron Microscope) to determine whether the LPDs are PIDs or not.

[0038] The polishing condition adjustment step S13 includes a correlation evaluation step of obtaining correlation data between the F / T value during the polishing process of the silicon wafer obtained in the F / T value calculation step S11 and the number of PIDs of the silicon wafer obtained in the PID evaluation step S12. The correlation data between the F / T value and the number of PIDs may be a correlation table or a correlation formula. The correlation data is updated by adding the results of the current polishing batch to the cumulative correlation data of past polishing batches.

[0039] In the polishing condition adjustment step S13, by referring to the correlation data thus prepared in advance, polishing conditions are determined that will result in a target F / T value that will make the number of PIDs on the silicon wafer equal to or less than a threshold value (for example, equal to or less than 30). For example, if the F / T value calculated in the F / T value calculation step S11 is lower than the target F / T value, the polishing conditions are changed so that the F / T value becomes higher. If the F / T value calculated in the F / T value calculation step S11 is equal to or greater than the target F / T value, there is no need to change the polishing conditions.

[0040] The polishing conditions determined in this manner are applied to the polishing steps of the next batch and thereafter. The application of new polishing conditions is preferably performed in the next batch, but may also be performed in the batches after that. For example, when a wafer polishing apparatus polishes a first silicon wafer in a first polishing step (first polishing batch) and then polishes a second silicon wafer in a second polishing step (second polishing batch), the polishing condition adjustment step S13 in the first polishing step refers to the correlation data to determine polishing conditions that will yield the target F / T value, and the second polishing step polishes the second silicon wafer under the polishing conditions determined in the polishing condition adjustment step S13 in the first polishing step.

[0041] Although the polishing conditions for adjusting the F / T value are not particularly limited, it is preferable to adjust the F / T value using at least one of the rotation speed of the rotary platen 10 and the applied pressure of the polishing head 13. As described above, it is known that the F / T value increases as the rotation speed of the rotary platen 10 decreases and as the applied pressure of the polishing head 13 decreases. Therefore, by reducing the rotation speed of the rotary platen 10, the F / T value can be increased and brought closer to the target F / T value. Furthermore, by increasing the applied pressure of the polishing head 13, the F / T value can be increased and brought closer to the target F / T value.

[0042] There is a certain correlation between the number of PIDs and the F / T value, and the number of PIDs tends to decrease as the F / T value increases. Therefore, by increasing the F / T value, the number of PIDs can be reduced, and it is possible to achieve 30 or fewer PIDs per wafer.

[0043] As described above, the method for polishing silicon wafers according to this embodiment includes an F / T value calculation step S11 in which, during the polishing process of the silicon wafer, the load current value F of the motor 11 a that rotates the rotary platen 10 and the surface temperature T of the polishing pad 12 are measured to calculate the F / T value; a PID evaluation step S12 in which the surface of the silicon wafer after the polishing process is completed is observed to determine the number of PIDs; and a polishing condition adjustment step S13 in which the polishing conditions for the polishing process of the next batch and thereafter are determined in consideration of the evaluation results of the PID evaluation step S12, thereby making it possible to increase the production yield of silicon wafers with a small number of PIDs.

[0044] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention, and it goes without saying that these modifications are also included in the scope of the present invention.

[0045] For example, in the above embodiment, the method for determining the conditions for finish polishing (final polishing) in a two-stage polishing process has been described, but the number of stages in the polishing process may be three or more.

[0046] Example 1: 300 mm diameter silicon wafer samples No. 1-1 to No. 1-6 were polished on one side under specified polishing conditions, and the number of PIDs in the polished wafer samples was determined. Epitaxial silicon wafers were used as the silicon wafer samples. The reason for this is that, while PIDs may have already occurred during the manufacturing process (polishing step) in the case of ordinary polished wafers, in the case of epitaxial wafers, the surface of the silicon substrate is covered with an epitaxial film, and the PIDs on the wafer surface are reset.

[0047] The single-side polishing step was carried out in the order of rough polishing step → finish polishing step, and the conditions for the finish polishing were changed as appropriate.

[0048] In the finish polishing process, the rotation speed of the rotary platen was set to three levels: 20 rpm, 30 rpm, and 40 rpm, and the pressure applied by the polishing head was set to two levels: 5 kPa and 10 kPa. The polishing time in the finish polishing process was set to 160 seconds. In the finish polishing process, a slurry containing HEC (hydroxyethyl cellulose) was used as the water-soluble polymer. The polishing conditions are shown in Table 1, along with the evaluation results described below.

[0049]

[0050] During the polishing process, the load current value F of the motor driving the rotating platen and the surface temperature T of the polishing pad were monitored, and the average F / T value for 10 seconds immediately before the end of the polishing process was calculated as a representative value.

[0051] For PID evaluation, LPDs (Light Point Defects) were measured using a particle counter (SURFSCAN series SP-7) manufactured by KLA Corporation, and the actual LPDs were then observed with a SEM to determine whether they were PIDs or not. The SEM used was a KLA-Tencor eDR7280.

[0052] FIG. 4 is a graph showing the change in F / T value over time during the polishing process of a wafer sample.

[0053] As shown in Figure 4, the F / T value rises sharply and is unstable immediately after the start of the polishing process, but stabilizes after 60 seconds. It can also be seen that the F / T value varies depending on the rotation speed of the rotating platen, with the F / T value increasing as the rotation speed decreases. As shown in the figure, when the applied pressure was 10 kPa, the F / T value was approximately 0.59 (A / °C) at a rotation speed of the rotating platen of 20 rpm, approximately 0.44 (A / °C) at 30 rpm, and approximately 0.39 (A / °C) at 40 rpm. Also as shown in the figure, when the applied pressure was 5 kPa, the F / T value was approximately 0.43 (A / °C) at a rotation speed of the rotating platen of 20 rpm, approximately 0.38 (A / °C) at 30 rpm, and approximately 0.32 (A / °C) at 40 rpm.

[0054] Furthermore, as can be seen from a comparison between when the polishing head pressure is 10 kPa and when it is 5 kPa, when the rotation speed of the rotary platen is fixed, the F / T value increases as the polishing head pressure increases. For example, when the rotation speed is 20 rpm and the pressure is 5 kPa, the F / T value is approximately 0.43, while when the rotation speed is 20 rpm and the pressure is 10 kPa, the F / T value is approximately 0.59, which is larger than when the pressure is 5 kPa.

[0055] Fig. 5 is a graph showing the results of measuring the number of PIDs in wafer samples polished under the conditions of Fig. 4, with the horizontal axis representing the average F / T value (hereinafter simply referred to as F / T value) for the 10 seconds immediately prior to the end of the polishing process of Fig. 4, and the vertical axis representing the reduction in the number of PIDs per wafer (pcs / wf). That is, the number of PIDs in Fig. 5 is shown as a relative value with the maximum PID value as the reference.

[0056] As shown in Figure 5, the PID count decreases as the F / T value increases. As described above, when the pressurization pressure was constant at 10 kPa, the F / T value increased from 0.39 to 0.44 as the rotation speed decreased from 40 rpm to 30 rpm, and the PID count decrease tended to decrease from -3.0 to -5.3 as the F / T value increased. Furthermore, when the pressurization pressure was 10 kPa and the rotation speed was 20 rpm, the PID count was missing. When the pressurization pressure was constant at 5 kPa, the F / T value increased from 0.32 to 0.38 to 0.43 as the rotation speed decreased from 40 rpm to 30 rpm to 20 rpm, and the PID count decrease tended to decrease from 0 (reference value) to -2.0 to -4.3 as the F / T value increased.

[0057] From the above results, it was found that there is a correlation between the number of PIDs and the F / T value, and the larger the F / T value, the smaller the number of PIDs. In particular, when the F / T value is 0.27 or more, the number of PIDs can be reduced to 30 or less, which is a sufficient reduction in the number of PIDs.

[0058] Example 2 In order to confirm the reproducibility of the polishing test in Example 1, the same polishing test as in Example 1 was conducted as Example 2 using a wafer polishing apparatus different from that used in Example 1. That is, epitaxial silicon wafer samples No. 2-1 to 2-6 having a diameter of 300 mm were polished under predetermined polishing conditions, and the PID counts of the polished wafer samples were determined. The polishing conditions and evaluation results are shown in Table 2. The evaluation results are also shown in FIGS. 6 and 7.

[0059]

[0060] FIG. 6 is a graph showing the change in F / T value over time during the polishing process of a wafer sample.

[0061] 6, the F / T value rises sharply and is unstable immediately after the start of the polishing process, but stabilizes after 60 seconds from the start of the polishing process. It is also clear that the F / T value changes depending on the rotation speed of the rotating platen, with the F / T value increasing as the rotation speed decreases.

[0062] As shown in the figure, the F / T value when the applied pressure was 10 kPa was approximately 0.53 (A / °C) when the rotational speed of the rotating platen was 20 rpm, approximately 0.44 (A / °C) when it was 30 rpm, and approximately 0.37 (A / °C) when it was 40 rpm. Also, as shown in the figure, the F / T value when the applied pressure was 5 kPa was approximately 0.33 (A / °C) when the rotational speed of the rotating platen was 20 rpm, approximately 0.28 (A / °C) when it was 30 rpm, and approximately 0.24 (A / °C) when it was 40 rpm. Furthermore, as can be seen from a comparison between when the applied pressure of the polishing head was 10 kPa and when it was 5 kPa, it can be seen that when the rotational speed of the rotating platen was fixed, the F / T value increased as the applied pressure of the polishing head increased.

[0063] Fig. 7 is a graph showing the results of measuring the number of PIDs in wafer samples polished under the conditions of Fig. 6, with the horizontal axis representing the average F / T value (hereinafter simply referred to as F / T value) for the 10 seconds immediately prior to the end of the polishing process of Fig. 6, and the vertical axis representing the reduction in the number of PIDs per wafer (pcs / wf). That is, the number of PIDs in Fig. 7 is shown as a relative value with the maximum PID value as the reference.

[0064] As shown in Figure 7, the PID count decreases as the F / T value increases. As shown above, when the pressurized pressure was constant at 10 kPa, the F / T value increased from 0.37 to 0.44 and 0.53 as the rotation speed decreased from 40 rpm to 30 rpm to 20 rpm, and the PID count decrease tended to decrease from -5.6 to -5.9 and -6.6 as the F / T value increased. When the pressurized pressure was constant at 5 kPa, the F / T value increased from 0.24 to 0.28 and 0.33 as the rotation speed decreased from 40 rpm to 30 rpm to 20 rpm, and the PID count decrease tended to decrease from 0 (reference value) to -1.2 and -4.5 as the F / T value increased.

[0065] DESCRIPTION OF SYMBOLS 1 Wafer polishing apparatus 10 Rotating surface plate 11 Rotation mechanism 11a Motor 11b Current measurement circuit 12 Polishing pad 13 Polishing head 14 Pressure and rotation mechanism 15 Slurry supply mechanism 16 Radiation thermometer 17 Control unit F Load current value S1 Slicing process S2 Beveling process S3 Lapping process S4 Etching process S5 Double-sided polishing process S6 Single-sided polishing process S6a Rough polishing process S6b Finish polishing process S7 Cleaning process S11 F / T value calculation process S12 PID evaluation process S13 Polishing condition adjustment process W Wafer

Claims

1. A method for polishing silicon wafers, comprising: pressing a silicon wafer held by a polishing head against a polishing pad attached on a rotating platen, and rotating the polishing pad and the rotating platen while supplying a slurry to the surface of the polishing pad, thereby polishing one side of the silicon wafer, the method comprising: an F / T value calculation step of measuring a load current value F of a motor that rotates the rotating platen and a surface temperature T of the polishing pad during the polishing process of the silicon wafer, and calculating an F / T value; a PID evaluation step of observing the surface of the silicon wafer after the polishing process of the silicon wafer and counting the number of PIDs (Polishing Induced Defects); and a polishing condition adjustment step of referring to correlation data between the F / T value and the number of PIDs prepared in advance, to determine polishing conditions under which a target F / T value is obtained such that the number of PIDs of the silicon wafer is equal to or less than a threshold value; and applying the polishing conditions obtained in the polishing condition adjustment step to the polishing processes of the next batch and thereafter.

2. A method for polishing silicon wafers according to claim 1, comprising: a first polishing step of polishing a first silicon wafer; and a second polishing step of polishing a second silicon wafer different from the first silicon wafer using the same wafer polishing apparatus as used in the first polishing step, wherein the F / T value calculation step calculates an F / T value during the first polishing step, the PID evaluation step counts the number of PIDs by observing a surface of the first silicon wafer after the first polishing step, the polishing condition adjustment step refers to the correlation data and determines polishing conditions that result in a target F / T value that makes the number of PIDs of the first silicon wafer equal to or less than the threshold value, and the second polishing step polishes the second silicon wafer under the polishing conditions obtained in the polishing condition adjustment step.

3. The method for polishing silicon wafers according to claim 2, wherein the second polishing step adjusts the F / T value by adjusting at least one of the rotation speed of the rotating platen and the applied pressure of the polishing head.

4. The method for polishing silicon wafers according to claim 2, wherein, when the F / T value determined in the first polishing step is smaller than the target F / T value, the second polishing step increases the F / T value by making the rotation speed of the rotating platen in the second polishing step slower than the rotation speed of the rotating platen in the first polishing step, or by making the applied pressure of the polishing head in the first polishing step greater than the applied pressure of the polishing head in the second polishing step.

5. The method for polishing silicon wafers according to claim 2, wherein the second polishing step polishes the second silicon wafer under polishing conditions such that the F / T value is 0.2 (A / °C) or more and 0.6 (A / °C) or less.

6. The method for polishing silicon wafers according to claim 2, wherein the F / T value calculation step calculates the F / T value using data acquired within a fixed period immediately prior to the end of the first polishing step.

7. The method for polishing silicon wafers according to claim 1, wherein the threshold value of the number of PIDs is 30 or less.

8. The method for polishing silicon wafers according to claim 7, wherein the silicon wafer has a diameter of 300 mm.

9. A method for polishing silicon wafers according to claim 1, comprising: a rough polishing step of roughly polishing silicon wafers; and a finish polishing step of finish polishing the silicon wafers after the rough polishing step, wherein the F / T value calculation step, the PID evaluation step, and the polishing condition adjustment step are performed in the finish polishing step.

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