System and method for single cycle dynamic hysteresis error control

Abstract

A signal quantizing module comprising: a combining module configured to combine an input signal and a feedback signal to generate a combined signal; an integrator module coupled to the combining module and configured to: generate, using the combined signal, an integrated signal; and a quantizer configured to generate an output signal based on, at least in part, the integrated signal, wherein the output signal is looped back to provide the feedback signal for the combining and integrator modules, and wherein, the quantizer is further configured to: when the quantizer is triggered at a first time point, compare an input to the quantizer with a threshold hysteresis, and responsive to the input to the quantizer reaches the threshold hysteresis, adjust the threshold hysteresis by an amount that characterizes a difference between a target hysteresis and the input to the quantizer at the first time point.

Description

SYSTEM AND METHOD FOR SINGLE CYCLE DYNAMIC HYSTERESIS ERROR CONTROLTECHNICAL FIELD

[0001] This disclosure generally relates to signal processing devices and in particular to devices for providing discrete or quantized outputs. Particular embodiments of the disclosure relate to mixed-signal circuits that combine both analog and digital functionalities, such as in analog-to digital-converters. However, it will be appreciated that the present disclosure is suitable more broadly for other applications.BACKGROUND

[0002] Hysteresis is a phenomenon in which the response of a system depends not only on the current input but also on the input history. Specifically, hysteresis introduces a tolerance band around a triggering threshold, causing the system to have different behavior when the input is rising compared to when the input is falling. Mixed-signal circuits often include a quantizer or a comparator with hysteresis characteristics where the input threshold to drive the output from low to high is different from the input threshold that drives the output from high to low. In this context, hysteresis generally represents the amount of minimum overdrive needed to change the output, which can introduce a “dead zone” or a region of input values where no change in output occurs despite a fluctuating input.

[0003] Any discussion of the background art throughout the specification should in no way be considered as an admission that such art is widely known or forms part of common general knowledge in the field.SUMMARY

[0004] In one aspect, the implementations provide a signal quantizing module that includes: a combining module configured to combine an input signal and a feedback signal; an integrator module coupled to the combining module and configured to: generate, using the summed signal, an integrated signal; and a quantizer controlled by a clock and configured to generate an output signal based on, at least in part, the integrated signal, wherein the output signal is looped back to provide the feedback signal for the summing and integrator circuits, and wherein, the quantizer is further configured to: at a clock cycle edge when the quantizer is triggered at afirst time point, compare an input to the quantizer with a threshold hysteresis, and responsive to the input to the quantizer crossing the threshold hysteresis, adjust the threshold hysteresis by an amount that characterizes a difference between a target hysteresis and the input to the quantizer at the first time point.

[0005] Implementations may include one or more of the following features.

[0006] In the signal quantizing module, when the quantizer is triggered at a second time point after the first time point, the quantizer may operate to compare the input to the quantizer at the second time point with the threshold hysteresis that has been adjusted based on the amount determined at the first time point. Responsive to a change in the input signal to the signal quantizing module, the change may be propagated through the signal quantizing module to affect the output signal of the quantizer as early as one clock cycle later. The threshold hysteresis may include a symmetric pair of a positive hysteresis level and a negative hysteresis level.

[0007] The positive hysteresis level may be adjusted each time the input to the quantizer exceeds the positive hysteresis level while the output signal is at a digital low. The negative hysteresis level may be adjusted each time the input to the quantizer falls under the negative hysteresis level while the output signal is at a digital high. The amount for adjusting the positive hysteresis level when the input to the quantizer exceeds the current positive hysteresis level may be determined by a gap between the input to the quantizer and the current positive hysteresis level. The amount for adjusting the negative hysteresis level when the input to the quantizer falls under the negative hysteresis level may be determined by a gap between the negative hysteresis level and the input to the quantizer. The amount for adjusting the positive hysteresis level when the input to the quantizer exceeds the positive hysteresis level may be determined by an average of a first difference between the input to the quantizer and the target hysteresis and a second difference between the target hysteresis and the input to the quantizer. The amount for adjusting the negative hysteresis level when the input to the quantizer falls under the negative hysteresis level may also be determined by the average of the first difference and the second difference.

[0008] The threshold hysteresis may be adjusted on each clock cycle edge when the quantizer is triggered such that the difference between the target hysteresis and the input to the quantizer is without a tonal appearance. When the input signal is at a constant level that is above a quantization threshold of the quantizer, the output signal may exhibit no tonal appearance. A spectrum of the output signal exhibits a power level under lOOdB between 20Hz and 20kHz. Theclock cycle edge may include a rising edge. The clock cycle edge may include a falling edge. The clock may be characterized by a frequency higher than a frequency of the output signal generated by the quantizer. The frequency of the clock may be higher than the frequency of the output signal by a factor of up to 100.

[0009] The signal quantizing module may further include: a limiter circuit coupled to the quantizer such that the output signal of the quantizer is range bounded. The signal quantizing module may further include: a filter circuit coupled to an output of the quantizer and configured to process the output signal of the quantizer and generate a modulated signal for at least one downstream circuit coupled to the signal quantizing module. The signal quantizing module may be a high order modulator comprising multiple stages of the combining module and the integrator circuit arranged in a cascade. Each stage in the cascade may include an instance of the combining module and an instance of the integrator circuit coupled thereto. Each integrator circuit may include a capacitor. Each combining module may include an operational amplifier configured to: sum an input signal and the feedback signal; and drive the integrator circuit coupled thereto. The quantizer may include a gate-controlled comparator. The signal quantizing module may further include: a digital filter coupled to the quantizer and configured to receive the output signal; and a decimator coupled to the digital filter and configured to generate a digital signal output for the signal quantizing module.

[0010] In another aspect, the implementations may include a signal quantizing module comprising: a plurality of input terminals configured to receive a plurality of input signals that are continuous temporally and characterized by a frequency range; a combiner coupled to the input terminals configured to process the plurality of input signals; an output port coupled to the combiner and configured to generate one of a set of pre -determined levels based on, at least in part, results from the combiner, wherein the signal quantizing module is driven by a set of threshold hysteresis values, wherein the signal quantizing module is operable to generate a series of trigger events with an occurring frequency that exceeds the frequency range of the input signals, such that, at a first trigger event of the series of trigger events, the output port generates an output based on, at least in part, a threshold hysteresis value and a result of the combiner processing the plurality of input signals, and at a second trigger event that is subsequent to the first trigger event, in response to the output of the combiner crossing threshold hysteresis value from the set of threshold hysteresis values, one or more threshold hysteresis values is updated by an amountdependent on, at least in part, a difference between a target hysteresis and the output of the combiner at the first trigger event.

[0011] The implementations may include one or more of the following features.

[0012] The one or more threshold hysteresis may be updated based on, at least in part, the difference between the target hysteresis and the output of the combiner at the first trigger event, and a duration between the first and second trigger events. The first or the second trigger event may be generated from a clock external to the signal quantizing module and independent of the input signals. The second trigger event may be created by the signal quantizing module internally, based on, at least in part, a duration since the first trigger event.

[0013] In one implementation, there is provided a signal quantizer for quantizing an input signal, the signal quantizer comprising a dynamic hysteresis adjustment feedback loop to adjust a hysteresis threshold, wherein the adjustment to the hysteresis threshold is based at least in part on a difference between the input to the quantizer and a target hysteresis level of the quantizer.

[0014] The adjustment may be made in response to a reoccurring trigger.

[0015] The reoccurring trigger may comprise a clock signal having a regular clock cycle.

[0016] The adjustment may be made within the same clock cycle.

[0017] The signal quantizer may comprise a positive hysteresis threshold and a negative hysteresis threshold and the same adjustment is made to both the positive and negative hysteresis thresholds.

[0018] The quantizer may comprise a positive hysteresis threshold and a negative hysteresis threshold and a separate adjustment is made to the positive hysteresis threshold and the negative hysteresis threshold.

[0019] The input to the quantizer may be provided by a delta-sigma modulator.

[0020] The signal quantizer may form part of an analog-to-digital converter or a digital- to-analog converter.

[0021] In another implementation, there is provided a method of operating a quantizer, the method comprising: accumulating the sum of an input signal and a past output of the quantizer to produce an accumulated signal; in response to a trigger, comparing the accumulated signal with one or more threshold values; andupon determining that the accumulated signal exceeds the one or more threshold values, selectively adjusting at least one of the one or more threshold values by an amount that is based at least in part on a difference between the accumulated signal and a target threshold value.

[0022] In a further implementation, there is provided a threshold comparator for comparing an input signal with a threshold value. The threshold comparator comprises a dynamic hysteresis adjustment feedback loop that adjusts a hysteresis threshold around the threshold value. The adjustment to the hysteresis threshold is based at least in part on a difference between the input to the comparator and a target hysteresis level of the comparator.

[0023] Implementations according to the present disclosure may be realized in computer implemented methods, hardware computing systems, and tangible computer readable media. For example, a system of one or more computers can be configured to perform particular actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0024] The details of one or more implementations of the subject matter of this specification are set forth in the description, the claims, and the accompanying drawings. Other features, aspects, and advantages of the subject matter will become apparent from the description, the claims, and the accompanying drawings.DESCRIPTION OF DRAWINGS

[0025] Example embodiments of the disclosure will now be described, by way of example only, with reference to the accompanying drawings in which:

[0026] Fig. 1A illustrates an example of a diagram of a first order sigma-delta modulator as used in prior art.

[0027] Figs. IB to ID show various waveforms as well as a representative noise spectrum associated with the example.

[0028] Fig. 2A illustrates an example of a diagram of a second order sigma-delta modulator as used in prior art.

[0029] Figs. 2B to 2F show various waveforms as well as a representative noise spectrum associated with the example.

[0030] Figs. 3A-3B illustrate an example of a first order sigma-delta modulator with single cycle dynamic hysteresis control according to the implementations of the present disclosure.

[0031] Figs. 3C-3E show various waveforms as well as a representative noise spectrum associated with the example.

[0032] Figs. 3C to 3H show comparable waveforms as well as a representative noise spectrum associated with a first order sigma-delta modulator under static hysteresis control.

[0033] Fig. 4A illustrates an example of a diagram of a second order sigma-delta modulator with single cycle dynamic hysteresis control according to the implementations of the present disclosure.

[0034] Fig. 4B shows a representative noise spectrum of the example of Fig. 4A.

[0035] Fig. 4C shows a representative noise spectrum of a second order sigma-delta modulator under static hysteresis control.

[0036] Figs. 5 A and 5B respectively show diagrams that compare and contrast static hysteresis control and dynamic hysteresis control according to some implementations of the present disclosure.

[0037] Figure 6 illustrates a process flow diagram showing a method of operating a quantizer according to one implementation.

[0038] Eike reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0039] Embodiments of the present disclosure will be described with reference to signal processing devices for providing discrete or quantized outputs such as signal quantizers. The operation of these devices will be described in the context of mixed-signal circuits such as analog- to-digital converters. However, it will be appreciated that the disclosure is applicable to broader signal processing aspects such as hysteretic controllers, event cameras and machine learning models such as neural networks.

[0040] The devices are preferably adapted to process input signals that have a temporal order or temporal continuity indicating the information they contain is temporally varying over time.

[0041] As an example of a mixed-signal circuit, a sigma-delta modulator converts a continuous analog, or high bit pulse code modulation (PCM) digital signal, into a higher frequency, low bit output where the pulse density represents the signal level in the band of interest. To be compatible with D-class audio or power inverters (e.g., as used in electric vehicles known as EV, photovoltaic (PV) converters, generators etc), the output frequency is generally kept low enough so as to minimize power losses and distortion as needed for the application. To achieve these desirable attributes using known art, a significant number of sequential stages are required to maintain a satisfactory signal to noise ratio (SNR) and total harmonic distortion (THD), through a process known as “noise shaping.” The added stages and noise shaping measures would lead to circuit complexity, extraneous delay / phase-shift, decreased stability, spurious tones, and pronounced deadbands. The implementations of the present disclosure, however, can achieve high over sampling ratio (OSR) and low quantization noise in the band of interest with only two (2) or fewer stages, while reducing tone magnitude and pushing the tone frequency below the band of interest. The implementations incorporate a dynamic hysteretic error correcting quantizer / comparator, which can be installed on a variety of systems where quantization error can be measured and used to correct hysteresis error dynamically on the basis of each trigger or clock cycle.

[0042] In more detail, the implementations pursue a dynamic hysteresis adjustment using measured quantization error from one cycle to adjust a hysteresis threshold used at the next or a subsequent cycle rather than polarity-based hysteresis or range-based quantizer. For example, US6,924,757 describes an approach in which hysteresis is changed according to a range of theinput signal. This approach can cause a step response and potential instability, thus requiring many stages for maintaining performance. In contrast, the implementations of the present disclosure can adjust a hysteresis threshold at every clock cycle (or a subset of clock cycles) to correct the instantaneous quantisation error (e.g., from the immediately preceding clock cycle), leading to far fewer stages for achieving circuit functionalities. The implementations can allow the output switching frequency (Fsw) to be slowed while maintaining a high clock frequency where the accumulator would ramp to positive and negative values rather than simply change polarity (e.g., toggling). Such features can reduce not just the quantization error by orders of magnitude, but also generally eliminate deadbands even in a single stage design. Additionally, as the hysteresis threshold is variable and changes over time at the granularity of each clock cycle, the Finite State Machine (FSM) repetition which causes tones is greatly expanded to include the number of possible states. As a result, tones are greatly reduced in both magnitude and frequency. Further, some implementations may incorporate an overflow protection of, for example, only one accumulator guaranteeing system wide stability. In various implementations, Over Current Protection (OCP) can be merged with a delta sigma modulator so that inverters (e.g., as used by D-class audio amplifiers, and EV motors) can have limit protection combined with the signal encoder.

[0043] The implementations incorporate low complexity single bit high quality signal reproduction, which can fit easily into existing micro controllers, thus enabling mass-market high- quality signal conversion. Notably, the implementations can provide a single bit output that is natively compatible with switching output stages and inherently linear when the transfer function has full-scale positive and negative reference points, thereby rendering a multi-bit quantizer unnecessary. In various implementations, the output switching frequency (Fsw) is low enough to drive D-class / power inverters directly with no interim filtering and remodulation circuits. Significantly, the implementations pursue single cycle quantization error correction that can be used on, for example, sigma-delta modulators. For example, the implementations incur ultralow propagation delay as a result of low complexity and parallel quantization correction. The ultralow propagation delay can be instrumental in realizing noise cancellation over a wideband and enabling low latency variable frequency motor control. The implementations incorporate open loop that allows analog volume control by controlling the output voltage without bit shifting, while maintaining the dynamic range of the output so that no bits are lost. Moreover, the implementationsallow for stability protection. For example, real-time Over Current Protection (OCP) can be embedded with a quantizer or comparator of the implementations.

[0044] The implementations can drive a large network (e.g., a neural network) of similar nodes with improved hysteretic control. The nodes of the network can receive multiple input signals that are continuous in time and characterized by a frequency range. The network can include a combiner that combines the input signals and generates a single output value. When this network is presented with data representing a continuously updating source of information, the hysteretic quantization imparted can improve the general performance and stochastic behaviour linearity of the network, leading to improved performance by virtue of using backward propagation of error to update the weighting value of the inputs in the combiner. In this manner, the implementations can be effective for deploying both digital-based and analog-based neural networks, while using either synchronous (clocked) or spontaneous or spiked (internally generated trigger) operation, or using any combination of operations.

[0045] The implementations can also improve the general level and stability of event activations in sensors having a large number of individual sensing and quantizing units related to a physical input, such as light. For example, in an event based digital camera, each pixel generates an output at regular or irregular intervals based on detected events corresponding to changes in light intensity. The output can be in the form of three states - up, down, or no event. In conventional designs, the selection of the output state, or the triggering of an up or down event, is based on the output from a single light-dependent signal and a logarithmic or similar nonlinear combination. Using the disclosed implementations to provide updates of the hysteresis thresholds related to the transition events can allow for improved effective performance when representing the changing input signal with fewer output events. In this manner, the disclosed implementations can improve the operation of threshold comparators used in neuromorphic sensing.

[0046] Fig. 1A illustrates an example of a diagram 100 of a first order sigma-delta modulator as used in prior art. As a logic illustration, the diagram 100 shows electrical components (e.g., capacitors) are represented as mathematical devices (e.g., “Sigma” accumulators). Input signal 101 (V_in) may be bounded within a range of, for example, +1 to -IV. Summing circuit 102 represents a combining module in which the currents controlled by V_in and DAC- are summed. This represents the “Delta” operation (e.g., V_in - V(DAC)). Here, DAC refers to digital-to-analog converter. V(DAC) represents the feedback signal from quantizer 104. In general terms, V(DAC)represents quantizer output. The result of the “Delta” operation is then accumulated in capacitor Cl, which performs the “Sigma” operation, as represented by integrator 103. In analog-input systems, the integrator 103 may be an analog integrator, which can be implemented using either switched-capacitor techniques or standard analog linear techniques. In digital-input systems, the integrator 103 are discrete-time integrators, implemented with standard digital hardware such as adders and registers.

[0047] Here, XI is the resulting output of integrator 103. Quantizer 104 is coupled to integrator 103 to receive the resulting output XI. Quantizer 104 outputs high when XI is positive, and low when XI is negative. Quantizer 104 is time gated by a clock signal CLK, allowing the output of quantizer 104 to reach DAC+ (and its complement DAC-) at every rising edge of the clock signal. The clock signal can be 50MHz. Within the confines of this disclosure, the terms of “quantizer” (as a 1 -bit quantizer) can be used interchangeably as a “comparator.” The output of quantizer 104 can be provided to a 1 -bit digital-to-analog (DAC) converter (e.g., module 105) so that a feedback signal (DAC-) is provided to the summing circuit 102. The output of quantizer 104 is also provided to a digital filter or digital decimator so that a continuous output can be generated to drive downstream devices or components.

[0048] Fig. IB shows, in macro view, a diagram 110 that includes examples of voltage waveforms generated by the sigma-delta modulator in Fig. 1A. In the diagram 110, V_in, corresponding to waveform 111, is a 100p V constant voltage. This voltage is high enough to pass a quantization threshold of quantizer 104. V(X1), corresponding to waveform 113, illustrates the integrator repeating pattern and quantisation error. The repeating pattern impact can be seen in V(Out+), which corresponds to waveform 114 as a filtered representation of the comparator output. For example, a two-stage output filter with a roll-off frequency of 50kH can be used to filter the output of quantizer 104, as explained above. The V(DAC-) shown in Fig. IB as waveform 112 exhibits an average frequency of 23.75MHz, which can be far too fast for a real switch mode power stage.

[0049] Fig. 1C shows, in micro view, a diagram 120 that includes the same examples from Fig. IB where the time scale has been zoomed to better illustrate the time quantization impact on integrator XI and V(Out+). The step appearance in V(X1), corresponding to waveform 123, at around 160ps is the result of the integrator taking two clock cycles to be triggered instead of previously triggering at one clock cycle. The step appearance results in a DC offset, as reflectedin the filtered output shown in V(out+), corresponding to waveform 124. At this clock frequency, V(X1), corresponding to waveform 123, is within a 42mV peak-to-peak range. Specifically, the peak-to-peak voltage of XI is about 40.27mV in Fig. 1C as a result of taking two (2) clock cycles to transition. Waveform 122 shows the zoomed view of V(DAC-), which exhibits the average frequency of 23.75MHz. Waveform 121 shows V_in, which is the lOOpV constant voltage sufficiently high to pass the quantization threshold of quantizer 104.

[0050] While Figs. IB to 1C show results of the high switching frequency (Fsw) quantisation error and spurious tones, Figs. ID to IE respectively show results of low Fsw quantisation error and spurious tones. For example, Fig. ID includes a diagram 130 showing the resulting waveforms when the clock signal is reduced to 1MHz. As a result, the output switching frequency (Fsw) of V(DAC-), which corresponds to waveform 132, is limited to around 500kHz. Here, a similar looping pattern results at a much slower rate, and with much larger quantization error. Notably, V(X1), which corresponds to waveform 133, is now over 2.2V peak-to-peak. Waveform 131 shows V_in, which is the l OOpV constant voltage sufficiently high to pass the quantization threshold of quantizer 104. Waveform 134 shows the filtered output V(Out+). Fig. IE includes a diagram 140 which shows the resulting noise spectrum in the band of interest. As shown in Fig. IE, the noise spectrum in the band of interest has a noise level starting at -74dB (relative to OdB, which corresponds to maximum output).

[0051] Fig. 2A illustrates an example of a diagram 200 of a second order sigma-delta modulator as used in prior art. Similar to Fig. 1A, the diagram 200 shows the logic diagram. Input signal 201 (V_in) may be bounded within a range of, for example, +1 to -IV. Summing circuit 202 may perform summing of currents controlled by V_in and DAC-. The summing represents the “Delta” operation (e.g., V_in - V(DAC)). The result of the Delta operation is then accumulated in capacitor Cl, which performs the “Sigma” operation, as represented by integrator 203. Here, XI is the resulting signal of integrator 203, which is the first stage of the sigma-delta modulator. Summing circuit 204 may perform summing of currents controlled by V(X1) and DAC-, the result of which is then accumulated by integrator 205. Here, X2 is the resulting output of integrator 205. Quantizer 206 is coupled to integrator 205 to receive the resulting output X2. Quantizer 206 outputs high when X2 is positive, and low when X2 is negative. Quantizer 206 is time gated by a clock signal CLK, allowing the output of quantizer 206 to reach DAC+ (and its complement DAC-) at every rising edge of the clock signal. The output ofquantizer 206 can be provided to 1-bit DACs (e.g., module 207 and 208) so that respective feedback signals are provided to summing circuits 202 and 204.

[0052] Figs. 2B to 2F show various waveforms as well as a representative noise spectrum associated with the second order sigma-delta modulator. For example, Figs. 2B and 2C show, respectively, diagram 210 (macro view) and diagram 220 (micro view), each including examples of voltage waveforms generated by the second order sigma-delta modulator in Fig. 2A. For example, diagram 210 shows waveform 211 for V_in, which is a l OOpV constant voltage sufficiently high for the quantization threshold of quantizer 206. Waveform 212 shows an example of V(DAC-), which exhibits an average frequency of 23.75MHz. Here, the clock frequency is 50MHz. As noted above, this frequency is far too fast for a real switch mode power stage. Waveforms 213 and 214 respectively show examples of V(X1) and V(X2), illustrating the integrator repeating pattern and quantisation error. Waveform 215 shows an example of V(Out+) as a filtered representation of the comparator output. Diagram 220 shows the same examples with the micro view where the time scale has been zoomed in to better illustrate the time quantization impact on integrator XI and X2 and V(Out+). Here, waveforms 223, 224, and 225 respectively correspond to V(X1), V(X2), and V(Out+). Waveforms 221 and 222 respectively correspond to V(V_in) and V(DAC-). These examples demonstrate quantisation error and spurious tones when using a high switching frequency (Fsw) under a clock frequency of 50MHz.

[0053] In comparison, Figs. 2D and 2E show waveforms resulting from a slower switching frequency (Fsw). As shown, diagram 230 (macro view) and diagram 240 (micro view) include examples of voltage waveforms generated by the second order sigma-delta modulator in Fig. 2A when the clock signal is at 1MHz. Using a clock frequency of 1MHz, the switching frequency (Fsw) of V(DAC-), which corresponds to waveform 232 in Fig. 2D and waveform 242 in Fig. 2E, is limited to around 500kHz. This lowered switching frequency results in a similar looping pattern at a much slower rate, albeit with much larger quantization error. Notably, V(X1), which corresponds to waveform 233 in Fig. 2D and waveform 243 in Fig. 2E, and V(X2), which corresponds to waveform 234 in Fig. 2D and waveform 244 in Fig. 2E, are both over 2.2V peak- to-peak. Waveform 231 in Fig. 2D and waveform 241 in Fig. 2E show V_in, which is the lOOp V constant voltage sufficiently high to pass the quantization threshold of quantizer 206. Waveform 235 in Fig. 2D and waveform 245 in Fig. 2E show the filtered output V(Out+). Fig. 2F includesdiagram 250 which shows the resulting noise spectrum in the band of interest, with a noise level starting at -84dB (relative to OdB, which corresponds to maximum output).

[0054] Preferred implementations of the present disclosure will now be described.

[0055] Referring first to Fig. 6, there is illustrated a process flow diagram showing a method 600 of operating a quantizer according to one implementation. The method 600 comprises, at step 601 accumulating the sum of an input signal and a past output of the quantizer to produce an accumulated signal. This accumulation may be a result of a summing and integrating circuit in a delta-sigma modulator as described above.

[0056] At step 602, in response to a trigger (e.g. a clock signal), the accumulated signal is compared with one or more target hysteresis thresholds. The comparison may be made by feeding the accumulated signal to one or more comparators in which the one or more target threshold values represent hysteresis thresholds. The hysteresis thresholds define the range of input values over which the comparator does not switch its output state. This range creates a threshold band or buffer zone to prevent frequent switching due to small fluctuations or noise in the input signal. The one or more comparators may have one hysteresis threshold, two hysteresis thresholds (e.g. an upper and a lower threshold) or a greater number of hysteresis thresholds.

[0057] At step 603, a determination is made as to whether the accumulated signal is greater than a corresponding target hysteresis threshold value (or lower than a lower target hysteresis threshold value). For an upper hysteresis threshold, if the accumulated signal is not greater than the threshold value, then control returns to step 601 and accumulation at a next trigger or clock cycle begins. Similarly, for a lower hysteresis threshold, if the accumulated signal is not less than the threshold value, then control returns to step 601 and accumulation at a next trigger or clock cycle begins. In this case, the quantizer still produces a quantized output but the threshold value is not adjusted.

[0058] At step 604, upon determining that the accumulated signal exceeds the one or more threshold values (or is lower in the case of a lower hysteresis threshold), at least one of the one or more threshold values are selectively adjusted. By way of example, if an upper threshold value is exceeded, then that threshold is adjusted. Where there are multiple thresholds (e.g. an upper and a lower threshold), those thresholds may be adjusted by the same amount or by a different amount depending on the overshoot or undershoot measured. Specifically, the threshold(s) are adjusted by an amount that is based on a difference between the accumulated signal and a target hysteresisthreshold value. The target hysteresis threshold value is a system parameter that may be predefined and may be based on a comparator reference level. In some embodiments, the target hysteresis threshold value is set based on a target frequency of operation of the quantizer. In some embodiments, the target hysteresis threshold value is set based on a target application of a device in which the signal quantizer or signal quantizing module operates. In some embodiments the target threshold(s) may be changed. In some embodiments, the target hysteresis threshold is fixed over time. In other embodiments, the target hysteresis threshold may be varied over time in conjunction with the dynamic hysteresis control described herein.

[0059] Where an upper and a lower hysteresis threshold is dynamically adjusted, the dynamic adjustment of the thresholds may be made independent of one another or the adjustment may be dependent or proportional to one another.

[0060] At step 605, the quantizer state is changed, a quantizer output is produced and control returns to step 601 with the updated hysteresis threshold value(s) applied.

[0061] Turning now to Figs. 3A-3B illustrate an example of a first order sigma-delta modulator with single cycle dynamic hysteresis control according to the implementations of the present disclosure. Although the implementations will be described with reference to voltage signals, it will be appreciated that the implementations apply equally to various other types of signals that can be processed.

[0062] For example, Fig. 3A illustrates a diagram 300 of a first order dynamic hysteresis sigma-delta modulator according to some implementations of the present disclosure. Diagram 300 is a logic illustration which shows electrical components (e.g., capacitors) represented as mathematical devices (e.g., “Sigma” accumulators). Input signal 301 (V_in) may be bounded within a range of, for example, between + 1 and - 1 V. A combining module in the form of summing circuit 302 may perform the summing of currents controlled by V_in and DAC-. The summing represents the “Delta” operation, e.g., as provided by V_in - DAC. The result of the Delta operation is then accumulated in capacitor Cl of integrator 303, which performs the “Sigma” operation. Here, XI is the resulting output of integrator 303. Quantizer 304 is coupled to integrator 303 to receive the resulting output XI.

[0063] Quantizer 304 operates a dynamic hysteresis control in which a hysteresis threshold is adjusted at each clock cycle. More generally, where a regular clock signal is not provided, the hysteresis threshold may be dynamically adjusted by another reoccurring trigger, which is eitherinternal or external to the system. Where quantizer 304 comprises high and low transitions, this adjustment may affect both the transition from low to high, and the transition from high to low, as connoted by boxes 304A and 304B. In particular, at a clock cycle edge or trigger signal when the quantizer is triggered, the quantizer may compare an input to the quantizer with the target hysteresis threshold. Responsive to the current input to the quantizer crossing the hysteresis threshold, the hysteresis threshold is adjusted by an amount that characterizes a difference between the target hysteresis threshold and the input to the quantizer so that the adjusted hysteresis threshold is applied when the quantizer is triggered the next time (e.g., at the next clock cycle). Where the quantizer incorporates a sigma-delta modulator, the input to the quantizer represents the current accumulator value of the modulator. However, in other types of systems the input to the quantizer represents other inputs.

[0064] The hysteresis threshold that is dynamically adjusted represents a current error value that is used to modify the system behaviour to reduce the quantization error. This is different from the target hysteresis threshold, which is a system parameter that either stays constant or may be separately modified over time. Importantly, in the present invention, the level of adjustment to the current hysteresis threshold is always based at least in part on, or with reference to, the level of the target hysteresis threshold. This is a distinct point of difference over prior art systems such as US6,924,757. In particular, the adjustment may be made independently of the range of the input signal to be quantized.

[0065] As mentioned above, the adjustment to the hysteresis threshold is performed based on a difference between the target hysteresis threshold and the input to the quantizer. Here, a “difference” may refer to an exact difference calculation such as a simple subtraction or it may represent a relative difference between the two values so that the correction applied reduces the error or difference in subsequent samples. In other words, the system uses the difference as an indicator of how much the target hysteresis threshold was missed by and to determine a correction that will reduce that difference. In some embodiments, the adjustment may be a fraction of the determined difference between the target hysteresis threshold and the input to the quantizer. In some embodiments, the adjustment may be made based on memory or knowledge of previous adjustments to the hysteresis threshold.

[0066] Quantizer 304 is time gated by a clock signal CLK, allowing the output of quantizer304 to reach DAC+ (and its complement DAC-) when the quantizer is triggered at every edge ofthe clock signal. The edge may be the rising edge, or the falling edge, or both. In some embodiments, the quantizer is triggered at other times relative to a clock or trigger signal. The clock signal can be 50MHz. The output of quantizer 304 can be provided to a 1-bit digital-to- analog (DAC) converter (e.g., buffer module 305) so that a feedback signal (DAC-) is provided to the summing circuit 302. An output 306 of quantizer 304 is also provided to a digital filter or digital decimator so that a continuous output can be generated to drive downstream devices or components.

[0067] Fig. 3B provides a representative modelling diagram 310 of the same first order dynamic hysteresis sigma-delta modulator of Fig. 3 A. Input signal V_in (311) is modeled as a voltage source V 1. Currents controlled by input signal V_in (311) and feedback signal V(DAC-) (315) are summed at node 312 where a summing circuit can be implemented. This summing corresponds to the “Delta” operation (e.g., V_in - V(DAC)). The result of the Delta operation is then accumulated in accumulator 313 with capacitor C2, which performs the “Sigma” operation. As illustrated, accumulator 313 includes overflow protection, for example, using range-limiting diode D2. Here, XI is the resulting output of accumulator 313. Quantizer 314 is coupled to accumulator 313 to receive the resulting output XI as its input. Quantizer 314 includes a dynamic hysteresis comparator 314A, which is controlled by a dynamic hysteresis in which a threshold hysteresis is adjusted at each clock cycle or recurring trigger times so that the adjusted threshold hysteresis is applied when the quantizer is triggered the next time (e.g., at the next clock cycle). This adjustment of threshold hysteresis is performed by updating the threshold hysteresis value(s) of the comparator or other device from which the output is triggered from low to high (or vice versa). An initial target hysteresis threshold may be predefined and set based on a desired frequency of operation or a desired application of a device. This target hysteresis threshold is then updated dynamically.

[0068] Quantizer 314 also includes a D flip flop 314B that is time gated by a clock signal CLK, represented as voltage source V2 (316). This configuration allows the output of quantizer 314 to reach DAC+ (and its complement DAC-) at every rising edge of the clock signal. The clock signal can be 50MHz. A feedback signal (DAC-) is provided to summing node 312 in the modelling diagram.

[0069] Fig. 3C shows a diagram 320 illustrating an example of dynamic hysteresis control according to some implementations of the present disclosure. In diagram 320, waveform 322represents V(DAC-) while waveform 323 represents V(X1). Line 324 represents the target level of positive hysteresis (pos_Hyst), which can be set at, for example 500mV. Lines 329 A and 329 B represent the inputs to the quantizer. In this example, the target negative hysteresis (neg_Hyst) is set at -500mV. Line 321 represents that actual level of hysteresis threshold - pos_Hyst - that is dynamically updated. Initially, line 324 and line 321 are identical, both at 500mV in this example. At a first clock edge T1 where the V(X1) is above line segment 321 A, the output of the quantizer goes from high to low, causing V(X1) to fall. Segment 325D1 corresponds to the difference between the peak of V(X1) and line 324 at Tl. This difference is also known as quantization error (Qerr), which is the amount of overshoot in this example at TL The overshoot amount is subtracted from the target hysteresis threshold pos_Hyst, which leads to a drop of line 321, resulting in line segment 32 IB. At the next clock edge T2 where V(X1) is above line segment 321B, the difference between V(X1) and line 324 is measured. Here the peak value of V(X1) is still slightly above line 324. As a result, the difference represented by segment 325D2 is again subtracted from line 321, pushing it lower to line segment 321C. In the event of a third event T3 (not shown) where V(X1) peak is below line 321, the quantization error would be negative, and would therefore cause line 321 to be raised up by that amount. Notably, similar dynamic adjustment is performed on neg_Hyst, independent of the dynamic adjustment to pos_Hyst. Fig. 3D shows a diagram 330 illustrating a macro view of single cycle dynamic hysteresis quantizer error correction that spans more than 19 positive peaks of V(X1).

[0070] Fig. 3E shows a diagram 340 illustrating an example of the noise spectrum of a first order sigma-delta modulator with single cycle dynamic hysteresis according to some implementations of the present disclosure. The noise spectrum covers a band of interest of the audio range (e.g., from 20Hz to 20kHz). As explained above, an input of lOOpV is used (to cause a pattern response). Here, the noise is below -lOOdB with no apparent tones, whereas with the static hysteresis the worst tone is around -74dB, as shown above in Fig. 2F. Thus, the improvement associated with implementations of the present disclosure is demonstrated.

[0071] Figs. 3F and 3G respectively show the macro view diagram 350 and micro view diagram 360 of waveforms generated by a first order static hysteresis sigma delta, as described in, e.g., US6,924,757B2 where the hysteresis control is applied according to a range of the input voltage to the sigma-delta modulator. The quantization error and spurious tones are shown in both the macro view diagram 350 and the micro view 360. Fig. 3H includes diagram 370, whichshows the noise spectrum of V(Out+) where the noise floor is under -lOOdB, but with pronounced spikes of tonal noise in the kilo-Hertz range.

[0072] Fig. 4A illustrates an example of a diagram of a second order sigma-delta modulator with single cycle dynamic hysteresis control according to the implementations. Similar to Fig. 2A, the diagram 400 shows a logic diagram where the input signal 401 (V_in) is bounded within a range of, for example, +1 to -IV. Summing circuit 402 may perform summing of currents controlled by V_in and DAC-. The summing represents the “Delta” operation (e.g., V_in - V(DAC)). The result of the Delta operation is then accumulated in capacitor Cl, which performs the “Sigma” operation, as represented by integrator 403. Here, XI is the resulting signal of integrator 403, which is the first stage of the sigma-delta modulator. Summing circuit 404 may perform summing of currents controlled by V(X1) and V(DAC-), the result of which is then accumulated by integrator 405. Here, X2 is the resulting output of integrator 405. Quantizer 406 is coupled to integrator 405 to receive the resulting output X2. Quantizer 406 operates a dynamic hysteresis control consistent with the example shown in quantizer 304 of Fig. 3A. The hysteresis adjustment is performed at each clock cycle and affects both the transition from low to high, and the transition from high to low, as connoted by boxes 406A and 406B. Quantizer 406 is time gated by a clock signal CLK, allowing the output of quantizer 406 to reach DAC+ (and its complement DAC-) at every rising edge of the clock signal. The output of quantizer 406 can provide a feedback signal (DAC-) to the summing circuit 402 (via buffer 407) and summing circuit 404 (via buffer 408).

[0073] Fig. 4B includes diagram 410, which shows the noise spectrum of the 2ndorder sigma-delta modulator of Fig. 4A. Fig. 4C includes diagram 420, which shows the noise spectrum of the 2ndorder sigma-delta modulator of Fig. 2A. A side-by-side comparison reveals that the noise spectrum of Fig. 4C has distinct tones, starting at -105dB, in the kilo-hertz range while the noise spectrum of Fig. 4C only shows a tone under -117dB, which is barely above the noise floor. The improved performance over known prior art is thus demonstrated.

[0074] The following pseudo code provides an example of a dynamic hysteresis adjustment process according to some implementations of the present disclosure.If ( Output == low ){ if (input >= positive_hysteresis){Output = high positive_hysteresis = positive_hysteresis + ( target_hysteresis - input )}} else if (input <= negative_hysteresis){Output = low negative_hysteresis= negative_hysteresis - ( target_Hysteresis + input )}

[0075] Initially, the dynamic hysteresis adjustment process, as implemented on a mixed- signal circuit (such as a sigma-delta modulator that includes a quantizer or comparator), may determine whether a clock signal that drives the mixed-signal circuit is running at a clock edge. If the clock signal has not reached a clock edge, e.g., a rising edge, or a falling edge, no action is needed because no triggering is taking place.

[0076] Responsive to the clock signal reaching a clock edge, the dynamic hysteresis adjustment process may determine whether the output of, e.g., the quantizer, is at the logic low. Responsive to determining that the output of the quantizer is at the digital low, the dynamic hysteresis adjustment process may determine whether the input to the quantizer has increased to reach the level of the positive hysteresis (pos_Hyst). As explained above, the presence of hysteresis introduces an amount of overdrive needed to change the output, which can depend on the toggling direction of the quantizer (e.g., whether from digital low to digital high, or from digital high to digital low). Here, if the comparison between the input and the level of positive hysteresis reveals that the input is increasing and reached the level of positive hysteresis, the output of the quantizer is toggled from digital low to digital high. Within the same clock cycle, the level of positive hysteresis is adjusted to accommodate the difference between the input and a targethysteresis when the comparison is made so that at the next clock cycle, the adjusted positive hysteresis, which remembers the error from the earlier clock cycle, can be used to cumulatively further correct the error. The examples above (e.g., from Figs. 3A to 3C) show a target hysteresis at 500mV when V_in is bounded within the range of -1 and +1 V. Because the target hysteresis is applied equally to the upper bound, and lower bound, the overall result is zero.

[0077] Responsive to determining that the output of the quantizer is not at the digital low, the dynamic hysteresis adjustment process may determine whether the input to the quantizer has decreased to reach the level of the negative hysteresis (neg_Hyst). Given the binary nature of the quantizer, when the output of the quantizer is not at the digital low, it is at the digital high. Here, if the comparison between the input and the level of positive hysteresis reveals that the input is decreasing and has reached the level of negative hysteresis, the output of the quantizer is toggled from digital high to digital low. Within the same clock cycle, the level of negative hysteresis is adjusted to accommodate the difference between the input and the negative hysteresis when the comparison is made so that at the next clock cycle, the adjusted negative hysteresis can be used to cumulatively further correct the error.

[0078] In the above example, the adjustment amount is applied to either one of the positive hysteresis and the negative hysteresis based on a measured difference between the input and the target hysteresis. In other examples, the adjustment amount can be applied to both the positive hysteresis and the negative hysteresis based on the average of errors on both the positive and negative sides.

[0079] While the examples above describe a sigma-delta modulator, the implementations can be applied to a wide variety of mixed-signal circuits that have a quantizer or a comparator with hysteresis characteristics. As explained in detail above, the implementations include a dynamic hysteretic error correcting quantizer / comparator in which the hysteretic error is corrected dynamically in each clock cycle so that the correction takes effect immediately at the next clock cycle. Significantly, the correction of the implementations of the present disclosure does not depend on the range of input voltages. The performance of the implementations, as measured by the noise spectra shown above, demonstrate marked improvements in terms of substantially lowered noise floor and reduced tonal appearance. Indeed, the implementations can adjust hysteresis at each clock cycle to correct the instantaneous quantization error, and needs far fewer stages, e.g., in a sigma-delta modulator. The reduced complexity can achieve a slow down of theswitching frequency while maintaining a high clock rate and the associated oversampling ratio. In this manner, the quantization error is reduced by orders of magnitude, as evidenced by the noise spectra of the implementations. Moreover, the deadband, where the output does not change even though the input is fluctuating, can be eliminated by implementations of the present disclosure. The benefits and advantages of the implementations of the present disclosure are not limited to the above discussion.

[0080] By way of illustration, the implementations can be incorporated in a variety of hysteresis control applications (e.g., switching power supplies and motor control). In such exemplary applications, maintaining accurate control of a physical quantity (e.g., voltage, current) are advantageous. Such advantages include accuracy, precision, and stability associated with hysteresis controllers consistent with the implementations of the present disclosure. Because hysteresis controllers are designed to maintain a controlled parameter within a narrow hysteresis band, the error introduced due to hysteresis can lead to a lack of accuracy and precision in maintaining the desired parameter within the specified range. The hysteresis controllers may overshoot or undershoot the setpoint, resulting in less precise control, as well as deadbands - where small changes to the input have no impact on output. Hysteresis controllers can exhibit hunting or chattering behaviour when the controlled parameter fluctuates rapidly around the hysteresis band due to the controller constantly switching between on and off states. Such fluctuations can cause a host of issues, including decreased system stability. Indeed, hysteresis error can affect the stability of the control system. The hysteresis error can introduce oscillations and hinder settling to a stable operating point. To mitigate hysteresis error in hysteresis controllers, the implementations can further incorporate techniques such as improved feedback mechanisms, smaller hysteresis bands, and digital signal processing. The implementations may further incorporate advanced control techniques and algorithms such as, for example, proportional- integral-derivative (PID) controllers. Further, the implementations can include a variety of techniques depending on the specific application as well as the trade-offs between simplicity, cost, and performance.

[0081] Figs. 5A and 5B respectively show diagrams 500 and 510 that compare and contrast static hysteresis control and dynamic hysteresis control according to some implementations of the present disclosure. Diagram 500 shows a hysteretic control scheme which turns the switch OFF to start ramp down when curve 501 reaches the upper limit 502 and turns the switch ON whencurve 502 reaches the lower limit 503. The average is then set at the average of the upper and lower limits. The ON and OFF times (and thus the switching frequency) vary as the input and output signal change to maintain the curve 501. However, in a practical implementation of hysteretic control, comparator delays are involved where the switch will not turn ON and OFF at the instant when curve 501 hits the limits, but after a small delay time, as illustrated. Given these delays, the actual average may deviate from the desired level.

[0082] In comparison, diagram 510 shows a hysteretic control scheme according to some implementations of the present disclosure where the upper limit and the lower limit are adjusted based on the error seen at the comparator, e.g., at each clock cycle. For illustration, the upper limit and the lower limit are initially set at levels 512A and 513 A respectively. When curve 511 ramps up and overshoots level 512A (e.g., based on comparing a value on curve 511 and the upper limit), the upper limit is updated to level 512B to account for the error seen by the comparator. The switch is then turned OFF so that curve 511 ramps down. When curve 511 crosses level 513 A (e.g., based on comparing a value on curve 511 with the lower limit), the lower limit is then updated to level 513B to account for the error seen by the comparator. Such dynamic adjustment is shown as “modified hysteresis” in Fig. 5B.

[0083] The invention can achieve high OSR and low quantisation noise in the band of interest with typically only 2 or fewer stages, all while reducing tone magnitude and frequency below the band of interest. The invention works with any system where quantisation error can be measured and used to correct dynamic hysteresis.

[0084] Benefits of embodiments of the present disclosure include:• Low complexity, single bit high quality signal reproduction, fitting easily in existing micro controllers enabling mass market high quality signal conversion.• Single bit output, natively compatible with switching output stages and inherently linear (multibit unnecessary)• Output switching frequency (Fsw) low enough to drive D-class / power inverters directly- no interim filtering and remodulation.• Single cycle, quantization error correction works with any sigma-delta configuration.• Ultra low propagation delay (due to low complexity and parallel quantization correction.) Critical for wide bandwidth noise cancellation, enables low latency variable frequency motor control etc.Simple stability protection• Open loop allows “analog” volume control by varying output voltage without bit shifting, maintaining dynamic range (no lost bits due to shifting)• Real-time Over Current Protection (OCP) embedded in converter Interpretation

[0085] Throughout this specification, use of the terms “hysteresis level”, threshold hysteresis”, “hysteresis threshold”, “hysteresis value” or the like are intended to be synonymous. In this regard, mention of “control” or “adjustment” to hysteresis is intended to mean controlling or adjusting the hysteresis threshold.

[0086] A mixed-signal circuit is an integrated circuit or electronic system that processes both analog and digital signals. It combines analog circuitry, which handles continuously variable signals, with digital circuitry, which processes discrete, binary signals. This integration allows for the interaction and conversion between analog and digital domains, enabling functions such as analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), signal conditioning, and complex data processing within a single device. Mixed-signal circuits are essential in applications where both types of signals coexist, such as in telecommunications, audio and video processing, instrumentation, and control systems.

[0087] A quantizer is a component in the process of signal quantization, responsible for converting a continuous range of signal values into a finite set of discrete levels. This transformation involves mapping the input signal's amplitude to the nearest value within a predefined set of levels, effectively discretizing the signal for further digital processing, storage, or transmission. The process of quantization inherently introduces quantization noise or error, which is the difference between the actual analog value and its quantized representation. Quantizers are widely used in digital signal processing, telecommunications, audio and video compression, and various other applications that require the conversion of continuous signals to discrete digital data.

[0088] A hysteresis threshold in a quantizer refers to the specific input levels that determine when the quantizer will change its output state, incorporating a form of memory to prevent rapid toggling between adjacent quantization levels. In a quantizer with hysteresis, thereare typically two thresholds for each decision boundary: one for increasing the output level and one for decreasing it.

[0089] Described methods, processes, or logic flows represent one or more examples of functionality consistent with the present disclosure and are not intended to limit the disclosure to the described or illustrated implementations, but to be accorded the widest scope consistent with described principles and features. The described methods, processes, or logic flows can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output data. The methods, processes, or logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, for example, a central processing unit (CPU), a graphic processing unit (GPU), an FPGA (field programmable gate array), or an ASIC (application specific integrated circuit). For example, the described logic flows can be performed by firmware, which can be installed and activated on a mixed-signal circuit.

[0090] In the claims below and the description herein, any of the terms "comprising", "comprised of", "which comprises" or similar are open terms that mean including at least the elements / features that follow, but not excluding others. Thus, the term "comprising" and its variations, when used in the claims or description, should not be interpreted as being limitative to the means or elements or steps listed thereafter. For example, the scope of the expression a device comprising A and B should not be limited to devices consisting only of elements A and B. Similarly, any of the terms "including", "which includes", "that includes" or similar as used herein are also open terms that also mean including at least the elements / features that follow the term, but not excluding others. Thus, "including" is synonymous with and means "comprising".

[0091] As used herein, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

[0092] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what can be claimed, but rather as descriptions of features that can be specific to particular implementations. Certain features that are described in this specification in the context of separate implementations or embodiments can also be implemented, in combination, in a single implementation or embodiment. Conversely,various features that are described in the context of a single implementation can also be implemented in multiple implementations, separately, or in any sub-combination. Moreover, although previously described features can be described as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination can be directed to a sub-combination or variation of a sub-combination.

[0093] Particular implementations of the subject matter have been described. Other implementations, alterations, and permutations of the described implementations and embodiments are within the scope of the following claims as will be apparent to those skilled in the art. While operations are depicted in the drawings or claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed (some operations can be considered optional), to achieve desirable results.

Claims

CLAIMSWhat is claimed is:

1. A signal quantizer for quantizing an input signal, the signal quantizer comprising a dynamic hysteresis adjustment feedback loop to adjust a hysteresis threshold, wherein the adjustment to the hysteresis threshold is based at least in part on a difference between the input to the quantizer and a target hysteresis level of the quantizer.

2. The signal quantizer of claim 1 wherein the adjustment is made in response to a reoccurring trigger.

3. The signal quantizer of claim 2 wherein the reoccurring trigger comprises a clock signal having a regular clock cycle.

4. The signal quantizer of claim 3 wherein the adjustment is made within the same clock cycle.

5. The signal quantizer of claim 1 wherein the quantizer comprises a positive hysteresis threshold and a negative hysteresis threshold and the same adjustment is made to both the positive and negative hysteresis thresholds.

6. The signal quantizer of claim 1 wherein the quantizer comprises a positive hysteresis threshold and a negative hysteresis threshold and a separate adjustment is made to the positive hysteresis threshold and the negative hysteresis threshold.

7. The signal quantizer of claim 1 wherein the input to the quantizer is provided by a deltasigma modulator.

8. The signal quantizer of claim 1 forming part of an analog-to-digital converter.

9. A method of operating a quantizer, the method comprising:accumulating the sum of an input signal and a past output of the quantizer to produce an accumulated signal; in response to a trigger, comparing the accumulated signal with one or more threshold values; upon determining that the accumulated signal exceeds the one or more threshold values, selectively adjusting at least one of the one or more threshold values by an amount that is based at least in part on a difference between the accumulated signal and a target threshold value.

10. A signal quantizing module comprising: a combining module configured to combine an input signal and a feedback signal to generate a combined signal; an integrator module coupled to the combining module and configured to: generate, using the combined signal, an integrated signal; and a quantizer configured to generate an output signal based on, at least in part, the integrated signal, wherein the output signal is looped back to provide the feedback signal for the combining and integrator modules, and wherein, the quantizer is further configured to: when the quantizer is triggered at a first time point, compare an input to the quantizer with a threshold hysteresis, and responsive to the input to the quantizer reaches the threshold hysteresis, adjust the threshold hysteresis by an amount that characterizes a difference between a target hysteresis and the input to the quantizer at the first time point.

11. The signal quantizing module of claim 10, wherein, when the quantizer is triggered at a second time point after the first time point, the quantizer operates to compare the input to the quantizer at the second time point with the threshold hysteresis that has been adjusted based on the amount determined at the first time point.

12. The signal quantizing module of claim 10 or claim 11, wherein, responsive to a change in the input signal to the signal quantizing module, the change is propagated through the signal quantizing module to affect the output signal of the quantizer as early as one clock cycle later.

13. The signal quantizing module of any one of claims 10 to 12, wherein the threshold hysteresis comprises a symmetric pair of a positive hysteresis level and a negative hysteresis level, wherein the positive hysteresis level is adjusted each time the input to the quantizer exceeds the positive hysteresis level while the output signal is at a digital low, and wherein the negative hysteresis level is adjusted each time the input to the quantizer falls under the negative hysteresis level while the output signal is at a digital high.

14. The signal quantizing module of claim 13, wherein the amount for adjusting the positive hysteresis level when the input to the quantizer exceeds the positive hysteresis level is determined by a gap between the input to the quantizer and the positive hysteresis level, and wherein the amount for adjusting the negative hysteresis level when the input to the quantizer falls under the negative hysteresis level is determined by a gap between the negative hysteresis level and the input to the quantizer.

15. The signal quantizing module of claim 13, wherein the amount for adjusting the positive hysteresis level when the input to the quantizer exceeds the positive hysteresis level is determined by an average of a first difference between the input to the quantizer and the target hysteresis and a second difference between the target hysteresis and the input to the quantizer, and wherein the amount for adjusting the negative hysteresis level when the input to the quantizer falls under the negative hysteresis level is also determined by the average of the first difference and the second difference.

16. The signal quantizing module of any one of claims 10 to 15, wherein the threshold hysteresis is adjusted when the quantizer is triggered such that the difference between the target hysteresis and the input to the quantizer is without a tonal appearance.

17. The signal quantizing module of any one of claims 10 to 16, wherein, when the input signal is at a constant level that is above a quantization threshold of the quantizer, the output signal exhibits no tonal appearance.

18. The signal quantizing module of any one of claims 1 to 17, wherein a spectrum of the output signal exhibits a power level under lOOdB between 20Hz and 20kHz.

19. The signal quantizing module of any one of claims 1 to 18, wherein the quantizer is triggered at a clock cycle edge.

20. The signal quantizing module of claim 19 wherein the clock cycle edge comprises a rising edge.

21. The signal quantizing module of claim 20, wherein the clock cycle edge comprises a falling edge.

22. The signal quantizing module of claim 20 or claim 21 , wherein the clock is characterized by a frequency higher than a frequency of the output signal generated by the quantizer.

23. The signal quantizing module of claim 22, wherein the frequency of the clock is higher than the frequency of the output signal by a factor of up to 100.

24. The signal quantizing module of any one of claims 10 to 23, further comprising: a limiter circuit coupled to the quantizer such that the output signal of the quantizer is range bounded.

25. The signal quantizing module of any one of claims 10 to 24, further comprising: a filter circuit coupled to an output of the quantizer and configured to process the output signal of the quantizer and generate a modulated signal for at least one downstream circuit coupled to the signal quantizing module.

26. The signal quantizing module of any one of claims 1 to 25, wherein the signal quantizing module is a high order modulator comprising multiple stages of the summing circuit and the integrator circuit arranged in a cascade, and wherein each stage in the cascade includes an instance of the combining module and an instance of the integrator module coupled thereto.

27. The signal quantizing module of any one of claims 10 to 26, wherein each integrator module comprises a capacitor.

28. The signal quantizing module of any one of claims 10 to 27, wherein each combining module comprises an operational amplifier configured to: sum an input signal and the feedback signal; and drive the integrator module coupled thereto.

29. The signal quantizing module of any one of claims 10 to 28, wherein the quantizer comprises a gate-controlled comparator.

30. The signal quantizing module of any one of claims 10 to 29, further comprising: a digital filter coupled to the quantizer and configured to receive the output signal; and a decimator coupled to the digital filter and configured to generate a digital signal output for the signal quantizing module.

31. A signal quantizing module comprising: a plurality of input terminals configured to receive a plurality of input signals that are continuous temporally and characterized by a frequency range; a combiner coupled to the input terminals configured to process the plurality of input signals; an output port coupled to the combiner and configured to generate one of a set of predetermined levels based on, at least in part, results from the combiner, wherein the signal quantizing module is driven by a set of threshold hysteresis values,wherein the signal quantizing module is operable to generate a series of trigger events with an occurring frequency that exceeds the frequency range of the input signals, such that, at a first trigger event of the series of trigger events, the output port generates an output based on, at least in part, a threshold hysteresis value and a result of the combiner processing the plurality of input signals, and at a second trigger event that is subsequent to the first trigger event, in response to the output of the combiner crossing threshold hysteresis value from the set of threshold hysteresis values, one or more threshold hysteresis values is updated by an amount dependent on, at least in part, a difference between a target hysteresis and the output of the combiner at the first trigger event.

32. The signal quantizing module of claim 31 , wherein the one or more hysteresis threshold is updated based on, at least in part, the difference between the target hysteresis and the output of the combiner at the first trigger event, and a duration between the first and second trigger events.

33. The signal quantizing module of claim 31 or claim 32, wherein the first or the second trigger event is generated from a clock external to the signal quantizing module and independent of the input signals.

34. The signal quantizing module of any one of claims 31 to 33, wherein the second trigger event is created by the signal quantizing module internally, based on, at least in part, a duration since the first trigger event.

35. The signal quantizer or signal quantizing module of any one of the preceding claims wherein the target hysteresis is set based on a target frequency of operation of the quantizer.

36. The signal quantizer or signal quantizing module of any one of claims 1 to 34 wherein the target hysteresis is set based on a target application of a device in which the signal quantizer or signal quantizing module operates.

37. A threshold comparator for comparing an input signal with a threshold value, the threshold comparator comprising a dynamic hysteresis adjustment feedback loop that adjusts a hysteresisthreshold around the threshold value, wherein the adjustment to the hysteresis threshold is based at least in part on a difference between the input to the comparator and a target hysteresis level of the comparator.

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