Semiconductor processing system and semiconductor processing method therefor

Abstract

Disclosed are a semiconductor processing system and a semiconductor processing method therefor. The semiconductor processing system comprises: a semiconductor processing device, comprising a first cavity part and a second cavity part, a first through-hole, and a second through-hole, wherein the cavity parts are each provided with a recessed groove formed by recessing from the surface of an inner wall of the corresponding cavity part, and a surface of a semiconductor wafer abuts against the surface of the inner wall on which the recessed groove is formed so as to form a closed channel; a wafer conveying device, comprising a manipulator and a control device, the manipulator being controlled by the control device to perform an angle adjustment operation on the semiconductor wafer; and a drive and valve assembly, used to control a fluid to enter the closed channel so as to process a partial region of the surface of the semiconductor wafer. The manipulator performs an angle adjustment operation on the semiconductor wafer, such that contaminating impurities in more selected regions of the semiconductor wafer can be extracted and detected.

Description

Semiconductor processing system and semiconductor processing method thereof

Technical field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor processing system and a semiconductor processing method thereof. [Background Technology]

[0002] As semiconductor size continues to decrease, impurities contained in the silicon wafer material itself have become a requirement that needs to be detected and monitored in quality control. However, current wafer contamination detection technology is limited to extracting and detecting impurity contamination on the wafer surface or performing destructive testing on the entire wafer material.

[0003] Chinese patent application numbers 201210171681.9 and 201210088237.0 disclose a microchamber processing device for wafer processing. The microchamber processing device includes a first chamber portion and a second chamber portion. The first chamber portion and the second chamber portion are relatively movable between an open position for loading and / or removing the wafer and a closed position for accommodating and processing the wafer under the drive of a drive device. When the first chamber portion and the second chamber portion are in the closed position, a microchamber is formed. The wafer is placed in the microchamber. The first chamber portion and / or the second chamber portion include one or more inlets for processing fluid to enter the microchamber and one or more outlets for processing fluid to exit the microchamber.

[0004] When the processing fluid enters the microchamber through the inlet of the microchamber to process the wafer, the direction of the processing fluid flow is generally fixed, but there is a lack of corresponding control mechanism to ensure the degree of reaction between the processing fluid and the wafer. Although the existing technology can ensure the extraction efficiency of surface pollutants when extracting and detecting wafer surface contamination as long as a sufficient reaction time is given, when extracting and detecting impurities inside the wafer material, since the liquid is required to corrode the wafer material, different reaction degrees will cause the corrosion depth of the processing fluid on the wafer surface to have a large error and be difficult to control. In this way, when detecting impurities inside the wafer material, the processing fluid collected after the reaction can only obtain a qualitative situation of the overall impurity contamination inside the wafer material, and cannot accurately obtain the quantitative situation of impurity contamination within a given depth range inside the wafer material. Further, it is even more impossible to obtain the distribution of impurity contamination at different depths inside the wafer.

[0005] To this end, Chinese patent application number 201710078489.8 discloses a wafer local processing method. However, this wafer local processing method can only extract and detect contaminants in a few local areas of the wafer, and there are many areas where contaminants cannot be extracted and detected.

[0006] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art.

[0007] [Summary of the invention]

[0008] An object of the present invention is to provide a semiconductor processing system and a semiconductor processing method thereof, which can extract and detect contaminant impurities in more selected areas of a semiconductor wafer.

[0009] To achieve the above objectives, the present invention provides a semiconductor processing system comprising:

[0010] A semiconductor processing apparatus comprising a first chamber portion and a second chamber portion movable relative to the first chamber portion between an open position and a closed position, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a microchamber is formed between the first and second chamber portions, and a semiconductor wafer can be accommodated in the microchamber. When the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be removed from or placed in the microchamber. The first chamber portion and / or the second chamber portion comprises a groove channel formed by a depression in an inner wall surface of the corresponding chamber portion, a first through-hole extending from the outside through the corresponding chamber portion to communicate with a first position of the groove channel, and a second through-hole extending from the outside through the corresponding chamber portion to communicate with a second position of the groove channel. When the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first and second chamber portions, a surface of the semiconductor wafer abuts against an inner wall surface forming the groove channel. At this time, the groove channel forms a closed channel due to the obstruction of the surface of the semiconductor wafer. The closed channel communicates with the outside through the first through-hole and the second through-hole.

[0011] A wafer transfer device, comprising a robot and a control device, wherein under the control of the control device, the robot performs an angle adjustment operation on a semiconductor wafer located between a first chamber portion and a second chamber portion, the angle adjustment operation comprising: picking up the semiconductor wafer located between the first chamber portion and the second chamber portion when the second chamber portion is in the open position relative to the first chamber portion and adjusting the angle of the semiconductor wafer; repositioning the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion, and rotating the repositioned semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer;

[0012] A drive and valve assembly controls the fluid to enter the closed channel through one of the first through hole and the second through hole when the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion. The fluid entering the closed channel can move along the guidance of the closed channel. At this time, the fluid can contact a partial area of ​​the surface of the semiconductor wafer. The fluid flowing through the surface of the semiconductor wafer flows out through the other through hole of the first through hole and the second through hole and is extracted.

[0013] According to another aspect of the present invention, the present invention provides a semiconductor processing method based on the semiconductor processing system described above, comprising: moving the second chamber portion to an open position relative to the first chamber portion; under the control of a control device, the manipulator performs an angle adjustment operation on the semiconductor wafer located between the first chamber portion and the second chamber portion, the angle adjustment operation comprising: picking up the semiconductor wafer located between the first chamber portion and the second chamber portion when the second chamber portion is in the open position relative to the first chamber portion and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer; moving the second chamber portion to a closed position relative to the first chamber portion; injecting fluid into the groove channel through one of the first through hole and the second through hole, the fluid traveling along the closed channel until the other through hole of the first through hole and the second through hole, and extracting the fluid from the other through hole.

[0014] Compared with the prior art, in the present invention, since the robot can perform angle adjustment operations on the semiconductor wafer, contamination impurities in more selected areas of the semiconductor wafer can be extracted and detected.

[0015] It should be understood that this summary is provided only for the purpose of summarizing some embodiments in order to provide a basic understanding of some aspects of the present invention. Therefore, the above-mentioned embodiments are merely examples and should not be interpreted as narrowing the scope or concept of the present invention in any way. The features, aspects, and advantages of the various embodiments will become apparent upon reading the following detailed description and the accompanying drawings, which illustrate the principles of some embodiments by way of example.

Brief Description of the Drawings

[0016] The present invention will be more readily understood with reference to the accompanying drawings and the following detailed description, wherein like reference numerals correspond to like structural components, and wherein:

[0017] FIG1a is a schematic cross-sectional view of a semiconductor processing apparatus according to an embodiment of the present invention;

[0018] FIG1b is an enlarged schematic diagram of circle A in FIG1a;

[0019] FIG1c is an enlarged schematic diagram of circle B in FIG1a;

[0020] FIG2 a is a top view of the second chamber portion in one embodiment of the present invention;

[0021] FIG2 b is an enlarged schematic diagram of circle C in FIG2 a ;

[0022] FIG2c is an enlarged schematic diagram of circle D in FIG2a;

[0023] FIG2 d is a schematic cross-sectional view along the section line AA in FIG2 a ;

[0024] FIG2e is an enlarged schematic diagram of circle E in FIG2d;

[0025] FIG2 f is an enlarged schematic diagram of circle F in FIG2 a ;

[0026] FIG3 a is a top view of the first chamber portion in one embodiment of the present invention;

[0027] FIG3 b is an enlarged schematic diagram of circle G in FIG3 a ;

[0028] FIG3 c is an enlarged schematic diagram of circle H in FIG3 a ;

[0029] FIG3 d is a schematic cross-sectional view along the section line BB in FIG3 a ;

[0030] FIG3e is an enlarged schematic diagram of circle I in FIG3d;

[0031] FIG3 f is an enlarged schematic diagram of circle J in FIG3 a ;

[0032] FIG4 a is a schematic cross-sectional view of a semiconductor processing device according to another embodiment of the present invention;

[0033] Figure 4b is an enlarged schematic diagram of circle K in Figure 4a;

[0034] FIG5 a is a top view of the first chamber portion in one embodiment of the present invention;

[0035] FIG5b is a schematic cross-sectional view along the section line CC in FIG5a;

[0036] FIG5c is an enlarged schematic diagram of circle L in FIG5a;

[0037] FIG6 a is a top view of the second chamber portion in another embodiment of the present invention;

[0038] FIG6b is an enlarged schematic diagram along circle M in FIG6a;

[0039] FIG. 7 is a schematic flow chart of a semiconductor processing method according to an embodiment of the present invention.

[0040] FIG8 is a schematic structural diagram of a semiconductor processing system according to another embodiment of the present invention;

[0041] FIG. 9 is a schematic flow chart of a semiconductor processing method according to another embodiment of the present invention. [Specific embodiment]

[0042] Some embodiments of the present invention will be described more fully below with reference to the accompanying drawings, some, but not all, of which are listed. Indeed, various embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this disclosure thorough and complete and will fully convey the scope of the invention to those skilled in the art. For example, unless otherwise stated, referring to something as first, second, etc. should not be construed as implying a particular order. Furthermore, something may be described as being higher than something (unless otherwise stated) when it is actually lower than something, and vice versa; similarly, something described as being on the left may be on the right, and vice versa. The same reference figure number always represents the same element.

[0043] The details of the present invention can be more clearly understood in conjunction with the accompanying drawings and the description of the specific embodiments of the present invention. However, the specific embodiments of the present invention described herein are for illustrative purposes only and are not to be construed as limiting the present invention in any way. Based on the teachings of the present invention, skilled artisans can conceive of any possible variations based on the present invention, all of which should be considered within the scope of the present invention. It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there can be an intermediate element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there can be an intermediate element. The terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, internal communication between two elements, direct connection, or indirect connection through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are intended only to describe specific embodiments and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] Part 1

[0046] In order to better extract and detect contaminants in the wafer, a semiconductor processing device is also proposed in this application.

[0047] Figure 1a is a schematic cross-sectional view of a semiconductor processing apparatus 100 according to one embodiment of the present invention. Figure 1b is an enlarged schematic view of circle A in Figure 1a; and Figure 1c is an enlarged schematic view of circle B in Figure 1a. As shown in Figure 1a, the semiconductor processing apparatus 100 includes a first chamber section 110 and a second chamber section 120. In this embodiment, the first chamber section 110 is the upper chamber section, and the second chamber section 120 is the lower chamber section. In other embodiments, the lower chamber section may be defined as the first chamber section, and the upper chamber section may be defined as the second chamber section.

[0048] The first chamber portion 110 includes an upper chamber plate 111 and a first flange 112 extending downward from a periphery of the upper chamber plate. The second chamber portion 120 includes a lower chamber plate 121 and a first groove 122 recessed downward from a periphery of the lower chamber plate 121 .

[0049] The first chamber portion 110 is movable between an open position and a closed position relative to the second chamber portion 120. When the first chamber portion 110 is in the open position relative to the second chamber portion 120, a semiconductor wafer can be placed on or removed from the inner wall surface of the second chamber portion 120. When the first chamber portion 110 is in the closed position relative to the second chamber portion 120, the first flange 112 cooperates with the first groove 122 to form a sealed microchamber between the upper chamber plate and the lower chamber plate. The semiconductor wafer can be accommodated in the microchamber to await subsequent processing.

[0050] Figure 2a is a top view of the second chamber portion 120 according to one embodiment of the present invention. Figure 2b is an enlarged schematic diagram of circle C in Figure 2a. Figure 2c is an enlarged schematic diagram of circle D in Figure 2a. Figure 2d is a cross-sectional schematic diagram along section line AA in Figure 2a. Figure 2e is an enlarged schematic diagram of circle E in Figure 2d. Figure 2f is an enlarged schematic diagram of circle F in Figure 2a.

[0051] As shown in Figures 2a-2f, the second chamber portion 120 includes a groove channel 124 formed by a depression formed from an inner wall surface 123 of the second chamber portion 120 facing the microchamber, a first through-hole 125 extending from the outside through the second chamber portion to communicate with a first position of the groove channel 124, and a second through-hole 126 extending from the outside through the second chamber portion to communicate with a second position of the groove channel 124. The cross-section of the groove channel 124 can be U-shaped, V-shaped, or semicircular, or other shapes. The number of through-holes within the groove channel 124 can be greater than or equal to one.

[0052] As shown in Figures 1a, 1b, and 1c, when the first chamber portion 110 is in the closed position relative to the second chamber portion 120 and the semiconductor wafer 200 is accommodated in the microchamber, one surface (lower surface) of the semiconductor wafer 200 abuts against the inner wall surface 123 forming the groove channel 124. At this time, the groove channel 124 forms a closed channel with the help of the obstruction of the surface of the semiconductor wafer 200. The closed channel is connected to the outside through the first through hole 125 and the second through hole 126. During use, the processing fluid can enter the closed channel through the first through hole 125. The fluid entering the closed channel can move forward along the guidance of the closed channel. At this time, the processing fluid can contact and treat a portion of the surface of the semiconductor wafer 200. The fluid that has treated the surface of the semiconductor wafer 200 can flow out and be extracted through the second through hole 126. In this way, not only can the flow direction and flow rate of the processing fluid be accurately controlled, but the amount of processing fluid can also be greatly saved.

[0053] In one embodiment, as shown in Figures 2a, 2b, and 2c, the groove channel 124 is spirally arranged, wherein the first through hole 125 is located in the central region of the spiral groove channel (the region indicated by circle D), and the second through hole 126 is located in the peripheral region of the spiral groove channel 124 (the region indicated by circle C). The first through hole 125 can be used as an inlet, and the second through hole 126 can be used as an outlet. In other embodiments, the first through hole 125 can be used as an outlet, and the second through hole 126 can be used as an inlet.

[0054] In one embodiment, as shown in Figures 2d, 2e, and 2f, the first through-hole 125 includes a first buffer opening portion 125a that is directly connected to the groove channel 124 and is deeper and wider than the groove channel 124, and a first through-hole portion 125b that is directly connected to the first buffer opening portion 125a. The provision of the first buffer opening portion 125a prevents the initial velocity of the processing fluid entering through the first through-hole 125 from being too high, which could lead to over-processing of the central area of ​​the semiconductor wafer. The second through-hole 126 includes a second buffer opening portion 126a that is directly connected to the groove channel 124 and is deeper and wider than the groove channel 124, and a second through-hole portion 126b that is directly connected to the second buffer opening portion 126a. The provision of the second buffer opening portion 126a prevents the processing fluid from being unable to be discharged from the second through-hole 126 in a timely manner and overflowing. Preferably, the first buffer opening portion 125a can be a tapered groove, and the second buffer opening portion 126a can be a cylindrical groove.

[0055] Figure 3a is a top view of the first chamber portion 110 in one embodiment of the present invention; Figure 3b is an enlarged schematic diagram of circle G in Figure 3a; Figure 3c is an enlarged schematic diagram of circle H in Figure 3a; Figure 3d is a sectional schematic diagram along the section line BB in Figure 3a; Figure 3e is an enlarged schematic diagram of circle I in Figure 3d; Figure 3f is an enlarged schematic diagram of circle J in Figure 3a.

[0056] 3a to 3f , the first chamber portion 110 includes an upper chamber plate 111 and a first flange 112 extending downward from the periphery of the upper chamber plate 111. The first chamber portion 110 has a groove channel 113 recessed from an inner wall surface 113 of the first chamber portion facing the microchamber. The groove walls of the groove channels 114 formed on the inner wall surface 113 of the first chamber portion (the portion between adjacent groove channels 114) correspond to the groove walls of the groove channels 124 formed on the inner wall surface 123 of the second chamber portion 120 (the portion between adjacent groove channels 124) ( FIG. 1b and FIG. 1c ). Thus, when the first chamber portion 110 is in the closed position relative to the second chamber portion 120 and the semiconductor wafer 200 is accommodated in the microchamber, the groove walls of the groove channels 114 of the first chamber portion 110 can press against the corresponding position of the semiconductor wafer 200, allowing the semiconductor wafer 200 to more tightly abut the groove walls of the groove channels 124 of the second chamber portion 120, thereby improving the sealing performance of the resulting closed channel. In addition, the groove walls of the groove channels 114 formed on the inner wall surface 113 of the first chamber portion (the portion between adjacent groove channels 114) and the groove walls of the groove channels 124 formed on the inner wall surface 123 of the second chamber portion 120 (the portion between adjacent groove channels 124) can also be arranged in an interlaced manner.

[0057] In another alternative embodiment, the structures of the first chamber portion 110 and the second chamber portion can be interchangeable or have the same structure. In this case, the upper surface of the semiconductor wafer 200 forms a closed channel together with the groove of the first chamber portion 110. The processing fluid flowing through the closed channel can process the upper surface or the lower surface of the semiconductor wafer 200, or both surfaces simultaneously.

[0058] Figure 4a is a schematic cross-sectional view of another embodiment of a semiconductor processing apparatus 200 according to the present invention; Figure 4b is an enlarged schematic view of the circle K in Figure 4a. The semiconductor processing apparatus 400 in Figure 4a differs from the semiconductor processing apparatus in Figure 1a in that the structure of the first chamber portion 410 in Figure 4a differs from that of the first chamber portion 110 in Figure 1a. Figure 5a is a top view of the first chamber portion 410 according to one embodiment of the present invention; Figure 5b is a schematic cross-sectional view taken along section line CC in Figure 5a; and Figure 5c is an enlarged schematic view of the circle L in Figure 5a. As shown in Figures 5a to 5c, the first chamber portion 410 includes an upper chamber plate 411, a first flange 412, a first inner wall surface 413 facing the microchamber, a second groove 414, a second flange 415 located between the first inner wall surface 413 and the second groove 414, and a channel 416 located in the center of the first inner wall surface 413. The second flange 415 abuts against the semiconductor wafer 200 and the first inner wall surface 413 to form a closed space, which is connected to the outside world through the channel 416. Fluid can enter this closed space through the channel 416 to generate pressure, and force the semiconductor wafer 200 to abut more tightly against the groove wall of the groove channel 124 of the second chamber portion 120, thereby improving the sealing performance of the resulting closed channel.

[0059] Figure 6a is a top view of another embodiment of the second chamber portion 620 of the present invention; Figure 6b is an enlarged schematic view along circle M in Figure 6a. Multiple grooves 624 are formed by recessing the inner wall surface 623 of the second chamber portion 620 facing the microchamber. Figure 6a shows five grooves 624, but other numbers may be used in other embodiments. Each groove 624 corresponds to a first through-hole 625 and a second through-hole 626. The different grooves 624 of the second chamber portion 620 are located in different regions of the inner wall surface 623. This allows for independent treatment of different regions.

[0060] The present invention also provides a semiconductor processing method using the semiconductor processing apparatus. As shown in FIG7 , the semiconductor processing method 700 includes the following steps.

[0061] Step 710 , placing the second chamber portion 120 in an open position relative to the first chamber portion 110 ;

[0062] Step 720 , placing the semiconductor wafer between the second chamber portion 120 and the second chamber portion 110 ;

[0063] Step 730 , placing the second chamber portion 120 in a closed position relative to the first chamber portion 110 ;

[0064] Step 740 , injecting fluid into the groove channel 124 through the first through hole 125 ;

[0065] Step 750 , driving the fluid along the closed channel to the second through hole 126 ;

[0066] In step 760 , the fluid is extracted from the second through hole 126 .

[0067] In one embodiment, element detection can be performed based on the extracted fluid, so that the elements remaining on the surface of the semiconductor wafer and their concentrations can be obtained.

[0068] In one embodiment, the fluid is a liquid or a gas, and is a reaction fluid or an extraction fluid. The reaction fluid is capable of reacting with the surface of the semiconductor wafer in contact with it. The extraction fluid is capable of extracting contaminants from the surface of the semiconductor wafer in contact with it.

[0069] The fluid can be driven to move within the closed channel by a driving fluid, or by air pressure, such as by a vacuum pump, to draw a vacuum. The driving fluid can be an ultrapure gas or liquid that is not easily reactive, such as nitrogen, helium, argon, ultrapure water, acetone, tetrachloromethane, or the like.

[0070] In another embodiment, the first through hole 125 may also serve as a fluid outlet, and the second through hole 126 may serve as a fluid inlet.

[0071] Part 2

[0072] FIG8 is a schematic structural diagram of another embodiment of a semiconductor processing system 600 according to the present invention. As shown in FIG8 , the semiconductor processing system 600 includes a semiconductor processing device 810 , a wafer transfer device 820 , and a drive and valve assembly 830 .

[0073] The semiconductor processing device 810 may be the semiconductor processing device described in the above embodiments. Preferably, the second chamber portion of the semiconductor processing device 810 is shown in FIG6 a.

[0074] The wafer transfer device 820 includes a robot and a control device. Under the control of the control device, the robot can perform an angle adjustment operation on a semiconductor wafer located between the first chamber portion and the second chamber portion. The angle adjustment operation includes: when the second chamber portion is in the open position relative to the first chamber portion, picking up the semiconductor wafer located between the first chamber portion and the second chamber portion, adjusting the angle of the semiconductor wafer, repositioning the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion, and rotating the repositioned semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer.

[0075] The drive and valve assembly 830 controls the fluid to enter the closed channel through one of the first through hole and the second through hole when the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion. The fluid entering the closed channel can move forward along the guidance of the closed channel. At this time, the fluid can contact a partial area of ​​the surface of the semiconductor wafer. The fluid flowing through the surface of the semiconductor wafer flows out through the other through hole of the first through hole and the second through hole and is extracted.

[0076] In one embodiment, there are multiple grooves, each corresponding to a first through hole and a second through hole. Different grooves are located in different areas of the inner wall surface, and the center of at least one groove is spaced a predetermined distance from the center of the inner wall surface where the at least one groove is located. More preferably, the centers of multiple grooves are spaced a predetermined distance from the center of the inner wall surface where the multiple grooves are evenly distributed around the center of the inner wall surface where the multiple grooves are located, and the center of one groove coincides with the center of the inner wall surface where the groove is located. Specifically, as shown in Figures 6a and 6b, there are five grooves 624, namely 6241, 6242, 6243, 6244, and 6245. The centers of grooves 6241, 6242, 6244, and 6245 are spaced a predetermined distance from the center of the inner wall surface where the groove is located. The center of groove 6243 coincides with the center of the inner wall surface where the groove is located.

[0077] In another embodiment, there may be one groove track, the center of which is spaced a predetermined distance from the center of the inner wall surface, and the groove track is located in a local area of ​​the inner wall surface. For example, as shown in Figures 6a and 6b, in a modified embodiment, only one of the five groove tracks 624 may be retained, such as any one of groove tracks 6241, 6242, 6244, and 6245.

[0078] As shown in FIG6a , after the manipulator performs an angle adjustment operation on the semiconductor wafer located between the first chamber portion and the second chamber portion, the areas on the semiconductor wafer corresponding to the grooves 6241, 6242, 6244, and 6245 will change. For example, if the control device sets the predetermined angle to 45 degrees, then after the manipulator performs an angle adjustment operation on the semiconductor wafer located between the first chamber portion and the second chamber portion, the areas corresponding to the grooves 6241, 6242, 6244, and 6245 will change after the semiconductor wafer rotates 45 degrees along its center. At this time, the grooves 6241, 6242, 6244, and 6245 are used again to extract and detect contaminants on the surface of the semiconductor wafer. This allows for extraction and detection of contaminants on more selected areas (or even any area) of the semiconductor wafer as needed.

[0079] Obviously, the control device can set the predetermined angle as needed. The predetermined angle can be any angle, such as 2 degrees, 5 degrees, 45 degrees, 135 degrees, etc. In one embodiment, under the control of the control device, the robot can perform multiple angle adjustments on the semiconductor wafer located between the first chamber portion and the second chamber portion. For example, if the second chamber portion in Figure 6a only contains groove channel 6241, the predetermined angle can be set to 45 degrees. By repeating the angle adjustment operation eight times, the groove channel 6241 can traverse the entire perimeter of the semiconductor wafer. After each angle adjustment operation, the drive and valve assembly 830 uses the groove channel 6241 to perform fluid extraction and testing, thereby enabling fluid processing of different selected areas of the semiconductor wafer using a single groove channel 6241. Furthermore, if the groove channel 6241 is relatively small, the predetermined angle can be reduced, such as to 10 degrees, to allow the groove channel 6241 to traverse the entire perimeter of the semiconductor wafer. In other embodiments, the groove track may not traverse all areas of the semiconductor wafer.

[0080] In one embodiment, under the control of the control device, the robot also performs a semiconductor wafer loading operation, and the semiconductor wafer loading operation includes: the robot picks up a semiconductor wafer from the outside (such as an external wafer box), and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located in the open position relative to the first chamber part; under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located in the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside (such as an external wafer box).

[0081] In one embodiment, different semiconductor wafers can be placed in the microchamber at different angles using a robot, with the same groove channel corresponding to different regions of the different semiconductor wafers. When processing each semiconductor wafer, the drive and valve assembly drives fluid to flow through each groove channel and extract the fluid. Based on the extracted fluid, test data for each semiconductor wafer is obtained, and the test data of different semiconductor wafers are combined to obtain uniformity test data for the semiconductor wafers. Specifically, taking the second chamber portion shown in FIG6a as an example, a batch of semiconductor wafers is processed. A first portion of the semiconductor wafers are sequentially placed in a semiconductor processing device at the same angle for contamination and impurity extraction and detection. A second portion of the semiconductor wafers are rotated 45 degrees and then placed in a semiconductor processing device for contamination and impurity extraction and detection. The test data of the first portion of the semiconductor wafers and the test data of the second portion of the semiconductor wafers are combined to obtain uniformity test data for the batch of semiconductor wafers. This can reduce the extraction area for each semiconductor wafer by nearly half, but the test data of more than two semiconductor wafers can be combined to obtain uniformity test data.

[0082] In one embodiment, multiple channels are selected from a plurality of channels. When processing a semiconductor wafer, the drive and valve assembly drives the same fluid to flow sequentially through the selected channels. Specifically, taking the second chamber portion shown in FIG6a as an example, channels 6241, 6243, and 6244 are selected for contaminant extraction and detection. The drive and valve assembly can drive the same fluid to flow sequentially through the selected channels 6241, 6243, and 6244. Specifically, after the fluid flows out of channel 6241, it is driven again to channel 6243. Then, after flowing out of channel 6243, it is driven again to channel 6244. Finally, the fluid is extracted and tested to obtain test data. In this way, the same fluid can flow through more and selected surface areas of the semiconductor wafer, improving detection accuracy and detection rate, and providing more options.

[0083] In another embodiment, at least one of the multiple groove channels is selected, and when processing different semiconductor wafers, the drive and valve assembly drives the same fluid to repeatedly flow through the selected at least one groove channel. Specifically, taking the second chamber portion shown in Figure 6a as an example, groove channel 6241 is selected, and then the drive and valve assembly drives the same fluid to flow through groove channel 6241 to extract contaminants from the first semiconductor wafer. The second semiconductor wafer is then replaced, and the same fluid is again used to flow through groove channel 6241 to extract contaminants from the second semiconductor wafer. The third semiconductor wafer is then replaced, and the same fluid is again used to flow through groove channel 6241 to extract contaminants from the third semiconductor wafer. This process is repeated, and the resulting fluid is tested to obtain test data. In this way, the same area of ​​different semiconductor wafers can be repeatedly tested to improve test accuracy and detection rate.

[0084] In another embodiment, the above extraction and detection schemes may be mixed.

[0085] 9 is a flow chart of another embodiment of a semiconductor processing method based on the semiconductor processing system of the present invention. The semiconductor processing method includes the following steps.

[0086] Step 910 , positioning the second chamber portion in an open position relative to the first chamber portion;

[0087] Step 920: Under the control of the control device, the robot arm performs an angle adjustment operation on the semiconductor wafer located between the first chamber portion and the second chamber portion. The angle adjustment operation includes: when the second chamber portion is in the open position relative to the first chamber portion, picking up the semiconductor wafer located between the first chamber portion and the second chamber portion and adjusting the angle of the semiconductor wafer; repositioning the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion; and rotating the repositioned semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer.

[0088] Step 930 , causing the second chamber portion to be in a closed position relative to the first chamber portion;

[0089] Step 940 : injecting fluid into the groove channel through one of the first through hole and the second through hole, the fluid traveling along the closed channel to the other through hole of the first through hole and the second through hole, and extracting the fluid from the other through hole.

[0090] In one embodiment, the semiconductor processing method further includes: under the control of the control device, the robot also performs a semiconductor wafer loading operation, and the semiconductor wafer loading operation includes: the robot picks up an external semiconductor wafer and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located in the open position relative to the first chamber part; under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located in the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside.

[0091] For the same contents of the semiconductor processing method and the semiconductor processing system, please refer to the introduction of the semiconductor processing system, which will not be repeated here.

[0092] The above description is intended to be illustrative rather than restrictive. Although the present invention has been described with reference to specific illustrative examples, it should be understood that the present invention is not limited to the described embodiments. The scope of the present invention should be determined with reference to the claims and the full scope of equivalents to which the claims are entitled.

[0093] The "one example (embodiment)" or "example (embodiment)" referred to herein means that the specific features, structures or characteristics associated with the embodiment may be included in at least one implementation of the present invention. The "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it necessarily a separate or selected embodiment that is mutually exclusive with other embodiments. "Multiple" and "several" in the present invention mean two or more. "And / or" in the present invention means "and" or "or". In addition, the terms "first", "second", "third", "fourth" and the like used herein are intended to be used as labels to distinguish different elements, and may not necessarily have sequential meanings according to their numerical designations. Therefore, the terms used herein are only for the purpose of describing specific implementations and are not intended to be limiting.

[0094] It should also be noted that in some alternative embodiments, the functions / actions noted may not occur in the order noted in the figures. For example, two figures shown in succession may actually be performed substantially simultaneously or may sometimes be performed in reverse order, depending on the functions / actions involved.

[0095] Although the method operations are described in a particular order, it should be understood that other operations can be performed between the described operations. The described operations can be adjusted so that they occur at slightly different times, or the described operations can be distributed throughout the system. The system allows multiple unrelated programs to be processed simultaneously.

[0096] Many modifications and other implementations of the present invention involve those skilled in the art who have relevant industry knowledge and some original data. Therefore, it should be understood that the present invention is not limited to the specific embodiments disclosed, but also includes other embodiments modified within the scope of the appended claims. In addition, although the foregoing description and related drawings describe the implementation of specific embodiment combinations of elements and functions, within the scope of the appended claims, elements and functions that are implemented in different combinations by substitution are also included. The appended claims also include combinations of elements and functions that are different from the elements and functions explicitly described above. Although specific terms are used herein, they are intended to be generally descriptive only and not for limiting purposes.

Claims

1. A semiconductor processing system, characterized in that: It includes: A semiconductor processing device, comprising a first chamber portion, and a second chamber portion movable between an open position and a closed position relative to the first chamber portion, wherein when the second chamber portion is located at the closed position relative to the first chamber portion, a micro chamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the micro chamber, and when the second chamber portion is located at the open position relative to the first chamber portion, the semiconductor wafer can be taken out or put in, the first chamber portion and / or the second chamber portion has a groove channel formed by a depression from the inner wall surface of the corresponding chamber portion, a first through hole passing through the corresponding chamber portion from the outside to communicate with the first position of the groove channel, and a second through hole passing through the corresponding chamber portion from the outside to communicate with the second position of the groove channel, when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion, the surface of the semiconductor wafer abuts against the inner wall surface forming the groove channel, and at this time, the groove channel forms a closed channel by blocking the surface of the semiconductor wafer, and the closed channel communicates with the outside through the first through hole and the second through hole; A wafer conveying device, comprising a robot and a control device, wherein under the control of the control device, the robot performs an angle adjustment operation on a semiconductor wafer located between a first chamber portion and a second chamber portion, wherein the angle adjustment operation comprises: picking up the semiconductor wafer located between the first chamber portion and the second chamber portion when the second chamber portion is located at the open position relative to the first chamber portion and adjusting the angle of the semiconductor wafer, re-placing the semiconductor wafer after the angle adjustment between the first chamber portion and the second chamber portion, and rotating the re-placed semiconductor wafer by a predetermined angle relative to the previously placed semiconductor wafer; A drive and valve assembly controls the fluid to enter the closed channel through one of the first through hole and the second through hole when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion. The fluid entering the closed channel can move along the guidance of the closed channel. At this time, the fluid can contact a partial area of ​​the surface of the semiconductor wafer. The fluid flowing through the surface of the semiconductor wafer flows out through the other through hole of the first through hole and the second through hole and is extracted.

2. The semiconductor processing system according to claim 1, wherein: There is one groove, the center of which is spaced a predetermined distance from the center of the inner wall surface, and the groove is located in a local area of ​​the inner wall surface; or There are multiple grooves, each of which corresponds to a first through hole and a second through hole. Different grooves are located in different areas of the inner wall surface, and the center of at least one groove is separated from the center of the inner wall surface where the at least one groove is located by a predetermined distance.

3. The semiconductor processing system according to claim 2, characterized in that The centers of the plurality of grooves are spaced a predetermined distance from the center of the inner wall surface, wherein the plurality of grooves are evenly distributed around the center of the inner wall surface. The center of one groove track coincides with the center of the inner wall surface where the groove track is located.

4. The semiconductor processing device according to claim 2, wherein: Each groove track is spirally formed, wherein the first through hole is located in the central area of ​​the spiral groove track, and the second through hole is located in the peripheral area of ​​the spiral groove track.

5. The semiconductor processing system according to claim 1, wherein: Under the control of the control device, the robot also performs a semiconductor wafer loading operation, the semiconductor wafer loading operation comprising: the robot picks up an external semiconductor wafer and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part; Under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located at the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside.

6. The semiconductor processing system according to claim 1, wherein: The control device is capable of setting the predetermined angle, Under the control of the control device, the robot performs one or more angle adjustment operations on the semiconductor wafer located between the first chamber part and the second chamber part.

7. The semiconductor processing system according to claim 2, wherein: Different semiconductor wafers are placed in the micro-chamber at different angles by a robot, and the same groove corresponds to different areas of the different semiconductor wafers. When processing each semiconductor wafer, the drive and valve assembly drives the fluid to flow through each groove channel and extract it, and obtains the detection data of each semiconductor wafer based on the extracted fluid, and obtains the uniformity detection data of the semiconductor wafer by combining the detection data of different semiconductor wafers.

8. The semiconductor processing system according to claim 2, wherein: Selecting a plurality of groove channels, wherein the drive and valve assembly drives the same fluid to flow through the selected plurality of groove channels in sequence when processing a semiconductor wafer; or At least one of the plurality of groove channels is selected, and when processing different semiconductor wafers, the drive and valve assembly drives the same fluid to flow through the selected at least one groove channel repeatedly.

9. The semiconductor processing system according to claim 1, wherein: The fluid is a liquid or a gas, the fluid is a reaction fluid or an extraction fluid, The reactive fluid is capable of reacting with the surface of the semiconductor wafer in contact with it, The extraction fluid is capable of extracting contaminants from the surface of the semiconductor wafer with which it comes into contact.

10. A semiconductor processing method of a semiconductor processing system, the semiconductor system comprising a semiconductor processing device, a wafer conveying device and a drive and valve assembly, The semiconductor processing device comprises a first chamber portion, a second chamber portion movable between an open position and a closed position relative to the first chamber portion, wherein when the second chamber portion is located at the closed position relative to the first chamber portion, a micro chamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the micro chamber, and when the second chamber portion is located at the open position relative to the first chamber portion, the semiconductor wafer can be taken out or put in, the first chamber portion and / or the second chamber portion has a groove channel formed by a depression from the inner wall surface of the corresponding chamber portion, a first through hole passing through the corresponding chamber portion from the outside to communicate with the first position of the groove channel, and a second through hole passing through the corresponding chamber portion from the outside to communicate with the second position of the groove channel, when the second chamber portion is located at the closed position relative to the first chamber portion and the semiconductor wafer is accommodated between the first chamber portion and the second chamber portion, the surface of the semiconductor wafer abuts against the inner wall surface forming the groove channel, and at this time, the groove channel forms a closed channel with the help of the blocking of the surface of the semiconductor wafer, and the closed channel communicates with the outside through the first through hole and the second through hole; The wafer conveying device includes a robot and a control device. It is characterized in that The semiconductor processing method comprises: causing the second chamber portion to be in an open position relative to the first chamber portion; Under the control of the control device, the robot performs an angle adjustment operation on the semiconductor wafer located between the first chamber part and the second chamber part, and the angle adjustment operation includes: picking up the semiconductor wafer located between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part and adjusting the angle of the semiconductor wafer, and placing the semiconductor wafer after the angle adjustment The semiconductor wafer is placed between the first chamber portion and the second chamber portion, and the re-placed semiconductor wafer is rotated by a predetermined angle relative to the previously placed semiconductor wafer; bringing the second chamber portion into a closed position relative to the first chamber portion; A fluid is injected into the recessed channel through one of the first through hole and the second through hole, and the fluid travels along the closed channel to the other through hole of the first through hole and the second through hole, from which the fluid is extracted.

11. The semiconductor processing method according to claim 10, characterized in that: It also includes: Under the control of the control device, the robot also performs a semiconductor wafer loading operation, the semiconductor wafer loading operation comprising: the robot picks up an external semiconductor wafer and places the semiconductor wafer between the first chamber part and the second chamber part when the second chamber part is located at the open position relative to the first chamber part; Under the control of the control device, the robot also performs a semiconductor wafer unloading operation, and the semiconductor wafer unloading operation includes: when the second chamber part is located at the open position relative to the first chamber part, the robot picks up the semiconductor wafer in the semiconductor processing device and places it outside.

12. The semiconductor processing method according to claim 10, characterized in that: There is one groove, the center of which is spaced a predetermined distance from the center of the inner wall surface, and the groove is located in a local area of ​​the inner wall surface; or There are multiple grooves, each of which corresponds to a first through hole and a second through hole. Different grooves are located in different areas of the inner wall surface, and the center of at least one groove is separated from the center of the inner wall surface where the at least one groove is located by a predetermined distance.

13. The semiconductor processing method according to claim 10, characterized in that: The control device is capable of setting the predetermined angle, Under the control of the control device, the robot performs one or more angle adjustment operations on the semiconductor wafer located between the first chamber part and the second chamber part.

14. The semiconductor processing method according to claim 12, characterized in that: Different semiconductor wafers are placed in the micro-chamber at different angles by a robot, and the same groove corresponds to different areas of different semiconductor wafers. When processing each semiconductor wafer, the drive and valve assembly drives the fluid to flow through each groove channel and extract it, and obtains the detection data of each semiconductor wafer based on the extracted fluid, and obtains the uniformity detection data of the semiconductor wafer by combining the detection data of different semiconductor wafers.

15. The semiconductor processing method according to claim 12, characterized in that: Selecting a plurality of groove channels, wherein the drive and valve assembly drives the same fluid to flow through the selected plurality of groove channels in sequence when processing a semiconductor wafer; or At least one of the plurality of groove channels is selected, and when processing different semiconductor wafers, the drive and valve assembly drives the same fluid to flow through the selected at least one groove channel repeatedly.

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