High voltage and high current power system and method

Abstract

In a first embodiment provided herein, a high voltage and high power module (also referred to as a SuperMOS) comprising SiC MOSFETs that are connected in series and parallel configurations that can operate in concert to one another as, or equivalent to, a single device that could operate in high voltage and high current range. To mitigate mismatch operations due to multiple singled and paralleled devices, the exemplary power module includes both dynamic and static voltage balancing components as well as dynamic current balance circuit comprising a voltage gate clamp that are connected via a secondary parallel connection to ensure concerted dynamic current sharing.

Description

HIGH VOLTAGE AND HIGH CURRENT POWER SYSTEM AND METHODStatement of Government Support

[0001] This invention was made with government support under Grant numbers DE- EE0008348 and DE-AC05-00OR22725 awarded by the Department of Energy and Grant number N00014-21-1-2124 awarded by the Office of Naval Research. The government has certain rights in the invention.Related Application

[0002] This PCT application claims priority to, and the benefit of, U.S. Provisional Patent Application No. 63 / 588,658, filed October 6, 2023, entitled, “Methods of fabricating high voltage and high current power devices,” which is incorporated by reference herein in its entirety.Background

[0003] A power module, also referred to as a power electronic module, physically contains power components for power applications. The power components (often as semiconductor dies) are typically soldered or sintered on a power electronic substrate that carries the component as a mass-manufactured device. Compared to discrete power devices as discrete power semiconductors in plastic housings such as TO-247 or TO-220, the power module provides a higher power density. Intelligent Power Systems are a complete power management solution having both power conversion components and control units.

[0004] There are benefits and needs to have a more direct and standardized connection to medium voltage grid to integrate renewable energy sources (RESs) such as solar photovoltaic (PV), wind, biogas, and hydropower into the existing power system. There are also benefits and needs to do the same provide electric infrastructure that can accommodate such distributed power generation resources as energy storage as well as accommodate new loads such as electrical vehicles and electrical vehicle chargers.Summary

[0005] Five exemplary systems and methods are disclosed herein that can either directly connect to a medium voltage grid or improve operation for classes of modules or devices that do so.

[0006] Efficient medium-voltage high-current power semiconductor devices are crucial for achieving higher energy efficiency in many important applications such as industry motor drives, solar, wind, and battery storage energy systems. A medium voltageSiC power module is considered the best candidate to replace Si IGBT modules in these applications. In a first embodiment provided herein, a high voltage and high power module (also referred to as a SuperMOS) is disclosed comprising SiC MOSFETs that are connected in series and parallel configurations that can operate in concert to one another as, or equivalent to, a single device that could operate in the high voltage and high current range. To mitigate mismatch operations due to multiple singled and paralleled devices, the exemplary power module includes both dynamic and static voltage balancing components as well as a dynamic current balance circuit comprising a voltage gate clamp that is connected via a secondary parallel connection to ensure concerted dynamic current sharing.

[0007] High-frequency power switches with higher bidirectional blocking voltages are needed for medium voltage grid applications such as Solid State Transformers (SST). In a second embodiment provided herein, an exemplary AC switch is disclosed comprising two or more identical parts in source-to-source connection, and each part includes multiple kV SiC MOSFETs in series. To mitigate mismatch operations due to multiple paralleled devices, the exemplary AC switch includes a minimized gate signal mismatch operation and an RC snubber circuit.

[0008] In a third embodiment provided herein, an exemplary single-stage AC-AC converter is disclosed that can provide a high-efficiency, high power-density multi-kV medium voltage (MV) solid-state transformer (SST). The exemplary converter includes a half-bridge LLC resonant converter and multi-kV SiC AC switch that can provide soft switching for the MV switches across wide voltage and load ranges. The LLC-SST module can be used as a building block in three-phase architectures for replacing a line frequency transformer (LFT) in the medium voltage power system.

[0009] Increased adoption of electric vehicles, photovoltaic, and battery energy storage systems is driving the need for high-current SiC power modules. The state-of-the-art multichip module is substantially more expensive than the IGBT module. In a fourth embodiment provided herein, an exemplary high-power SiC intelligent power module (IPM) with repackaged parallel discrete SiC devices is disclosed that can proivde low cost, low parasitic inductance, and high switching speed operations.

[0010] With more and more power electronics-based resources and loads being integrated into the grid, there is a strong desire to standardize the grid power electronics building block to further reduce the cost. In a fifth embodiment provided herein, an exemplary high-power density, low-cost air-cooled multi-kVA SiC Intelligent Power Stage (IPS) is disclosed that employs a six-phase leg using discrete SiC devices that can work as agrid interface converter in multiple applications, such as a PV inverter or a PV plus storage inverter. With a two-stage configuration, the three-phase legs of the exemplary IPS can form an interleaved multiphase DC-DC converter, while the other three-phase legs work as a standard three-phase inverter. The integrated intelligent gate driver can drive the two paralleled SiC devices with balanced current sharing.

[0011] In some aspects, the techniques described herein relate to a power module (e.g., hybrid medium voltage power module) including: a module housing including (i) two high power connections (e.g., source and drain), including a first connection and a second connection and (ii) a control connection (e.g., fiber optic connection); an integrated switch assembly disposed in the module housing including a plurality of sets of plurality of switching elements (e.g. TO-247 packaged SiC MOSFET), wherein each set of the plurality of switching elements form a branch that are individually connected in parallel configuration to other parallel branches, and wherein each branch has a respective set of the plurality of switching elements that includes a respective plurality of switching elements connected in series connection to one another; an isolated power supply (e.g., high-voltage isolated power supply) disposed in the module housing; and a single gate driver disposed in the module housing, receiving control signal from the control connection, and electrically coupled to the isolated power supply and the integrated switch assembly, the gate driver being configured to (i) singularly and concertedly turn on the plurality of sets of plurality of switching elements in concert with one another from a single command signal and (ii) singularly and concertedly turn off the plurality of sets of plurality of switching elements from the single command signal, to have the plurality of sets of plurality of switching elements act as a single switch (e.g., for direct medium voltage switching), wherein each switching element of the plurality of switching elements has a static voltage balance component (e.g., resistor) across the drain and source terminal of the switching element, a dynamic voltage balance component (e.g., capacitor) across the drain and gate terminal of the switching element, and a gate voltage clamp component, wherein at least one of static voltage balance component, the dynamic voltage balance component, or the gate to source voltage clamp component (e.g., Zener) for each branch is connected in parallel configuration to corresponding static voltage balance components, dynamic voltage balance components, or gate voltage clamp components of other parallel branches, (where each switching element is integrated together to form a single device; thus, not a plurality of discrete elements)

[0012] In some aspects, the techniques described herein relate to a power module, wherein the static voltage balance component for each branch is connected in a parallel configuration to corresponding static voltage balance components of other parallel branches.

[0013] In some aspects, the techniques described herein relate to a power module, wherein the dynamic voltage balance component for each branch is connected in a parallel configuration to corresponding dynamic voltage balance components of other parallel branches.

[0014] In some aspects, the techniques described herein relate to a power module, wherein the gate voltage clamp component for each branch is connected in a parallel configuration to corresponding gate voltage clamp components of other parallel branches.

[0015] In some aspects, the techniques described herein relate to a power module, where the switching element is a semiconductor die (e.g., SiC MOSFET die), and the electrical connections are made through wire bond.

[0016] In some aspects, the techniques described herein relate to a power module, wherein the plurality of sets of plurality of switching elements include at least a first plurality of switching elements, a second plurality of switching elements, a third plurality of switching elements, and a fourth plurality of switch elements, wherein each set of plurality of switching elements includes at least a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, and a sixth switching element, wherein the first switching element is connected to the first connection and the second switching element, the second switching element is connected to the third switching element, the third switching element is connected to the fourth switching element, the fourth switching element is connected to the fifth switching element, and the fifth switching element is connected to the sixth switching element, and wherein the first switching element of each of the first plurality of switching elements, the second plurality of switching elements, the third plurality of switching elements, and the fourth plurality of switch elements are connected in parallel connection, wherein the second switching element of each of the first plurality of switching elements, the second plurality of switching elements, the third plurality of switching elements, and the fourth plurality of switch elements are connected in parallel connection, wherein the third switching element of each of the first plurality of switching elements, the second plurality of switching elements, the third plurality of switching elements, and the fourth plurality of switch elements are connected in parallel connection, and wherein the fourth switching element of each of the first plurality of switching elements, the second plurality of switching elements, the third plurality ofswitching elements, and the fourth plurality of switch elements are connected in parallel connection.

[0017] In some aspects, the techniques described herein relate to a power module, herein the plurality of sets of plurality of switching elements, the gate driver, and the isolated power supply are repeated to form a half bridge (e.g. equivalent to two high power switches in series) configuration, a full bridge configuration (e.g. equivalent to two high power switches in series and then in parallel with another two high power switches), or a three phase bridge (e.g. equivalent to three branches each consisting of two high power switches in series).

[0018] In some aspects, the techniques described herein relate to a power module, wherein the plurality of sets of a plurality of switching elements include 4 switching elements, 6 switching elements, 8 switching elements, 10 switching elements, 12 switching elements, 14 switching elements, 16 switching elements, 18 switching elements, or 20 switching elements, configured in a half-bridge configuration.

[0019] In some aspects, the techniques described herein relate to a power module, wherein the gate driver is configured to receive a PWM signal through an optical fiber and send the fault feedback signal through another optical fiber, wherein the plurality of sets of plurality of switching elements has a number less than a number of optical fiber.

[0020] In some aspects, the techniques described herein relate to a power module, wherein the plurality of sets of plurality of switching elements have a main half-bridge loop of parallel branches configured to be symmetric to each other to have a minimal mismatch in parasitic inductance of the main power loop, and wherein each branch having the respective set of the plurality of switching elements has a gate loop configured to be symmetric to each other to have a minimal mismatch in parasitic inductance of the gate loop.

[0021] In some aspects, the techniques described herein relate to a power module, wherein each branch having a respective set of the plurality of switching elements is fixably attached to a printed circuit board and in thermal contact to a single baseplate for the module.

[0022] In some aspects, the techniques described herein relate to a power module, wherein each branch having a respective set of the plurality of switching elements is fixably attached to a printed circuit board and in thermal contact to a respective baseplate for the branch.

[0023] In some aspects, the techniques described herein relate to above-discussed method, including: providing a first command signal to the gate driver to singularly and concertedly turn on the plurality of sets of plurality of switching elements in concert with oneanother; providing a second command signal to the gate driver to singularly and concertedly turn off the plurality of sets of plurality of switching elements in concert with one another.

[0024] In some aspects, the techniques described herein relate to a power module including: a module housing including (i) a base plate, (ii) high power connections (e.g., source and drain), including a first connection and a second connection and (iii) a control connection (e.g., fiber optic connection); an integrated switch assembly disposed in the module housing including a plurality of discrete switching devices (e.g. TO-247 packaged device) configured in a bridge configuration (e.g., half-bridge, full-bridge, three-phase, dual- full-bridge, and six-phase legs modules), including a first discrete device and a second discrete device, wherein the first discrete device is positioned at a first location on and in thermal contact with the base plate, and wherein the second discrete device is positioned at a second location on and in thermal contact with the base plate, wherein each of the plurality of discrete switching devices, including first discrete device and the second discrete device, has a lead frame extending from a respective housing of the discrete switching device; a decoupling capacitors and snubber module assembly in electrical connection with the lead frame for pairs of the plurality of discrete switching devices, wherein the decoupling capacitors and snubber module assembly includes a printed circuit board housing one or more decoupling capacitors and one or more snubber capacitors (e.g., to minimize loop inductance and provide effective switching speed).

[0025] Discrete device may be any SiC module, Austin SuperMOS module series, or Austin SuperMOS module series + parallel.

[0026] In some aspects, the techniques described herein relate to a power module, wherein the decoupling capacitors and snubber module assembly are not coupled to the base plate.

[0027] In some aspects, the techniques described herein relate to a power module, wherein the decoupling capacitors and snubber module assembly are coupled to the base plate.

[0028] In some aspects, the techniques described herein relate to a power module, wherein the first discrete device and the second discrete device are direct copper bonded to the base plate.

[0029] In some aspects, the techniques described herein relate to a power module, including: an integrated gate driver disposed within the module housing and electrically coupled to the integrated switch assembly, the integrated gate driver being configured to turnon and turn off the plurality of discrete switching devices including the first discrete device and the second discrete device.

[0030] In some aspects, the techniques described herein relate to a power module, wherein the bridge configuration is selected from the group consisting of a half-bridge, a fullbridge, a three-phase bridge, a dual-full-bridge bridge, and a six-phase legs module bridge.

[0031] In some aspects, the techniques described herein relate to an above-discussed method; applying solder paste to the DBC location; positioning the DBC on the base plate providing a second printed circuit board mold for device location; applying solder paste to the plurality of discrete switching devices and placing the plurality of discrete switching devices on the DBC; reflowing the solder; attaching the decoupling capacitors and snubber module assembly to the lead frame for the pairs of the plurality of discrete switching devices.

[0032] In some aspects, the techniques described herein relate to a power module or the method, wherein the discrete switching module includes the power module.

[0033] In some aspects, the techniques described herein relate to a self-contained intelligent power stage system including: a base plate and heatsink assembly; a power semiconductor unit including a plurality of discrete switching devices (e.g., SiC power MOSFET) having a six phase leg bridge in thermal connection to the base plate and heatsink assembly; a gate driver in electrical connection to discrete switching devices to turn on and turn off the plurality of discrete switching devices; a sensor and LC filter assembly electrically coupled to the plurality of discrete switching devices of the power semiconductor unit; a contactor assembly including a first set of contactors for connection to an AC grid (e.g., having AC filter) and a second set of contacts for connection to a DC bus (e.g., having a DC filter); and a local controller in electrical connection to the gate driver, wherein the local controller is configured to operate the six phase leg bridge in a two-stage configuration each having a three-phase leg, including a first three-phase leg and a second three-phase leg, wherein the first three-phase leg is configured to operate as an interleaved multiphase DC-DC converter, and wherein the second three-phase leg is configured to operate a DC-AC converter as a three-phase inverter.

[0034] In some aspects, the techniques described herein relate to a system, wherein the gate driver is configured to drive the six-phase leg bridge formed by two or more paralleled SiC devices with balance current sharing.

[0035] In some aspects, the techniques described herein relate to a system, wherein the system is configured as a grid interface converter (e.g., as photovoltage inverter or battery inverter)).

[0036] In some aspects, the techniques described herein relate to a system, wherein the local controller and the sensor and LC filter assembly includes driver-integrated overcurrent protection circuit, temperature sensing circuit, and online voltage measurement circuit (e.g., to provide fast overcurrent protection and online health monitoring capability).

[0037] In some aspects, the techniques described herein relate to a system, wherein the base plate and heatsink assembly is a passive heat block or an active heat block.

[0038] In some aspects, the techniques described herein relate to a system, wherein the discrete switching module includes the power module.

[0039] In some aspects, the techniques described herein relate to a power switch system (e.g., high frequency power switches with high bidirectional blocking voltages, e.g., solid state transformer) including: a first plurality of high-voltage switching devices (e.g., 1700V SiC MOSFETs) configured in series connection to one another; and a second plurality of high-voltage switching devices (e.g., 1700V SiC MOSFETs) configured in series connection to one another, wherein the first plurality of high-voltage switching devices are identical and in source-to-source connection with another gate driver in electrical connection with the second plurality of high-voltage switching devices; and a gate driver including a pulse transformer (e.g., single-input-multiple-output magnetic coupled pulse transformer) in electrical connection with the first plurality of high-voltage switching devices and the second plurality of high-voltage switching devices to turn on and turn off the first plurality of high- voltage switching devices and the second plurality of high-voltage switching devices (e.g., with minimal gate signal mismatch among series connected device to mitigate voltage sharing across the devices); and a gate driver isolated power supply comprising a pulse transformer (e.g., single-input-multiple-output magnetic coupled pulse transformer) in electrical connection with the first plurality of high-voltage switching devices and another gate driver isolated power supply in electrical connection with the second plurality of high- voltage switching devices to provide power supplies to each of the power devices in the first plurality of high-voltage switching devices and the second plurality of high-voltage switching devices.

[0040] In some aspects, the techniques described herein relate to a system including: an RC snubber capacitor electrically connected between a drain terminal and a source terminal of the respective switching device of the plurality of high-voltage switching devices.

[0041] In some aspects, the techniques described herein relate to a system including: a single-stage AC-AC converter configured as a multi-kV medium voltage (MV) solid-statetransformer (SST), the converter including: a half-bridge LLC resonant converter and multi- kV SiC AC switch.

[0042] In some aspects, the techniques described herein relate to a system, wherein the LLC-SST module is employed as a building block in a three-phase medium voltage power system.Brief Description of the Drawings

[0043] Figs. 1A, IB, 1C, ID, 2, 3, 4, 5A, and 5B show an example intelligent power module (IPM) in accordance with a first illustrative embodiment comprising medium voltage SiC MOSFETs.

[0044] Figs. 1 A - 1C each shows an example silicon carbide (SiC) half-bridge intelligent power module (IPM) having both dynamic and static voltage balancing components as well as a dynamic current balance circuit comprising a voltage gate clamp that are connected via a secondary parallel connection to ensure concerted dynamic current sharing according to the first illustrative embodiment.

[0045] Fig. ID shows an example silicon carbide half-bridge intelligent power module with a die-level package. The module has ultra-low on-state resistance, excellent thermal handling capability, and reduced power loop parasitic inductance.

[0046] Fig. 2 shows an example operation flow of the fabricated process of the exemplary intelligent power module according to the first illustrative embodiment.

[0047] Fig. 3 shows the simulation waveforms of the two parallel configurations of the exemplary intelligent power module according to the first illustrative embodiment.

[0048] Fig. 4 shows an example gate loop layout of the exemplary intelligent power module (IPM) according to the first illustrative embodiment.

[0049] Figs. 5A - 5B show the small signal models for the parallel configurations of the series-parallel silicon carbide half-bridge intelligent power module according to the first illustrative embodiment.

[0050] Fig. 6 shows an example intelligent power system (IPS) in accordance with a second illustrative embodiment comprising an AC switch for medium voltage grid applications. In particular, Fig. 6 shows the example medium voltage solid state transformer as an LLC-based solid state transformer module.

[0051] Figs. 7 and 8 show an example medium voltage solid state transformer in accordance with a third illustrative embodiment that can be implemented as a single-phase single-stage AC-AC modular building block can be directly connected to kV single-phase or kV three-phase distribution grid according to the third illustrative embodiment.

[0052] Fig. 7 shows an example single-phase single-stage inductor-inductor- capacitor-based (LLC-based) solid state transformer (SST) module according to the third illustrative embodiment.

[0053] Fig. 8 shows the three-phase architectures of medium voltage systems based on the exemplary LLC-based solid-state transformer module according to the third illustrative embodiment.

[0054] Figs. 9 and 10 show an example medium voltage intelligent power module in accordance with a fourth illustrative embodiment that can be implemented using repackaged discrete silicon carbide devices according to the fourth illustrative embodiment.

[0055] Fig. 9 shows the example silicon carbide (SiC) intelligent power module (IPM) using repackaged discrete silicon carbide devices (i.e., repackaged intelligent power module) according to the fourth illustrative embodiment.

[0056] Fig. 10 shows a cross-sectional diagram of a standard silicon carbide (SiC) power module and an exemplary repackaged intelligent power module according to the fourth illustrative embodiment.

[0057] Fig. 11 shows an example high power an intelligent power stage in accordance with a fourth illustrative embodiment comprising a silicon carbide intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0058] Figs. 12 - 13 show experimental and simulation results for the first medium voltage embodiment. In particular, Figs. 12A - 12B show the on-resistance distribution and voltage distribution of the MOSFET devices (i.e., switches) in a fabricated intelligent power module (IPM).

[0059] Figs. 13A - 13B show the simulated waveforms of two parallel configurations of the branches in the fabricated intelligent power module (IPM) according to the first illustrative embodiment.

[0060] Fig. 13C shows the measured current waveform during the turn-on transient of the fabricated intelligent power module (IPM) according to the first illustrative embodiment.

[0061] Figs. 14A - 141 show experimental and simulation results for a series cascode IPM device in accordance with another illustrative embodiment.

[0062] Figs. 15 - 22 show experimental and simulation results for the second medium voltage embodiment. In particular, Figs. 15A - 15C show the circuit diagram and prototype of a fabricated alternating current (AC) switch power module with 30kV insulation capability according to the second illustrative embodiment.

[0063] Fig. 16 shows the partial discharge test (in Coulomb) with time for the fabricated alternating current (AC) switch power module according to the second illustrative embodiment.

[0064] Fig. 17 shows the gate signal turn-on and turn-off transient mismatch test results of the fabricated alternating current (AC) switch power module according to the second illustrative embodiment.

[0065] Fig. 18 shows the turn-off transient simulation results for the fabricated alternating current (AC) switch power module with and without a scrubber circuit according to the second illustrative embodiment.

[0066] Fig. 19 shows the single pulse test (SPT) circuit and typical waveforms at 10kV / 15A with Cs = 660pF according to the second illustrative embodiment.

[0067] Figs. 20A - 20B show the drain voltage and drain-to-source voltage measurements across the bottom MOSFET devices for the fabricated alternating current (AC) switch power module according to the second illustrative embodiment.

[0068] Fig. 21 A shows the average drain voltage after the turn-off for the fabricated alternating current (AC) switch power module according to the second illustrative embodiment.

[0069] Fig. 21B shows the voltage unbalance ratio at 10kV / 15A with three different snubber capacitances for the fabricated alternating current (AC) switch power module according to the second illustrative embodiment.

[0070] Figs. 22A - 22B show the results for the turn-on and turn-off losses and leakage current test of the fabricated alternating current (AC) switch power module according to the second illustrative embodiment.

[0071] Figs. 23 - 28 show experimental and simulation results for the third medium voltage embodiment. In particular, Figs. 23 A - 23B show the simulated line cycle operation and simulated operation waveforms for one switching cycle of the exemplary single-phase single-stage LLC-based solid state transformer module.

[0072] Fig. 24 shows the output capacitor stored energy as a function of the drain-to- source terminal voltage according to the third illustrative embodiment.

[0073] Fig. 25 shows the fabricated 7.2kV / 100kVA LLC-SST prototype based on a half-bridge LLC resonant converter and a 15kV alternating current (AC) switch power module according to the third illustrative embodiment.

[0074] Figs. 26A - 26B show the estimated efficiency curve and the detailed loss breakdown at lOOkVA of the fabricated LLC-based solid-state transformer (SST) module according to the third illustrative embodiment.

[0075] Fig. 27 shows the thermal test results of a single switch Sia of the fabricated LLC-based solid-state transformer (SST) module with ambient temperature Ta=21°C according to the third illustrative embodiment.

[0076] Fig. 28 shows the power test results of the fabricated LLC-based solid state transformer module under 300V AC input and 4.2kV AC output with IkQ resistive load bank according to the third illustrative embodiment.

[0077] Figs. 29 - 33 show experimental and simulation results for the fourth medium voltage embodiment.

[0078] In particular, Fig. 29 shows the fabrication process for a fabricated repackaged intelligent power module (IPM) according to the fourth illustrative embodiment.

[0079] Fig. 30 shows the fabricated repackaged intelligent power module (IPM) with the busbar and pulse-width modulation (PWM) receiver according to the fourth illustrative embodiment.

[0080] Fig. 31 A shows a state-of-the-art 1200V power module in high-performance 62 mm packaging according to the fourth illustrative embodiment.

[0081] Fig. 3 IB shows the fabricated 1200 V / 240 A / 4.3mQ six-phase repackaged intelligent power module with the heatsink, busbar, and PWM receiver according to the fourth illustrative embodiment.

[0082] Fig. 32 shows the switching transients for 455A turn-ON and 480A turn-OFF of the fabricated repackaged intelligent power module according to the fourth illustrative embodiment.

[0083] Figs. 33A - 33B shows the measured efficiency curve and temperature of two- stage DC-DC / DC-AC operation in the fabricated repackaged intelligent power module according to the fourth illustrative embodiment.

[0084] Figs. 34 - 44 show experimental and simulation results for the fifth multi-kVA embodiment. In particular, Fig. 34 shows a fabricated IPS system.

[0085] Fig. 35 shows a repackaged six-phase silicon carbide (SiC) intelligent power module (IPM) employed by the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0086] Fig. 36 shows the simulated thermal management of the repackaged silicon carbide intelligent power module (IPM) employed by the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0087] Fig. 37 shows the gate driver circuit, including the parasitic inductance employed by the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0088] Fig. 38 shows a gate driver-integrated circuit for online on-state voltage measurement (OVM) in the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0089] Figs. 39A - 39B show on-state voltage and temperature waveforms when a SiC device in the fabricated intelligent power stage (IPS) system operated in a buck operation and in an inverter operation according to the fifth illustrative embodiment.

[0090] Fig. 40 shows the circuit diagram and the fabricated hardware of the auxiliary power supply employed by the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0091] Fig. 41 shows the experimental result for the auxiliary power supply employed by the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0092] Fig. 42A shows a control framework of the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0093] Fig. 42B shows an interleaved dual-loop DC-DC control mechanism with phase current balancing of the local controller of the fabricated intelligent power stage (IPS) system according to the fifth illustrative embodiment.

[0094] Fig. 43 shows the switching waveform and temperature readings of the fabricated intelligent power stage (IPS) system in the 75kW DC-AC test according to the fifth illustrative embodiment.

[0095] Fig. 44 shows the DC-AC stage efficiency and DC-DC plus DC-AC two-stage efficiency for the fabricated intelligent power stage (IPS) system measured by the Hioki PW6001 power analyzer according to the fifth illustrative embodiment.Detailed Description

[0096] Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and / or discussion of such references is provided merely to clarify the description ofthe disclosed technology and is not an admission that any such reference is “prior art” to any aspects of the disclosed technology described herein. In terms of notation, “[n]” corresponds to the nth reference in the list. For example, [1] refers to the first reference in the list. All references cited and discussed in this specification are incorporated herein by reference in their entirety and to the same extent as if each reference was individually incorporated by reference.

[0097] Example System #1 - Series-parallel silicon carbide (SiC) half-bridge intelligent power module (IPM)

[0098] Efficient medium-voltage high-current power semiconductor devices are crucial for achieving higher energy efficiency in many important applications such as industry motor drives, solar, wind, and battery storage energy systems. A medium voltage SiC power module is considered the best candidate to replace Si IGBT modules in these applications. In a first embodiment provided herein, a power module (also referred to as a superMOS) is disclosed comprising kV SiC MOSFETS that are connected in series and parallel configurations that can operate in concert with one another as, or equivalent to, a single device that could operate in the kV range. To mitigate mismatch operations due to multiple singled and paralleled devices, the exemplary power module includes both dynamic and static voltage balancing components as well as a dynamic current balance circuit comprising a voltage gate clamp that is connected via a secondary parallel connection to ensure concerted dynamic current sharing.

[0099] Figs. 1 A - 1C, 2, 3, 4, 5A, and 5B show an example intelligent power module (IPM) in accordance with a first illustrative embodiment comprising medium voltage SiC MOSFETs. In Figs. 1 A - 1C, an example silicon carbide (SiC) half-bridge intelligent power module (IPM) is shown to have both dynamic and static voltage balancing components as well as a dynamic current balance circuit comprising a voltage gate clamp that is connected via a secondary parallel connection to ensure concerted dynamic current sharing.

[0100] Specifically, Fig. 1 A shows example power modules 100a and 100b, each comprises a module housing, an integrated switch assembly, an isolated power supply, and a gate driver. The power module 100a in subpanel (a) has a module housing comprising two high power connections (e.g., source and drain), including a first connection, a second connection, and a control connection (e.g., fiber optic connection). The integrated switch assembly of the power module 100a, disposed in the module housing, comprises a plurality of sets of plurality of switching elements. Each set (e.g., 102a, 102b, 102c, 102d; also shown as 102a’ - 102d’) of the plurality of switching elements 104 forms a branch that is individuallyconnected in parallel 102 configuration to other parallel branches 102. Each branch 102a 102d has a respective set of the plurality of switching elements connected in series connection to one another.

[0101] The set 102a includes a plurality of switching elements (e.g., 104a - 104c and 104d - 104f) connected in series as a half-bridge. The set 102b of the plurality of switching elements (e.g., 104g - 104i and 104p - 104r) also includes symmetric and identical switches connected in series also as a half bridge. The set 1022 of the plurality of switching elements (e.g., 104j - 1041 and 104s - 104u) also includes symmetric and identical switches connected in series also as a half-bridge. The set 1022 of the plurality of switching elements (e.g., 104m- 104o and 104v - 104x) also includes symmetric and identical switches connected in series also as a half-bridge. The SiC half-bridge may function like a traditional half-bridge circuit; only two gate drivers are used to drive the upper and lower devices.

[0102] The isolated power supply 106 (e.g., high-voltage isolated power supply) is disposed in the module housing and supplies power to the entire module 100a. To provide high-voltage galvanic isolation for the integrated gate driver, a high-voltage isolated power supply may be used. A 30-kV insulated wire may be employed as the primary winding of the isolated power supply. The coupling capacitance between the primary and secondary sides of the transformer may have a low value (e.g., 3 pF).

[0103] The gate driver 108, disposed in the module housing and electrically coupled to the isolated power supply and the integrated switch assembly, is configured to singularly and concertly turn on and turn off the plurality of sets 102a - 102d of the plurality of switching elements 104 in concert with one another from a single command signal, to have the plurality of sets of plurality of switching elements 104 acts as a single switch (e.g., for direct medium voltage switching). The gate driver 108 may receive a PWM signal through an optical fiber and send the fault feedback signal through another optical fiber in which the plurality of sets of plurality of switching elements has a number less than a number of optical fibers.

[0104] In the example shown in Figs. 1 A, IB, and 1C, each switching element (e.g., 104a - 104o) has a static voltage balance component, a dynamic voltage balance component, and a gate voltage clamp component. In power module 100a, the gate voltage clamp component for each branch is connected in a parallel configuration to corresponding gate voltage clamp components of other parallel branches. The core part of the switch may be formed by a series connection of SiC MOSFETs with static and dynamic balancing networks. RI-R6, as static voltage balancing components, may be used to achieve the static voltagebalance. Ci-Ce, as dynamic voltage balancing components, may be used for the dynamic voltage balancing as well as part of the turn-on gate circuits for upper switches Q2-Q6. Rg2-Rg6 may be damping resistors that are used to limit the charging and discharging currents in the gate branch during switching. Dz2~Dz6, as game voltage clamping components, may be implemented are Zener diodes for clamping the gate voltages of Q2-Q6.

[0105] The midpoint of the two sets 102 of switches is defined as the SW node. The high-side switch may be used as a synchronous rectifier in a boost converter. During the deadtime, after the low-side switch is turned off, the SW voltage begins to rise. C1-C6 and Coss of Q1-Q6 of the low-side switch are being charged, and those of the high-side switch are being discharged by the load current. Since the SiC MOSFET’s Coss are much smaller than C1-C6, they are discharged faster; therefore, a positive voltage will be established on Vgs2_H-Vgs6_H of the high-side switch. Instead of following the voltage on VgsiH that is negative during the deadtime, Vgs2_H-Vgs6_n may switch on automatically during the SW voltage rise even if Vgsi H remains low. In other words, Vgs2_H-Vgs6_n may switch on automatically every time the current flows from the source to drain under this condition.

[0106] The diode of device QI and channel ON-state resistance of device Q2-Q6 (instead of the body diode of device Q2-Q6) may determine the deadtime loss. It can be determined that Vgs2_n may switch on before Vgsi H PWM is given during deadtime; therefore, the channel of Q2 is conducting the reverse current. The same can happen to Vgs3_H—Vgs6_H.

[0107] The plurality of sets of plurality of switching elements include at least a first plurality of switching elements (e.g., 102a), a second plurality of switching elements (e.g., 102b), a third plurality of switching elements (e.g., 102c), and a fourth plurality of switching elements (e.g., 104d). The multiple sets 102 switches in parallel configuration allows the module 100 to carry a higher current. Each set of plurality of switching elements includes at least a first switching element (e.g., 104a), a second switching element (e.g., 104b), a third switching element (e.g., 104c), a fourth switching element (e.g., 104d), a fifth switching element (e.g., 104e), and a sixth switching element (e.g., 104f). The multiple switches 104 in series configuration allows the module 100 to carry higher voltage. The plurality of sets of plurality of switching elements (102a - 102d) may include 4 switching elements, 6 switching elements, 8 switching elements, 10 switching elements, 12 switching elements, 14 switching elements, 16 switching elements, 18 switching elements, or 20 switching elements, configured in a half-bridge configuration, e.g., having n branches each having m switches. The number n of branches 102 may be 2, 3, 4, 5, 6, 7, 8, 9, 10. In some embodiments, thenumber n is greater than 10. The number m of device 104 for a branch 102 may be 2, 3, 4, 5, 6, 7, 8, 9, 10. In some embodiments, the number n is greater than 10. The switches and sets may be configured also as a full-bridge, a three-phase bridge, a dual-full-bridge, or six-phase legs modules.

[0108] The switching element is a semiconductor die (e.g., SiC MOSFET die). The electrical connections may be made through wire bond and other packaging techniques, e.g., as described in relation to J. Tong, R. Yu and A. Q. Huang, "Design, Packaging, and Characterization of a 6.8kV / 160A SiC SuperCascode Half-Bridge Module for Medium Voltage Applications," 2023 IEEE Energy Conversion Congress and Exposition (ECCE), Nashville, TN, USA, 2023, pp. 5538-5542, doi: 10.1109 / ECCE53617.2023.10362553.

[0109] The kV SiC MOSFETS may be configured for greater than 10 kV, e.g., 11 kV, 12 kV, 13 kV, 14 kV, 15 kV, 16 kV, 17 kV, 18 kV, 19 kV, 20 kV, 21 kV, 22 kV, 23 kV, 24 kV, 25 kV, 26 kV, 27 kV, 28 kV, 29 kV, 30 kV, 31 kV, 32 kV, 33 kV, 34 kV, 35 kV, 36 kV,37 kV, 38 kV, 39 kV, 40 kV, 51 kV, 52 kV, 53 kV, 54 kV, 55 kV, 56 kV, 57 kV, 58 kV, 59 kV, 60 kV. In some embodiments, the kV SiC MOSFETS may be configured for greater than 100 kV. In some embodiments, the SiC MOSFETS may be configured for less than kV operation, e.g., 100 V, 200V, 300V, 400V, 500V, 600 V, 700 V, 800 V, 900 V, or 1000V.

[0110] The plurality of sets of plurality of switching elements each has a main halfbridge loop, e.g., 101, 103 (shown as 101’, 103’) and parallel branches of such loop configured to be symmetric to each other to have a minimal mismatch in parasitic inductance. Each branch also has a gate loop configured to be symmetric to each other to have minimal mismatch in parasitic inductance.[OHl] Each branch 102 of the power module 101a and its associated plurality of switching elements 104 may be fixably attached to a printed circuit board and in thermal contact with a single baseplate for the module. In other embodiments, the baseplate may be coupled to a set of branches rather than to all of the branches.

[0112] The power module 100b, shown in subpanel (b), is a prior art power module whose parallel configuration does not have parallel connections 120a - 120d as present in the power module 100a.

[0113] Example IPMs #2 and #3. Figs. IB - 1C shows example power modules 100c and lOOd having different parallel configurations between the branches. As shown in Fig. IB, in power module 100c, the dynamic voltage balance component for each branch is connected in parallel configuration (e.g., 122a - 122d) to corresponding dynamic voltage balance components of other parallel branches.

[0114] As shown in Fig. 1C, in power module lOOd, the static voltage balance component for each branch is connected in parallel configuration (e.g., 124a - 124d) to corresponding static voltage balance components of other parallel branches.

[0115] Example Method. Fig. 2 shows an example operation flow of the fabrication process 200 of an exemplary power module. The method 200 includes providing (202) a first command signal to the gate driver to singularly and concertly turn on the plurality of sets of plurality of switching elements in concert with one another.

[0116] The method 200 further includes providing (204) a second command signal to the gate driver to singularly and concertly turn off the plurality of sets of plurality of switching elements in concert with one another.

[0117] Silicon carbide half-bridge intelligent power module. The parallel configuration (i.e., connection) in the exemplary IPM can address parameter mismatches in threshold voltage and gate loop inductance, e.g., due to a strong negative feedback mechanism inherent in the parallel connection. In Fig. 1 A, the parallel configuration shown in subpanel (a), referred to as configuration 1, shows an additional parallel connection between the balancing network for individual 1.2kV SiC MOSFETs. The parallel configuration shown in subpanel (b), referred to as configuration 2, shows a typical series / parallel connection of a matrix switch. Fig. 3, subpanel (a) shows the current output of the exemplary device 100a. Subpanel (b) shows the current output of a similar device that lacks the additional parallel connection among the gate voltage clamp components.

[0118] The exemplary IPM can address the static current sharing issue between the branches because the positive temperature coefficient (PTC) of the silicon MOSFET on-state resistance helps with static current sharing during paralleled MOSFETs and can help avoid a thermal runaway condition [9],

[0119] For the exemplary IPM, each branch's drain-source on resistance (Rds, on) is the summation of three discrete devices, the variation of the Rds, on can affect the static current sharing. However, higher current branches can result in high temperatures. Like Si MOSFET, the Rds, on of the SiC MOSFET also have the PTC characteristic; the one with higher junction temperature can see higher increases of the Rds, on hence starts to balance the branch current. So the static current balancing issue in the exemplary IPM is similar to standard MOSFET parallel operation. A thermal equilibrium may be reached eventually to avoid thermal runaway.

[0120] Paralleling SiC MOSFETs can also address the dynamic current sharing issue

[0010] , There are mainly two types of mismatches: one comes from device parameters, and theother comes from the circuit parameters. For the exemplary IPM, the latter's influence is greater due to the hybrid integration concept that involves various passive components and a large footprint. The main half-bridge loop of the parallel branches is perfectly symmetric to each other, resulting in a minimum mismatch in the parasitic inductance of the main power loop. Another mismatch is the gate loop since four gate loops are involved in each switch.

[0121] Gate loop inductance is another factor that needs to be considered in terms of dynamic current sharing. Fig. 4 shows an example gate loop layout of the exemplary intelligent power module (IPM). Because all 4 branches (e.g., 110, 112, 114, 116) in parallel are driven by only one gate driver, it is not easy to guarantee perfect equal gate loop inductances, as shown in Fig. 4. This mismatch can result in gate signal delay during turn-on and turn-off In summary, the mismatch of threshold voltage (Vth) and gate loop inductance may cause dynamic current mismatch during switching transient.

[0122] Analysis of parallel method. Fig. 3 shows the simulation waveforms of the two parallel configurations of the exemplary power module 100. The simulated waveform of configuration 2, shown in subpanel (b), indicates a dynamic current mismatch 304 (i.e., unbalanced) for configuration 2. In contrast, the simulated waveform of configuration 1, shown in subpanel (a), has a very good turn-on performance, i.e., stable current waveform 302. To explain the reason behind this, Figs. 5A - 5B show the small signal models of the two configurations.

[0123] In configuration 2, shown in Fig. 5A, there is a transient current unbalance caused by the voltage difference on the mutual inductance (Lm) between the paralleled branches (e.g., 502, 504). This is because the device during turn-on, is a voltage-controlled current source; therefore, a small difference in gate voltage will introduce a noticeable transient current unbalance. Gate resistor provides damping to the inductor-capacitor (LC) oscillation (506a - 506c), as shown in Fig. 5A.

[0124] Because of the direct connection across the balancing network, as shown in Fig. 5B, configuration 1 provides a negative feedback loop (e.g., 508a, 508b) that offsets the difference caused by the individual device connection. The gate resistors in the feedback loop also provide additional oscillation damping (e.g., 510a, 510b). Therefore, configuration 1 provides inherent immunity to mismatch during the turn-on transient.

[0125] Discussion. A study developed and evaluated a 3.6kV / 400A SiC half-bridge intelligent power module (IPM) is developed based on a novel series-parallel approach to lower voltage devices. Twenty-four 1200V SiC MOSFETs are integrated into the IPM together with a high isolation voltage gate power supply, gate driver, and overcurrentprotection. The study developed the series / parallel approach which guarantees dynamic voltage sharing amount series connected devices and current sharing among paralleled branches. Experimental results are included to demonstrate the superior performance of the developed high powerlPM.

[0126] Efficient medium-voltage high-current power semiconductor devices were crucial for achieving higher energy efficiency in many important applications such as industry motor drives, solar, wind, and battery storage energy systems. Medium voltage SiC power module was considered the best candidate to replace Si IGBT modules in these applications due to its superior static and dynamic performance [1], One approach to developing medium voltage SiC power switches was through single-chip technology, which has been developed by several vendors ranging from 3.3kV to 15kV [1], [2], [3], [4], [5], Another approach was through hybrid integration. A 15 kV SiC power switch based on the super cascode configuration of SiC JFET is shown in [6],

[0127] A previous study developed a 7.2kV / 60A SiC Austin SuperMOS switch based on series connection of 1.2kV SiC MOSFETs in [7], To enable higher current operation and address the parameter mismatch of multiple paralleled devices, this study developed an exemplary 3.6kV / 400A half-bridge SuperMOS Intelligent Power Module (TPM) employing a parallel connection method of the SuperMOS devices to guarantee excellent dynamic current sharing.

[0128] To enable higher current operation, a 3.6kV / 400A half-bridge SuperMOS Intelligent Power Module (IPM) was implemented and reported in APEC 2021 [8], Due to the parameter mismatch of multiple paralleled devices, dynamic current unbalance is identified as the biggest issue. The exemplary system employs the parallel connection method of the SuperMOS to guarantee excellent dynamic current sharing, which enables the development of the 3.6kV / 400A SuperMOS as the highest current rating hybrid medium voltage power module ever reported.

[0129] Additional description of the exemplary system may be found in Zhang, Liqi, et al. "A Novel Series-Parallel Design of The 3.6 kV / 400A SiC Austin SuperMOS." 2023 IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, 2023., which is incorporated by reference herein in its entirety.

[0130] Additional descriptions of features of the exemplary system are provided in Guo, Zhi cheng, et al. "A Novel 3.6 kV / 400A SiC Intelligent Power Module (IPM)." 2021 IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, 2021 and Zhang, Liqi, Soumik Sen, and Alex Q. Huang. "7.2-kV / 60-A Austin SuperMOS: Anintelligent medium -voltage SiC power switch." IEEE Journal of Emerging and Selected Topics in Power Electronics 8.1 (2019): 6-15, each of which is incorporated by reference herein.

[0131] Example #4. In some embodiments, the switching element is a semiconductor die (e.g., SiC MOSFET die) that is made to the wire bond and other packaging techniques, e.g., as described in relation to J. Tong, R. Yu and A. Q. Huang, "Design, Packaging, and Characterization of a 6.8kV / 160A SiC SuperCascode Half-Bridge Module for Medium Voltage Applications," 2023 IEEE Energy Conversion Congress and Exposition (ECCE), Nashville, TN, USA, 2023, pp. 5538-5542, doi: 10.1109 / ECCE53617.2023.10362553.

[0132] Fig. ID shows a power module with multiple SiC JFET dies connected in series in each switch position. Ml is a low voltage MOSFET in cascode configuration with the first JFET. RI~R4 are used for static voltage balancing, and Ci~C4 are used for dynamic voltage balancing. Rgi~Rg4 are damping resistors that limit the gate loop charging and discharging currents in the capacitor branch during the turn-on and turn-off transients. Di-Ds are avalanche diodes for voltage clamping and enhancing the turn-on performance. Rd is the damping resistor for limiting the diode loop leakage. All components are placed on a DBC board with an isolation voltage higher than lOkV. Silicone gel may be used to encapsulate the module. A thick nickel-plated copper baseplate may be soldered to the other side of the DBC for mechanical support.

[0133] The semiconductor die (e.g., SiC MOSFET die) has electrical connection to the wire bond may be applied to the power modules as described in relation to Figs. 1 A - 1C.

[0134] Example System #2 - Alternating current (AC) switch power module

[0135] High-frequency power switches with higher bidirectional blocking voltages are needed for medium voltage grid applications such as Solid State Transformer (SST). In a second embodiment provided herein, an exemplary AC switch is disclosed comprising two or more identical parts in source-to-source connection, and each part includes multiple kV SiC MOSFETs in series. To mitigate mismatch operations due to multiple paralleled devices, the exemplary AC switch includes a minimized gate signal mismatch operation and an RC snubber circuit.

[0136] In some embodiments, the number of identical parts in a source-to-source connection is 2, 3, 4, 5, 6, 7, 8. In some embodiments, the number of branches is greater than 8. The number of devices in each branch may include 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 MOSFETs. In some embodiments, the number of devices per branch is greater than 20.

[0137] Fig. 6 shows the circuit configuration of the exemplary AC switch power module consisting of two identical modular parts, Sa and Sb, in source-to-source connection, and each of the parts includes ten SiC MOSFETs 602 in series (AMO). As shown in Fig. 6, the ten SiC MOSFET devices 602 are driven by a common gate signal from a grounded distribution board 604. The 30kV galvanic isolation (by the isolated driver board 606) can be achieved using pulse transformers (e.g., 608a - 608d) between the grounded signal distribution board 604 and power devices (610a - 610d). Additional isolation of the PWM signal is achieved using optical fiber 612 to increase the noise immunity of the controller boards (e.g., 604, 606).

[0138] The in-between auxiliary power supplies and PWM gate driver circuits may implemented together on one printed circuit board (i.e., distribution board). Single-input- multiple-output magnetic coupled approach may be adopted to minimize the gate signal time delay mismatch of the exemplary AC switch power module.

[0139] The exemplary AC switch power module employs two mechanisms to mitigate the voltage sharing across the devices during the switching transient: (i) minimum gate signal mismatch and (ii) proper resistor-capacitor snubber circuit.

[0140] Minimum gate signal mismatch. The cascaded SiC MOSFETs may be driven by a common gate signal from the single-input-multiple-output magnetic coupled pulse transformer. The parasitic capacitance between the primary and secondary winding of the gate signal pulse transformer for each MOSFET device may be minimized (e.g., around only around 0.2pF) to enable a high dv / dt response (1.5V / ns) at the rising and falling edge of the PWM signal at the input of the gate driver circuit. Together with a high-speed rail-to-rail comparator (e.g., TLV3502 with propagation delay 4.5ns), the maximum gate signal delay mismatch at the output of the gate driver circuit (right before the ten SiC MOSFETs) can be limited to less than 10ns.

[0141] RC snubber circuit. Static voltage sharing of the cascaded devices may be enabled using a resistor (e.g., one 10MQ resistor) across each device's drain-to-source terminal. The discharging current may be configured to be around 100 times the maximum leakage current of the SiC devices at 1.2kVdc.

[0142] Dynamic voltage sharing of series-connected MOSFET devices may be affected by the gate signal mismatch time, which may cause a voltage unbalance between the MOSFET devices. A dv / dt snubber capacitor (G =Csnubber) across each device's drain-to- source terminal may be used to mitigate the voltage unbalance issue.

[0143] The dv / dt snubber capacitors may enable a satisfactory voltage balance without any additional balancing mechanisms. The extra energy stored in the snubber capacitors may be discharged to the source or load with proper power converter design.

[0144] Discussion. High-frequency power switches with higher bidirectional blocking voltages are needed for medium voltage grid applications such as Solid State Transformer (SST). The study developed a 15kV / 50A SiC AC switch based on 1700V SiC MOSFETs in series connection. The AC switch included two identical parts in source-to-source connection and each part includes ten 1700V SiC MOSFETs in series. The ten SiC MOSFETs were driven by a common gate signal. The mismatch of the gate signals was a key factor considered in the study that could affect the voltage sharing across the devices. The mismatch was experimentally studied and was observed to be less than 10ns. SIMetrix simulations at 12kV / 5A turn-off transient were performed based on the tested mismatch time, and a dynamic balancing capacitor was then designed to achieve satisfactory voltage balance.10kV / 15A single pulse test (SPT) was carried out to verify the feasibility of the designed AC switch. Actual voltage balancing during turn-on and turn-off are experimentally observed. Other functionalities and qualities of the fabricated AC switch are characterized for future SST applications. Auxiliary gate power supplies with 30kV galvanic isolation capability are designed to support the intended medium voltage applications.

[0145] In the last decade, wide-bandgap (WBG) semiconductor devices such as SiC MOSFETs have attracted great attention in power electronics. Compared to Silicon IGBTs with the same voltage ratings, the most important capabilities of the SiC MOSFETs were similar or lower on-state voltage drop, higher switching frequencies resulting from majority carrier operation mechanism, and higher operating temperatures

[0011] , Device voltage ratings can also be scaled to much higher voltages, such as 15kV or higher, paving the way for various medium voltage applications such as Solid State Transformers (SST)

[0012]

[0013] , DC circuit breakers

[0014] , and Medium Voltage Drives (MVD)

[0015] , An SST based on 15kV SiC MOSFET was demonstrated in

[0016] , which met the criteria for integration with a 7.2kV distribution grid in the United States. Other researches has also been demonstrated to accelerate the applications of SiC power MOSFETs

[0017]

[0018] .

[0146] However, 15kV SiC MOSFETs were not commercially available at the moment. For this reason, various attempts have been made to address this gap. Modular converter topologies based on converter input series output parallel (ISOP) connections can be used as a viable solution for medium voltage applications such as that reported in

[0019] , Another method was to develop a high-voltage SiC power device based on device seriesconnections such as those reported in

[0020] -

[0022] . In those developments, a single gate driver was used to drive the series connected devices, and the dynamic voltage balancing was achieved by properly designing the dynamic balancing capacitors. For the traditional series- connected device approach, the challenge is the large number of auxiliary gate drivers with sufficient insulation capability and minimum mismatch (time delay), in addition to the static and dynamic voltage balancing issues [23-25],

[0147] So far, all reported high-voltage SiC switches were unidirectional voltageblocking devices. Additional devices or power stages, such as an unfolding bridge, were needed for medium-voltage AC applications

[0026] , This increased the control complexity, especially for reactive power mode operation, and reduced the power density, efficiency, and reliability.

[0148] Therefore, in order to further reduce the size and weight of the SST, a high- voltage AC switch was needed. The study presented the development and experimental results of an exemplary 15kV / 50A SiC AC switch power module based on 1.7kV SiC MOSFET in series. The exemplary AC switch power module consisted of two identical parts in source-to-source connection and each part includes ten 1700V SiC MOSFETs. The ten SiC MOSFETs are driven by a common gate signal. Single-input multiple-output drive approach was adopted to minimize the gate signal time delay mismatch.

[0149] To meet the criteria for integration with three three-phase 12.47 / 7.2 kV wye distribution grid in the United States, a separate auxiliary power supply with high galvanic isolation capability was implemented herein. The exemplary system employed a half-bridge LLC-based magnetic coupled auxiliary power supply design. 30kVdc insulation test and 8.0 kVrms partial discharge (PD) test were performed to verify the feasibility of the design under 7.2kVac.

[0150] Additional descriptions of the exemplary system may be found in Xu, Wei, and Alex Q. Huang. "15-KV / 50-A SiC AC Switch Based on Series Connection of 1.7-KV MOSFETs." IEEE Transactions on Industry Applications 59.5 (2023): 6543-6555, which is incorporated by reference herein in its entirety.

[0151] Example System #3 - Inductor-inductor-capacitor solid-state transformer (LLC-SST) module

[0152] In a third embodiment provided herein, an exemplary single-stage AC-AC converter is disclosed that can provide a high-efficiency high power-density multi-kV medium voltage (MV) solid-state transformer (SST). The exemplary converter includes a half-bridge LLC resonant converter and multi-kV SiC AC switch that can provide softswitching for the MV switches across wide voltage and load ranges. The LLC-SST module can be used as a building block in three-phase architectures for replacing a line frequency transformer (LFT) in the medium voltage power system.

[0153] To improve the efficiency and power density, an exemplary single-phase single-stage AC- AC modular building block based on half bridge inductor-inductor-capacitor (LLC) resonant converter and a 15kV SiC AC switch, i.e., LLC-based solid state transformer, is developed. The exemplary LLC-based solid-state transformer (LLC-SST) module can be directly connected to 7.2kV single phase or 13.8kV three-phase distribution grid under Y configuration. Each modular converter achieves required galvanic isolation through a medium-frequency transformer (MFT), which plays a critical role in determining the system isolation, efficiency, power density, and thermal performance.

[0154] Fig. 7 shows an example single-phase single-stage LLC-SST module. The high voltage side 701 of the modular converter is directly connected to the 7.2kV AC distribution grid (i.e., AC switch power module 704) through two 15kV AC switches (e.g., 5i, S2) and capacitor resonant tank 702 (e.g., Cri, C ). The resonant tank 702 is also used for a capacitive voltage divider in the half-bridge circuit.

[0155] A half-sine voltage Vpri (shown as 705) is generated across the filter capacitor Cpri (shown as 706) on the low voltage side. The half-sine voltage 705 is converted to a 480V AC grid by a silicon insulated-gate bipolar transistor (IGBT) unfolding bridge 708. As shown in Fig. 7, Qi - Q4, Pi - P4, and 5i - S2 are all active devices such that bidirectional operation can be achieved. The capacitance of resonant tank C i equals that of G-2, i.e., the two capacitors evenly share the high side grid voltage.

[0156] Fig. 8 shows the three-phase architectures of medium voltage systems based on the exemplary LLC-SST module. Specifically, subpanel (a) shows a 12.47kV AC / 13.8kV AC four-wire medium voltage system. Subpanel (b) shows a 6.9kV AC three-wire voltage system. As show in Fig. 8, a modular series connection between modules A, B, and C is eliminated from the high voltage side to simplify the control and reduce the cost. The total power rating is determined by the number of the LLC-SST modules paralleled in each phase. The exemplary single-phase single-stage LLC-SST module can be used as a building block for replacing the line frequency transformer in the medium voltage power system.

[0157] Zero voltage switching design based on AC switch power module. The exemplary LLC-SST always operates at unity voltage gain mode, so it employs a soft switching mechanism over a wide voltage range. The two switching mechanisms employed by the exemplary LLC-SST include AC switching and zero voltage switching (ZVS).

[0158] Discussion.

[0159] The instant study was conducted that developed a single-stage AC-AC converter for realizing a high-efficiency high power-density 7.2kV medium voltage (MV) solid-state transformer (SST) based on a half-bridge LLC resonant converter and 15kV SiC AC switch. The topology can address major challenges in MV SSTs, such as achieving soft switching for the MV switches across wide voltage and load ranges. The topology was analyzed through both time domain analysis and first harmonic approximation to provide useful equations for circuit design. The LLC-based SST (LLC-SST) can operate at unity voltage gain mode, soft switching behavior over a wide voltage range is investigated, and proper fully zero voltage switching (ZVS) design methodology. The developed 15kV SiC AC switch was based on 1700V SiC MOSFETs in series connection and was tested at a DC voltage of 10kV / 15A. Parameters, such as Eon, Eoir, E0Ss, Rds, on, and leakage current, of the fabricated AC switch were characterized for system design. A full-scale lOOkVA and compact LLC-SST module that converts 480Vac to 7.2kVac was developed to verify the theoretical analysis. The LLC-SST modular power density is around 25W / inch3. Peak efficiency was expected to be higher than 98.5%. A 300Vac to 4.2kVac preliminary power test with IkQ resistive load bank (18kW) has been demonstrated to verify the feasibility of the proposed single-stage AC-AC converter and validity of the fabricated 15kV AC switch operation. The exemplary LLC-SST module can be used as a building block in three-phase architectures (6.9kVac three-wire and 12.47kVac / 13.8kVac four-wire) for replacing line frequency transformer (LFT) in the medium voltage power system.

[0160] Medium-voltage (2-35kV) solid-state transformer (SST) is a key power electronics technology capable of replacing the line frequency transformer (LFT) and provides many advanced grid-supporting functionalities such as reactive power compensation, voltage regulation, fast frequency response, power flow control and fault isolation

[0028] -

[0032] , However, many technical challenges related to component level voltage and current stress, and system level efficiency, power density, reliability and galvanic isolation must be addressed before the technology is ready for commercial applications

[0033] -

[0035] ,

[0161] To improve the efficiency and power density, the study developed a singlephase, single-stage AC-AC modular building block based on half bridge LLC resonant converter and a novel 15kV SiC AC switch. The exemplary LLC-based SST (LLC-SST) module can be directly connected to a 7.2kV single phase or 13.8kV three-phase distribution grid under the Y configuration. Each modular converter achieves required galvanic isolationthrough a medium-frequency transformer (MFT), which plays a critical role in determining the system isolation, efficiency, power density, and thermal performance. The study focused on the novel single-stage LLC-SST topology analysis and 7.2kV / 100kVA full-scale modular converter hardware design.

[0162] Discussion. Increased adoption of electric vehicles, photovoltaic, and battery energy storage systems is driving the need for high-current SiC power modules. The state-of- the-art multichip module is substantially more expensive than the IGBT module. The instant study developed a cost-effective packaging methodology for high-power SiC intelligent power modules (IPMs) with discrete SiC devices.

[0163] The exemplary IPM integrates the gate drivers, decoupling capacitors, snubbers, discrete SiC devices, direct bond copper, base plate, temperature sensors, and overcurrent protection circuits, achieving very low loop inductance and thermal resistance, and more than 50% cost reduction. A 1200 V / 480 A / 2.15 mQ half-bridge IPM is presented for comparison with commercial counterparts. A 1200 V / 240 A / 4.3 m six-phase IPM was developed, and its performance was experimentally verified.

[0164] The rapid growth of renewable energy was driving the demand for power semiconductors. SiC MOSFETs were replacing Si IGBT because of significantly reduced losses [1’]. From the packaging point of view, power modules were widely used since they were preconfigured in commonly used topologies, making it easy for the end customers of high power converter design. Many new packaging efforts were developed to reduce the loop inductance in order to take advantage of SiC's faster-switching speed [2’]. These improvements usually require advanced packaging structures and new materials. Another packaging trend was to increase the level of module integration to include the gate driver, decoupling capacitor, sensor, EMI filter, and thermal management component. These highly integrated or intelligent power modules (IPM) further reduce the end user's complexity and make the implementation close to plug-and-play. However, these SiC power modules were offered at a premium price caused of the high cost of SiC dies and module packaging costs. Another factor that drove up the cost was the lack of standardization; every vendor's module design was proprietary and different, making second sourcing very difficult.

[0165] In contrast, the instant study developed a cost-effective packaging concept for high-performance SiC IPM based on repackaging discrete SiC devices. The exemplary repackaged IPM integrates the gate drivers, decoupling capacitors, snubbers, discrete SiC devices, direct bond copper (DBC), base plate, temperature sensors, and overcurrent protection circuits, providing excellent loop inductance, thermal resistance, and intelligenceat half of the cost when compared with commercially available SiC power modules solutions. A family of configurations can be developed based on this concept, such as half-bridge, fullbridge, three-phase, dual-full-bridge, and six-phase legs modules.

[0166] Example System #4 - Repackaged silicon carbide (SiC) intelligent power module

[0167] Increased adoption of electric vehicles, photovoltaic, and battery energy storage systems is driving the need for high-current SiC power modules. The state-of-the-art multichip module is substantially more expensive than the IGBT module. In a fourth embodiment provided herein, an exemplary high-power SiC intelligent power module (IPM) with repackaged parallel discrete SiC devices is disclosed that can provide low cost, low parasitic inductance, and high switching speed operations.

[0168] Fig. 9 shows an example power module 900, also referred to as high- performance SiC intelligent power module using repackaged discrete SiC devices (i.e., repackaged IPM), comprising a module housing, an integrated switch assembly, a decoupling and snubber module assembly, and an integrated gate driver.

[0169] In the power module 900, the module housing comprises (i) a base plate 910, (ii) high power connections (e.g., source and drain), including a first connection and a second connection, and (iii) a control connection (e.g., fiber optic connection).

[0170] The integrated switch assembly, disposed in the module housing, comprises a plurality of switching devices (e.g., 906a, 906b) configured in a bridge configuration (e.g., half-bridge, full-bridge, three-phase, dual-full-bridge, and six-phase legs modules), including a first discrete device and a second discrete device.

[0171] The first discrete device is positioned at a first location on and in thermal contact with the base plate 910, and the second discrete device is positioned at a second location on and in thermal contact with the base plate 910. The first discrete device and the second discrete device can be direct copper bonded (e.g., 908a, 908b) to the base plate 910.

[0172] Each of the plurality of discrete switching devices, including the first discrete device and the second discrete device, has a lead frame 912 extending from a respective housing of the discrete switching device.

[0173] The decoupling capacitors and snubber module assembly 904, in electrical connection with the lead frame 914 for pairs of the plurality of discrete switching devices (906a, 906b), includes a printed circuit board 916 housing one or more decoupling capacitors and one or more snubber capacitors (e.g., to minimize loop inductance and provide effective switching speed).

[0174] The decoupling capacitors and snubber module assembly 904 can be coupled to the base plate 910. The decoupling capacitors and snubber module assembly 904 may not be coupled to the base plate 910.

[0175] The integrated gate driver disposed within the module housing and electrically coupled to the integrated switch assembly, is configured to turn on and turn off the plurality of discrete switching devices, including the first discrete device and the second discrete device.

[0176] Repackaged silicon carbide intelligent power module. Fig. 9 shows an example high-performance SiC intelligent power module (IPM) using repackaged discrete SiC devices (i.e., repackaged IPM). As shown in Fig. 9, the exemplary repackaged IPM integrates the gate drivers (e.g., 902a - 902d), decoupling capacitors and snubbers 904, discrete SiC devices (e.g., 906a, 906b), direct bond coppers (DBC) (e.g., 908a, 908b), base plate 910, temperature sensors (e.g., 912a, 912b), and overcurrent protection circuits (not shown), providing excellent loop inductance, thermal resistance, and intelligence at half of the cost when compared with commercially available SiC power modules solutions. A family of configurations can be developed based on this concept, such as half-bridge, full-bridge, three-phase, dual-full-bridge, and six-phase legs modules.

[0177] Fig. 10 shows a cross-sectional diagram of a standard SiC power module and an exemplary repackaged intelligent power module. The conventional power module packaging shown in subpanel (a) is based on the standard multiple-chip wire-bonding manufacturing process in a custom housing. Compared to discrete devices (e.g., MOSFET), the automation level is lower, partly contributing to the higher manufacturing cost. Paralleled dies also have intrinsic current sharing and thermal coupling issues, requiring substantial switching speed "slowing down."

[0178] To address the high cost, high parasitic inductance, and low switching speed issue, a packaging concept is developed based on repackaging discrete devices in parallel to form a high-power module. A power module based on parallel discrete devices shown in subpanel (b) has access to each device's gate. The current can be more directly controlled, improving current sharing, and switching speed. The manufacturing cost is also reduced since there is no wire bonding step in the new package approach; all the processes can be done with reflow soldering.

[0179] Compared with conventional packaging, the exemplary repackaged IPM only adds one additional copper and solder layer (e.g., 1002a, 1002b) to the thermal path, as shown in subpanel (b). The impact is negligible since those materials have superior thermalconductivity. The copper layer can potentially enlarge the effective heat spreading angle, thus benefiting the thermal resistance. Repackaged discrete devices as power modules are attractive for improved performance, lower price, lower design difficulty, and more flexible supply chain strategy.

[0180] Example System #5 - Silicon carbide (SiC) intelligent power stage (IPS) system

[0181] With more and more power electronics-based resources and loads being integrated into the grid, there is a strong desire to standardize the grid power electronics building block to further reduce the cost. In a fifth embodiment provided herein, an exemplary high-power density, low-cost air-cooled multi-kVA SiC Intelligent Power Stage (IPS) is disclosed that employs a six-phase leg using discrete SiC devices that can work as a grid interface converter in multiple applications, such as a PV inverter or a PV plus storage inverter. With a two-stage configuration, the three-phase legs of the exemplary IPS can form an interleaved multiphase DC-DC converter, while the other three-phase legs work as a standard three-phase inverter. The integrated intelligent gate driver can drive the two paralleled SiC devices with balanced current sharing.

[0182] Fig. 11 shows an example self-contained intelligent power stage (IPS) system 1100 (also referred to as SiC IPS system) comprising a base plate and heatsink assembly, a power semiconductor unit, a gate driver, a sensor and inductor-capacitor (LC) filter assembly, a contactor assembly, and a local controller.

[0183] In the IPS system 1100, the power semiconductor unit 1102 comprises a plurality of discrete switching devices (e.g., 1103a - 1103e) having a six-phase leg bridge in thermal connection to the base plate and heatsink assembly (not shown).

[0184] The gate driver 1112, in electrical connection to discrete switching devices (e.g., 1103a - 1103e), turns on and turns off the plurality of discrete switching devices. The gate driver 1112 is configured to drive the six-phase leg bridge as two paralleled SiC devices with balance current sharing.

[0185] The sensor and LC filter assembly 1110 is electrically coupled to the plurality of discrete switching devices (e.g., 1103a - 1103e) of the power semiconductor unit 1102.

[0186] The contactor assembly 1122 comprises a first set of contactors for connection to an AC grid (e.g., having AC filter 1114) and a second set of contacts for connection to a DC bus (e.g., having a DC filter 1116).

[0187] The local controller 1104, in electrical connection to the gate driver 1112, is configured to operate the six-phase leg bridge in a two-stage configuration, each having athree-phase leg, including a first three-phase leg and a second three-phase leg. The first three- phase leg (e.g., 1103d - 1103f) is configured to operate as an interleaved multiphase DC-DC converter, and the second three-phase leg (e.g., 1103a - 1103c) is configured to operate a DC-AC converter as a three-phase inverter.

[0188] The IPS system is configured as a grid interface converter as a photovoltage inverter.

[0189] The local controller 1104 and the sensor and LC filter assembly 1110 include a driver-integrated overcurrent protection circuit, temperature sensing circuit, and online voltage measurement circuit (e.g., to provide fast overcurrent protection and online health monitoring capability).

[0190] In the IPS system 1100, the base plate and heatsink assembly can be a passive heat block or an active heat block.

[0191] The gate driver 1112 is configured to drive the six-phase leg bridge as two paralleled SiC devices with balance current sharing.

[0192] SiC intelligent power stage (IPS) system. Fig. 11 shows the structure of the exemplary silicon carbide intelligent power stage (IPS) system. As shown in Fig. 11, the exemplary IPS system integrates the power semiconductor unit 1102, thermal management components (not shown), local controller 1104, plug-and-play auxiliary power supply 1106, sensors 1108, and passive components to achieve multifunctionalities. The exemplary IPS utilizes an exemplary six-phase leg SiC intelligent power module packaged with discrete SiC devices (i.e., repackaged IPM) as power semiconductor unit 1102 to achieve the high efficiency, high density, and low-cost target. With a two-stage configuration, the three-phase legs of the exemplary IPS system can form an interleaved multiphase DC-DC converter, while the other three-phase legs work as a standard three-phase inverter. The integrated intelligent gate driver 1112 can drive the two paralleled SiC devices with balanced current sharing. The driver-integrated overcurrent protection circuit, temperature sensing circuit, and online voltage measurement circuit (not shown) provide fast overcurrent protection and online health monitoring capability. A natural-convection-cooled self-contained auxiliary power supply unit 1106 is employed to power up the entire exemplary IPS from both AC side 1114 and DC side 1116. The exemplary IPS system has a communicate interface 1118 with the master controller 1120 for grid-supporting functions (e.g., PWM, sensing, auxiliary power) and can monitor the condition of power semiconductors online to predict lifetime and schedule maintenance.

[0193] Discussion. With more and more power electronics-based resources and loads being integrated into the grid, there is a strong desire to standardize the grid power electronics building block to further reduce the cost. The exemplary system implemented a high-power density, low-cost air-cooled 75kVA SiC Intelligent Power Stage (IPS) as a possible solution for this purpose. The six-phase leg IPS was developed using discrete SiC devices, hence achieving very high power density and low cost. An intelligent gate driver is designed with integrated overcurrent protection, on-state voltage measurement, and temperature sensing functions to enable versatile and intelligent functionalities.

[0194] The integrated auxiliary power supply was designed to start the system from both DC and AC sides. The IPS has built-in communication interface to communicate with other controllers to form a much larger and multiple converter systems and microgrids. The developed IPS is tested at 75kW in a two-stage DC-AC mode. The DC-DC stage is a closed loop controlled by the local controller, while the DC-AC stage responds to the modulation index from an external system controller. Measured full load two-stage power stage efficiency is 98.1% at 75kW.

[0195] The modem power grid was undergoing significant changes to accommodate new generations and loads, such as renewable energy generation and electric vehicle fast chargers, where power electronics-based converters served the essential rule to interconnect the source and the load to the AC grid. These grid interface power electronics converters and their enhanced control had an excellent opportunity to provide grid support functionalities, such as power control, voltage regulation, grid inertia support, frequency response, and load demand regulation [14’], [15’]. Provided that the control is coordinated and robust, there can be an opportunity to increase the grid's reliability, resilience, efficiency, and flexibility [16’], [17’]. However, these were all based on the assumption that the hardware was reliable and interoperable between different vendors.

[0196] With a vision to standardize the power electronics interfaces grid applications, the previous studies developed a concept of Intelligent Power Stages (IPSs) [17’-20’]. The IPS was a multiport, modular, scalable, adaptable, and flexible fundamental building block with plug-and-play features. The IPSs served as the grid interface and provided bidirectional AC or DC power flow control from multiple resources to multiple loads responding to the system controller's command. With the standardized IPS, the energy system can achieve a reduced Balance of System (BOS) cost, operation cost, and maintenance cost. In order to obtain a highly efficient and compact IPS, the use of SiC devices was preferred in the exemplary IPS system instead of Si IGBT. SiC provides superior conduction and switchingperformance, but the power module cost can be relatively high for high-power IPS implementation. Using a discrete SiC power device was a lower-cost option, but the design was more challenging [21 ’], [22’]. In addition, the reliability of the power semiconductor was still the number one concern in power electronics converters; monitoring the device degradations online was a new trend in power electronics design that can provide optimal scheduled maintenance and avoid unnecessary system shutdown [24’], [25’].

[0197] The study developed an exemplary IPS system utilizing a six-phase leg SiC intelligent power module packaged with discrete SiC devices (i.e., repackaged IPM) to achieve the high efficiency, high density, and low-cost target. With a two-stage configuration, the three-phase legs of the exemplary IPS system can form an interleaved multiphase DC-DC converter, while the other three-phase legs work as a standard three-phase inverter. The integrated intelligent gate driver can drive the two paralleled SiC devices with balanced current sharing. The driver-integrated overcurrent protection circuit, temperature sensing circuit, and online voltage measurement circuit provided fast overcurrent protection and online health monitoring capability.

[0198] An additional description of the exemplary system may be found in Chen, Zibo, et al. "A high power density 75kva air-cooled sic intelligent power stage (ips) as a universal building block for grid applications." 2023 IEEE Applied Power Electronics Conference and Exposition (APEC). IEEE, 2023, which is incorporated by reference herein in its entirety.

[0199] Experimental Results and Additional Examples

[0200] A set of studies was conducted to develop the exemplary power modules and systems for achieving higher energy efficiency in medium-voltage high-current power semiconductor devices and applications. Experimental results, simulation results, and additional examples and implementation details for each of the Embodiments #1 - #5 are provided below.

[0201] Embodiment #1 - Series-parallel silicon carbide half-bridge intelligent power module (IPM)

[0202] The study developed a second parallel connection method for high-current SuperMOS that is immune to parameter mismatches in threshold voltage and gate loop inductance due to a strong negative feedback mechanism inherent in the parallel connection. The configuration enabled the successful development of a 3.6kV / 400A SuperMOS IPM with superior performance.

[0203] Figs. 12 - 13 show experimental and simulation results for the first medium voltage embodiment. In particular, Figs. 12A - 12B show the on-resistance distribution and voltage distribution of the MOSFET devices (i.e., switches) in a fabricated intelligent power module (IPM). Gate loop speed can affect the dynamic current sharing. The threshold voltage (Vth) distribution of multiple C3M0021120D devices is tested by curve tracer at Ids=15mA and room temperature, as shown in Figs. 12A and 12B, which shows the variation range is between 2.75V and 2.96V, again about 10% variations. Figs. 13A - 13B show the simulated waveforms of two parallel configurations of the branches in the fabricated intelligent power module (IPM). Fig. 13C shows the measured current waveform during the turn-on transient of the fabricated intelligent power module (IPM).

[0204] In the study, to enable higher current operation, the development of the 3.6kV / 400A Austin SuperMOS half-bridge IPM [8] was based on a parallel connection of four identical 3.6kV / 100A SiC Austin SuperMOS half bridges. Fig. 1A, subpanel (b) shows the half-bridge power module and its circuit schematic. The IPM uses a series-first and parallel-second configuration involving a total of 12 devices for each switch. Isolated power supply and gate drive units are also integrated. The IPM only has two control signal inputs and two fault indicator outputs. Control signals are fed into the Austin SuperMOS IPM through two optic fiber interfaces.

[0205] For the developed IPM, 1200V discrete SiC MOSFET C3M0021120D was used. Since each branch’s Rdson is the summation of three discrete device, the variation of the Rds, on will affect the static current sharing.

[0206] Results. The study tested the drain-source on resistance (Rds, on) distribution of the MOSFET devices in a fabricated IPM by curve tracer at gate-source voltage Vgs= 20V and room temperature, as shown in Fig. 12A. The Rds, on variation, range is between 18mQ and 20.5mQ, or about 10% variations. This variation suggests that the static current sharing can be affected by this small variation. However, higher current branches will result in high temperatures. Like Si MOSFET, the Rds, on of the SiC MOSFET also have the PTC characteristic; the one with higher junction temperature will see higher increases of the Rds, on hence starts to balance the branch current. So the static current balancing issue in the SuperMOS IPM is similar to standard MOSFET parallel operation. A thermal equilibrium will be reached eventually to avoid thermal runaway.

[0207] The study tested the threshold voltage (Vth) distribution of multiple MOSFET devices in the fabricated IPM by curve tracer at drain-source current / *= 15mA and roomtemperature, as shown in Fig. 12B, which shows the variation range is between 2.75V and 2.96V, again about 10% variations.

[0208] Figs. 13A - 13B show the simulated waveforms of the two parallel configurations in the fabricated IPM. As shown in Fig. 13B, configuration 2 had a noticeable transient current unbalance caused by the voltage difference on the mutual inductance (Lm) between the paralleled branches because the fabricated IPM during turn-on was a voltage- controlled current source. As shown in Fig. 13 A, configuration 1 had a minimal transient current unbalance because configuration 1 provided a negative feedback loop that offset the difference caused by the individual device connection.

[0209] The study validated the dynamic current sharing in a double pulse test setup at 2kV / 200A. Fig. 13C shows the measured current waveform during the turn-on transient of the fabricated IPM.

[0210] For the rising edge of the current waveform, there was slight current unbalance in the current waveform in configuration “2,” as shown in subpanel (a), while the current waveform was perfectly balanced in configuration “1” as shown in subpanel (b). The maximum dynamic current imbalance during the turn-on transient of configuration 2 was about 30% of the switching current, while it was almost negligible in configuration 1.

[0211] Second configuration. In another configuration, the study developed and characterized a design, packaging of a 6.8kV / 160A Austin SiC SuperCascode halfbridge power module having die-level package. The package has four 1.7kV SiC JFET dies in each switch position. The exemplary module exhibits ultra-low on-state resistance, excellent thermal handling capability, and reduced power loop parasitic inductance. Direct bonded copper (DBC) substrate is utilized to achieve excellent thermal performance as well as the high voltage insulation required for a 6.8 kV module. The static and dynamic performance of the module was analyzed experimentally.

[0212] Medium-voltage wide bandgap semiconductor devices such as the 3.3-15 kV SiC MOSFETs [27’][28’] are reported with superior performance compared with Si IGBTs. However, the high cost of thick SiC epitaxial layer [29’] can hamper the commercial introduction of medium voltage SiC devices and modules. On the other hand, medium voltage SiC switches are critical components for the grid edge electrification and renewable energy integration. Example applications are solid-state transformers (SST) designed for various use cases [30’] as well as medium voltage motor drive [31’]. To address this gap, series connection of LV devices provides an alternative method to achieving high blocking voltages. In addition, compared to the traditional series connection concept, cascodeconfiguration requires only one gate terminal, and can be realized by using low voltage JFET [32’] or MOSFET [33 ’]-[34’]. Researchers in [33’] [34’] demonstrated a novel three- terminals 7.2V SiC Austin SuperMOS power switch utilizing six series-connected 1.2kV SiC MOSFETs with only one gate driver. However, the MOSFET based configuration results in a reduced gate voltages for devices on the top of the string. This increases the overall Rds, on.

[0213] From this perspective, normally-on JFET based cascode [32’][35’] is better and the total on-resistance is equal to the sum of all devices in the string.

[0214] Figs. 14A - 141 show experimental and simulation results for a series cascode IPM device in accordance with another illustrative embodiment. Specifically, Fig. 14A shows 6.8kV / 160A Austin Super-Cascode prototype (size: 15cm* 15cm*2cm) and its parameters. Fig. 14B shows blocking characteristics from module DC+ to Dcat lOkV and test setup. Fig. 14C shows a Q3D module and result for the developed module power loop inductance at 100kHz. Fig. 14D shows a SolidWorks Flow Thermal simulation model and quadrants at RT. result (100W device loss at RT). Fig. 14E shows an I-V curve of the low side switch in the module in the first and third Fig. 14D SolidWorks Flow Thermal simulation model and quadrants at RT. Fig. 14F shows an Austin SuperCascode Module Switching performance at 5kV / l 10A. Fig. 14G shows Dynamic voltage sharing at 5kV / l 10A (a)turn-on (b) turn-off. Fig. 14H shows an Austin SuperCascode Qoss and Eoss as a function of the voltage. Fig. 141 shows an Austin SuperCascode Eoff as a function of the current.

[0215] The study developed for the first time a 6.8-kV / 160A Austin SuperCascode half-bridge power module based on series connection of four low on-resistance 1.7kV SiC JFETs at the die-level. Furthermore, two 6.8 kV switches are integrated into a single module to form a half bridge. All components are placed on a high voltage insulated DBC substrate for better thermal performance as well as to decrease the module size and weight. As a result, a much lower power loop parasitic inductance is achieved in the developed module.

[0216] 6.8KV supercascode half-bridge module. Fig. ID shows a schematic of a6.8kV / 160A SiC SuperCascode module. Fig. 14A shows two SuperCascode switches packaged inside a module. The table of Fig. 14A shows a summary of the specification of the module.

[0217] Configuration of Austin SuperCascode half-bridge. In an example prototype, four 1700V / 5.7mohm SiC JFET dies manufactured by United Silicon Carbide are connected in series in each switch position to achieve the 6.8kV blocking per the schematic of Fig. ID. Mi is a low voltage 40V MOSFET in cascode configuration with the first JFET. R1-R4 are used for static voltage balancing, and Ci~C4 are used for dynamic voltage balancing.Rgl~Rg4 are damping resistors that limit the gate loop charging and discharging currents in the capacitor branch during the turn-on and turn-off transients. D1 D3 are avalanche diodes for voltage clamping and enhancing the turn-on performance. Rd is the damping resistor for limiting the diode loop leakage. All components are placed on a 1mm thick AIN DBC board with an isolation voltage higher than lOkV [34’]. Silicone gel was used to encapsulate the module. A 2mm thick nickel-plated copper baseplate was soldered to the other side of the DBC for mechanical support.

[0218] Operation principle of the Austin SuperCascode half bridge. Unlike the traditional series switch, the Austin SuperCascode only needs one gate control terminal. In the on state, a positive gate voltage is applied to the MOSFET and JFETs (Ji—Jd) through the diode Di to D3 connected between the gates of the devices. To turn off the Austin SuperCascode, a negative gate driver signal (-5 V) is applied to MOSFET’ s gate, and Mi is turned off. Then Mi’s Vds increases, boosting the potential of Ji’s source, resulting in the negative voltage across Ji’s gate to source. Once Ji’s Vgsvoltage reaches its pinch-off voltage, Ji is turned off, and its Vds rise subsequently, leading to the turn-off of J2. Similarly, all the SiC JFETs (Ji-Jd) are turned off one by one. The voltage sharing between each device is achieved by RI~R4 for static and Ci~C4 for dynamic. When Ji turns off, the inductive load current shifts to two paths: one path charges the Ji Coss, and the other one discharges Cgsof J2 and charges Ci. Similarly, during other JFETs turn-off, the C2-C4 is charged. So, the dynamic balance can be achieved if the ith capacitor is determined by C£=- balance —d v -oltage Q 9

[0219] Insulation and DBC Layout Design. The developed module used a high insulation voltage AIN DBC substrate with a 1mm thickness. It has an excellent thermal conductivity of 170W / mK and a high dielectric strength of 20kV / mm at room temperature. The packaged module substrate has been subjected to a lOkV DC isolation test. The voltage was applied between the DC+ terminal and the baseplate terminal. No leakage current was observed during the test, demonstrating the high insulation capability of the developed module [34’]. The high and low side switches were placed in a U-shaped pattern to reduce the power loop inductance. The two DC terminals are on one side of the module, and the switch node (midpoint) terminal was on the other side of the module. The DBC pattern was designed to avoid the DBC corner electric field crowding and surface breakdown. Fig. 14D shows the DC blocking test setup and result from DC+ to DC-. There is no partial discharge at lOkV. With the U loop and die-level packaging, and die-level packaging, the total loopparasitic inductance from the DC+ terminal to DC- terminal is estimated to be 98.6nH, A Q3D model is developed to extract parasitic inductance in the power loop. The model is shown in Fig. 14C.

[0220] Thermal performance and DC current rating. In the developed module, 1mm AIN DBC with an excellent thermal conductivity of 170W / mK were soldered onto a 2 mm Nickle plated Copper baseplate and SiC JFET dies were soldered to the surface of the DBC. Based on the simulation and test result in [34’]. The junction to baseplate thermal resistance Rjc for each die is 0.3875°C / W . Fig. 14D shows the SolidWorks Flow thermal simulation result. For JFET operating at an elevated junction temperature of 175°C, Rds, on is 15mohm. Based on this, the DC current rating of the module is determined as 160.6A

[0221] Static performance. I-V curves, including the forward and reverse conductions of the Austin SuperCascode, were characterized at room temperature, as shown in Fig. 14E. The forward on-state resistance of the module is 47.7mQ for a Vgsof +20V. For reverse conduction at Vgs= +20V, the resistance of the module was approximately 33mQ. For reverse conduction with an Mi gate bias Vgs= 0 V, the knee voltage was around 0.7V, which was determined by the Mi body diode.

[0222] Dynamic Switching performance. Fig. 14F shows the switching performance of the Austin SuperCascode at 5kV / l 10A. Measured dV / dt is 17 kV / ps for turn-off and 10 kV / ps for turn-on, respectively. Fig. 14G shows the dynamic voltage sharing performance during 5kV / l 10A switching. The voltages of each JFET’s drain to the ground were measured and plotted. The dynamic voltage balancing was well achieved at turn-on and turn-off transients.

[0223] Dead time requirement and switching frequency. To understand the deadtime requirement in ZVS converters, the output charge Qoss of the Austin SuperMOS was extracted from the SiMetrix simulations and shown in Fig. 14H. At 5kV, Qoss of the SuperCascode is 10.234uC. For an LLC converter operating with a turn-off current of 10A (magnetizing current), this deadtime limitation can be calculated as tdmin=Qoss / Imax= 10.234uC / (10A / 2)=2046.8ns.

[0224] In an LLC converter, the total deadtime required is therefore 2046.8ns. The deadtime may be limited to be less than 10% of the switching period to maintain a meaningful power transfer capability. Therefore, the maximum soft-switching frequency limit can be set as fzvs,max < l / (2tdmin)* 10=24.4 kHz.

[0225] Another limitation is the switching loss-based limitation. Fig. 141 summarizes the accurate turn-off loss for the Austin SuperCascode Half-bridge module, which can becalculated by SiMetrix simulation and the loss may be used for loss calculation in ZVS enabled converters.

[0226] Embodiment #2 - Alternating current (AC) switch power module

[0227] The study developed a 15kV / 50A AC switch power module based on 1.7 kV SiC MOSFET in series. 30 kVdc insulation and 8.0 kVrms partial discharge (PD) tests were demonstrated to prove the developed auxiliary power supply is capable of the 12.47 / 7.2 kVac system operation. The series-connected SiC devices of the AC switch was driven by a common gate signal. A mismatch of the gate signals between different channels was verified to be less than 10ns. Single pulse test results proved that the maximum voltage unbalance ratio during turn-off at 10kV / 15A can be limited about 138V by using a small capacitor snubber. Inductive switching energy was extracted from the SPT with different snubber capacitances at 10kV / 15A. The prototyped AC switch can be used as a building block for medium voltage power electronic systems.

[0228] Figs. 15 - 22 show experimental and simulation results for the second medium voltage embodiment. In particular, Figs. 15A - 15C show the circuit diagram and prototype of a fabricated alternating current (AC) switch power module with 30kV insulation capability. Fig. 16 shows the partial discharge test (in Coulomb) with time for the fabricated alternating current (AC) switch power module. Fig. 17 shows the gate signal turn-on and turn-off transient mismatch test results of the fabricated alternating current (AC) switch power module. Fig. 18 shows the turn-off transient simulation results for the fabricated alternating current (AC) switch power module with and without scrubber circuit. Fig. 19 shows the single pulse test (SPT) circuit and typical waveforms at 10kV / 15A with Cs = 660pF. Figs. 20A - 20B show the drain voltage and drain-to-source voltage measurements across the bottom MOSFET devices for the fabricated alternating current (AC) switch power module. Fig. 21 A shows the average drain voltage after turn-off for the fabricated alternating current (AC) switch power module. Fig. 21B shows voltage unbalance ratio at 10kV / 15A with three different snubber capacitances for the fabricated alternating current (AC) switch power module. Figs. 22A - 22B show the results for the turn-on and turn-off losses and leakage current test of the fabricated alternating current (AC) switch power module.

[0229] Fabricated AC switch power module. Figs. 15A - 15C show the circuit diagram and prototype of the fabricated AC switch power module with 30kV insulation capability. In the fabricated AC switch power module shown in Fig. 15 A, the input voltage Vin was +24V from the ground distribution board 1502, and the output voltage +15V / -8V(V1 / V2) at the low dropout (LDO) regulators 1506a - 1506c, was selected based on the suggested gate-source voltage of the SiC MOSFETs.

[0230] The fabricated AC switch power module also utilized multiple pulse transformers 1504a - 1504c to maximize the isolation of voltage pulse transmission from the voltage delivery to LDO regulators. Fig. 15B shows the prototype of the fabricated AC switch power module employing multiple pulse transformers.

[0231] The study achieved the 30kV galvanic isolation using pulse transformers, as shown in Fig. 15C. A 30kV silicone rubber insulated wire, which was the common primary winding 1508a, passed through the center of the ten transformer cores. Secondary windings 1508b were closely attached to the surface of the transformer core. The coupling capacitance between the primary and secondary side of the power transmission transformer had a low value of 1.5pF which enabled a high noise immunity.

[0232] Fig. 16 shows the partial discharge test (in Coulomb) with time for the fabricated AC switch power module. The fabricated AC switch power module passed the 30kV DC insulation test and 8.0kVrms partial discharge-free (PD-free) test as shown in Fig. 16. The maximum static discharge measured in Coulombs at 8kVrms was less than 50pC. The peak discharge short pulse (around 300pC in Fig. 16) resulted from the voltage ramp-up during the test. These results indicated that the fabricated AC switch power module was capable of three phase 12.47 / 7.2kV wye distribution grid operation (phase to neutral peak voltage is 10.2kV due to the wye configuration). Additional research, such as potting, can be done to meet higher insulation targets while balancing the need for power density.

[0233] Fig. 17 shows the gate signal turn-on and turn-off transient mismatch test results. Due to the oscilloscope channel limits, only eight gate-source voltages (Fgj_i-s) of the ten cascaded SiC MOSFETs were shown in the waveforms. The minimum gate signal mismatch ensured an allowable voltage sharing even without any balancing techniques.

[0234] The study conducted SIMetrix simulations to demonstrate the effect of 10ns gate signal mismatch. The ten devices were divided into six groups, of which the gate signal delays were set to 0, 2, 4, 10 ns, respectively. Fig. 18 shows the turn-off transient SIMetrix simulation results for the fabricated AC switch power module with and without a scrubber circuit.

[0235] Subpanel (a) shows the turn-off transient under 12kV / 5A. The maximum voltage unbalance between all ten serial-connected MOSFET devices was 330V. Subpanel (b) shows the turn-off transient simulation results with G=0.5nF. Maximum voltage unbalance was limited to 60V with the same gate signal delays.

[0236] AC switch power module characterization. The study tested the switching performance of the fabricated 15kV AC switch power module. Fig. 19 shows the single pulse test (SPT) circuit and typical waveforms at 10kV / 15A with Cs = 660pF. As shown in subpanel (a), both the top and bottom devices (Sa and Sb) were half of the AC switch which can be assembled through rewiring of the two devices. As shown in subpanel (b), the overall falling edge dv / dt at turning on was around (dv / dt)oN = -194V / ns and the rising edge dv / dt at turning off was around (dv / dt)oFF= 45V / ns. This high dv / dt verified the noise immunity and reliability of the presented gate driver design inthe fabricated AC switch power module.

[0237] Voltage Unbalance Ratio. Fig. 20A shows the drain voltage measurements(Vds2) across the bottom device Sb with C=660pF. Each measurement Vd i-n(w=2,3...,10) denotes the voltage across the common source (DC-) to the drain terminal of the / / th device. Vdsi _i is the drain to source voltage across the most bottom MOSFET. Fig. 20B shows the drain to source voltage Vds2 n (n=l ,2...,10) across the / / th cascaded MOSFET in the bottom device Sb with G=660pF.

[0238] The voltage unbalance ratio of the series-connected ten devices can be defined per Equation 1.(Eq. 1)

[0239] In Equation 1, / Vis the number of the series-connected devices (AMO), Vdc is the DC link voltage, i.e., the static drain to source voltage across the bottom device Sb before turn-on, Vds2 max and Vd _min is the maximum and minimum drain voltage among the O cascaded MOSFETs after turn-off, respectively.

[0240] Fig. 21 A shows the average drain voltage Vd _n (n= 1 ,2..., 10) after turn-off at 10kV / 15A with three different snubber capacitances. Fig. 21B shows the voltage unbalance ratio calculated using Equation 1 versus the dv / dt snubber capacitance. Three different capacitor values were selected in the comparison. With the increase of the Cs from 660pF to 1.5nF, the voltage unbalance ratio was reduced by 30% (from 19.84% to 13.8%).

[0241] Inductive Switching Energy. Fig. 22A shows comparative results of turn-on and turn-off losses of the fabricated 15kV SiC AC switch power module. The switching energy Eon, Eoff, and Eoss can be calculated as shown in Equations 2, 3, 4, respectively.(Eq. 2)(Eq. 4)

[0242] In Equations 2, 3, 4, Vds(f) and Ids(f) is the measured drain voltage across the bottom device Sb and the drain current flowing through the device, respectively, EOSS,MOS is the energy stored in the output capacitance Coss of the single SiC MOSFET (e.g., G3R20MT17K) under 1000V. Propagation time mismatch between the voltage and current probes were ignored in this calculation.

[0243] In order to tradeoff between a satisfactory voltage balancing performance and reasonable switching loss, a dv / dt snubber capacitor range from 400 to 600pF across each MOSFET was recommended.

[0244] Leakage Current. The total leakage current was determined by the static voltage balancing 10MQ resistor across each device's drain-to-source terminal. Fig. 22B shows the leakage current test results versus the drain-source voltage V of the fabricated AC switch power module. Table 1 shows other electrical characteristics of the fabricated AC switch power module.Table 1

[0245] Embodiment #3 - Inductor-inductor-capacitor solid state transformer (LLC- SST) module

[0246] The study developed a single-phase, single-stage AC-AC converter for realizing a 7.2kV / 100kVA medium voltage (MV) solid-state transformer (SST) based on the half-bridge LLC resonant converter and 15kV SiC AC switch. The LLCSST topology was analyzed with time domain analysis to provide useful equations and understanding for hardware design. The half-bridge LLC-SST always operates under the unity voltage gain mode; the soft switching capability can be guaranteed across full voltage and load ranges. The developed LLCSST modular converter can be used as a building block for replacing LFT in three-phase medium voltage power systems (6.9kV three-wire and 12.47kV / 13.8kV four- wire).

[0247] A 15kV / 50A SiC AC switch based on 1700V SiC MOSFETs in series connection was developed and evaluated. 30kVdc insulation and 8.0kVrms partial discharge (PD) tests have been demonstrated to prove the developed 15kV AC switch is capable of maximum 13.8 / 8.0kVac three-phase four-wire system operation. A single pulse test (SPT) was performed on the AC switch at a DC voltage of 10kV / 15A. Critical parameters, such as Eon, Eoff, Eoss, Rds, on, and leakage current, of the developed AC switch were characterized.

[0248] The study developed a lOOkVA full-scale and compact LLC-SST module that

[0249] directly converts 480Vac to 7.2 kVac. The modular power density is around 25W / inch3. Peak efficiency is expected to be higher than 98.5%. A 300Vac to 4.2kVac preliminary power test with IkQ resistive load bank (18kW) has been demonstrated to verify the feasibility of the proposed LLC-SST module and validity of the fabricated 15kV / 50A SiC AC switch.

[0250] Figs. 23 - 28 show experimental and simulation results for the third medium voltage embodiment. In particular, Figs. 23 A - 23B show the simulated line cycle operation and simulated operation waveforms for one switching cycle of the exemplary single-phase single-stage LLC-based solid state transformer module. Fig. 24 shows the output capacitor stored energy as a function of the drain-to-source terminal voltage. Fig. 25 shows the fabricated 7.2kV / 100kVA LLC-SST prototype based on a half-bridge LLC resonantconverter and a 15kV alternating current (AC) switch power module. Figs. 26A - 26B show the estimated efficiency curve and the detailed loss breakdown at lOOkVA of the fabricated LLC-based solid-state transformer (SST) module. Fig. 27 shows the thermal test results of a single switch Sia of the fabricated LLC-based solid-state transformer (SST) module with ambient temperature Ta=21°C. Fig. 28 shows the power test results of the fabricated LLCbased solid state transformer module under 300V AC input and 4.2kV AC output with IkQ resistive load bank.

[0251] Simulated line cycle operation. Fig. 23 A shows the simulated line cycle operation of the exemplary single-phase, single-stage LLC-SST module. Voltage Vab (shown in Fig. 7) was connected to a 480V AC power grid on the low voltage side. The half-bridge LLC circuit always operated at unity voltage gain mode. The study adopted an open loop control of the resonant LLC stage and an adaptive deadtime regulation in the simulation.

[0252] Sia and Sib were the gate signals of the top and bottom switch of the AC switch Si, as shown in Fig. 7, respectively. The gate signal of Sia was kept ON during the negative half cycle, and switched at around 50% duty cycle during the positive half cycle. The gate signal for Sib was complementary, with the gate turned on during the positive half cycle and switched at around 50% during the negative half cycle. In this sense, the devices Sia and Sib behaved as AC switch capable of blocking current and voltage in both directions. Pi was the gate signal of low voltage side MOSFET (shown in Fig. 7), which switched at 50% duty cycle and had the same frequency as the AC switch. Qi was the gate signal for the IGBT unfolding bridge (shown in Fig. 7) which switched at line frequency 60Hz. Vpnwas the half-sine voltage generated across the low voltage side AC link capacitor Cpn. Ipn was the current flowing through the transformer's primary side winding.

[0253] Simulated switching cycle operation. Since the operation principle of the LLC- SST was the same for the positive and negative half cycles of the AC grid, the study focused on the analysis of the positive half cycle. During the positive half cycle, the low voltage side IGBTs Qi, Q , and high voltage side switches Sib, Sib (shown in Fig. 7) were kept ON. Full soft switching can be realized for the rest of devices on both the primary and secondary side with a proper design of switching frequency fs, deadtime td, and magnetization inductance Lm.

[0254] Fig. 23B shows the simulated operation waveforms for one switching cycle of the exemplary LLC-SST module. VPand Vs were the primary and secondary side transformer winding voltages, respectively. Imwas the transformer magnetization current on the primary side. Ipri and heed were the primary and secondary side transformer winding current. Io was the output current on the high voltage side within one switching cycle, which can be treatedas one constant DC value due to the dominant low-frequency 60Hz component (switching resonant ripple was ignored here). Icri and Icri were the current flow through the two resonant capacitors, Cri and Cri. Table 2 shows two major operation modes within one switching cycle.Table 2

[0255] Fabricated LLC-SST module. The fabricated single-stage AC-AC LLC-SST module required a proper ZVS design across the entire input voltage range. Due to the nonlinearity of MOSFET's Coss / Qoss versus the drain-source voltage, the zero-voltage switching (ZVS) conditions for both the high-voltage and low-voltage sides were more complicated than that of a DC-DC converter.

[0256] For the configuration of 480V AC input and 7.2kV AC output, the AC switches in the associated AC switch power module can achieve zero current switching (ZCS); the actual switching loss may depend on the energy stored in output capacitance (Eoss) as shown in Equation 6.(Eq 6)

[0257] In Equation 6, N is the number of the series-connected MOSFETs (AMO), Cs is the snubber capacitance across each MOSFET's drain-to-source terminal, Vdc is the terminal voltage across the AC switch, EMOS is the energy stored in the output capacitance Coss of the single SiC MOSFET (e.g., G3R20MT17K). Fig. 24 shows the output capacitor stored energy as a function of drain-to-source terminal voltage, EMOS =fiVds').

[0258] For the configuration of 7.2kV AC input and 480V AC output, the ZVS behavior of the AC switch under this condition was only associated with terminal voltage, turn-off transient current, and dead time. The LLC-SST operated at the resonant frequency f- based on the time-domain analysis in Equation 5. The turn-off current of the AC switch can be defined per Equation 7.(Eq. 7)

[0259] To achieve fully ZVS, sufficient turn-off current and deadtime were required to charge / discharge the corresponding device of the AC switch. By applying the energy conservation equation before and after the ZVS transition, the required ZVS condition from the energy point of view can be defined per Equation 8.(Eq. 8)

[0260] As an additional condition, a sufficient dead-time should satisfy Equation 9.(Eq. 9)

[0261] In Equation 9, Iseca (tofff) is the secondary side transformer winding current during the dead-time interval, td = ton - toff is the dead-time, Qoss Vdc) is the equivalent output charge of the corresponding device of the AC switch. A minimum dead-time td,min = 500ns was used to avoid a short circuit.

[0262] According to Equations 7 - 9, the ZVS constraint of the AC switch was independent of load conditions. However, Qossand Eossof the AC switch were nonlinear functions of the applied terminal voltage Vdc, which meant that the ZVS condition changed with the applied terminal voltage. Therefore, proper design of magnetization inductanceswitching frequency fs, and dead-time td were necessary.

[0263] 100 kVA LLC-SST Hardware Design. Fig. 25 shows the fabricated7.2kV / 100kVA LLC-SST prototype based on a half-bridge LLC resonant converter and the developed 15kV AC switch. A 99.8% efficient 100 kVA medium voltage transformer (MFT), as shown in Fig. 25, with a power capability of more than 200 kW, was also fabricated and tested. Table 3 shows the key specifications of the fabricated lOOkVA 480V / 7.2kV AC LLC- SST module.Table 3

[0264] The LLC-SST modular power density was around 25W / inch3. Fig. 26A shows the estimated efficiency curve of the fabricated LLC-SST module. As shown in Fig. 26A, peak efficiency under 480V / 7.2kV AC configuration was higher than 98.5%, and the estimated efficiency at lOOkVA was 97.58%. Fig. 26B shows the detailed loss breakdown at lOOkVA for the fabricated LLC-SST module.

[0265] Thermal dissipation test and power test. The bottleneck of the fabricated 7.2kV / 100kVA LLC-SST module thermal design was on the 15kV AC switch. To verify the thermal dissipation capability of the AC switch, the study connected source-drain terminal of one switch Sia to a DC power source to forward bias all body diodes.

[0266] Fig. 27 shows the thermal test results of the single switch Sia, with ambient temperature Ta=21°C. The total power loss on the single switch Sia is 200W, which generated a temperature rise of 90°C on the device case. This predicted the maximum junction temperature can be Tj,max=135°C with 200W power loss and 40°C ambient temperature for single switch Sia. The above results proved that the AC switch can dissipate 120W power loss (on a single switch) for 7.2kV / 100kVA continuous operation with 97.5% efficiency.

[0267] Fig. 28 shows the power test results of the fabricated LLC-SST module under 300V AC input and 4.2 kVAc output with 1 kQ resistive load bank. The total power was 18kW. The test verified the feasibility of the fabricated single-stage ac-ac LLC-SST module and the validity of the fabricated 15kV AC switch power module.

[0268] Embodiment #4 - Silicon carbide intelligent power module (SiC IPM) using repackaged discrete silicon carbide devices (i.e„ repackaged IPM)

[0269] The instant study developed and evaluated a cost-effective SiC power module packaging methodology. A family of SiC IPM was packaged with commercially available discrete SiC devices. The developed IPMs integrated the gate drivers, decoupling capacitors, snubbers, discrete SiC devices, DBC, base plate, temperature sensors, and overcurrent protection circuits inside the power module, providing excellent loop inductance, thermal resistance and intelligence at half cost. The power loop inductance of 1200 V / 480 A / 2.15 mQ half-bridge module was extracted in Ansys Q3D to be 6.2 nH for the entire commutation loop, including contributions from the TO-247 packaging and busbar.

[0270] A 1200 V / 240 A / 4.3mQ six-phase SiC IPM was experimentally validated in the 850 V / 480 A (2X rating) double pulse test and 75 kW two-stage dc-ac converter test. The 75 kW two-stage dc-dc / dc-ac full load efficiency is 98.1%, including all passive component losses and six-phase legs.

[0271] Figs. 29 - 33 show experimental and simulation results for the fourth medium voltage embodiment. In particular, Fig. 29 shows the fabrication process for a fabricated repackaged intelligent power module (IPM). Fig. 30 shows the fabricated repackaged intelligent power module (IPM) with the busbar and pulse-width modulation (PWM) receiver. Fig. 31A shows a state-of-the-art 1200V power module in high-performance 62 mm packaging. Fig. 3 IB shows the fabricated 1200 V / 240 A / 4.3mQ six-phase repackaged intelligent power module with the heatsink, busbar, and PWM receiver. Fig. 32 shows the switching transients for 455 A tum-ON and 480 A turn-OFF of the fabricated repackaged intelligent power module. Figs. 33A - 33B shows the measured efficiency curve and temperature of two-stage DC-DC / DC-AC operation in the fabricated repackaged intelligent power module.

[0272] Fabricated repackaged SiC IPM. Fig. 29 shows the fabrication process for a fabricated repackaged intelligent power module. The fabricated process started with component preparations (subpanel a), including bending the discrete devices, soldering the decoupling and snubber capacitor card, and the gate driver board. The study then attached the print circuit board-made (PC-made) mold to the direct bonded copper (DBC) location (subpanel b). The study applied solder paste to the DBC and placed the DBC on the base plate (subpanel c) before attaching the PCB-made mold to the semiconductor (e.g., MOSFET) location (subpanel d). The study then applied solder paste to the semiconductor and placed the semiconductor on the DBC (subpanel e), and the module was then ready for reflow soldering. Finally, the study assembled the temperature sensor, decoupling capacitor, and gate driver (subpanels f, g). The study added the module frame and encapsulation materials as the last step.

[0273] The DBC provided an insulated low thermal resistance path and offered no electric connection, so the DBC layout was straightforward. Smaller pieces of the DBC were used to prevent the coefficient of thermal expansion (CTE) mismatch. The number of devices and phases was flexible in the fabrication process.

[0274] Power loop optimization and electromagnetic interference (EMI) reduction. Power loop parasitic inductance was a barrier to fast switching, causing higher switching losses and overshoot voltages [6’]. The decoupling capacitor was integrated into the fabricated repackaged IPM. An optimized layout with magnetics flux cancelation can help reduce the loop inductance on the busbar, and the total loop inductance for a 480A module was extracted in Ansys Q3D to be around 6.2 nH. The power loop was also symmetrical, essential for current dynamic sharing.

[0275] Fig. 30 shows a fabricated repackaged IPM with the busbar and PWM receiver. As shown in Fig. 30, the fabricated repackaged IPM has two primary commutation loops: the power loop 3002 for the active switch and the capacitor loop 3004 between the decoupling capacitor and the DC link capacitor.

[0276] The power loop 3002 decided the overshoot voltage when the device was turned OFF and caused a high-frequency oscillation, mainly between the device Coss and the power loop inductance. The capacitor loop 3004 did not overly influence the switching speed or overshoot voltage. However, the capacitor loop 3004 generated a low-frequency oscillation between the decoupling capacitor and the capacitor loop inductance. Most parasitic inductance in the capacitor loop came from the lead inductance between the decoupling capacitor card and the busbar. The overshoot voltage was well managed in the fabricated repackaged IPM, so the fabricated repackaged IPM can be used on higher DC-link voltage, thus improving voltage utilization. For example, the study tested a 1200 V / 240 A / 4.3mQ six-phase IPM at 900V at full current without overshoot concern. The PCB for decoupling capacitors only passed through a high-frequency oscillation current during the switching transient, and it damped quickly; thus, the PCB for decoupling capacitors did not require heavy copper layers.

[0277] Fast- switching SiC devices brought in additional challenges in EMI and required bulky EMI filters at the converter level. Since the power semiconductor devices were the source of the EMI, reducing the EMI within the power module was desirable. Previous studies showed that a closer and adequate decoupling capacitor can help with the EMI problems [7’], [8’], as well as integrating the EMI filters [9’] or adding EMI shielding layers [10’]. The fabricated repackaged IPMs integrate additional snubbers (e.g., As and Cs in Fig. 30) inside the power module, which can tradeoff between the EMI reduction and loss.

[0278] Gate driver and sensors. Optimizing the gate driving loop was an essential part of high-power SiC module design since it directly influenced the switching speed and current balancing. Commercially available power modules had parallel dies inside and used an external gate driver chip to drive multiple dies. Due to this layout arrangement, each die had a different gate driving loop and different loop inductance.

[0279] A gate resistor was typically added to each die loop to slow the switching and compensate for this mismatch. For example, Fig. 31 A shows a 1200 V power module in high- performance 62 mm packaging. As shown in Fig. 31 A, two dies on the edge (e.g., 3102, 3104) had different loop lengths, and the total gate driving loop inductance was even more prominent when adding the external inductance from the driver board.

[0280] The fabricated repackaged SiC IPMs had a short and symmetric gate driving loop, as shown in Fig. 30. The gate driver chips had direct access to every single die, and the dedicated driving network and symmetrical loop inductance can result in balanced transient current sharing [11’]. The gate driver design needed to be careful with more device parallel. There can be other options to improve the driving performance, such as using a single driver module with impedance matching, a multi-driver module, or a combination [12’].

[0281] Temperature sensing can be a preferred function for modem power modules. However, for conventional modules such as that shown in Fig. 31 A, the temperature measurement was usually taken at one side of the module and the module cannot indicate the junction temperature of each die. This temperature information was usually enough for temperature monitoring and protection but was hard to implement in active thermal management.

[0282] In the fabricated repackaged SiC IPMs, each temperature sensor sensed the temperature of one of the two paralleled devices. Since both devices were placed close to each other on the same DBC, the temperature coupling was strong. Hence, the fabricated repackaged IPM had an accurate temperature of all SiC power devices. The isolated temperature information was sent out by the duty cycle of a 400 kHz PWM signal, which the microcontroller can process. The programmable hardware-based overcurrent protection was also embedded with the gate driving circuits to achieve fast overcurrent protection.

[0283] Experimental validations. Fig. 3 IB shows a fabricated 1200 V / 240 A / 4.3mQ six-phase repackaged IPM with the heatsink, busbar, and PWM receiver. The frame was opened from the top to show its internal structure.

[0284] Double Pulse Test. The 1200 V / 240 A / 4.3 mQ six-phase IPM was evaluated in an 850 V / 480 A (2X rating) low-side double pulse test (DPT). Fig. 32 shows the switching transients for 455 A turn-ON and 480 A turn-OFF. The current among the two parallel devices was well-balanced during the switching. Top traces presented the Vds voltage on the parallel switches separately, measured by the THDP0200 voltage probe. Bottom traces presented the drain current of the two paralleled devices, measured by the TRCP0300 current probe.

[0285] 75 kW Two-Stage DC-DC / DC-AC Test. The study also evaluated the fabricated repackaged six-phase IPM in a two-stage DC-DC / DC-AC converter [13’]. The boost DC-DC stage consisted of interleaved three-phase legs, while the DC-AC stage was a standard two-level three-phase inverter. The input DC voltage was 500 V and was boosted to 830V intermediate DC-link; then, the input DC voltage was inverted to 480V AC output connected to a resistive load. The switching frequency was 30 kHz.

[0286] Fig. 33A shows the measured efficiency curve of a two-stage DC-DC / DC-AC operation. As shown in Fig. 33 A, at 75 kW full load, an excellent efficiency of 98.1% was obtained by a power analyzer, including the loss on the fabricated repackaged SiC IPM and all passive components. The device temperature at 75 kW was only 81.2°C, measured by a FLIR E60 thermal camera, as shown in Fig. 33B. The high-power test result demonstrated the extraordinary electrical and thermal performance of the fabricated repackaged SiC IPM.

[0287] Embodiment #5 - Silicon carbide (SiC) intelligent power stage (IPS) system

[0288] The study designed and implemented a 75kVA two-stage multiport SiC intelligent power stage (IPS). The IPS is a multiport, modular, scalable, adaptable, and flexible building block with plug-and-play features. A six-phase SiC power module was packaged with discrete devices, providing very high density and low cost for the power unit. The intelligent gate driver can drive the parallel SiC device with balanced current sharing. The driver-integrated overcurrent protection circuit, temperature sensing circuit, and online voltage measurement circuit provided fast overcurrent protection and online health monitoring information. A natural-convection-cooled auxiliary power supply was designed to start the system from both the DC and AC sides. The IPS has interoperability to communicate with the master controller for grid-supporting functions and can monitor the condition of power semiconductors online to predict lifetime and schedule maintenance. The communication was achieved by SCI protocol through optic fiber at 6.25Mbps. The developed IPS was tested to 75kW in the two-stage DC-AC mode with all the intelligent functions working. The DC-DC stage was closed-loop controlled by the local controller, while the DC-AC stage responds to the modulation index from the master controller.

[0289] Full load two-stage power stage efficiency was measured at 98.1% at 75kW, and the peak efficiency is measured at around 98.2%. The hotspot captured by the thermal camera was around 81.2°C at 75kW operation, which verifies the design.

[0290] Figs. 34 - 44 show experimental and simulation results for the fifth multi-kVA embodiment. In particular, Fig. 34 shows a fabricated IPS system. Fig. 35 shows a repackaged six-phase silicon carbide (SiC) intelligent power module (IPM) employed by the fabricated intelligent power stage (IPS) system. Fig. 36 shows the simulated thermal management of the repackaged silicon carbide intelligent power module (IPM) employed by the fabricated intelligent power stage (IPS) system. Fig. 37 shows the gate driver circuit, including the parasitic inductance employed by the fabricated intelligent power stage (IPS) system. Fig. 38 shows a gate driver-integrated circuit for online on-state voltage measurement (OVM) in the fabricated intelligent power stage (IPS) system. Figs. 39A - 39B show on-statevoltage and temperature waveforms when a SiC device in the fabricated intelligent power stage (IPS) system operated in a buck operation and in an inverter operation. Fig. 40 shows the circuit diagram and the fabricated hardware of the auxiliary power supply employed by the fabricated intelligent power stage (IPS) system. Fig. 41 shows the experimental result for the auxiliary power supply employed by the fabricated intelligent power stage (IPS) system. Fig. 42A shows a control framework of the fabricated intelligent power stage (IPS) system. Fig. 42B shows an interleaved dual-loop DC-DC control mechanism with phase current balancing of the local controller of the fabricated intelligent power stage (IPS) system. Fig. 43 shows the switching waveform and temperature readings of the fabricated intelligent power stage (IPS) system in the 75kW DC-AC test. Fig. 44 shows the DC-AC stage efficiency and DC-DC plus DC-AC two-stage efficiency for the fabricated intelligent power stage (IPS) system measured by the Hioki PW6001 power analyzer.

[0291] Fabricated IPS system. Table 4 shows the system parameters of the fabricated IPS system.Table 4

[0292] The fabricated IPS system was configured as a two-stage DC-AC converter, the DC-DC stage included three-phase legs as an interleaved DC-DC converter, and the other three-phase legs consisted of the three-phase inverter. The DC side input voltage range was 500V-900V, and the inverter was rated at 75kVA. The AC output was connected to the 480V grid. The interleaved DC-DC stage had a 1 lOpH inductor on each phase leg, while the DC- AC stage only had 4 pH since the DC-AC stage was externally configured and responding to the command from the master controller.

[0293] Fig. 34 shows the fabricated IPS system. As shown in Fig. 34, the fabricated IPS system included the power unit, gate driver, local controller, sensors, auxiliary powersupply, contactor driver, thermal management components, and all the passive components as a standard modular building block.

[0294] Silicon carbide intelligent power module (i.e., unit). The power semiconductor switch was a critical component in the fabricated IPS system. Wide bandgap technology such as SiC MOSFET substantially eliminated the barriers between high power and high efficiency. In the fabricated IPS system, a six-phase SiC power module was repackaged with discrete SiC devices to achieve a low-cost solution. The SiC power module, heatsink, fans, gate driver, PCB bus bar, DC link capacitor, and local controller were all integrated as a high- density power unit.

[0295] Fig. 35 shows the repackaged six-phase silicon carbide (SiC) intelligent power module employed by the fabricated intelligent power stage system. The highly integrated 150kW (2x75kW) power unit had a power density of 22kW / L (360W / in3), and the semiconductor cost was around $8.8 / kW. The study used the aluminum nitride Direct Bonded Copper (DBC) as the thermal interface between the SiC switch and the heatsink because of its superior thermal conductivity.

[0296] The thermal management was verified in flow simulations where 1920W total loss was injected. Fig. 36 shows the simulated thermal management of the repackaged silicon carbide intelligent power module employed by the fabricated intelligent power stage system. As shown in subpanel (a), the device in the middle had the highest temperature, 134°C, while the device on the edge had a 12°C temperature difference. The study further extracted the thermal resistance. When 1986W loss was injected into the hardware by body diode reverse conduction, the hot spot in the middle was 104°C, which was observed by a thermal camera.Subpanel (b) shows the thermal flow managed by the repackaged IPM of the fabricated IPS system.

[0297] Intelligent gate driver. In the fabricated IPS system, two discrete devices were in parallel to realize each switch function in the six-leg IPS. Driving parallel devices required a dedicated design to ensure current balance and avoid inter-device oscillations. Fig. 37 shows the gate driver circuit, including the parasitic inductance employed by the fabricated IPS system. The mismatch in threshold voltage (Vth) had the most influence on dynamic current balance during the switching [12’], [13’]. Rgand Rgswere optimized to damp the inherent oscillations between the two SiC devices.

[0298] The study further developed a gate driver-integrated circuit for online on-state voltage measurement (OVM), as shown in Fig. 38, and online temperature measurement (OTM). The driver-integrated circuits can measure the device conduction voltage drop Vds onand the device junction temperature Tj for both topside device 3802 and bottom-side device 3804 in real-time while maintaining regular switching operation and over-current protection. The Rds on can be extracted as the online health condition indicator. The acquired data can further predict the device's lifetime status if an appropriate degradation model is applied. A gate driver integrated OVM and its signal conditioning circuit can be implemented to measure the device's on-resistance (Rds on, Rsd on) in real-time.

[0299] Targeting online conditioning in high-power and high-density SiC converters, the OVM and OTM circuits should be accurate and small. The study selected UCC21750 as the gate-driving IC with fast switching, over-current protection, and soft turn-off. The OVM measurement used a high-impedance precision isolated operational amplifier with a 1 : 1 fixed gain. The input impedance was high, so the influence on the gate driving and OC protection was minimized. The sensing was implemented for top and bottom SiC FETs with minimum additional components. Fig. 39A shows an on-state voltage measurement waveform as channel 1 (CHI) when the SiC device (e.g., MOSFET) was operating in a buck converter. Channel 3 (CH3) was a flag when the digital signal processor (DSP) read voltage measurements in each switching cycle. Fig. 39B shows online on-resistance and temperature measurements in 800V DC to 480V AC 22kW operation.

[0300] Plug-and-play auxiliary power supply. Fig. 40 shows the circuit diagram and the fabricated hardware of the auxiliary power supply employed by the fabricated intelligent power stage system. As shown in Fig. 40, the plug-and-play auxiliary power supply (APS) provided housekeeping power and cooling fan power for the fabricated IPS system. The APS obtained the power from either the AC side or the DC side.

[0301] The study also integrated a naturally cooled diode bridge rectifier unit 4002 (shown as 4002’) with an aluminum-based PCB substrate into the APS. The study verified the thermal performance, with 3 A current conducted on each phase. The hot spot captured by the thermal camera was around 87°C, corresponding to more than IkW auxiliary power capability.

[0302] Fig. 41 shows the experimental result for the auxiliary power supply employed by the fabricated ISP system. The APS was connected to the DC power supply and 480V grid simultaneously. As shown in Fig. 41, the APS was first powered by the DC power supply, where the voltage was 850V DC. After stepping off the DC power supply, the APS was powered by the grid side and maintained the APS DC bus at 670V.

[0303] Control interactions. The fabricated IPS system had good interoperability to cooperate with the master controller or IPSs. The interface, interconnections, communicationprotocols, messages between the entities, timing requirements and synchronization, coordinated hierarchical control, and multiple grid functions can be achieved with standardization.

[0304] Fig. 42A shows a control framework of the fabricated ISP system. As shown in Fig. 42A, the IPS local controller had its local decisionmaking capability. With multiple built-in sensors inside the fabricated IPS system, the fabricated IPS system has various levels of protection, and the protection level can be user adjusted. The fabricated IPS system had its housekeeping power supply and closed-loop control for the DC-DC converter. The IPS can respond to the master controller to achieve the AC side control and grid support functions.

[0305] The communication between the fabricated IPS system and the master controller was essential to achieve the desired control and protection. A control protocol to standardize the communication between the fabricated IPS system and the master controller was proposed in a previous study [6’]. Table 5 shows the communications between the fabricated IPS system and the master controller. As is shown in Table 5, the proposed control had two communication channels (control channel and data channel) and a synchronization channel. The control channel transmitted the AC voltage reference or duty ratios from the master controller to the fabricated IPS system. In contrast, the data channels exchanged information between the two controllers, such as the IPS operation status and health monitoring.Table 5

[0306] Fig. 42B shows the interleaved dual-loop DC-DC control mechanism with phase current balancing of the local controller of the fabricated IPS system. Responding to the command from the master controller, the DC bus voltage was fixed at the desired value with various input voltage ranges. The outer voltage loop compares the bus voltage with the voltage reference then generates the current reference for the inner loop, which finally determines the duty cycle of the DC-DC stage devices. In the control mechanism shown in Fig. 42B, a current-sharing controller was employed on top of the current loop to balance the current in each phase. A compensation signal, which was calculated with a difference between 1 / 3 of the reference and the phase current, was added to the duty cycle of each phase. When any phase current is lower than others, the current sharing controller may increase the duty cycle of that phase to increase the current. Since the current unbalance usually comes from some fixed circuit parameter mismatches, a proportional controller can well balance the three phases' current.

[0307] Evaluation results. The study developed and tested the fabricated IPS system to its full power rating. The DC input side was connected to a DC power supply, while the AC side was connected to a resistive load bank. The DC input voltage was 600V, the DC link voltage was maintained around 820V, and the AC output voltage was 480V line to line. The DC-DC stage ran in closed loop interleaving mode while the DC-AC stage was open loop.

[0308] Fig. 43 shows the switching waveform and temperature readings of the fabricated IPS system in the 75kW DC-AC test. The highest device temperature captured by a thermal camera was 81.2°C at around 24°C room temperature. The local controller also read and recorded the device temperature through the embedded temperature sensors. As shown in subpanel (b), the fabricated IPS system (i.e., converter) took around 300s to reach thermal balance, and the junction temperature was around 95°C. Subpanel (c) shows the thermal camera and embedded sensor temperature reading comparison, wherein the embedded temperature sensor reading can better represent the device junction temperature.

[0309] Fig. 44 shows the DC-AC stage efficiency (subpanel a) and DC-DC plus DC- AC two-stage efficiency (subpanel b) for the fabricated IPS system measured by the Hioki PW6001 power analyzer (subpanel c). The peak efficiency for the IPS was around 98.2%, and the full load efficiency was about 98.1%. The efficiency measurement included the semiconductor loss, magnetic loss, cable loss, and sensor loss. The power consumption by the control system, fans, and contactor drivers were separately measured to be around 150W.

[0310] Conclusion

[0311] It must also be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Ranges may be expressed herein as from “about” or “ 5 approximately” one particular value and / or to “about” or “approximately” another particular value. When such a range is expressed, other exemplary embodiments include one particular value and / or the other particular value.

[0312] By “comprising” or “containing” or “including,” is meant that at least the name compound, element, particle, or method step is present in the composition or article or method but does not exclude the presence of other compounds, materials, particles, method steps, even if the other such compounds, material, particles, method steps have the same function as what is named.

[0313] In describing example embodiments, terminology will be resorted to for the sake of clarity. It is intended that each term contemplates its broadest meaning as understood by those skilled in the art and includes all technical equivalents that operate in a similar manner to accomplish a similar purpose. It is also to be understood that the mention of one or more steps of a method does not preclude the presence of additional method steps or intervening method steps between those steps expressly identified. Steps of a method may be performed in a different order than those described herein without departing from the scope of the present disclosure. Similarly, it is also to be understood that the mention of one or more components in a device or system does not preclude the presence of additional components or intervening components between those components expressly identified.

[0314] The following patents, applications and publications as listed below and throughout this document are hereby incorporated by reference in their entirety herein. Reference List #1[1] A. Q. Huang, " 15 kV SiC MOSFET: An Enabling Technology for Medium Voltage Solid State Transformers," CPSS Trans. Power Electron. Appl., vol. 2, no. 2, pp. 118-130,2017, doi: 10.24295 / cpsstpea.2017.00012.[2] G. Romano, S. Wirths, A. Mihaila, Y. Arango, A. Ruiz, and L. Knoll, "RuggedDynamic Behaviour of 3.3kV SiC Power MOSFETs with High-k Gate Dielectric," Proc. Int. Symp. Power Semicond. Devices ICs, vol. 2021 -May, pp. 263-266, 2021, doi: 10.23919 / ISPSD50666.2021.9452193.[3] M. Sakai, S. Toyoshima, K. Wada, M. Furumai, T. Tsuno, and Y. Mikamura, "3.3KV SiC power module with low switching loss," SEI Tech. Rev., no. 81, pp. 51- 55, 2015.[4] J. L. Hostetler, P. Alexandrov, X. Li, L. Fursin, and A. Bhalla, "6.5 kV SiC normally-off JFETs - Technology status," 2nd IEEE Work. Wide Bandgap Power Devices Appl. WiPDA 2014, pp. 143-146,2014, doi: 10.1109 / WiPDA.2014.6964642.[5] J. B. Casady et al., "New Generation lOkV SiC Power MOSFET and Diodes forIndustrial Applications," PCIM Eur. 2015; Int. Exhib. Conf. Power Electron. Intell. Motion, Renew. Energy Energy Manag. Proc., no. May, pp. 1-8,2015.[6] X. Song, A. Q. Huang, and S. Sen, "15-kV / 40-A FREEDM Supercascode : ACost-Effective SiC High-Voltage and," vol. 53, no. 6, pp. 5715-5727, 2017.[7] L. Thang, S. Sen, and A. Q. Huang, "7.2-kV / 60-A Austin SuperMOS: AnIntelligent Medium- Voltage SiC Power Switch," IEEE J. Emerg. Sei. Top. Power Electron., vol. 8, no. 1, pp. 6-15,2020, doi: 10.1109 / JESTPE.2019.2951602.[8] Z. Guo, L. Zhang, S. Sen and A. Q. Huang, "A Novel 3.6kV / 400A SiC IntelligentPower Module (IPM)," 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), 2021, pp. 39-43, doi: 10.1109 / APEC42165.2021.9487034.[9] G. Wang, J. Mookken, J. Rice, and M. Schupbach, "Dynamic and static behavior of packaged silicon carbide MOSFETs in paralleled applications," Conf. Proc. - IEEE Appl. Power Electron. Conf. Expo. APEC, pp. 1478-1483,2014, doi: 10.1109 / APEC.2014.6803502.

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[0011] A. Q. Huang, "Power Semiconductor Devices for Smart Grid and Renewable Energy Systems," in Proceedings of the IEEE, vol. 105, no. 11, pp. 2019-2047, Nov. 2017, doi: 10.1109 / JPROC.2017.2687701.

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[0020] X. Song, A. Q. Huang, S. Sen, L. Zhang, P. Liu and X. Ni, "15-kV / 40-A FREEDM Supercascode: A Cost-Effective SiC High-Voltage and High- Frequency Power Switch," in IEEE Transactions on Industry Applications, vol. 53, no. 6, pp. 5715-5727, Nov.-Dec. 2017.

[0021] L. Zhang, S. Sen and A. Q. Huang, "7.2-kV / 60-A Austin SuperMOS: AnIntelligent Medium- Voltage SiC Power Switch," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 1, pp. 6-15, March 2020, doi: 10.1109 / JESTPE.2019.2951602.

[0022] Z. Guo, L. Zhang, S. Sen and A. Q. Huang, "A Novel 3.6kV / 400A SiCIntelligent Power Module (1PM)," 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), 2021, pp. 39-43, doi: 10.1109 / APEC42165.2021.9487034.

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[0024] I. Lee and X. Yao, "Voltage Balancing Control with Capacitor Charging Method for Series Connected SiC MOSFET Submodules," 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020, pp. 3125-3130, doi: 10.1109 / ECCE44975.2020.9235723.

[0025] C. Li, S. Chen, H. Luo, C. Li, W. Li and X. He, "A Modified RC Snubber WithCoupled Inductor for Active Voltage Balancing of Series-Connected SiC MOSFETs," in IEEE Transactions on Power Electronics, vol. 36, no. 10, pp. 11208-11220, Oct. 2021.

[0026] W. Xu et al., "Hardware Design and Demonstration of a lOOkW, 99% EfficiencyDual Active Half Bridge Converter Based on 1700V SiC Power MOSFET," 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2020, pp. 1367-1373, doi: 10.1109 / APEC39645.2020.9124401.

[0027] W. Xu, A. Vetrivelan, Z. Guo, R. Yu and A. Q. Huang, "Efficiency Optimization of Dual Active Bridge Converter Based on dV / dt Snubber Capacitors," 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), 2021, pp. 647-653, doi: 10.1109 / APEC42165.2021.9487159.

[0028] A. Q. Huang, "Power Semiconductor Devices for Smart Grid and Renewable Energy Systems," in Proceedings of the IEEE, vol. 105, no. 11, pp. 2019-2047, Nov. 2017, doi: 10.1109 / JPROC.2017.2687701.

[0029] A. Q. Huang, "Medium- Voltage Solid-State Transformer: Technology for aSmarter and Resilient Grid," in IEEE Industrial Electronics Magazine, vol. 10, no. 3, pp. 29-42, Sept. 2016, doi: 10.1109 / MIE.2016.2589061.

[0030] W. Xu, Z. Guo, A. Vetrivelan, R. Yu and A. Q. Huang, "Hardware Design of a13.8-kV / 3-MVA PV Plus Storage Solid-State Transformer (PVS-SST)," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 10, no. 4, pp. 3571-3586, Aug. 2022, doi: 10.1109 / JESTPE.2021.3082033.

[0031] X. Song, C. Peng and A. Q. Huang, "A Medium- Voltage Hybrid DC Circuit Breaker, Part I: Solid-State Main Breaker Based on 15 kV SiC Emitter Tum- OFF Thyristor," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 5, no. 1, pp. 278-288, March 2017, doi:10.1109 / JESTPE.2016.2609845.

[0032] Q. Zhu, L. Wang, A. Q. Huang, K. Booth and L. Zhang, "7.2-kV Single-StageSolid-State Transformer Based on the Current-Fed Series Resonant Converter and 15-kV SiC mosfets," in IEEE Transactions on Power Electronics, vol. 34, no. 2, pp. 1099-1112, Feb. 2019, doi: 10.1109 / TPEL.2018.2829174.

[0033] W. Xu, R. y. Yu, Z. Guo and A. Q. Huang, "Design of 1500V / 200kW 99.6%Efficiency Dual Active Bridge Converters Based on 1700V SiC Power MOSFET Module," 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020, pp. 6000-6007, doi: 10.1109 / ECCE44975.2020.9235903.

[0034] H. Wen, J. Gong, X. Zhao, C. -S. Yeh and J. -S. Lai, "Analysis of Diode ReverseRecovery Effect on ZVS Condition for GaN-Based LLC Resonant Converter," in IEEE Transactions on Power Electronics, vol. 34, no. 12, pp. 11952-11963, Dec. 2019, doi: 10.1109 / TPEL.2019.2909426.

[0035] Y. Du, J. Wang, G. Wang and A. Q. Huang, "Modeling of the High-Frequency Rectifier With 10-kV SiC JBS Diodes in High-Voltage Series Resonant Type DC-DC Converters," in IEEE Transactions on Power Electronics, vol. 29, no. 8, pp. 4288-4300, Aug. 2014, doi: 10.1109 / TPEL.2013.2288642.

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[0042] Q. au, L. Wang, D. Chen, L. Zhang, and A. Q. Huang, "Design and implementation of a 7.2 kV single stage AC-AC solid state transformer based on current source series resonant converter and 15 kV SiC MOSFET," in Proc.IEEE Energy Conyers. Congr. Expo. (ECCE), Cincinnati, OH, USA, Oct. 2017, pp. 1288-1295, doi: 10.1109 / ECCE.2017.8095938.

[0043] D. Dong, M. Agamy, J. Z. Bebic, Q. Chen, and G. Mandrusiak, "A modular SiC high-frequency solid-state transformer for medium-voltage applications: Design, implementation, and testing," IEEE J. Emerg. Sei. Topics Power Electron., vol.7, no. 2, pp. 768-778, Jun. 2019, doi: 10.1109 / JESTPE.2019.2896046.

[0044] S. Madhusoodhanan et al., "Solid-state transformer and MV grid tie applications enabled by 15 kV SiC IGBTs and 10 kV SiC MOSFETs based multilevel converters," IEEE Trans. Ind. Appl., vol. 51, no. 4, pp. 3343-3360, Jul. / Aug.2015, doi: 10.1109 / TIA.2015.2412096.

[0045] A. Anurag, S. Acharya, Y. Prabowo, V. Jakka, and S. Bhattacharya, "Mobile utility support equipment based solid state transformer (MUSES ST) for MV grid interconnection with Gen3 10 kV SiC MOSFETs," in Proc. IEEE Energy Conyers. Congr. Expo. (ECCE), Portland, OR, USA, Sep. 2018, pp. 450-457, doi: 10.1109 / ECCE.2018.8557388.

[0046] W. Xu et al., "Hardware Design and Demonstration of a lOOkW, 99% EfficiencyDual Active Half Bridge Converter Based on 1700V SiC Power MOSFET," 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), 2020, pp. 1367-1373, doi: 10.1109 / APEC39645.2020.9124401.

[0047] W. Xu and A. Q. Huang, "15kV / 50A SiC AC Switch Based On SeriesConnection of 1.7kV MOSFETs," 2022 MEE Energy Conversion Congress and Exposition (ECCE), 2022, pp. 1-6, doi: 10.1109 / ECCE50734.2022.9947463.

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Claims

What is claimed:

1. A power semiconductor module comprising: a module housing comprising (i) two high power connections, including a first connection and a second connection and (ii) a control connection; an integrated switch assembly disposed in the module housing comprising a plurality of sets of plurality of switching elements, wherein each set of the plurality of switching elements form a branch that are individually connected in parallel configuration to other parallel branches, and wherein each branch has a respective set of the plurality of switching elements that includes a respective plurality of switching elements connected in series connection to one another; an isolated power supply disposed in the module housing; and a single gate driver disposed in the module housing, receiving control signal from the control connection, and electrically coupled to the isolated power supply and the integrated switch assembly, the gate driver being configured to (i) singularly and concertedly turn on the plurality of sets of plurality of switching elements in concert with one another from a single command signal and (ii) singularly and concertedly turn off the plurality of sets of plurality of switching elements from the single command signal, to have the plurality of sets of plurality of switching elements act as a single switch, wherein each switching element of the plurality of switching elements has a static voltage balance component across the drain and source terminal of the switching element, a dynamic voltage balance component across the drain and gate terminal of the switching element, and a gate to source voltage clamp component, wherein at least one of static voltage balance component, the dynamic voltage balance component, or the gate voltage clamp component for each branch is connected in a parallel configuration to corresponding static voltage balance components, dynamic voltage balance components, or gate voltage clamp components of other parallel branches.

2. A power semiconductor module comprising: a module housing comprising (i) two high power connections, including a first connection and a second connection and (ii) a control connection; an integrated switch assembly disposed in the module housing comprising a plurality of switching elements, wherein the plurality of switching elements form a branch that are individually connected in series connection to one another; an isolated power supply disposed in the module housing; anda single gate driver disposed in the module housing, receiving control signal from the control connection, and electrically coupled to the isolated power supply and the integrated switch assembly, the gate driver being configured to (i) singularly and concertedly turn on the plurality of switching elements in concert with one another from a single command signal and (ii) singularly and concertedly turn off the plurality of switching elements from the single command signal, to have the plurality of switching elements act as a single switch.

3. The power module of claim 1, wherein the static voltage balance component for each branch is connected in a parallel configuration to corresponding static voltage balance components of other parallel branches.

4. The power module of claim 1, wherein the dynamic voltage balance component for each branch is connected in a parallel configuration to corresponding dynamic voltage balance components of other parallel branches.

5. The power module of claim 1, wherein the gate voltage clamp component for each branch is connected in a parallel configuration to corresponding gate voltage clamp components of other parallel branches.

6. The power module of any one of claims 1-5, where the switching element is a semiconductor die, and the electrical connections are made through wire bond.

7. The power module of any one of claims 1-5, wherein the plurality of sets of plurality of switching elements, the gate driver, and the isolated power supply are repeated to form a half bridge configuration, a full bridge configuration, or a three-phase bridge.

8. The power module of any one of claims 1 - 7, wherein the plurality of sets of plurality of switching elements have a main half-bridge loop of parallel branches configured to be symmetric to each other to have a minimal mismatch in parasitic inductance of the main power loop, and wherein each branch having the respective set of the plurality of switching elements has a gate loop configured to be symmetric to each other to have a minimal mismatch in parasitic inductance of the gate loop.

9. The power module of any one of claims 1 - 8, wherein each branch having a respective set of the plurality of switching elements is fixably attached to a printed circuit board and in thermal contact to a single baseplate for the module.

10. The power module of any one of claims 1 - 8, wherein each branch having a respective set of the plurality of switching elements is fixably attached to a printed circuit board and in thermal contact to a respective baseplate for the branch.

11. A method of operating the power module of any one of claims 1-10, comprising: providing a first command signal to the gate driver to singularly and concertedly turn on the plurality of sets of plurality of switching elements in concert with one another; providing a second command signal to the gate driver to singularly and concertly turn off the plurality of sets of plurality of switching elements in concert with one another.

12. A power module comprising: a module housing comprising (i) a base plate, (ii) high power connections, including a first connection and a second connection, and (iii) a control connection; an integrated switch assembly disposed in the module housing comprising a plurality of discrete switching devices configured in a bridge configuration, including a first discrete device and a second discrete device, wherein the first discrete device is positioned at a first location on and in thermal contact with the base plate, and wherein the second discrete device is positioned at a second location on and in thermal contact with the base plate, wherein each of the plurality of discrete switching devices, including first discrete device and the second discrete device, has a lead frame extending from a respective housing of the discrete switching device; a decoupling capacitor and snubber module assembly in electrical connection with the lead frame for pairs of the plurality of discrete switching devices, wherein the decoupling capacitors and snubber module assembly includes a printed circuit board housing one or more decoupling capacitors and one or more snubber capacitors.

13. The power module of claim 12, wherein the decoupling capacitors and snubber module assembly is not coupled to the base plate.

14. The power module of claim 12, wherein the decoupling capacitors and snubber module assembly is coupled to the base plate.

15. The power module of any one of claims 12 - 14, wherein the first discrete device and the second discrete device are direct copper bonded to the base plate.

16. The power module of any one of claims 12 - 15, comprising: an integrated gate driver disposed within the module housing and electrically coupled to the integrated switch assembly, the integrated gate driver being configured to turn on and turn off the plurality of discrete switching devices, including the first discrete device and the second discrete device.

17. The power module of any one of claims 12 - 16, wherein the bridge configuration is selected from the group consisting of a half-bridge, a full-bridge, a three-phase bridge, a dual- full-bridge bridge, and a six-phase legs module bridge.

18. A method of fabricating a power module comprising: providing a first printed-circuit board mold for direct bond copper (DBC) connection on the base plate of the power module of any one of claims 12-17; applying solder paste to the DBC location; positioning the DBC on the base plate providing a second printed circuit board mold for device location; applying solder paste to the plurality of discrete switching devices and placing the plurality of discrete switching devices on the DBC; reflowing the solder; and attaching the decoupling capacitors and snubber module assembly to the lead frame for the pairs of the plurality of discrete switching devices.

19. A method of claim 18, wherein the discrete switching device comprises a TO-247 packaged device.

20. A self-contained intelligent power stage system comprising: a base plate and heatsink assembly;a power semiconductor unit comprising a plurality of discrete switching devices having a six-phase leg bridge in thermal connection to the base plate and heatsink assembly; a gate driver in electrical connection to discrete switching devices to turn on and turn off the plurality of discrete switching devices; a sensor and LC filter assembly electrically coupled to the plurality of discrete switching devices of the power semiconductor unit; a contactor assembly comprising a first set of contactors for connection to an AC grid and a second set of contacts for connection to a DC bus; and a local controller in electrical connection to the gate driver, wherein the local controller is configured to operate the six-phase leg bridge in a two-stage configuration, each having a three-phase leg, including a first three-phase leg and a second three-phase leg, wherein the first three-phase leg is configured to operate as an interleaved multiphase DC-DC converter, and wherein the second three-phase leg is configured to operate a DC-AC converter as a three-phase inverter.

21. The system of claim 20, wherein the gate driver is configured to drive the six-phase leg bridge formed by two or more paralleled SiC devices with balance current sharing.

22. The system of claim 20 or 21, wherein the system is configured as a grid interface converter.

23. The system of any one of claims 20 - 22, wherein the local controller and the sensor and LC filter assembly includes driver-integrated overcurrent protection circuit, temperature sensing circuit, and online voltage measurement circuit.

24. The system of any one of claims 20 - 23, wherein the base plate and heatsink assembly is passively cooled or actively cooled.

25. The system of any one of claims 20 - 24, wherein the discrete switching module comprises a SiC power MOSFET.

26. A power semiconductor switch system comprising: a first plurality of high-voltage switching devices configured in series connection to one another; anda second plurality of high-voltage switching devices configured in series connection to one another, wherein the first plurality of high-voltage switching devices are identical and in source-to-source connection with another gate driver in electrical connection with the second plurality of high-voltage switching devices; and a gate driver comprising a pulse transformer in electrical connection with the first plurality of high-voltage switching devices and the second plurality of high-voltage switching devices to turn on and turn off the first plurality of high-voltage switching devices and the second plurality of high-voltage switching devices; and a gate driver isolated power supply comprising a pulse transformer in electrical connection with the first plurality of high-voltage switching devices and another gate driver isolated power supply in electrical connection with the second plurality of high-voltage switching devices to provide power supplies to each of the power devices in the first plurality of high-voltage switching devices and the second plurality of high-voltage switching devices.

27. The system of claim 26 comprising: an RC snubber capacitor electrically connected between a drain terminal and a source terminal of the respective switching device of the plurality of high-voltage switching devices.

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