Display control method, display driver IC, and electronic device

Abstract

A display control method, a display driver IC (DDIC) (31), and an electronic device (101), relating to the field of image display, and used for implementing adaptive adjustment of the frame rate of a display screen (294) by the DDIC (31). The display control method comprises: step S1, receiving image data; step S2, in a first scanning interval in a first refresh time period scanning the display screen (294) on the basis of the image data, the first scanning interval being the minimum time for completing scanning of one image frame, and a time period after the first scanning interval in the first refresh time period being a first holding interval; step S3, sending a plurality of tearing effect (TE) signals in the first holding interval, the TE signals being used for indicating that the image data has been refreshed; and step S4, if new image data has been received in the first holding interval, restarting from the step S2.

Description

Display control method, display driver chip, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 17, 2023, with application number 202311548717.5 and invention name “Display control method, display driver chip and electronic device”, the entire contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of image display, and in particular to a display control method, a display driver chip, and an electronic device. Background Art

[0003] With the popularity of organic light-emitting diode (OLED) displays such as low-temperature polycrystalline oxide (LTPO) displays and low-temperature poly-silicon (LTPS) displays, the displays of many electronic devices support switching between different frame rates.

[0004] Traditionally, the upper layer determines the display's frame rate based on the current electronic device's application scenario, then sends a command to the display driver IC (DDIC) to set the display's frame rate. However, due to the wide variety of applications (APPs) within the application layer, it's difficult to accurately identify the application scenario, making it impossible to accurately determine the display's frame rate. Alternatively, the delay in identifying the application scenario can be excessive, resulting in delayed frame rate switching, which can cause display freezes and impact the user experience.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a display control method, a display driver chip, and an electronic device for implementing DDIC to adaptively adjust the frame rate of a display screen.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a display control method is provided, including: step S1, receiving image data; step S2, scanning the display screen according to the image data in a first scanning interval in a first refresh period; the period after the first scanning interval in the first refresh period is a first holding interval, and the first scanning interval refers to the minimum time to complete the scanning of a frame of image; step S3, sending multiple tearing effect TE signals in the first holding interval, the TE signal is used to indicate that the image data has been refreshed; step S4, if new image data is received in the first holding interval, restarting execution from step S2.

[0009] The display control method provided by the embodiment of the present application is that, in the holding interval of the refresh period, the DDIC sends multiple TE signals to the processor, instead of waiting until the refresh period ends to send the TE signal. The inverse of the period from the start of the scanning interval of the refresh period to the completion of sending any TE signal is equal to a frame rate (the frame rate is essentially also a frequency). When the processor needs the display screen to be refreshed at a certain frame rate, there is no need to directly instruct the DDIC to set the frame rate of the display screen. It is only necessary to fixedly respond to the TE signal corresponding to the frame rate and send image data to the DDIC. In other words, the DDIC provides multiple TE signals for the processor to select in a finer granularity during the holding interval of the refresh period. The processor can respond to any of the TE signals at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (that is, the frame rate expected by the processor) determines the frame rate at which the DDIC refreshes the display screen, thereby enabling the DDIC to adaptively adjust the frame rate of the display screen.

[0010] In one possible implementation, if no new image data is received during the first hold interval, the image displayed on the display screen is maintained during the first hold interval. Because the DDIC sends multiple TE signals during the first hold interval, it is possible that new image data is received during the first hold interval. If no new image data is received, the current frame is maintained, eliminating the need for frequent refreshes, thereby reducing power consumption.

[0011] In one possible implementation, the TE signal is further transmitted before the first scanning interval is about to end. At the end of the first scanning interval, the DDIC is ready to receive new image data. Upon receiving the new image data, the DDIC returns to the first scanning interval for refresh, thereby achieving the highest base frame rate (the inverse of the duration of the first scanning interval).

[0012] In one possible embodiment, if no new image data is received during the first hold interval, the process further includes: scanning the display screen based on the most recently received image data during a second scan interval in a second refresh period following the first refresh period; the period following the second scan interval in the second refresh period being a second hold interval; sending multiple TE signals during the second hold interval; and restarting execution from step S2 if new image data is received during the second hold interval. More frame rates may be selected for self-refresh.

[0013] In one possible implementation, if no new image data is received during the second hold interval, the image displayed on the display screen is maintained during the second hold interval. Because the DDIC sends multiple TE signals during the second hold interval, it is possible that new image data is received during the second hold interval. If no new image data is received, the current frame is maintained, eliminating the need for frequent refreshes, thereby reducing power consumption.

[0014] In one possible implementation, the method further includes sending a TE signal before the second scanning interval is about to end. When the first scanning interval ends, the DDIC is ready to receive new image data. When receiving new image data, the DDIC can return to the first scanning interval for refresh, thereby shortening the DDIC response time.

[0015] In one possible implementation, the difference between the duration of the second hold interval and the duration of the first hold interval is m times the period of the TE signal, where m is a positive integer. The duration of the hold interval between different refresh periods is stepped by the period of the TE signal, so that the hold interval can accommodate an integer number of TE signal periods, thereby improving the utilization of the hold interval.

[0016] In one possible implementation, the period of the TE signal is k times the period of the emission (EM) signal, where k is a positive integer. The EM signal is used to control the illumination of pixels of a display screen. That is, the frequency of the EM signal is k times the frequency of the TE signal.

[0017] In a second aspect, a display control method is provided, including: step S1, the processor sends image data to the display driver chip DDIC; step S2, the DDIC scans the display screen according to the image data in the first scanning interval in the first refresh period; the period after the first scanning interval in the first refresh period is the first holding interval; the first scanning interval refers to the minimum time to complete the scan of a frame of image; step S3, in the first holding interval, the DDIC sends multiple tearing effect TE signals to the processor, and the TE signal is used to indicate that the image data has been refreshed; step S4, the processor responds to any TE signal in the first holding interval and sends new image data to the DDIC in the first holding interval; if the DDIC receives new image data in the first holding interval, execution is restarted from step S2.

[0018] In a possible implementation, the method further includes: if the DDIC does not receive new image data within the first holding interval, holding the image displayed on the display screen within the first holding interval.

[0019] In a possible implementation, the method further includes: before the first scanning interval is about to end, the DDIC sends a TE signal to the processor.

[0020] In one possible embodiment, if the DDIC does not receive new image data within the first holding interval, the method further includes: within a second scanning interval in a second refresh period after the first refresh period, the DDIC scans the display screen according to the most recently received image data; the period after the second scanning interval in the second refresh period is a second holding interval; within the second holding interval, the DDIC sends multiple TE signals to the processor; the processor sends new image data to the DDIC within the first holding interval in response to any TE signal within the second holding interval; if the DDIC receives new image data within the second holding interval, execution is restarted from step S2.

[0021] In a possible implementation, the method further includes: if the DDIC does not receive new image data within the second holding interval, holding the image displayed on the display screen within the second holding interval.

[0022] In a possible implementation, the method further includes: before the second scanning interval is about to end, the DDIC sends a TE signal to the processor.

[0023] In a possible implementation manner, the difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer.

[0024] In a possible implementation, the period of the TE signal is k times the period of the transmitted EM signal, where k is a positive integer. The EM signal is used to control the light emission of pixels of the display screen.

[0025] In a third aspect, a display driver chip is provided, which is used to execute the method described in the first aspect and any embodiment thereof.

[0026] In a fourth aspect, an electronic device is provided, comprising a processor, a display screen, and a DDIC as described in the third aspect and any embodiment thereof, wherein the processor is configured to send image data to the DDIC; the DDIC is configured to scan the display screen according to the image data in a first scanning interval in a first refresh period; the period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time required to complete the scanning of a frame of image; the DDIC is further configured to send multiple tearing effect TE signals to the processor in the first holding interval, the TE signal being used to indicate that the image data has been refreshed; the processor is further configured to send new image data to the DDIC in the first holding interval in response to any TE signal in the first holding interval; the DDIC is further configured to return to the first scanning interval in the first refresh period if new image data is received in the first holding interval, and scan the display screen according to the new image data.

[0027] In a fifth aspect, a computer-readable storage medium is provided, comprising instructions, which, when executed on an electronic device, causes the electronic device to execute the method as described in the first aspect and any embodiment thereof, or to execute the method as described in the second aspect and any embodiment thereof.

[0028] In a sixth aspect, a computer program product comprising instructions is provided. When the instructions are executed on the above-mentioned electronic device, the electronic device executes the method as described in the first aspect and any embodiment thereof, or executes the method as described in the second aspect and any embodiment thereof.

[0029] The technical effects of the second to sixth aspects refer to the technical effects of the first aspect and any of its embodiments and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0031] FIG2 is a schematic structural diagram of a display control circuit provided in an embodiment of the present application;

[0032] FIG3 is a schematic diagram illustrating the relationship between a tearing effect (TE) signal and a frame rate of a display screen according to an embodiment of the present application;

[0033] FIG4 is a schematic diagram of a display screen refresh by row according to an embodiment of the present application;

[0034] FIG5 is a schematic diagram of a DDIC provided by an embodiment of the present application performing self-refresh in sequence according to frame rates corresponding to different sequences;

[0035] FIG6 is a schematic diagram of a software architecture provided in an embodiment of the present application;

[0036] FIG7 is a schematic diagram of switching the frame rate of a display screen provided by an embodiment of the present application;

[0037] FIG8 is a schematic diagram of a display control method provided in an embodiment of the present application;

[0038] FIG9 is a schematic diagram of a TE signal transmission frequency provided in an embodiment of the present application;

[0039] FIG10 is a schematic diagram of another TE signal transmission frequency provided in an embodiment of the present application;

[0040] FIG11 is a schematic diagram of another software architecture provided in an embodiment of the present application;

[0041] FIG12 is a schematic diagram of another display control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] First, some concepts involved in this application are described.

[0043] The terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0044] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0045] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0046] An embodiment of the present application provides an electronic device, which is an electronic device with a display screen. The electronic device can be mobile or fixed. The electronic device can be deployed on land (for example, indoors or outdoors, handheld or vehicle-mounted, etc.), on water (for example, ships, etc.), or in the air (for example, airplanes, balloons, and satellites, etc.). The electronic device can be referred to as user equipment (UE), access terminal, terminal unit, subscriber unit, terminal station, mobile station (MS), mobile station, terminal agent, or terminal device, etc. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a smart bracelet, a smart screen, a smart watch, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in self-driving, a terminal in remote medical, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, etc. The embodiments of the present application do not limit the specific type and structure of the electronic device. A possible structure of the electronic device is described below.

[0047] Taking a mobile phone as an example, FIG1 shows a possible structure of an electronic device 101. The electronic device 101 may include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, a sensor module 280, a button 290, a motor 291, an indicator 292, a camera 293, a display 294, and a subscriber identification module (SIM) card interface 295. Optionally, in some embodiments, an audio digital signal processor (ADSP) 243 is also included.

[0048] It should be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0049] The processor 210 may include one or more processing units, for example: the processor 210 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a baseband processor, and a neural-network processing unit (NPU). Among them, different processing units may be independent devices or integrated into one or more processors. For example, the processor 210 may be an application processor AP. Alternatively, the processor 210 may be integrated into a system on chip (SoC). Alternatively, the processor 210 may be integrated into an integrated circuit (IC) chip. The processor 210 may include an analog front end (AFE) and a micro-controller unit (MCU) in an IC chip.

[0050] The processor 210 executes the display control method provided in the embodiment of the present application by executing the program and computer instructions stored in the internal memory 221.

[0051] Processor 210 may also include a memory for storing computer instructions and data. In some embodiments, the memory in processor 210 is a cache memory. This memory can store computer instructions or data that have just been used or are being recycled by processor 210. If processor 210 needs to use the computer instructions or data again, it can directly access the memory. This avoids repeated accesses, reduces processor 210 latency, and thus improves system efficiency.

[0052] In some embodiments, the processor 210 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface.

[0053] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can be used to process audio signals and sensor data. When the processor is in a dormant state, the ADSP 243 can still keep working, thereby reducing the power consumption of the electronic device.

[0054] It is understood that the interface connection relationship between the modules illustrated in the embodiments of the present application is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 may also adopt a different interface connection method from the above embodiments, or a combination of multiple interface connection methods.

[0055] The wireless communication function of the electronic device 101 can be implemented through the antenna 1, the antenna 2, the mobile communication module 250, the wireless communication module 260, the modem processor, and the baseband processor.

[0056] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 101 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0057] The mobile communication module 250 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the electronic device 101. The wireless communication module 260 can provide solutions for wireless communications including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., applied to the electronic device 101. In some embodiments, the antenna 1 of the electronic device 101 is coupled to the mobile communication module 250, and the antenna 2 is coupled to the wireless communication module 260, so that the electronic device 101 can communicate with the network and other devices through wireless communication technology.

[0058] The external memory interface 220 can be used to connect an external memory card, such as a micro SanDisk (Micro SD) card, to expand the storage capacity of the electronic device 101. The external memory card communicates with the processor 210 via the external memory interface 220 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0059] The internal memory 221 can be used to store computer executable program code, which includes computer instructions. The processor 210 executes various functional applications and data processing of the electronic device 101 by running the computer instructions stored in the internal memory 221. In addition, the internal memory 221 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0060] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0061] The electronic device 101 can implement audio functions such as music playback and recording through the audio module 270 , the speaker 270A, the receiver 270B, the microphone 270C, the headphone jack 270D, and the application processor.

[0062] The audio module 270 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. In some embodiments, the audio module 270 can be set in the processor 210, or some functional modules of the audio module 270 can be set in the processor 210. The speaker 270A, also known as the "speaker", is used to convert audio electrical signals into sound signals. The receiver 270B, also known as the "earpiece", is used to convert audio electrical signals into sound signals. The microphone 270C, also known as the "microphone" or "microphone", is used to convert sound signals into electrical signals. The electronic device 101 can be provided with at least one microphone 270C. The headphone jack 270D is used to connect wired headphones. The headphone jack 270D can be a USB interface 230, or it can be a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0063] The buttons 290 include a power button, a volume button, and the like. The buttons 290 may be mechanical buttons or touch buttons. The electronic device 101 may receive button inputs and generate key signal inputs related to the user settings and function control of the electronic device 101. The motor 291 may generate vibration prompts. The motor 291 may be used for vibration prompts for incoming calls or for touch vibration feedback. The indicator 292 may be an indicator light that may be used to indicate the charging status, power level changes, messages, missed calls, notifications, and the like. The SIM card interface 295 is used to connect a SIM card. The SIM card may be connected to or disconnected from the electronic device 101 by inserting or removing the SIM card interface 295. The electronic device 101 may support one or N SIM card interfaces, where N is a positive integer greater than one. The SIM card interface 295 may support nano SIM cards, micro SIM cards, SIM cards, and the like. In some embodiments, the electronic device 101 uses an embedded SIM (eSIM) card. The eSIM card can be embedded in the electronic device 101 and cannot be separated from the electronic device 101.

[0064] The electronic device 101 can implement a camera function using an ISP, a camera 293, a video codec, a GPU, a display 294, and an application processor. The ISP is used to process data fed back by the camera 293. In some embodiments, the ISP can be provided within the camera 293. The camera 293 is used to capture still images or videos. In some embodiments, the electronic device 101 can include one or N cameras 293, where N is a positive integer greater than one.

[0065] Electronic device 101 can implement display functions through a GPU, display screen 294, and an application processor. A GPU is a microprocessor for image processing that connects display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 210 may include one or more GPUs that execute computer instructions to generate or modify display information.

[0066] The sensor module 280 may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, an angle sensor, etc. When the display screen 294 is a foldable screen, the angle sensor can detect the folding angle of the display screen 294, and the folding angle range is 0-180 degrees.

[0067] The battery 241 may include one or more batteries to power the load.

[0068] The power management module 240 is configured to receive charging input from a charger. The charger can be a wireless charger, such as a wireless charging dock or another electronic device 101 with reverse wireless charging functionality. The power management module 240 can receive wireless charging input via the electronic device's wireless charging coil 242. Alternatively, the charger can be a wired charger, for example, via the USB port 230. The power management module 240 is also referred to as a charging chip.

[0069] The power management module 240 can not only charge the battery 241 but also power the electronic device. The power management module 240 receives input from the battery 241 and provides power to the processor 210, the internal memory 221, the external memory interface 220, the display 294, the camera 293, and the wireless communication module 260. The power management module 240 can also be used to monitor parameters such as the capacity, voltage, battery cycle count, and battery health status (leakage, impedance) of the battery 241. In other embodiments, the power management module 240 can also be provided in the processor 210.

[0070] Display screen 294 is used to display images, videos, and the like. Display screen 294 includes a display panel. In some embodiments, electronic device 101 may include one or more display screens 294. The display screen involved in the embodiments of the present application may be an OLED display screen with a variable frame rate. With the popularity of OLED displays such as LTPO displays and LTPS displays, many OLED displays can support switching between different frame rates. LTPO displays, in particular, support lower frame rates, such as 120 Hz, 90 Hz, 90 Hz, 30 Hz, 10 Hz, and even a flicker-free 1 Hz frame rate. This is because OLED displays include thin film field effect transistors (TFTs) for driving pixel light. However, TFTs in LTPS displays are prone to leakage, while TFTs in LTPO displays use an indium gallium zinc oxide (InGaZnO) process. This results in minimal leakage current through the TFT after the capacitor coupled to the TFT gate is fully charged. This ensures that the voltage applied to the TFT gate remains constant for a long time, allowing the pixels driven by the TFT to remain illuminated for a long time, thereby achieving a very low frame rate.

[0071] As shown in Figure 2, display screen 294 can be connected to display driver IC (DDIC) 31 via a flexible circuit board. Processor 210 sends image data to DDIC 31 via the display serial interface (DSI). DDIC 31 then refreshes the image displayed on display screen 294 based on the image data. As shown in Figures 2 and 3, after completing the refresh of a frame of image data, DDIC 31 feeds back a frame synchronization signal—a tearing effect (TE) signal—to processor 210. The TE signal indicates that a frame of image data has been refreshed. After completing the drawing and synthesis of the next frame of image data, processor 210 does not send the next frame of image data to DDIC 31 until it receives the TE signal corresponding to the previous frame of image data. Therefore, the frequency of the TE signal varies with the frame rate of display screen 294.

[0072] The TE signal can achieve frame synchronization between the processor 210 and the DDIC 31, that is, prevent the image data sent by the processor 210 to the DDIC 31 from being synchronized with the image data refreshed by the DDIC 31 to the display screen 294, resulting in display tearing on the display screen 294 (part of the display screen 294 displays the previous frame of image, while the remaining area displays the next frame of image). As shown in Figure 4, since the display screen 294 completes the refresh of a frame of image row by row, the DDIC 31 cannot send the TE signal too early. Otherwise, it will receive new image data before completing the refresh of the previous frame of image, which will cause the above-mentioned display tearing problem. The ideal state is that after the DDIC 31 completes the refresh of the previous frame of image, it receives the image data of the next frame of image, thereby starting the refresh of the next frame of image. Therefore, the DDIC 31 can send the TE signal in advance when refreshing the last few rows of pixels of the display screen 294, so that the DDIC 31 can receive the new image data earlier.

[0073] The DDIC 31 may include a graphics random access memory (GRAM) or not. This application takes the DDIC 31 including the GRAM as an example for description, but is not intended to be limited thereto.

[0074] When DDIC 31 does not include GRAM, display screen 294 is called a video display screen. DDIC 31 cannot store image data and cannot achieve self-refresh of display screen 294. Only after processor 210 sends image data to DDIC 31 can DDIC 31 refresh the image displayed on the display screen according to the image data.

[0075] When DDIC 31 includes GRAM, the GRAM can be used to store image data, enabling self-refresh of display screen 294. In this case, display screen 294 is called a command display screen. After completing the drawing and synthesis of a frame of image data, processor 210 does not send a command to DDIC 31 until it receives a TE signal, indicating that image data will be written to the GRAM in DDIC 31, as well as the location coordinates of the image data to be written. Processor 210 then writes the image data to the GRAM in DDIC 31, and DDIC 31 reads the image data from the GRAM to refresh the image displayed on display screen 294. If processor 210 does not send new image data to DDIC 31, DDIC 31 can read the image data of the previous frame of image from the GRAM on its own and continuously refresh display screen 294 to display the previous frame of image, thereby achieving self-refresh of display screen 294.

[0076] As shown in Figure 5, in the prior art, when the processor 210 does not send new image data to the DDIC 31, the DDIC 31 continuously self-refreshes the previous frame image according to the frame rates corresponding to different sequences (essentially different refresh periods). Usually, the frame rates corresponding to different sequences can be set to different. For example, the frame rates corresponding to each sequence are gradually reduced, so that power consumption can be reduced while ensuring image smoothness. In addition, the number of repetitions can be set for each sequence, and the number of repetitions is used to indicate the number of times the self-refresh is repeated according to the frame rate corresponding to the sequence. In other words, the DDIC 31 can perform multiple self-refreshes at the same frame rate continuously. After executing each self-refresh, the DDIC 31 will send a TE signal to the processor 210.

[0077] For example, different sequences may include sequence 1 to sequence 8, etc., and the specific sequence is not limited. Taking sequence 1 to sequence 5 as an example, the frame rate of sequence 1 can be set to 120 Hz and the number of repetitions is 0 times (i.e., one self-refresh is performed at this frame rate); the frame rate of sequence 2 can be set to 60 Hz and the number of repetitions is 2 times (i.e., three self-refreshes are performed at this frame rate); the frame rate of sequence 3 can be set to 30 Hz and the number of repetitions is 2 times (i.e., three self-refreshes are performed at this frame rate); the frame rate of sequence 4 can be set to 10 Hz and the number of repetitions is 2 times (i.e., three self-refreshes are performed at this frame rate); and the frame rate of sequence 5 can be set to 1 Hz and the number of repetitions is 2 times (i.e., three self-refreshes are performed at this frame rate). In fact, the frame rates of the self-refresh of the DDIC 31 from sequence 1 to sequence 5 are: 120 Hz->60 Hz->60 Hz->60 Hz->30 Hz->30 Hz->30 Hz->10 Hz->10 Hz->10 Hz->5 Hz->5 Hz->5 Hz->1 Hz->1 Hz->1 Hz.

[0078] The time taken to complete a refresh is called a refresh period, so a sequence can include one or more refresh periods. Each refresh period includes at least a scan interval and optionally a hold interval. In the scan interval, DDIC 31 scans the display screen row by row based on the most recently received image data, that is, controls the TFTs driving the pixels to turn on row by row. The scan interval is the minimum time to complete the scan of a frame of image, and the reciprocal of the scan interval is called the basic frame rate (or base frequency), that is, no matter how the frame rate of the display screen is switched, the frame rate of the display screen will not be higher than the basic frame rate, otherwise it will not be enough time to complete the scan of a frame of image. In the hold interval, DDIC 31 maintains the image displayed on the display screen, that is, controls the TFTs driving the pixels to maintain the on state after scanning, so that the display screen continues to display the most recent frame of image.

[0079] If DDIC 31 still does not receive new image data from processor 210 after performing self-refresh in the last refresh period of the last sequence (e.g., the third refresh period of sequence 5), DDIC 31 maintains the refresh rate of the sequence (e.g., 1 Hz) to achieve self-refresh with minimal power consumption. If new image data is received from processor 210 during the self-refresh process of DDIC 31, it jumps back to the first sequence and repeats the above process.

[0080] In addition to DDIC 31 being able to control the display screen to self-refresh at a certain frame rate, the processor 210 can also control DDIC 31 to switch the frame rate of the display screen. For example, when the user performs a sliding operation on the display screen, it is desired that the frame rate of the display screen is 120hz or 90hz to avoid display freezes. When the display screen is displaying a video, it is desired that the frame rate of the display screen is 60hz or 30hz to reduce power consumption while ensuring image smoothness. When the display screen is displaying a still image, it is desired that the display screen further reduce the frame rate. For another example, when there are on-screen menu adjustment methods (on-screen display, OSD) layers such as barrage and user experience (UX) interactions in the video, it is desired that the frame rate of the display screen is 60hz; when there is no barrage or UX in the video, it is desired that the frame rate of the display screen is 30hz, and so on. The control logic for frame rate switching is relatively complex, and the frame rate of the display screen needs to be able to switch quickly.

[0081] From the perspective of the software architecture of the processor 210 , the following describes how the processor 210 executes the control logic for frame rate switching in the prior art.

[0082] From the perspective of software architecture, the program run by the processor 210 can be based on an operating system, such as Android. Apple (iOS) Windows As shown in FIG6 , the program running on the processor 210 is based on Android For example, the programs run by the processor 210 are layered according to their functions, and may include a kernel layer, a hardware abstraction layer (HAL), and an application layer.

[0083] The kernel layer includes the operating system (OS) kernel and hardware drivers for driving hardware resources, such as display drivers. The operating system kernel is used to manage the system's processes, memory, drivers, file systems, and network systems. The display driver is used to implement communication between the processor 210 and the DDIC 31. The HAL provides a set of device function interface specifications for implementing a virtual hardware platform to abstract the hardware, hide the hardware interface details, make the code hardware-independent, and be portable on multiple platforms. For example, the HAL includes a drawing rendering service (SurfaceFlinger). Among them, the drawing rendering service (SurfaceFlinger) is used to periodically render and draw image data, etc. The application layer may include APPs that need to display images, such as photo album APPs, video APPs, etc.

[0084] As shown in Figures 6 and 7, the control logic for the processor 210 to switch the frame rate of the display screen in the prior art is: the APP in the application layer of the processor 210 performs drawing and rendering to obtain image data, and sends it to the drawing and rendering service (SurfaceFlinger). The drawing and rendering service (SurfaceFlinger) identifies the application scenario of the electronic device (for example, the user performs a sliding operation on the display screen as mentioned above, or displays a video, or displays a static image), determines the frame rate of the display screen based on the identified application scenario, and sends a frame rate setting instruction and image data to the DDIC 31 through the display screen driver. The frame rate setting instruction is used to instruct the DDIC 31 to set the frame rate of the display screen. DDIC 31 sets the frame rate of the display screen according to the frame rate setting instruction. After completing the refresh of a frame image according to the image data, it sends a TE signal to the processor 210. The frequency of the TE signal is equal to the frame rate of the display screen. The display screen driver sends a vertical synchronization (VSYNC) signal to the APP through the drawing and rendering service (SurfaceFlinger). The frequency of the VSYNC signal is equal to the frequency of the TE signal, which is equal to the frame rate of the display screen. After receiving the VSYNC signal, the APP draws and renders a frame of image to obtain new image data, and sends it to the drawing and rendering service (SurfaceFlinger) to refresh the next frame of image, thereby achieving frame synchronization between the processor 210 and the DDIC 31.

[0085] However, due to the large number of application programs (APPs) in the application layer, it is difficult for the drawing rendering service (SurfaceFlinger) to accurately identify the application scenario, and thus it is unable to accurately determine the frame rate of the display. Alternatively, the delay in identifying the application scenario is too large, resulting in untimely switching of the display frame rate, which causes the display to freeze and affects the user experience.

[0086] The embodiment of the present application provides a display control method, in which the DDIC sends multiple TE signals to the processor during the hold interval of sequence 1 of self-refresh, instead of waiting until the self-refresh of the sequence is completed before sending the TE signal. The inverse of the period from the start of the scan interval of sequence 1 to the completion of sending any TE signal is equal to a frame rate (the frame rate is essentially also a frequency). When the processor needs the display to be refreshed at a certain frame rate, it is not necessary to instruct the DDIC to set the frame rate of the display. It is only necessary to send image data to the DDIC in response to the TE signal corresponding to the frame rate. In this way, the DDIC receives image data according to the frame rate (i.e., frequency), and after each image data is received, it jumps back to the scan interval of sequence 1 and scans the display according to the new image data. In other words, the DDIC provides multiple TE signals for the processor to select in a finer granularity during the hold interval of sequence 1. The processor can respond to any of the TE signals at any time to send new image data to the DDIC, and the DDIC refreshes the display in response to the received new image data. That is, the frequency at which the processor sends image data (i.e., the frame rate expected by the processor) determines the frame rate at which the DDIC refreshes the display, thereby realizing the DDIC adaptive adjustment of the frame rate of the display. As shown in FIG8 , the display control method includes:

[0087] S1. The processor sends image data to the DDIC.

[0088] Accordingly, the DDIC receives image data from the processor.

[0089] S2. In a first scanning interval of a first refresh period, the DDIC scans the display screen line by line according to the most recently received image data.

[0090] The first refresh period is Sequence 1, as described above. As shown in Figures 9 and 10, the first refresh period includes a first scan interval and a first hold interval following the first scan interval. During the first scan interval, the DDIC scans the display screen row by row based on the most recently received image data to complete a frame of image scanning. If no new image data is received during the first refresh period, the DDIC maintains the image displayed on the display screen during the first hold interval. This means that the TFTs driving the pixels remain in their post-scanning conductive state, and the display screen continues to display the most recently scanned frame of image.

[0091] The duration of the first refresh period is equal to the reciprocal of the lowest frame rate of sequence 1. For example, as shown in Figures 9 and 10, assuming that the lowest frame rate in the most common application scenario is 30 Hz, the duration of the first refresh period is equal to 33.33 ms. The duration of the first scan interval is equal to the reciprocal of the base frame rate. For example, as shown in Figures 9 and 10, assuming that the base frame rate is 120 Hz, the duration of the first scan interval is equal to 8.33 ms. For details about the base frame rate, please refer to the previous description and will not be repeated here.

[0092] S3. In the first refresh period, the DDIC sends a plurality of TE signals to the processor.

[0093] As shown in FIG9 , the DDIC can send multiple TE signals to the processor throughout the first refresh period, which can be referred to as high-frequency TE signals (e.g., a frequency of 360 Hz). Alternatively, as shown in FIG10 , the DDIC can send a TE signal A (e.g., a frequency of 120 Hz) to the processor just before the end of the first scan interval, and send multiple high-frequency TE signals (e.g., a frequency of 360 Hz) to the processor during the first hold interval, thereby forming a hybrid TE signal including different frequencies (e.g., 120 Hz and 360 Hz). The frequency of a TE signal refers to the reciprocal of the time between two adjacent TE signals.

[0094] Multiple TE signals can be sent at equal intervals, thus appearing to be periodic transmission (as shown in FIG9 ); or, multiple TE signals do not present periodic transmission or present partial periodic transmission (as shown in FIG10 ), and so on. This application takes the periodic transmission or partial periodic transmission of multiple TE signals as an example, but is not intended to be limited thereto. The period of the TE signal is k times the period of the emission (EM) signal, where k is a positive integer. For example, in FIG9 , the period of the TE signal is 1 times the period of the ordinary EM signal and 6 times the period of the high-frequency EM signal. The duration of the first holding interval is n times the period of the TE signal, where n is a positive integer. For example, in FIG9 and FIG10 , the duration of the first holding interval is 9 times the period of the TE signal.

[0095] The EM signal is used to control the on and off state of the TFTs in the OLED driver circuit, thereby controlling whether the pixels emit light. Since TFTs are typically PMOS (positive channel metal oxide semiconductor) structures, when the EM signal is high, the TFTs are turned off, preventing the TFT-driven OLED pixels from emitting light. When the EM signal is low, the TFTs are turned on, causing the TFT-driven OLED pixels to emit light.

[0096] When direct current (DC) dimming is used, the EM signal is low, and the OLED brightness is adjusted by adjusting the power of the OLED driver circuit. When pulse width modulation (PWM) dimming is used, the EM signal can be a PWM signal with a variable duty cycle, and the OLED brightness is adjusted by adjusting the duty cycle of the EM signal. For PWM dimming, since the scanning operations such as refreshing, resetting, compensating, and charging each row of OLED pixels are performed when the OLED pixels are not emitting light (i.e., the EM signal is high), the frequency of the TE signal is a multiple of the frequency of the EM signal. That is, the frequency of the EM signal is k times the frequency of the TE signal, or the period of the TE signal is k times the period of the EM signal, where k is a positive integer.

[0097] For example, assuming that the basic frame rate (the inverse of the duration of the scanning interval) mentioned above is 120 Hz, and high-frequency PWM dimming requires 18 EM signal pulses to complete the scanning of one frame of image, the frequency of the EM signal is 2160 Hz (120*18=2160 Hz), the frequency of the TE signal can be 360 ​​Hz, and the duration of the TE signal is 1 / 360=2.778 ms. The duration of each TE signal corresponds to the duration of 6 EM signals.

[0098] It should be noted that this application is not limited to the above example of a base frame rate of 120 Hz and a TE signal frequency of 360 Hz. The base frame rate and TE signal frequency can be flexibly set according to actual product requirements. For example, the base frame rate can also be 90 Hz, 144 Hz, etc., and the TE signal frequency can also be 120 Hz, 240 Hz, 360 Hz, 480 Hz, etc.

[0099] In addition, the solution shown in FIG10 has the advantage over the solution shown in FIG9 in that the solution of FIG9 enables the DDIC to receive new image data within the holding interval (e.g., the first holding interval) but not receive new image data within the scanning interval (e.g., the first scanning interval). The reason is that even if the DDIC sends a TE signal within the scanning interval, so that the DDIC receives new image data within the scanning interval, the DDIC cannot respond and refresh the image data, otherwise it will interrupt the currently ongoing scanning process, resulting in image tearing or other display anomalies. Instead, it is necessary to wait until entering the holding interval to process the above-mentioned image data. This can effectively avoid the risk of the DDIC being abnormally interrupted when scanning within the scanning interval.

[0100] S4. The processor responds to any TE signal in the first refresh period and sends new image data to the DDIC in the first refresh period. If the DDIC receives new image data in the first refresh period, it restarts from step S2 after a first preset time.

[0101] As shown in Figure 11, after DDIC 31 sends a high-frequency TE signal or a mixed TE signal to the processor 210, the display driver of the processor 210 responds to any TE signal among the multiple TE signals (for example, the most recently received TE signal) and sends a vertical synchronization (VSYNC) signal to the APP through the drawing and rendering service (SurfaceFlinger). The frequency of the VSYNC signal is equal to the frame rate at which the processor expects the display screen to refresh, such as 120hz, 90hz or 60hz. After receiving the VSYNC signal, the APP draws and renders a frame of image to obtain new image data, and after receiving the TE signal corresponding to the required frame rate, the new image data is sent to the drawing and rendering service (SurfaceFlinger), and then sent to the display driver. The display driver sends new image data to DDIC 31. DDIC can refresh the display screen according to the frequency of image data transmission. Compared with the traditional solution shown in Figure 6, the response is more timely and the performance is better.

[0102] The first preset time refers to the latest time between the following two times: the time when the image data is most recently received, and the time when the first holding interval starts.

[0103] That is, if the DDIC receives new image data during the first scanning interval, it waits for the first scanning interval to complete scanning the previous image frame, then restarts from step S2 to re-enter the first scanning interval and scan the next image frame. If the DDIC receives new image data during the first holding interval, it can directly stop holding the previous image frame and restart from step S2, i.e., re-enter the first scanning interval to scan the next image frame.

[0104] The above display control method is described below with reference to the example of FIG. 9 or FIG. 10 .

[0105] After the DDIC receives image data from the processor, it begins refreshing the display according to Sequence 1 (corresponding to the first refresh period). First, the DDIC completes scanning the display within the first scan interval and, just before the end of the first scan interval, sends a TE signal A (the frequency of this TE signal is 120 Hz) to the processor. When the processor sends image data to the DDIC in response to this TE signal A, the frequency of the processor sending image data is also 120 Hz. After TE signal A, the DDIC receives new image data from the processor, re-enters the first scan interval, and completes scanning a new frame of image. At this point, the display's frame rate adaptively becomes 120 Hz.

[0106] If the processor doesn't respond to TE Signal A from the DDIC, it periodically sends TE signals to the processor during the first hold interval. When the processor responds to TE Signal B (which has a frequency of 90 Hz) during the first hold interval and sends new image data to the DDIC, the processor actually also sends image data at a frequency of 90 Hz. After TE Signal B, the DDIC receives new image data from the processor, re-enters the first scanning interval, and completes scanning a new frame. At this point, the display's frame rate adaptively returns to 90 Hz.

[0107] Similarly, when the processor sends new image data to the DDIC in response to TE signal C (which has a frequency of 60 Hz) during the first hold interval, the processor actually also sends image data at a frequency of 60 Hz. After TE signal C, the DDIC receives new image data from the processor, re-enters the first scanning interval, and completes scanning a new frame of image. At this point, the display's frame rate adaptively returns to 60 Hz.

[0108] When the processor sends new image data to the DDIC in response to TE signal D (which has a frequency of 30 Hz) during the first hold interval, the processor actually also sends image data at a frequency of 30 Hz. After TE signal D, the DDIC receives new image data from the processor, re-enters the first scanning interval, and completes scanning a new frame of image. At this point, the display's frame rate adaptively returns to 30 Hz.

[0109] In actual use, the DDIC may continuously send TE signals at one or two frequencies, such as 360 Hz, 120 Hz, 90 Hz, 60 Hz, or 120 Hz and 360 Hz (a mixture of 120 Hz and 360 Hz). The TE signal frequency determines the maximum frequency at which the AP sends image data and the maximum frame rate at which the display refreshes—the base frame rate. The above display control method theoretically allows for adaptive frame rate adjustment from the base frame rate to a range of 1 / [(1 / base frame rate) + n*(1 / TE signal frequency)], where n refers to the duration of the first hold interval described above, which is n times the TE signal period. For example, in the example shown in Figure 9, n is 9, and the DDIC sends TE signals at 120 Hz. Therefore, the frequency range for the AP to send image data and the display's frame rate range are both: 120 Hz to 1 / [(1 / 120)+n*(1 / 360)] Hz, that is, frequencies or frame rates that are divisible by 120 Hz, such as 120 Hz, 60 Hz, 40 Hz, and 30 Hz. Similarly, if the DDIC sends TE signals at 60 Hz, the frequency range for the AP to send image data and the display's frame rate range are both: 60 Hz, 30 Hz, 20 Hz, and 10 Hz, which are divisible by 60 Hz.

[0110] Optionally, as shown in FIG12 , if the DDIC does not receive new image data within the first refresh period (including the first hold interval) corresponding to sequence 1, a subsequent sequence of self-refresh is performed. Specifically, the display control method further includes:

[0111] S5. In a second scanning interval in a second refresh period following the first refresh period, the DDIC scans the display screen according to the most recently received image data.

[0112] The second refresh period may refer to other self-refresh sequences other than sequence 1 (e.g., sequence 2 to sequence 8, etc.). Similar to the first refresh period, as shown in Figures 9 and 10, the second refresh period includes a second scanning interval and a second holding interval located after the second scanning interval. In the second scanning interval, the DDIC scans the display screen line by line based on the most recently received image data to complete the scan of one frame of image. If no new image data is received during the second refresh period, the DDIC maintains the image displayed on the display screen in the second holding interval, that is, controls the TFT that drives the pixel point to maintain the on-state after scanning, and the display screen continues to display the most recent frame of image.

[0113] The duration of each second refresh period is equal to the inverse of the minimum frame rate of the sequence corresponding to the refresh period. The minimum frame rates of each sequence can be the same or different. In particular, the minimum frame rates of each sequence can be reduced in sequence, so that the duration of the refresh period corresponding to each sequence increases in sequence. For example, the minimum frame rate of sequence 1 is 30hz, the minimum frame rate of sequence 2 is 24hz, the minimum frame rate of sequence 3 is 20hz, the minimum frame rate of sequence 4 is 15hz, the minimum frame rate of sequence 5 is 10hz, the minimum frame rate of sequence 6 is 5hz, and the minimum frame rate of sequence 7 is 1hz. At this time, the difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer.

[0114] S6. In the second refresh period, the DDIC sends multiple TE signals.

[0115] Similar to step S3, as shown in FIG9 , the DDIC may send multiple TE signals to the processor throughout the second refresh period, which may be referred to as high-frequency TE signals (e.g., a frequency of 360 Hz). Alternatively, as shown in FIG10 , the DDIC may send a TE signal (e.g., a frequency of 120 Hz) to the processor just before the end of the second scan interval, and send multiple high-frequency TE signals (e.g., a frequency of 360 Hz) to the processor during the second hold interval, thereby forming a hybrid TE signal including different frequencies (e.g., 120 Hz and 360 Hz).

[0116] The rest of step S6 is described in step S3 and will not be repeated here.

[0117] S7. The processor responds to any TE signal during the second refresh period and sends new image data to the DDIC during the second refresh period. If the DDIC receives new image data during the second refresh period, the process restarts from step S2 after a second preset time. If the DDIC does not receive new image data during the second refresh period, the process restarts from step S5.

[0118] Regarding the processor 210 sending new image data to the DDIC 31 in response to the TE signal, please refer to FIG11 for related description and will not be repeated here. The second preset time is the latest of the following two times: the time when the image data is most recently received, and the time when the second holding interval starts.

[0119] That is, if the DDIC receives new image data during the second scan interval, it waits for the second scan interval to complete scanning the previous image frame before resuming execution from step S2 to re-enter the first scan interval and scan the next image frame. If the DDIC receives new image data during the second hold interval, it can directly stop holding the previous image frame and re-start execution from step S2, i.e., re-enter the first scan interval and scan the next image frame. If the DDIC does not receive new image data during the second refresh period, it enters the next second refresh period and restarts self-refresh.

[0120] Similarly, the number of repetitions can be set for each sequence based on actual needs. For example, the number of repetitions for sequence 1 is set to 1, and the number of repetitions for sequences 2 through 7 is set to 3. Therefore, the next second refresh period can refer to the next sequence, such as entering sequence 3 from sequence 2, or the next second refresh period can refer to the same sequence, such as repeatedly entering sequence 2 according to the number of repetitions. For example, when the DDIC has not received new image data from the processor, the DDIC can self-refresh from sequence 1 to sequence 7, and the self-refresh frame rates are: 120 Hz -> 30 Hz -> 24 Hz -> 24 Hz -> 24 Hz -> 20 Hz -> 20 Hz -> 15 Hz -> 15 Hz -> 10 Hz -> 10 Hz -> 5 Hz -> 5 Hz -> 5 Hz -> 1 Hz. The DDIC then maintains the refresh rate of the last sequence (e.g., 1 Hz), thereby achieving self-refresh with the lowest power consumption. Adaptive frame rate adjustment from dynamic image refresh to static image refresh is possible.

[0121] In addition, since the DDIC sends high-frequency TE signals in the holding interval of each refresh period (i.e., sequence), it is not necessary to wait until the entire refresh period is over before sending the TE signal. Therefore, after any TE signal, the DDIC can respond to new image data from the processor and re-enter the first scanning interval at a faster speed to refresh the new image data.

[0122] The display control method provided by the embodiment of the present application is that, in the holding interval of the refresh period, the DDIC sends multiple TE signals to the processor, instead of waiting until the refresh period ends to send the TE signal. The inverse of the period from the start of the scanning interval of the refresh period to the completion of sending any TE signal is equal to a frame rate (the frame rate is essentially also a frequency). When the processor needs the display screen to be refreshed at a certain frame rate, there is no need to directly instruct the DDIC to set the frame rate of the display screen. It is only necessary to fixedly respond to the TE signal corresponding to the frame rate and send image data to the DDIC. In other words, the DDIC provides multiple TE signals for the processor to select in a finer granularity during the holding interval of the refresh period. The processor can respond to any of the TE signals at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (that is, the frame rate expected by the processor) determines the frame rate at which the DDIC refreshes the display screen, thereby enabling the DDIC to adaptively adjust the frame rate of the display screen.

[0123] An embodiment of the present application also provides a computer-readable storage medium, which includes instructions. When the instructions are executed on the above-mentioned electronic device, the electronic device executes the various steps in the above-mentioned method embodiment, such as executing the method shown in Figures 8 and 12.

[0124] An embodiment of the present application also provides a computer program product including instructions. When the instructions are executed on the above-mentioned electronic device, the electronic device executes the various steps in the above-mentioned method embodiment, for example, executes the method shown in Figures 8 and 12.

[0125] Regarding the technical effects of the computer-readable storage medium and the computer program product, refer to the technical effects of the previous method embodiments.

[0126] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0127] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0129] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0130] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0131] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0132] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0133] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display control method, characterized in that: include: Step S1, receiving image data; Step S2, scanning the display screen according to the image data in a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time to complete the scanning of one frame of image; Step S3: In the first holding interval, a plurality of tearing effect TE signals are sent, where the TE signals are used to indicate that the image data has been refreshed; Step S4: If new image data is received within the first holding interval, restart the process from step S2.

2. The method according to claim 1, characterized in that Also includes: If no new image data is received during the first holding interval, the image displayed on the display screen is held during the first holding interval.

3. The method according to claim 1 or 2, characterized in that: Also includes: Before the first scanning interval is about to end, a TE signal is sent.

4. The method according to any one of claims 1 to 3, characterized in that: If no new image data is received within the first holding interval, the method further includes: In a second scanning interval in a second refresh period after the first refresh period, the display screen is scanned according to the most recently received image data; the period after the second scanning interval in the second refresh period is a second holding interval; In the second holding interval, sending a plurality of the TE signals; If new image data is received within the second holding interval, the process restarts from step S2.

5. The method according to claim 4, characterized in that Also includes: If no new image data is received during the second holding interval, the image displayed on the display screen is held during the second holding interval.

6. The method according to claim 4 or 5, characterized in that: Also includes: Before the second scanning interval ends, a TE signal is sent.

7. The method according to any one of claims 4 to 6, characterized in that: The difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer.

8. The method according to any one of claims 1 to 7, characterized in that: The period of the TE signal is k times the period of the emitted EM signal, where k is a positive integer. The EM signal is used to control the light emission of pixels of the display screen.

9. A display control method, characterized in that: include: Step S1, the processor sends image data to the display driver chip DDIC; Step S2, the DDIC scans the display screen according to the image data in a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time to complete the scanning of one frame of image; Step S3: within the first holding interval, the DDIC sends a plurality of tearing effect TE signals to the processor, where the TE signals are used to indicate that image data has been refreshed; Step S4: The processor responds to any TE signal in the first holding interval, If the DDIC receives new image data within the first holding interval, the process restarts from step S2.

10. The method according to claim 9, characterized in that Also includes: If the DDIC does not receive new image data within the first holding interval, the image displayed on the display screen is held within the first holding interval.

11. The method according to claim 9 or 10, characterized in that: Also includes: Before the first scanning interval is about to end, the DDIC sends a TE signal to the processor.

12. The method according to any one of claims 9 to 11, characterized in that: If the DDIC does not receive new image data within the first holding interval, the method further includes: In a second scanning interval in a second refresh period after the first refresh period, the DDIC scans the display screen according to the most recently received image data; the period after the second scanning interval in the second refresh period is a second holding interval; In the second holding interval, the DDIC sends a plurality of TE signals to the processor; The processor sends new image data to the DDIC in the first holding interval in response to any TE signal in the second holding interval; if the DDIC receives new image data in the second holding interval, execution is restarted from step S2.

13. The method according to claim 12, characterized in that Also includes: If the DDIC does not receive new image data in the second holding interval, the image displayed on the display screen is held in the second holding interval.

14. The method according to claim 12 or 13, characterized in that Also includes: Before the second scanning interval is about to end, the DDIC sends a TE signal to the processor.

15. The method according to any one of claims 12 to 14, characterized in that: The difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer.

16. The method according to any one of claims 9 to 15, characterized in that: The period of the TE signal is k times the period of the emitted EM signal, where k is a positive integer. The EM signal is used to control the light emission of pixels of the display screen.

17. A display driver chip, characterized in that: The display driver chip is used to execute the method according to any one of claims 1 to 8.

18. An electronic device, characterized in that: It comprises a processor, a display screen and a display driver chip DDIC as claimed in claim 17; The processor is used to send image data to the DDIC; The DDIC is used to scan the display screen according to the image data in a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time to complete the scanning of one frame of image; The DDIC is further used to send a plurality of tearing effect TE signals to the processor within the first holding interval, wherein the TE signals are used to indicate that the image data has been refreshed; The processor is further configured to send new image data to the DDIC in the first holding interval in response to any TE signal in the first holding interval; The DDIC is also used to return to the first holding interval if new image data is received within the first holding interval. In the first scanning interval of the first refresh period, the display screen is scanned according to new image data.

19. A computer-readable storage medium, characterized in that: The method comprises instructions, which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 1 to 8, or to execute the method according to any one of claims 9 to 16.

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