Method for manufacturing semiconductor device, and semiconductor process apparatus

Abstract

Disclosed in the present application are a method for manufacturing a semiconductor device, and a semiconductor process apparatus. The method comprises: modifying a roughened layer by using a first process gas, so as to reduce the surface roughness of the roughened layer, wherein the first process gas comprises a chemical etching gas capable of reacting with the roughened layer, and a physical-bombardment gas capable of physically bombarding the roughened layer, the proportion of the physical-bombardment gas in the first process gas being greater than the proportion of the chemical etching gas in the first process gas; and etching the modified roughened layer, a second-conductive-type semiconductor layer, an active layer and a first-conductive-type semiconductor layer to a target depth by using a second process gas. The present application can reduce the loading effect of etching byproducts on a roughened surface on an etching process, thus improving the luminance and electrical stability of chips.

Description

Method for manufacturing semiconductor device and semiconductor process equipment TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, more particularly, relates to a method for manufacturing semiconductor device and semiconductor process equipment. BACKGROUND

[0002] At present, in order to prepare high-brightness LED chips, the industry often uses the scheme of directly increasing current to improve brightness; however, for the chip, as the loading current increases, the LED chip will overheat and age, affecting the service life. With the development and improvement of technology, it is necessary to optimize the process flow on the high-brightness LED improvement scheme, among which, the mainstream process technology will adopt roughening process treatment on the chip, on the one hand, the surface of the roughening treatment can increase the escape opportunity of photons; on the other hand, it can increase the light passing through multiple refractions into the critical angle beyond the critical incident angle, thereby improving the brightness performance of the device. For the roughening process of red and yellow light AlGaInP (aluminum gallium indium phosphide), adopting roughening treatment first and then etching process sequence can not only reduce the process sequence, but also ensure the side wall morphology on the basis of brightness improvement, reduce the side wall damage, and improve the electrical stability of the device. However, by using this roughening process sequence, in the etching process, due to the roughening and etching of the top roughening surface, the area of the top roughening surface increases, and the top is loose and porous, the etched side wall is rough, which seriously affects the electrical performance and light emitting effect of the device; secondly, for the red and yellow light etching process, the by-product corresponding to In and Al elements has high volatilization temperature and is difficult to volatilize; in particular, as the loading increases, the by-product is more difficult to desorb on the sample surface, thereby producing mask-like substances and gradually producing "black spots" (protrusions) on the etched side wall and bottom during the etching process, resulting in the risk of electric leakage during packaging. Therefore, how to realize an etching process of roughened surface red and yellow light AlGaInP is the key to improve the performance of LED chips.

[0003] SUMMARY

[0004] The purpose of the present application is to provide a method for manufacturing semiconductor device and semiconductor process equipment, which can reduce the influence of etching by-products on the roughened surface on the etching load, and improve the brightness and electrical stability of the chip.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present application provides a method for manufacturing semiconductor device, the semiconductor device comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer stacked from bottom to top, the surface of the second conductive type semiconductor layer having a roughened layer, the method comprising:

[0006] The roughened layer is modified by a first process gas to reduce the surface roughness of the roughened layer, the first process gas comprising a chemical etching gas capable of reacting with the roughened layer and a physical bombardment gas capable of physically bombarding the roughened layer, a proportion of the physical bombardment gas in the first process gas being greater than a proportion of the chemical etching gas in the first process gas;

[0007] The modified roughened layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer are etched to a target depth by a second process gas.

[0008] In some embodiments, the roughened layer comprises In element and / or Al element.

[0009] In some embodiments, the material of the roughened layer comprises AlGaInP.

[0010] In some embodiments, in the first process gas, a gas flow ratio of the physical bombardment gas to the chemical etching gas ranges from 5:1 to 20:1; or

[0011] A flow rate of the physical bombardment gas ranges from 25 sccm to 200 sccm, and a flow rate of the chemical etching gas ranges from 5 sccm to 40 sccm; or

[0012] In the first process gas, a total flow rate of the physical bombardment gas and the chemical etching gas ranges from 30 sccm to 240 sccm; or

[0013] In the step of etching the roughened layer by the first process gas, a pressure of a process chamber ranges from 2 mT to 8 mT.

[0014] In some embodiments, in the step of etching the roughened layer by the first process gas, the process parameters further comprise:

[0015] An upper electrode radio frequency power ranges from 300 W to 800 W;

[0016] A lower electrode radio frequency power ranges from 50 W to 300 W;

[0017] A process temperature ranges from 120℃ to 150℃;

[0018] A process time ranges from 10 s to 60 s.

[0019] In some embodiments, the chemical etching gas comprises Cl2, and the physical bombardment gas comprises Ar.

[0020] In some embodiments, the materials of the roughening layer, the first conductive type semiconductor layer and the second conductive type semiconductor layer are the same.

[0021] In some embodiments, the second process gas comprises Cl2, BCl3 and HBr.

[0022] In some embodiments, the gas flow ratio of Cl2, BCl3 and HBr in the second process gas ranges from 1:2:5 to 1:2:20; or

[0023] The flow rate of Cl2 in the second process gas ranges from 5sccm to 20sccm, the flow rate of BCl3 ranges from 20sccm to 40sccm, and the flow rate of HBr ranges from 25sccm to 100sccm; or

[0024] The chamber pressure ranges from 2mT to 6mT; or

[0025] In the step of continuing to etch the roughening layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer to a target depth by using the second process gas, the upper electrode radio frequency power ranges from 400W to 900W, and the lower electrode radio frequency power ranges from 200W to 450W.

[0026] In a second aspect, the present application provides a semiconductor process equipment, comprising a process chamber, a gas inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, the controller comprising at least one processor and at least one memory, the memory storing a computer program, the computer program being executed by the processor to implement the manufacturing method of the semiconductor device in the first aspect.

[0027] The present application has the following beneficial effects:

[0028] The etching method of the present application first uses a first process gas containing a chemical etching gas and a physical bombardment gas to modify the roughened layer, that is, to reduce the surface roughness of the roughened layer through the chemical etching effect of the chemical etching gas and the physical bombardment effect of the physical bombardment gas, and by making the proportion of the physical bombardment gas in the first process gas greater than the proportion of the chemical etching gas in the first process gas, on the one hand, the physical bombardment characteristics of the ions in the physical bombardment gas are used to ion bombard the roughened surface of the roughened layer to reduce the surface roughness; on the other hand, the use of a relatively small amount of chemical etching gas not only can adjust the bombardment effect, but also can increase the chemical etching of the roughened surface, further reduce the surface roughness of the roughened layer, and at the same time can etch the debris ionized by the ion bombardment to reduce the protrusion of the subsequent etching surface. Thus, the present application can reduce the load effect of the etching by-products of the roughened surface, reduce the protrusion of the subsequent etching surface, and in the subsequent process of etching to the target depth using the second process gas, since the modification process reduces the etching load of the roughened surface, a smoother etching morphology can be obtained, thereby improving the chip brightness and electrical stability.

[0029] The system of the present application has other characteristics and advantages, which will be apparent or will be described in detail in the drawings incorporated herein and the subsequent specific embodiments, which together serve to explain the specific principles of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description of exemplary embodiments of the present application taken in conjunction with the accompanying drawings, in which like reference characters refer to the like parts throughout the different views.

[0031] FIG. 1 shows a semiconductor device schematic diagram corresponding to each step of the conventional red-yellow light AlGaInP roughened surface etching process flow.

[0032] FIG. 2 shows an electron microscope image of the etching result of a related art AlGaInP roughened surface etching method.

[0033] FIG. 3 shows an electron microscope image of the etching result of a related art AlGaInP roughened surface etching method.

[0034] FIG. 4 shows a step diagram of a semiconductor device manufacturing method according to an embodiment of the present application.

[0035] FIGS. 5a-5c respectively show a semiconductor device schematic diagram corresponding to each step of a semiconductor device manufacturing method according to an embodiment of the present application.

[0036] FIG. 6 shows an electron microscope image of etching results of a semiconductor device manufacturing method according to an embodiment of the present application.

[0037] FIG. 7 shows a schematic diagram of a semiconductor processing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] A conventional red-yellow light AlGaInP roughening etching process flow is shown in FIG. 1. First, an AlGaInP epitaxial wafer is provided, which includes a GaAs layer, a first AlGaInP layer (AlGaInP1), a multi-quantum well layer (MQW), a second AlGaInP layer (AlGaInP2), and a GaP layer, and then new substrate bonding is performed. Specifically, a sapphire substrate (Al2O3) or a silicon substrate (Si substrate) is bonded to the GaP layer through a bonding layer (Bonding layer), and then the original substrate is peeled off, the GaAs layer is removed, and then the surface of the first AlGaInP layer on the epitaxial wafer is subjected to a full-surface roughening treatment. Then, a photoresist layer (PR) is formed on the roughened surface and is patterned, and then the film layer of the cutting path region exposed by the photoresist is etched to a target depth directly by one-step etching.

[0039] The BCl3+Cl2 system etching gas used in the related art is used for AlGaInP etching. For red-yellow light AlGaInP material etching, one-step etching is usually used, and if it is paused, the by-products produced are difficult to volatilize, which has a great impact on the surface morphology. A typical AlGaInP etching formula is: 1.5-5mT / SRF400-1500 / BRF50-500 / 10-150Cl2+5-50BCl3 / 4-8Tback He / 20-80℃chiller. Specifically, the chamber pressure ranges from 1.5mT to 5mT; the upper electrode radio frequency power ranges from 400W to 1500W; the lower electrode radio frequency power ranges from 50W to 500W; the gas flow rate of Cl2 ranges from 10sccm to 150sccm; the gas flow rate of BCl3 ranges from 5sccm to 50sccm; the back blowing gas (He) pressure ranges from 4Torr to 8Torr; and the temperature of the chiller ranges from 20℃ to 80℃. After etching using this formula, the sidewall and bottom are rough, as shown in FIG. 2.

[0040] The related art two generally uses Cl2+BCl3+HBr system gas to perform one-step AlGaInP etching. For red and yellow AlGaInP material etching, one-step etching is also used. If the process is paused, the generated by-products are difficult to volatilize, and have a great impact on the surface morphology. A typical AlGaInP etching formula is: 1.5-5mT / SRF300-1000 / BRF150-500 / 5~50Cl2+5~50BCl3+5~100HBr / 4~8Tback He / 0~80℃chiller. Specifically, the chamber pressure range is 1.5mT~5mT; the upper electrode radio frequency power range is 300W~1000W; the lower electrode radio frequency power range is 150W~500W; the Cl2gas flow range is 5sccm~50sccm; the BCl3gas flow range is 5sccm~50sccm; the HBr gas flow range is 5sccm~100sccm; the back gas (He) pressure is 4Torr~8Torr; and the temperature range of the temperature control system (chiller) is 0℃~80℃. After etching using the formula, the bottom morphology is abnormally raised and has high density, the top part is damaged, and the etching morphology cannot be guaranteed. The etching result is shown in FIG. 3.

[0041] The application provides a semiconductor device manufacturing method and a semiconductor process equipment, which can reduce the load effect of surface roughness of the roughening layer, and improve the brightness and electrical stability of the chip.

[0042] The application will be described in more detail below with reference to the drawings. Although the preferred embodiments of the application are shown in the drawings, it should be understood that the application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the application more thorough and complete, and to fully convey the scope of the application to those skilled in the art.

[0043] Embodiment 1

[0044] As shown in FIGS. 4 and 5a, the embodiment provides a semiconductor device manufacturing method, which includes a first conductive type semiconductor layer 4, an active layer 5, and a second conductive type semiconductor layer 6 stacked from bottom to top, and the second conductive type semiconductor layer 6 has a roughening layer 7 on the surface. It should be noted that from bottom to top refers to the direction away from the substrate layer 1.

[0045] The method includes the following steps:

[0046] S1: modifying the roughened layer 7 by using a first process gas to reduce the surface roughness of the roughened layer 7, the first process gas including a chemical etching gas capable of reacting with the roughened layer 7 and a physical bombardment gas capable of physically bombarding the roughened layer 7, the proportion of the physical bombardment gas in the first process gas being greater than the proportion of the chemical etching gas in the first process gas;

[0047] In some embodiments, the roughened layer 7 includes In element and / or Al element. In this embodiment, the material of the roughened layer 7 includes AlGaInP, the materials of the roughened layer 7, the first conductive type semiconductor layer 4 and the second conductive type semiconductor layer 6 are the same; and the active layer 5 is a multi-quantum well layer.

[0048] Specifically, as shown in FIG. 5a, the semiconductor device of the embodiment includes, from bottom to top, a substrate layer 1, a bonding layer 2, a GaP layer 3, a first conductive type semiconductor layer 4 of AlGaInP material, an active layer 5 (a multi-quantum well layer), a second conductive type semiconductor layer 6 of AlGaInP material, and a patterned photoresist layer 8, wherein the substrate layer 1 is a sapphire substrate or a silicon substrate. The second conductive type semiconductor layer 6 has a roughened layer 7 on the surface thereof, and the patterned photoresist layer 8 exposes a part of the second conductive type semiconductor layer 6. The roughened layer 7 is formed by roughening the surface of the second conductive type semiconductor layer 6.

[0049] In a specific embodiment, the method for preparing the semiconductor device includes:

[0050] The red-yellow light AlGaInP epitaxial wafer includes a GaP layer 3, a first conductive type semiconductor layer 4, an active layer 5, a second conductive type semiconductor layer 6 and a GaAs substrate (not shown). The red-yellow light AlGaInP epitaxial wafer is bonded to a new substrate by using a bonding technology, and the new substrate is the substrate layer 1 shown in FIG. 5a. The substrate layer 1 is typically a sapphire (Al2O3) or a Si substrate, and is usually a Si substrate.

[0051] The original GaAs substrate on the epitaxial wafer after the transfer of the substrate is laser peeled to separate the original GaAs substrate from the second conductive type semiconductor layer 6.

[0052] Then, a wet etching process is used to roughen the surface of the second conductive type semiconductor layer 6 on the surface to form a roughened layer 7. Depending on the roughening process, the surface roughness of the typical roughened layer 7 is in the range of 300 nm to 1200 nm (the surface roughness is represented by the roughening depth, and the roughening depth that is too shallow or too deep will affect the light emission effect).

[0053] Based on the above-mentioned surface-roughened semiconductor device, a photoresist mask layer 8 is formed, and photoetching is performed for etching preparation.

[0054] Then, the step S1 is performed, i.e., before the step S1 is performed, the roughened layer 7 with a certain surface roughness range has been obtained on the surface of the second-conductivity-type semiconductor layer 6 by the roughening treatment, and the step S1 is performed to modify the roughened layer 7 with a certain surface roughness range, and the surface roughness of the roughened layer 7 has been reduced.

[0055] The step S1 is performed to modify the roughened layer 7 by using the first process gas to reduce the surface roughness of the roughened layer 7. In the first process gas used, the chemical etching gas includes Cl2, and the physical bombardment gas includes Ar, i.e., the first process gas uses a combination of Cl2 and Ar.

[0056] In some embodiments, the proportion of the physical bombardment gas in the first process gas is greater than the proportion of the chemical etching gas in the first process gas.

[0057] The etching method of the present application first uses the first process gas containing the chemical etching gas and the physical bombardment gas to modify the roughened layer, i.e., the surface roughness of the roughened layer is reduced by the chemical etching effect of the chemical etching gas and the physical bombardment effect of the physical bombardment gas, and by making the proportion of the physical bombardment gas in the first process gas greater than the proportion of the chemical etching gas in the first process gas, on the one hand, the physical bombardment characteristics of the ions in the physical bombardment gas are used to bombard the roughened surface of the roughened layer to reduce the surface roughness, and on the other hand, a relatively small amount of chemical etching gas is used at the same time, which not only can adjust the bombardment effect, but also can increase the chemical etching of the roughened surface to further reduce the surface roughness of the roughened layer, and at the same time, the etching of the debris caused by the ion bombardment can be performed to reduce the generation of protrusions on the surface of the subsequent etching. Thus, the present application can reduce the load effect caused by the etching by-products of the roughened surface, reduce the generation of protrusions on the surface of the subsequent etching, and in the process of continuing to etch to the target depth by using the second process gas, since the etching load of the surface of the roughened layer is reduced by the modification treatment, a smoother etching morphology can be obtained, thereby improving the chip brightness and electrical stability.

[0058] On this basis, in some embodiments, the gas flow ratio of the physical bombardment gas (e.g., Ar) to the chemical etching gas (e.g., Cl2) in the first process gas ranges from 5:1 to 20:1. The gas flow ratio range is used to adjust the bombardment effect.

[0059] In some embodiments, the flow rate of the physical bombardment gas (e.g., Ar) ranges from 25 sccm to 200 sccm, and the flow rate of the chemical etching gas (e.g., Cl2) ranges from 5 sccm to 40 sccm.

[0060] In some embodiments, the total flow rate of the physical bombardment gas (e.g., Ar) and the chemical etching gas (e.g., Cl2) ranges from 30 seem to 240 seem.

[0061] In some embodiments, the pressure of the process chamber in the step S1 of etching the roughening layer 7 using the first process gas ranges from 2 mT to 8 mT.

[0062] In some embodiments, the process parameters used in the step S1 also include: the upper electrode radio frequency power ranges from 300 W to 800 W; the lower electrode radio frequency power ranges from 50 W to 300 W; the process temperature ranges from 120 °C to 150 °C; and the process time ranges from 10 s to 60 s.

[0063] The step S1 is a pre-processing step of the main etching step. In the implementation process, a physical bombardment gas (e.g., Ar) and a chemical etching gas (e.g., Cl2) are introduced into the process chamber of an inductively coupled plasma (ICP) device, wherein the flow rate ratio of the physical bombardment gas (e.g., Ar) and the chemical etching gas (e.g., Cl2) ranges from 5:1 to 20:1, which is mainly used to adjust the bombardment effect. A certain chamber pressure is maintained, and the pressure of the process chamber is selected as a fixed value between 2 mT and 8 mT. The gas in the process chamber is ionized to generate plasma by applying a certain upper electrode radio frequency power, and the upper electrode radio frequency power ranges from 300 W to 800 W. The plasma is accelerated downward to bombard and etch the surface of the roughening layer 7 by applying a certain lower electrode radio frequency power, and the lower radio frequency power ranges from 50 W to 300 W. The wafer (i.e., a semiconductor device) is placed on a quartz or SiC carrier plate, and a certain pressure of back-blowing gas (He) is introduced below the carrier plate for cooling the carrier plate and improving the uniformity of the carrier plate temperature. Conduction heat dissipation is performed to control the wafer surface temperature (i.e., the process temperature) above 120 °C without glue, for example, from 120 °C to 150 °C. The wafer surface temperature is determined by the radio frequency power (including the upper electrode radio frequency power and the lower electrode radio frequency power) in the process recipe and the chiller. Generally, after the radio frequency power in the process recipe is selected, the wafer surface temperature is basically determined in a certain range. The process time ranges from 10 s to 60 s, which is determined by the surface roughening thickness of the roughening layer 7 and the etching rate.

[0064] The chemical reaction formula involved in the etching process of the step S1 is as follows:

[0065] Ar→Ar + +e;

[0066] Cl2→Cl - +Cl*+e;

[0067] AlGaInP (bulk material) + Ar + + e→ AlGaInP↑ (molecule) + Ar (physical bombardment);

[0068] AlGaInP + Cl - → GaCl3↑ + AlCl3↑ + InCl3↑ + PCly↑ (y = 3, 5) (chemical etching);

[0069] This step S1 uses Cl2 + Ar gas system to etch the area of the roughening layer 7 surface without photoresist mask covering, and the roughening surface of other areas of the roughening layer 7 is not damaged due to the protection of the photoresist mask; in this step S1, the roughening surface of the roughening layer 7 without mask covering is mainly subjected to Ar + ion bombardment under suitable power conditions and the physical bombardment characteristics of Ar ions, so as to reduce the surface roughness; it is easy to understand that this step S1 is to modify the roughening layer 7 with a certain surface roughness range, and under the premise that the roughening layer 7 itself has a certain surface roughness, the roughening surface of the roughening layer 7 is subjected to Ar + ion bombardment, so as to reduce the surface roughness of the roughening layer 7. On the contrary, when Ar + ions are used to bombard the smooth surface, the surface roughness will be increased.

[0070] Secondly, in this process, a small amount of Cl2 is used, which can adjust the bombardment effect on one hand, and the small amount of Cl radicals can also increase the chemical etching of the roughening surface, further reducing the surface roughness of the roughening layer 7; in particular, the Cl radicals can also etch the debris bombarded by part of the Ar+ ions, reducing the protrusions on the subsequent etching surface.

[0071] It should be noted that the physical bombardment by Ar + ions is the main etching part, and most of the AlGaInP on the roughening surface of the roughening layer 7 will be bombarded by Ar + ions, but since the roughening surface of the roughening layer 7 is in a honeycomb shape (as shown in the roughening surface morphology of FIG. 6), there are many holes, so part of the small particles bombarded will be stuck at the bottom or sidewall of the roughening surface, at this time, the bombardment of Ar + ions cannot directly act, but only through chemical etching by Cl radicals, and as the etching proceeds, the etching temperature gradually rises, and a small amount of AlClx and InClx and other by-products produced by chemical etching gradually volatilize, thereby also reducing the production of micro-masks in the subsequent etching process, reducing the protrusions on the subsequent etching surface.

[0072] The process recipe of the present step S1 is for example: Pressure (chamber pressure) 2mT~8mT / SRF (upper electrode RF power) 300W~800W / BRF (lower electrode RF power) 50W~300W / 25sccm~200sccm Ar+5sccm~40sccm Cl2 / 4Torr~8Torr back He / chiller (chuck) temperature 0°C~70°C / process time 10s~60s (time can be adjusted according to roughening depth). The film structure after the present step S1 is completed is shown in FIG. 5b.

[0073] S2: etching the modified roughened layer 7, the second conductive type semiconductor layer 6, the active layer 5 and the first conductive type semiconductor layer 4 to a target depth by using a second process gas;

[0074] In the present step S2, the second process gas includes Cl2, BCl3 and HBr. In some embodiments, the gas flow ratio of Cl2, BCl3 and HBr in the second process gas ranges from 1:2:5 to 1:2:20.

[0075] In some embodiments, the flow rate of Cl2 ranges from 5sccm to 20sccm, the flow rate of BCl3 ranges from 20sccm to 40sccm, and the flow rate of HBr ranges from 25sccm to 100sccm.

[0076] In some embodiments, the upper electrode RF power ranges from 400W to 900W, and the lower electrode RF power ranges from 200W to 450W.

[0077] In some embodiments, the chamber pressure ranges from 2mT to 6mT.

[0078] In some embodiments, the process parameters used in the present step S2 further include: the upper electrode RF power ranges from 400W to 900W; the lower electrode RF power ranges from 200W to 450W; the process temperature ranges from 120°C to 150°C; and the process time ranges from 300s to 700s.

[0079] The step S2 is a main etching step. In the implementation process, after the first step etching (i.e., the pretreatment step) is completed, the main etching step is switched to directly perform the second step etching. In the etching process of the step S2, since the surface roughness of the roughening layer 7 is optimized, the Cl2+BCl3+HBr system is used for etching according to the smooth side wall morphology requirement. However, because the by-products of the AlGaInP material are difficult to volatilize, the etching gas and the radio frequency power in the process formula need to be controlled within a certain range to avoid affecting the electrical properties. Therefore, after the step S1 is completed, the Cl2, BCl3 and HBr gases are introduced into the process chamber, wherein the gas flow ratio of Cl2:BCl3:HBr ranges from 1:2:5 to 1:2:20. A certain chamber pressure is maintained, and the chamber pressure is selected to be a fixed value within the range of 2 mT to 6 mT. The gas in the process chamber is ionized to generate plasma by applying a certain upper electrode radio frequency power, and the upper electrode radio frequency power is selected within the range of 400 W to 900 W. Then, a certain lower electrode radio frequency power is applied to accelerate the plasma to bombard the material surface downward for etching, and the lower electrode radio frequency power is selected within the range of 200 W to 450 W. The wafer (i.e., the semiconductor device) is placed on a quartz or SiC carrier disc, a certain pressure of back blowing gas (He) is introduced below the carrier disc for cooling the carrier disc and improving the uniformity of the carrier disc temperature, conduction heat dissipation is performed, the wafer surface temperature above the carrier disc (i.e., the process temperature) is controlled to be above 120°C without glue, and the process time ranges from 300 s to 700 s.

[0080] The process formula of the step S2 is, for example, as follows: Pressure (chamber pressure) 2 mT to 6 mT / SRF (upper electrode radio frequency power) 400 W to 900 W / BRF (lower electrode radio frequency power) 200 W to 450 W / 5 sccm to 20 sccm Cl2+20 sccm to 40 sccm BCl3+25 sccm to 100 sccm HBr / 4 Torr back He / chiller (carrier disc) temperature 0°C to 70°C / process time 300 s to 700 s (which can be adjusted according to different etching depths or etching formulas). The film layer structure after the step S2 is completed is shown in FIG. 5c.

[0081] The etching result obtained by combining the process formulas of the steps S1 and S2 is shown in FIG. 6. It can be seen that the etching morphology of the semiconductor device obtained by the manufacturing method of the embodiment has a smooth bottom and side wall etching, thereby effectively improving the chip brightness and electrical stability.

[0082] It should be noted that the embodiment is exemplarily described by taking the roughened layer 7 of AlGaInP material as an example, and the method of the application is also applicable to etching of a roughened layer containing In element or Al element. Correspondingly, for roughened layers 7 of other different materials or first conductive type semiconductor layers 4, active layers 5 and second conductive type semiconductor layers 6 of other different materials, other corresponding first process gas and second process gas can be selected and replaced according to the requirement of the etching effect of the application.

[0083] Embodiment 2

[0084] Fig. 7 shows a structural schematic diagram of a semiconductor process equipment according to an embodiment of the application.

[0085] As shown in Fig. 7, the semiconductor process equipment 200 includes a process chamber 20, a gas inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C and a controller (not shown in Fig. 7). The controller includes at least one processor and at least one memory having a computer program stored therein, and the computer program is executed by the processor to implement the method for manufacturing the semiconductor device according to any one of the above embodiments.

[0086] Exemplarily, the controller can be an upper computer or a lower computer. The controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the interior of the process chamber 20, and can control the opening degree of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the evacuation of the interior of the process chamber 20 by the evacuation assembly to control the pressure (i.e. chamber pressure) in the interior of the process chamber 20 and to discharge the reaction by-products, etc.

[0087] The upper electrode assembly 20B includes a radio frequency coil 21, an upper radio frequency power supply 23 and an upper matching device 25. The controller is further configured to control the upper radio frequency power supply 23 to provide upper electrode radio frequency power to the radio frequency coil 21 through the upper matching device 25, so that the radio frequency coil 21 excites the process gas in the interior of the process chamber 20 to generate plasma 100.

[0088] The lower electrode assembly 20C includes a wafer supporting device 22, a lower radio frequency power supply 24 and a lower matching device 26. The controller is further configured to control the lower radio frequency power supply 24 to provide lower electrode radio frequency power to the lower electrode of the wafer supporting device 22 through the lower matching device 26, so that the lower electrode of the wafer supporting device 22 provides radio frequency bias to attract the plasma above the object to be etched (e.g. wafer) to bombard the object to be etched.

[0089] The semiconductor process equipment 200 of the embodiments of the present application can be an inductive coupled plasma (ICP) etching equipment, or can be a capacitively coupled plasma (CCP) etching equipment. The embodiments of the present application do not limit the type of the semiconductor process equipment 200.

[0090] The above has described the embodiments of the present application, the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for manufacturing a semiconductor device, wherein the semiconductor device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked from bottom to top, wherein the second conductive type semiconductor layer has a roughened layer on its surface, wherein: The method comprises: Modifying the roughening layer using a first process gas to reduce the surface roughness of the roughening layer, the first process gas comprising a chemical etching gas capable of reacting with the roughening layer and a physical bombardment gas capable of physically bombarding the roughening layer, wherein a proportion of the physical bombardment gas in the first process gas is greater than a proportion of the chemical etching gas in the first process gas; The modified roughening layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer are etched to a target depth using a second process gas.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The roughened layer includes In element and / or Al element.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The material of the roughening layer includes AlGaInP.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: In the first process gas, the gas flow ratio of the physical bombardment gas to the chemical etching gas is in a range of 5:1 to 20:1; or The flow rate of the physical bombardment gas is in the range of 25 sccm to 200 sccm, and the flow rate of the chemical etching gas is in the range of 5 sccm to 40 sccm; or In the first process gas, the total gas flow rate of the physical bombardment gas and the chemical etching gas is in the range of 30 sccm to 240 sccm; or In the step of etching the roughened layer using the first process gas, the pressure of the process chamber is in a range of 2 mT to 8 mT.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: In the step of etching the roughened layer using the first process gas, the process parameters used further include: The upper electrode radio frequency power range is: 300W ~ 800W; The radio frequency power range of the lower electrode is: 50W~300W; Process temperature range: 120℃~150℃; The process time range is: 10s to 60s.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The chemical etching gas includes Cl 2 , and the physical bombardment gas includes Ar.

7. The method for manufacturing a semiconductor device according to claim 3, wherein: The roughened layer, the first conductive type semiconductor layer, and the second conductive type semiconductor layer are made of the same material.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The second process gas includes Cl 2 , BCl 3 and HBr.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: In the second process gas, the gas flow ratio of Cl2, BCl3 and HBr is in the range of 1:2:5 to 1:2:20; or In the second process gas, the flow rate range of Cl2 is 5 sccm to 20 sccm, the flow rate range of BCl3 is 20 sccm to 40 sccm, and the flow rate range of HBr is 25 sccm to 100 sccm; or The chamber pressure range is 2mT to 6mT; or In the step of continuing to etch the roughening layer, the second conductive type semiconductor layer, the active layer and the first conductive type semiconductor layer to a target depth using a second process gas, the RF power range of the upper electrode is 400W to 900W, and the RF power range of the lower electrode is 200W to 450W.

10. A semiconductor process equipment comprising a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for manufacturing a semiconductor device according to any one of claims 1 to 9 is implemented.

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