Double-sided circuit board and method for manufacturing same

Abstract

The present invention is intended to prevent peeling away of a plated surface in double-sided plating by providing a prescribed plating-free area in a circuit pattern formed on a base material of a double-sided circuit board. The present invention provides a double-sided circuit board having a copper plating layer on both the front and back surfaces of an insulating base material, wherein the plating area of the copper plating layer has a sinter layer obtained by sintering an ink layer printed in a pattern with conductive ink, and at any point (99) within the plating area on at least one side out of the plating areas opposite each other on the front and back sides, a plating-free part (90) is formed within said plating area such that said point (99) lies within the range of a predetermined designated distance X from the nearest plating edge part.

Description

Double-sided circuit board and its manufacturing method

[0001] The present invention relates to a double-sided circuit board having plating layers on both the front and back sides of an insulating base material, and a method for manufacturing the same.

[0002] Conventionally, circuit boards have been manufactured using a subtractive method, in which a metal layer is formed on an insulating substrate (base material) such as resin, and then unnecessary portions of this metal layer are removed by etching to form a wiring pattern. This method requires the use of large amounts of water and excess metal that is discarded during etching, as well as many steps.

[0003] In response to this issue, the present applicant has proposed a method in which a conductive ink containing metal nanoparticles (metal fine particles) is applied only to the necessary areas on an insulating substrate made of a thermoplastic resin such as a polyimide film using an inkjet method or the like, and then the metal layer is thickened by plating to further reduce resistance (Patent Document 1). This method (non-subtractive method), which differs from conventional subtractive methods, enables significant simplification of the circuit board manufacturing process, particularly by significantly reducing the amount of water used and carbon dioxide emissions. This non-subtractive method can be said to be an environmentally friendly method for manufacturing circuit boards with fewer steps. Furthermore, the inkjet method is a reliable method for producing small quantities of circuit boards on demand with minimal time and cost.

[0004] Patent Document 2 discloses a method for forming circuits by applying a metal nanoparticle ink onto a polyether ether ketone substrate, forming a photosintered film, and then forming a plating layer on top of that, by applying a resin layer (underlayer) called a primer to the substrate for improvement. Photosintering uses a xenon lamp or similar heat source to sinter (fire) the metal nanoparticles, enabling selective heating of the metal nanoparticle ink while suppressing temperature rise in the substrate. This minimizes thermal effects and enables sintering in a short time, even for substrates with low heat resistance.

[0005] Generally, if a single-sided board can be produced using one technology, the same principle can be used to produce circuits on both sides of the board, and multiple circuit boards can be stacked to produce a board. Therefore, to create such multi-layered circuit boards, it is essential to form circuits on both sides of the board.

[0006] When manufacturing a conductive circuit by printing a circuit on a substrate using an inkjet method with a conductive ink containing metal nanoparticles and then sintering the metal nanoparticle layer on the surface, a method of printing on both sides of the substrate to form the circuit is also required.

[0007] Japanese Patent No. 6300213 Japanese Patent Application Laid-Open No. 2020-188074

[0008] Yuka Mochizuki, Shintaro Kubozuka, Satoru Shimizu, Surface Technology, Vol. 66, No. 10, 2015, pp. 462-465; S. Nakahara, C.Y. Mak and Y. Okinaka, 1993 J. Electrochem. Soc., 140, 533; Asumaru Nakamura, Kohei Ninomiya, Minoru Hotta, Journal of the Fuel Association, Vol. 67, No. 12 (1988), pp. 1038-1051

[0009] In the above context, when a seed layer is mounted on an insulating polyimide substrate (e.g., polyimide film) using a conductive ink containing metal nanoparticles in a non-subtractive method utilizing the photo sintering (PS) phenomenon of the metal nanoparticles, it has been discovered that when a circuit pattern is printed on both the front and back surfaces of the substrate, sintered (photo sintering), and then electroless plating is performed, a large number of defects known as blisters occur. "Blisters" are a phenomenon in which the plating surface becomes partially dome-shaped (convex) as shown in Figure 1 (see blisters 17).

[0010] When such a floating portion 17 occurs, the circuit is easily damaged and may be disconnected, so the occurrence of floating portion can be said to be a fatal defect.

[0011] It was found that the phenomenon of lifting, which does not occur at all when a circuit pattern is printed on one side of a substrate and then plated, occurs in large quantities when double-sided printing and plating are performed under the same conditions, and this phenomenon occurs with good reproducibility. Therefore, unless this problem is solved, it will be impossible to create a practical double-sided circuit board. In this disclosure, we use two hypotheses to explain the cause of lifting and show how to solve the problem.

[0012] It is known that hydrogen is involved in one of the causes of lifting in electroless plating, and many publications refer to this. Non-Patent Document 1 further describes that lifting is more likely to occur when plating in a formaldehyde bath due to the involvement of hydrogen. This paper also describes that the occurrence of lifting can be suppressed by cleaning the surface with ultraviolet (UV) radiation. This indicates that surface contamination is involved in the occurrence of lifting. In these descriptions, the involvement of hydrogen means the following:

[0013] That is, the reaction shown in the following formula 1 occurs on the surface of copper in the plating bath, and the plating grows due to the self-catalytic action of copper. Hydrogen is generated during this process. Cu 2+ + 2HCHO + 4OH- → Cu + 2HCOO - + H2O + H2↑ (Equation 1)

[0014] The rate at which hydrogen is generated is determined by the rate of the above-mentioned chemical reaction; for example, the higher the temperature, the greater the amount of hydrogen generated. It is also known that plating baths with high copper ion concentrations are more likely to produce lift-off, which is thought to be related to the increased rate of the above-mentioned reaction.

[0015] Therefore, the following hypotheses are possible: Hypothesis 1: When the amount of hydrogen generated exceeds the amount that can be released from gaps in the plated area, the hydrogen that is not fully released creates pressure below the plated surface, pushing up the plated surface.

[0016] The mechanism by which hydrogen is released from gaps in the plated region is disclosed in detail in Non-Patent Document 2. This paper describes that hydrogen escapes between crystal planes created by copper plating and is released to the outside.

[0017] On the other hand, it is known that the presence of dirt on the substrate surface increases the occurrence of lifting. Furthermore, when using conductive ink containing metal nanoparticles, lifting is more likely to occur in areas where sintering is insufficient (i.e., insufficient). Strengthening sintering reduces lifting. Since the contaminated areas do not receive a sufficient amount of ink, i.e., metal nanoparticles, they are thought to result in insufficient sintering density after sintering. Insufficient sintering means that the metal nanoparticles have not fully melted and solidified into a single mass. In other words, the surface area of ​​the metal nanoparticles remains large. Therefore, when the plating reaction occurs, the amount of hydrogen released during the reaction is relatively large due to their large surface area. In such areas, hydrogen is generated in excess of the amount released, which is thought to increase the internal pressure of the plating surface being formed by the hydrogen that is not released, resulting in lifting. This is consistent with the above hypothesis.

[0018] Next, consider the case where lifting occurs only when circuits are printed on both sides of a substrate and then plated on both sides. The phenomenon of lifting occurring on both sides when double-sided plating is performed under conditions where lifting does not occur with single-sided plating can be explained by the hydrogen causation hypothesis described above. In this case, it is necessary to consider the role of polyimide film as a substrate. As shown in Non-Patent Document 3, polyimide film has very high hydrogen permeability.

[0019] Hypothesis 2: If no lifting occurs on one side, hydrogen is released to the back side through the polyimide substrate, preventing the internal pressure of the plating layer 14 from increasing. This is shown in Figure 2(a). In contrast, when printing and plating is performed on both sides, as shown in Figure 2(b), the amount of hydrogen generated doubles, and the presence of the plating layer 14 on the back side prevents hydrogen from escaping from the back side through the polyimide substrate 11. This increases the internal pressure of the plating layer 14, making lifting 17 more likely to occur. If there is dirt or other areas where lifting is likely to occur, these will be the starting point for the lifting. At this time, it is thought that voids 18 containing accumulated hydrogen are formed on the back side of the lifting 17 in the plating layer 14.

[0020] The cause of the lifting in double-sided printing can be explained by these two hypotheses.

[0021] From the above considerations of the causes of floating, several facts could be explained by a hypothesis that hydrogen is involved. Based on this hypothesis, we have investigated countermeasures and this invention is the result. As will be described later, we will show that the problem of floating can be solved by a method that efficiently releases the generated hydrogen.

[0022] The present invention has been made against this background, and its object is to provide a double-sided circuit board and a method for manufacturing the same that can prevent the occurrence of floating of the plated surface in double-sided plating by providing a predetermined plating-deficient portion in a circuit pattern formed on both sides of an insulating base material using conductive ink.

[0023] In order to solve the above problem, in this disclosure, based on the hypothesis that hydrogen is the cause of the lifting that occurs when forming circuit patterns on both sides of a polyimide film in double-sided printing, a method was used in which the release route of hydrogen generated during the reaction was preset.

[0024] That is, the circuit pattern is designed to avoid creating circuit patterns with relatively large areas that face each other on both the front and back sides of the substrate (patterns that overlap when projected perpendicularly to the substrate surface), and to prevent excess hydrogen from accumulating and to allow it to be released to the outside from the plating edges, etc. The width of the circuit pattern is also designed to avoid being unnecessarily large.

[0025] Furthermore, they found that lifting did not occur in the case of patterns with fine lines less than a certain line width, and based on this finding, they hypothesized that hydrogen could be released from the plating edge on the front surface even when the back surface is plated over a large area.

[0026] Based on this hypothesis, guidelines for circuit pattern design can be created. More specifically, the double-sided circuit board of the present invention is, in one aspect, a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating substrate, wherein the plating regions of the copper plating layers comprise sintered layers formed by sintering ink layers printed in a pattern with conductive ink, and wherein a plating-defect portion is formed within an arbitrary point within at least one of the opposing plating regions on the front and back surfaces so that the point is within a predetermined distance from the nearest plating edge. With this configuration, hydrogen generated beneath the plating surface during the plating process is properly released to the outside, resulting in a high-quality double-sided circuit board with no floating on the plating surface.

[0027] In one aspect of the present invention, the shape of the plating void portion is, for example, any one of a line, a rectangle, a circle, a polygon, or a combination thereof that removes a part of the plating region.

[0028] In one aspect of the present invention, the plating-defective portion is formed in a printed image corresponding to the circuit pattern of the conductive ink.

[0029] In one aspect of the present invention, the plated end portion is constituted by the end portion of the base material in addition to the plating-deficient portion.

[0030] In one aspect of the present invention, the plated end portion is constituted by the plating-lacking portion as well as the peripheral portion of a hole for a via hole provided in the base material.

[0031] In one aspect of the present invention, the predetermined distance is a distance of less than 1 / 2 of the maximum width of the fine line pattern that does not cause the plating surface to lift even if the opposite surface has a solid plating area (a state in which the plating is applied or drawn uniformly over the entire specified area without any gaps, without any design or pattern).

[0032] In one aspect of the present invention, the periphery of the plating void portion forms a closed loop within the plating region.

[0033] In one embodiment of the present invention, the substrate is made of polyimide.

[0034] In one aspect of the present invention, the conductive ink is an ink containing metal nanoparticles.

[0035] In one aspect of the invention, the metal nanoparticles are copper nanoparticles.

[0036] In one aspect of the present invention, the printing method is an inkjet method.

[0037] In one embodiment of the present invention, the thickness of the copper plating layer is within the range of 3 μm to 100 μm.

[0038] In one aspect of the present invention, the sintered layer is a photosintered layer.

[0039] According to another aspect, the double-sided circuit board of the present invention is a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating base material, in which the plating regions of the copper plating layers have sintered layers formed by sintering ink layers printed in a pattern with conductive ink, and a plating-defective portion is formed in the plating regions on at least one surface so that relatively large areas of the plating regions do not face each other on the front and back surfaces. With this configuration, hydrogen generated below the plating surface during the plating process is released to the outside, thereby obtaining a high-quality double-sided circuit board with no floating on the plating surface.

[0040] According to one aspect of the present invention, a method for manufacturing a double-sided circuit board includes a method for manufacturing a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating substrate, the method comprising the steps of: applying a conductive ink containing metal nanoparticles in a pattern on the surface of the substrate; sintering the applied conductive ink; and performing an electroless copper plating process on the sintered layer formed by the sintering. In the conductive ink pattern, a plating-missing portion is formed within the plating region at any point on at least one of the opposing plating regions on the front and back surfaces, such that the point is within a predetermined distance from the nearest plating edge. This configuration allows hydrogen generated beneath the plating surface during the plating process to be released to the outside without causing the plating surface to lift. Furthermore, because electroless copper plating is performed on the sintered layer of conductive ink formed in a pattern, there is no need for a process for later removal of the sintered layer or part of the plating layer once formed.

[0041] This method for manufacturing a double-sided circuit board may further include a step of applying a resin solution for a resin layer to the surface of the substrate and curing it at a predetermined temperature before the step of applying the conductive ink in a pattern.

[0042] In one aspect of this method for manufacturing a double-sided circuit board, the sintering step is a step of photosintering the applied conductive ink.

[0043] According to the double-sided circuit board and manufacturing method thereof disclosed herein, by providing a predetermined plating-missing portion in the circuit pattern formed on both sides of the insulating base material using conductive ink, it is possible to prevent the occurrence of floating of the plated surface in double-sided plating.

[0044] 10 is an explanatory diagram of an example of "lifting" in electroless plating according to the prior art. It is an explanatory diagram of a hypothesis regarding the cause of lifting in double-sided printing. It is a cross-sectional view of a case where a circuit pattern is present on one side. It is a cross-sectional view of a case where a circuit pattern is present on both sides. It is a photograph showing the appearance of the front surface of lifting occurrence test pattern 1 in an embodiment. It is a photograph showing the appearance of the back surface of lifting occurrence test pattern 1 in an embodiment. It is a photograph showing the appearance of the front surface of lifting occurrence test pattern 2 in an embodiment. It is a diagram showing experimental result data in which the presence or absence of blisters for each line width was confirmed for a large number of double-sided circuit boards for testing using lifting occurrence test pattern 2. It is an explanatory diagram of a case where lifting did not occur when the line width of the circuit pattern of a double-sided circuit board was narrow. It is a diagram for summarizing locations where hydrogen generated under the plated surface during plating processing in a double-sided circuit board may be released without causing lifting, even when no plating missing portion is provided. It is a diagram showing an example of a design drawing for a double-sided circuit board having a 7 mm x 7 mm square with wiring patterns on both sides. It is a diagram for explaining an area cut out from the wiring on the front surface that is less likely to cause lifting on the back surface in the double-sided circuit board shown in FIG. 14(b) is a diagram illustrating a procedure for cutting out a portion of the back surface that may become raised and for making a slit as a plating missing portion in FIG. 10. FIG. 14(c) is a diagram illustrating requirements for forming a plating missing portion in an embodiment. FIG. 14(b) is an enlarged view of a portion of the plating missing portion in FIG. 14(b). FIG. 14(c) is a diagram illustrating another form of a plating missing portion in an embodiment. FIG. 14(d) is a diagram illustrating yet another form of a plating missing portion in an embodiment. FIG. 17 is a diagram illustrating yet another form of a plating missing portion together with FIG. 17.

[0045] The present invention will be described in detail below with reference to an embodiment thereof. This embodiment employs an approach in which, at the circuit pattern (wiring diagram) design stage, a route for releasing hydrogen generated during plating after double-sided printing with conductive ink on an insulating substrate is secured in advance.

[0046] <Configuration of Circuit Board> Fig. 3 shows a cross-sectional view that schematically illustrates the basic configuration of a circuit board having a circuit pattern on one side of a substrate, Fig. 3(a) showing a general configuration, and Fig. 3(b) showing a specific configuration example.

[0047] As shown in FIG. 3( a), the circuit board 10 is basically composed of a polyimide substrate 11 as an insulating substrate, a resin layer 12 applied to the substrate 11, a sintered layer 13 (conductive film) formed by sintering a metal nanoparticle layer (ink layer) formed by applying a conductive ink containing metal nanoparticles to the resin layer 12, and a plating layer 14 formed on the sintered layer 13. The plating layer 14 constitutes a conductive layer for the circuit. While the resin layer 12 is not necessarily a necessary element, providing the resin layer 12 can improve adhesion between the sintered layer and the plating layer and the substrate. This also applies to the configurations described below.

[0048] 3(b) shows a cross-sectional view of a circuit board in a partially printed wiring state. In this figure, the sintered layer 13a is formed by sintering an ink layer as a metal nanoparticle layer formed in a pattern. A plating layer 14a is formed on the sintered layer 13a. The plating layer 14a is formed in a similar pattern to the sintered layer 13a.

[0049] 4 shows a cross-sectional view of a double-sided circuit board in which circuit patterns exist on both the front and back surfaces of the substrate 11. The specific configuration of the components of the double-sided circuit board 10a is as follows.

[0050] (Substrate 11) In this embodiment, the material of the insulating substrate (insulating substrate) 11 is typically polyimide, but is not necessarily limited to this, and can be, for example, polyamideimide, liquid crystal polymer (LCP), polyetherketone, polyamide, polyester, epoxy resin, or polyethylene terephthalate. In this embodiment, the thickness is, for example, about 25 μm, but is not limited to this.

[0051] (Metal nanoparticle layer 13: ink layer: layer containing metal nanoparticles: sintered layer: conductive film) The thickness of the metal nanoparticle layer 13 in this embodiment is preferably 100 nm to 20 μm, more preferably 200 nm to 5 μm, and most preferably 500 nm to 2 μm. If this layer is too thin, the mechanical strength may be reduced. Conversely, if the ink coating layer is too thick, the manufacturing costs may increase because metal nanoparticles are generally more expensive than regular metals.

[0052] The metal of the metal nanoparticles is typically copper, which is advantageous in terms of cost, but is not necessarily limited to this.

[0053] The average particle size of the metal nanoparticles is preferably 1 nm to 200 nm, more preferably 10 nm to 100 nm. If the particle size is too small, the reactivity of the particles may be high, which may adversely affect the storage stability and stability of the ink. If the particle size is too large, it may be difficult to form a uniform thin film and the ink particles may be more likely to settle.

[0054] In conventional inks, even if metal nanoparticles are mixed, there is no reason to firmly fix the metal nanoparticles to a resin substrate such as polyimide. Only after a large number of metal nanoparticles are sintered can they adhere to the resin substrate. Furthermore, while inks using binders can fix the metal particles to a certain degree of strength, this is not the case when the concentration of metal nanoparticles is reduced. If the metal nanoparticles are not sintered, they will fall off and flow out, resulting in poor adhesion and potentially adversely affecting the plating bath.

[0055] (Plating Layer 14) The plating layer 14 as a conductive layer is formed by plating (electroless plating) on ​​the metal nanoparticle layer 13. For the electroless plating, a standard copper sulfate solution with formaldehyde as a reducing agent and a pH of 10 or higher can be used.

[0056] While copper, nickel, tin, silver, gold, and the like can be used as plating metals, copper is preferred from the viewpoints of economy and conductivity. However, copper plating may be combined with plating of other metals. For example, a nickel plating layer may be formed on a copper plating layer to prevent oxidation of the copper plating, and then gold plating may be formed. In this case, the nickel plating layer is formed as a barrier layer to prevent metal diffusion from the gold plating layer into the copper plating layer.

[0057] The thickness of the plating layer 14 is preferably 3 μm to 100 μm, and more preferably 3 μm to 35 μm. If the plating layer 14 is too thin, the mechanical strength may be insufficient and the conductivity may not be sufficient for practical use. Conversely, if the plating layer 14 is too thick, the time required for the plating process may be long, which may increase the manufacturing cost. In this embodiment, electroless plating is used as the plating process, but electrolytic plating may be used after electroless plating to increase the layer thickness.

[0058] <Method for manufacturing circuit board> (Primer application step) In this step, a resin solution for the resin layer 12 as a primer is applied to the surface of a polyimide substrate. Although there are no limitations on the method for applying the primer, a roll-to-roll coating method for polyimide film is preferred in consideration of productivity. The applied resin layer as a primer is cured at a temperature in the range of 150°C to 200°C. Note that this step is not essential to the present invention.

[0059] (Ink Application Process) In this process, an ink containing metal nanoparticles is applied to the surface of the substrate to which a primer has been applied and cured. This application is performed in a pattern on the substrate. A printing method can be used, and an inkjet method is typically used. However, this is not necessarily limited to the inkjet method, and other application methods may also be used. This conductive ink pattern is designed in advance so that at any point within the plating region on at least one of the opposing plating regions on both the front and back surfaces, a plating void is formed within the plating region so that the point is within a predetermined distance from the nearest plating edge.

[0060] After applying the conductive ink containing metal nanoparticles to the substrate, a drying process is performed to remove the solvent, if any. This process is similar to the drying process for known conductive inks. Methods for drying the conductive ink include heating in an oven or hot air drying.

[0061] (Sintering Process) After the ink application process and drying process, a sintering process is carried out. As a sintering method, in addition to photo-sintering, heat sintering using an oven or sintering by reduction treatment can also be used, but photo-sintering is used in this embodiment. For this purpose, a commercially available photo-sintering device, such as the photo-sintering device (B0320-A) manufactured by Ushio Inc., can be used. In this process, the distance between the substrate and the lamp is set, and the voltage, irradiation time, etc. are adjusted. Photo-sintering is completed instantly, so the time required to proceed to the next process is short.

[0062] (Plating step) The formed sintered layer is subjected to a plating process. This causes a plating metal to be deposited on the surface and inside of the sintered layer. The plating method is the same as a known plating process using a known plating solution, specifically electroless copper plating.

[0063] (Lifting Occurrence Test Pattern 1) To verify the relationship between circuit pattern size and lifting occurrence, the present inventors printed lifting occurrence test pattern 1 on both sides of a 25 μm thick polyimide film 51 (Kapton 100EN, manufactured by DuPont Toray) using a conductive ink containing copper nanoparticles with an inkjet device (ELP03, manufactured by Elephantech Co., Ltd.). This printed film was photosintered on each side using a photosintering device (B0320-A) manufactured by Ushio Inc., and electroless plating was performed in a formaldehyde bath to a thickness of 12 μm to prepare a test double-sided circuit board 50.

[0064] Figures 5 and 6 are photographs showing the appearance of the front and back of this lifting occurrence test pattern 1. The numbers printed alongside the test pattern in these photographs indicate the line width in millimeters. For example, 0.5 indicates a line width of 0.5 mm.

[0065] In the lifting occurrence test pattern 1 shown in Figure 5, the rectangular and linear white areas are the plated areas. The plated area on the back side is a single large rectangular solid pattern (filled in evenly with no gaps). In the photograph in Figure 5, the solid pattern on the back side is visible as a black area through the front side.

[0066] If you look closely at these photos, you can see crater-like depressions. These are the areas where the "floors" have collapsed. The floats initially expand into a dome shape, but once they grow larger they become soft, and after plating, the entire substrate is washed with water and the water droplets are blown away with compressed air, causing them to collapse.

[0067] These two photographs, one on the front side and one on the back side, show that the locations where the lifting occurred are characteristic. That is, when viewed from the front side first (Figure 5), the following can be confirmed. In Figure 5, for convenience, the locations where the lifting occurred are shown surrounded by white circular or elliptical lines. 1) There were no cases where lifting occurred with lines thinner than 0.6 mm in width, even when there was a large pattern on the back side. 2) There was a small area of ​​lifting with a line 1.6 mm in width (area 52). 3) With the wide pattern at the top of the figure, no lifting occurred in areas where there was no pattern on the back side (see area 53).

[0068] Furthermore, when viewed from the backside, which has a large solid plating area 55 (Figure 6), the following can be confirmed: 4) If there is a large plating area on the opposite side, a lift occurs there (area indicated by arrow 61). 5) If the opposite side has a fine line pattern, no lift occurs even if the area on this side is large (area indicated by arrow 62).

[0069] As described above, if the patterns on the front and back surfaces are properly positioned (in terms of size and positional relationship), it is possible to prevent the occurrence of lifting. In other words, the experimental results of lifting occurrence test pattern 1 show that the following requirements are roughly necessary to prevent the occurrence of lifting.

[0070] - Avoid overlapping of the front and back sides of a large area above a certain level. - When the line width is more than 0.6 mm, do not place a pattern with a large area on the back side.

[0071] (Lifting Occurrence Test Pattern 2) However, lifting occurrence test pattern 1 shown in Figures 5 and 6 cannot check line widths in the range greater than 0.6 mm and smaller than 1.6 mm. Figure 7 shows an example of another lifting occurrence test pattern 2 with a narrower range. In this test pattern, fine line patterns 72 ranging from 0.4 mm to 1.6 mm in 0.1 mm increments are printed on the front surface of polyimide film 71, and a large (rectangular) solid pattern 74 is printed on the back surface so as to cover part of these fine line patterns 72. A test double-sided circuit board 70 was fabricated based on this test pattern. The fabrication process was the same as that for double-sided circuit board 50 described above.

[0072] 8 shows experimental data for confirming the presence or absence of blisters for each line width for a large number (six in this example) of double-sided test circuit boards 70 using the lifting occurrence test pattern 2. In the figure, a "◯" indicates the presence of blisters, and an "X" indicates the absence of blisters. "Blisters" corresponds to the occurrence of one or more blisters on at least one of the front and back surfaces of the board.

[0073] As can be seen from the experimental results, it was confirmed that no blisters occurred for thin wires with a line width of 0.4 mm to 1.0 mm.

[0074] Based on the above results, we considered the following. Figure 9 shows a cross-sectional view of a double-sided circuit board in which the back surface has a relatively large (in this example, the entire surface) solid plating layer 14, and a linear circuit pattern is formed on the opposing front surface. From the above experimental results, it was found that if the line width a is 1.0 mm or less, no lifting occurs even when the back surface is covered with a large pattern. In other words, if the distance b, which is half the line width, is 0.5 mm or less, hydrogen generated by the plating reaction in the center of this line can escape from the plating edge. Therefore, in this case, even if the back surface has a large solid pattern, lifting can be avoided at a point on the front surface plating layer 14 as long as the distance from that point to the edge of the plating layer 14 (plating edge) is 0.5 mm or less.

[0075] On the other hand, it is thought that hydrogen can also escape from the lateral cross section of the substrate. In other words, the edges of the substrate function to release hydrogen in the same way as the plated edges. Therefore, even if the substrate surface is covered with a plated surface when c = 0, hydrogen is released from the edges of the substrate so that lifting can be avoided if the line width a is 1.0 mm or less.

[0076] As described above, the pattern line width that does not cause lifting can provide a solution for circuit design. That is, by creating a hydrogen outlet within 0.5 mm from the center of any circuit pattern, it is possible to achieve the same line width that does not cause lifting of 1.0 mm or less. In this case, the predetermined distance can be said to be a distance of less than half the maximum width of a fine line pattern that does not cause lifting of the plating surface even if the opposite side has a fully plated area.

[0077] FIG. 10 summarizes the locations where hydrogen generated under the plating surface during plating on a double-sided circuit board can be released to the outside without causing lifting, even when no plating-defective areas are provided. FIG. 10(a) shows via hole portions 81 and holes 83. Because a hole 84 is located in the center of these, the area (shaded area) indicated within the circle extending a predetermined distance from the periphery of the hole 84 is free from lifting. As shown in FIG. 10(b), the area (shaded area) within a predetermined distance inside the edge 85 of the substrate is also free from lifting. Furthermore, as shown in FIG. 10(c), the area (shaded area) within a predetermined distance inside the edge 86 of the plating area on the substrate is also free from lifting. The multiple shaded areas in FIGS. 10(a) through 15(c) function complementary to each other. That is, hydrogen generated under the plating surface at any point on a substrate is guaranteed to dissipate if that point falls within any of the shaded areas. Conversely, if there are plating areas that are not covered even when these multiple types of hatched areas are combined, it is necessary to provide a plating void of a predetermined shape and size so that points within such plating areas are contained within the plating void or the resulting hatched area.

[0078] (Application Example 1) Figure 11 shows an example of a design drawing for a 7 mm x 7 mm square double-sided circuit board with wiring patterns on both sides. Figure 11(a) shows the wiring diagram for the front side of this board, and Figure 11(b) shows the wiring diagram for the back side. For ease of comparison between the front and back sides, Figure 11(b) shows an image of the back side viewed from the front side to the back side without flipping the board. In this figure, the solid areas indicate the areas to be plated. In this example, the plating metal is copper. The round gray areas 81 indicate via holes that penetrate the front and back of the board. Furthermore, the gray circle on the white area indicates the location of a hole 83 shared with another board to be overlaid on this board. Although the via hole area 81 is not shown as a white area, there is a hole.

[0079] 11, if a circuit pattern is drawn on a polyimide substrate by inkjet printing using conductive ink, followed by sintering and electroless plating, there is a possibility that some areas may become detached. The following describes the procedure for preventing this detachment from occurring on this substrate.

[0080] Figure 12(a) is a reprint of the wiring diagram for the front surface of the board shown in Figure 11(a). Figure 12(b) shows an image of a portion of the wiring diagram in Figure 12(a) cut out from the area where it is okay to have a large solid pattern plated on the back surface. The black areas are the areas that will be plated. The area cut out in Figure 12(b) is made up of only relatively fine wiring patterns, so there is no risk of floating even if it is overlapped with the circuit pattern on the back surface in Figure 10(b).

[0081] For areas other than this cut-out area, the relationship with the back surface must be taken into consideration. If the problematic area on the back surface, which is the solid plated surface facing each other, is cut out, it will look like the image shown in Figure 13(a). In this example, the image in Figure 13(a) is a part of the circuit pattern on the back surface (Figure 11(b)).

[0082] Therefore, plating omissions are intentionally provided in the circuit pattern (image) of Figure 13(a) at the design stage. Plating omissions are blank spaces where the plating layer (and the underlying metal nanoparticle layer) are missing. Figure 13(b) shows slits 91-94 as an example of plating omissions. A slit is an elongated, approximately linear blank space, and may be straight or curved. These slits 91-94 meet the requirements for plating omissions in this disclosure, which will be described in detail below.

[0083] If the image of FIG. 13(b) is placed back onto the original circuit pattern of FIG. 11(b), it will look like FIG. 13(c).

[0084] In the case of such a double-sided wiring diagram, by providing the above-mentioned plating-defective portion, it is possible to prevent the occurrence of floating of the plating surface in double-sided plating.

[0085] (Requirements for plating voids) Next, we consider the requirements for forming plating voids. Four locations on the circuit pattern in Figure 14(a) are marked with stars as positions where lifting may occur (candidate lifting locations). The shaded areas are the areas to be plated. Each location marked with stars #1 to #4 is a candidate lifting location on the plating surface, with a distance to the plating edge of at least a specified distance (0.5 mm in this case). Here, the plating edge includes the periphery of the plating area, the periphery of the substrate, and the periphery of the via hole portion 81 and hole 83, which are indicated by circles.

[0086] 14(b), in the present disclosure, a plating defect 90 is provided on the plated surface so that the distance from any position within the plated area where lifting may occur to the non-plated portion is within a predetermined distance. In this example, the plating defect 90 is a combination of rectangular slits 95, 96 and a circular hole 97.

[0087] An enlarged view of the plating defect 90 is shown in Figure 15. As can be seen from this figure, by providing the plating defect 90 at any point 99 in the plating region where lifting may occur if the plating defect 90 were not present, the arbitrary point 99 falls within a predetermined distance X from the nearest plated end. Conversely, the shortest distance from the point 99 to the plated end is equal to or less than the predetermined distance X. In other words, when the plated regions of both surfaces projected perpendicularly to the substrate surface overlap over a relatively wide area, the plating defect 90 is formed so that at any point within the overlapping area, the point falls within the predetermined distance X from the nearest plated end. This configuration eliminates the cause of lifting.

[0088] (Other Forms of Plating Defects) Two methods for eliminating lifting are exemplified here. FIG. 16( a) shows the front and back surfaces of a circuit pattern, arranged one above the other. The area 65 enclosed by the dotted line is a candidate location for lifting during plating. As plating defect areas for solving this problem, FIG. 16( b) shows a case where a slit 66 is provided, and FIG. 16( c) shows a case where a circular hole 68 is drilled. Whether slit 66 or circular hole 68 is selected as the plating defect can be determined by assuming hydrogen generation and ensuring that the slit or hole is located within an appropriate distance as an escape route for hydrogen. As long as there are sufficient hydrogen escape routes, even if there are excessive slits or holes, there is no problem.

[0089] (Another Form of Plating Missing Portion) Here, we show how holes for hydrogen desorption paths are set on the plating surface by combining shapes. Figures 17(a) and 17(b) show images of the original front and back printed patterns. In contrast, Figures 18(a) and 18(b) show images of the front and back printed patterns after the treatment. As shown in Figure 18(b), in this example, plating missing portions 101 to 106 are formed by combining slits and circular holes, which is a more complex shape.

[0090] In the above examples, all of the plating voids are closed within the plating area, i.e., the periphery of the plating void forms a closed loop within the plating area. Such closed plating voids are typical of the plating voids of the present disclosure. However, as shown in part 107 of Figure 18(b), the plating voids may be open (open loop) to the outside of the substrate or to the plating edge, and the present invention does not exclude plating voids of this type.

[0091] (Modifications) While the preferred embodiment has been described above, various modifications and changes other than those mentioned above are possible. The materials, sizes, distances, thicknesses, shapes, ratios, etc. used are merely examples and are not necessarily limited to these.

[0092] 10 Circuit board 10a Double-sided circuit board 11 Base material (insulating base material) 12 Resin layer (primer layer) 13, 13a Metal nanoparticle layer (ink layer, sintered layer, conductive film) 14, 14a Plating layer 17 Lift (blister) 50 Double-sided circuit board 51 Polyimide base material (polyimide film) 52 Part 53 Area 55 Area 61 Arrow 62 Arrow 65 Area 66 Slit 68 Hole 70 Double-sided circuit board 71 Polyimide base material (polyimide film) 72 Fine line pattern 74 Large area (solid) pattern 81 Via hole part 83 Hole 84 Hole 85 Board edge 86 Plating edge 90 Missing plating part 91-96 Slit 97 Hole 99 Point 101-106 Missing plating part 107 Part

Claims

1. A double-sided circuit board having copper plating layers on both the front and back sides of an insulating base material, the plating area of ​​the copper plating layer having a sintered layer formed by sintering an ink layer printed in a pattern with conductive ink, and at any point within the plating area on at least one of the opposing plating areas on the front and back sides, a plating void is formed within the plating area so that the point is within a predetermined distance from the nearest plating end.

2. A double-sided circuit board as described in claim 1, wherein the shape of the plating-defective portion is one of a line, a rectangle, a circle, a polygon, or a combination of these, which removes a portion of the plating area.

3. The double-sided circuit board according to claim 1, wherein the plating-defective portion is formed in a printed image corresponding to the circuit pattern of the conductive ink.

4. A double-sided circuit board according to claim 1, wherein the plated end portion is composed of the end portion of the base material in addition to the plating-lacking portion.

5. A double-sided circuit board according to claim 1, wherein said plated end portion is constituted by, in addition to said plated-out portion, a peripheral portion of a hole for a via hole provided in said base material.

6. A double-sided circuit board as claimed in claim 1, wherein the predetermined distance is less than 1 / 2 the maximum width of the fine line pattern at which no floating of the plating surface occurs even if the opposite side has a completely solid plated area.

7. The double-sided circuit board according to claim 1, wherein the peripheral edge of the plating-defective portion forms a closed loop within the plating area.

8. The double-sided circuit board of claim 1, wherein the substrate is made of polyimide.

9. The double-sided circuit board of claim 3, wherein the conductive ink is an ink containing metal nanoparticles.

10. The double-sided circuit board of claim 9, wherein the metal nanoparticles are copper nanoparticles.

11. The double-sided circuit board according to claim 1, wherein the printing method is an ink-jet method.

12. The double-sided circuit board according to claim 1, wherein the thickness of the copper plating layer is within the range of 3 μm to 100 μm.

13. The double-sided circuit board according to claim 1, wherein the sintered layer is a photosintered layer.

14. A double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating base material, in which the plating area of ​​the copper plating layer has a sintered layer formed by sintering an ink layer printed in a pattern with conductive ink, and in which a plating-deficient portion is formed in the plating area on at least one side so that relatively large plating areas on the front and back surfaces do not face each other.

15. The double-sided circuit board according to claim 14, wherein the shape of the plating-defective portion is a slit that removes a part of the plating region of the plating layer, a rectangle, a circle, a polygon, or a combination of these.

16. The double-sided circuit board according to claim 14, wherein the peripheral edge of the plating defect forms a closed loop within the plating area.

17. A method for manufacturing a double-sided circuit board having copper plating layers on both front and back surfaces of an insulating base material, comprising the steps of: applying a conductive ink containing metal nanoparticles in a pattern onto the surface of the base material; sintering the applied conductive ink; and performing an electroless copper plating process on the sintered layer formed by sintering, wherein in the conductive ink pattern, at any point within the plating area on at least one of the opposing plating areas on the front and back surfaces, a plating void is formed within the plating area so that the point is within a predetermined distance from the nearest plating end.

18. A method for producing a double-sided circuit board as described in claim 17, further comprising a step of applying a resin solution for a resin layer to the surface of the substrate and curing the resin solution at a predetermined temperature prior to the step of applying the conductive ink in a pattern.

19. The method for producing a double-sided circuit board according to claim 17, wherein the sintering step is a step of photosintering the applied conductive ink.

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