Signal isolation circuit for transmitting multiple signals

Abstract

Disclosed is a signal isolation circuit for transmitting multiple signals. The signal isolation circuit is for transmitting multiple signals from a first domain to a second domain and includes: a multi-signal encoder configured to encode first to third signals into a single fourth signal in the first domain; a transceiver configured to transmit the fourth signal from the first domain to the second domain; and a multi-signal decoder configured to decode the first to third signals from the fourth signal in the second domain.

Description

Signal isolation circuit for multi-signal transmission

[0001] The present disclosure relates to a signal isolation circuit based on an on-off keying (OOK) method of signal transmission protocol.

[0002] The content described below merely provides background information related to the present embodiment and does not constitute prior art.

[0003] A signal isolation circuit is a circuit that exchanges data signals between two electrically isolated systems, typically operating at different ground potentials. These signal isolation circuits require an electrically isolated isolation channel, typically utilizing microtransformers, capacitors, magnetoresistors (giant magnetoresistors), or optoelectric devices.

[0004] OOK is a signal protocol that utilizes the digital state of signals transmitted over an isolated channel. For example, when a digital signal is high, it is transmitted over the isolated channel, and when it is low, it is not transmitted. In this case, the digital signal is modulated into a high-frequency signal at the transmitter, transmitted over the isolated channel, and then restored through demodulation at the receiver.

[0005] In the case of digital isolators and gate drivers using these isolation channels, there are many cases where two or more types of multi-signals must be transmitted. For example, a smart gate driver circuit that includes many protection circuit operation functions of switching elements is designed to transmit the results of each protection circuit operation through an isolation channel. In this case, in order to use the OOK signal transmission protocol, a transceiver circuit consisting of a transmitter, a receiver, and an isolation barrier is required. However, since a conventional transceiver circuit can transmit only one data signal in real time, the number of isolation channels required is equal to the number of data signals to be transmitted. In addition, although it is possible to transmit multiple signals using a serializer and a de-serializer, it is not suitable for applications such as gate driver circuits because it requires an oscillator and complex logic. Furthermore, to minimize power consumption in transceiver circuits, edge-triggered transceiver circuits require two isolation channels to transmit a single signal. While this approach offers the advantage of circuit simplicity, it increases the chip area of ​​integrated circuits, such as smart gate driver circuits or digital isolators that must process multiple signals, which can increase manufacturing costs and ultimately undermine product competitiveness.

[0006] The main purpose of the present disclosure is to provide a signal isolation circuit capable of transmitting multiple signals through one transceiver circuit including one isolation channel.

[0007] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0008] According to one aspect of the present disclosure, a signal isolation circuit for transmitting multiple signals from a first domain to a second domain is provided, comprising: a multi-signal encoder configured to encode first to third signals in the first domain into a fourth signal, wherein a pulse width of the fourth signal of the first domain is adjusted based on a first signal and a second signal of the first domain, and wherein generation of a pulse corresponding to a second signal of the first domain is adjusted based on the third signal of the first domain; a transceiver configured to transmit the fourth signal from the first domain to the second domain; and a multi-signal decoder configured to decode the first to third signals from the fourth signal in the second domain, wherein the first signal and the second signal of the second domain are generated based on the pulse width of the fourth signal of the second domain, and the third signal of the second domain is generated based on a time interval between pulses of the fourth signal of the second domain.

[0009] According to another aspect of the present disclosure, a multi-signal encoder for encoding multiple input signals into one output signal is provided, comprising: a pulse generator for generating a first pulse signal having a first pulse width based on a first input signal; a first pulse train generator for generating a second pulse signal having a second pulse width different from a first pulse width based on a second input signal having a first logic level, wherein the first pulse train generator is selectively deactivated based on a logic level of a third input signal; a second pulse train generator for generating a third pulse signal having a third pulse width different from the first pulse width and the second pulse width based on a second logic level of the second input signal, wherein the second pulse train generator is selectively deactivated based on the logic level of the third input signal; and a merging circuit for merging the first pulse signal, the second pulse signal, and the third pulse signal to generate the output signal.

[0010] According to another aspect of the present disclosure, a multi-signal decoder for decoding one input signal into multiple output signals is provided, the multi-signal decoder comprising: a first latch for generating a first output signal based on a time point at which a first pulse having a length longer than a first threshold pulse width is detected in the input signal; a second latch for generating a second output signal based on a time point at which a second pulse having a length shorter than the first threshold pulse width and longer than a second threshold pulse width is detected in the input signal and a time point at which a third pulse having a length shorter than the second threshold pulse width and longer than a third threshold pulse width is detected; and a pulse detection circuit for generating a third output signal based on whether a subsequent pulse has occurred within a predetermined threshold time from a time point at which a preceding pulse has occurred in the input signal.

[0011] In some embodiments, the pulse generator may generate the first pulse signal having one pulse in a time interval during which the first input signal has a predetermined logic level. The first pulse train generator may generate the second pulse signal having one or more pulses according to a length of a time interval during which the second input signal has the first logic level. The second pulse train generator may generate the third pulse signal having one or more pulses according to a length of a time interval during which the second input signal has the second logic level. The second pulse width may be smaller than the first pulse width, and the third pulse width may be smaller than the second pulse width. The merging circuit may include a logic gate merging the second pulse signal and the third pulse signal; and a multiplexer outputting one of the first pulse signal and the merged signal as the output signal based on the first pulse signal. The multi-signal encoder further includes an edge detection circuit that detects rising edges and falling edges of the second input signal to generate an edge detection signal, and the merged signal can be masked by the edge detection signal.

[0012] In some embodiments, the first latch may receive a first flag signal, the edge of which is formed corresponding to the time point at which the first pulse is detected, as a set input or a reset input. The second latch may receive a second flag signal, the edge of which is formed corresponding to the time point at which the second pulse is detected, and a third flag signal, the edge of which is formed corresponding to the time point at which the third pulse is detected, as either one of a set input and a reset input, respectively. The multi-signal decoder may further include a charge pump circuit that converts the input signal into a signal having a potential corresponding to a length of a pulse width; and an analog-to-digital converter that compares the potential of the converted signal with a plurality of reference voltages to generate one-hot codes. The first latch may receive a most significant bit of the one-hot code, and the second latch may receive the remaining bits except for the most significant bit. The analog-to-digital converter may include a plurality of comparators that compare the potential of the converted signal with the plurality of reference voltages to generate a thermometer code; and a masking circuit that converts the thermometer code into the one-hot code.

[0013] In some embodiments, the first signal of the first domain may be a short-circuit protection signal (SCP) output by a short-circuit protection circuit provided in the first domain, the second signal of the first domain may be a pulse-width modulated signal based on the temperature of an external switch element, module, or PCB, and the third signal of the first domain may be a power supply-and-internal temperature sensing signal (RDY) indicating whether the power supply and internal temperature of the first domain are normal.

[0014] According to embodiments of the present disclosure, multiple signals can be transmitted through a single isolation channel with minimal chip area and power consumption. While conventional signal isolation circuits require a maximum of four and a minimum of two transceiver circuits to transmit three types of multiple signals, the signal isolation circuit according to the present invention can transmit three types of multiple signals using just one transceiver circuit. Consequently, the chip area and power consumption of the integrated circuit can be reduced, thereby lowering manufacturing costs.

[0015] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0016] FIG. 1 is a schematic diagram showing the configuration of a signal insulation circuit according to one embodiment of the present disclosure.

[0017] FIG. 2 is a schematic diagram showing the configuration of a multi-signal encoder according to one embodiment of the present disclosure.

[0018] FIG. 3 is a timing diagram illustrating the operation of a multi-signal encoder according to one embodiment of the present disclosure.

[0019] FIG. 4 is a schematic diagram showing the configuration of a multi-signal encoder according to another embodiment of the present disclosure.

[0020] FIG. 5 is a timing diagram illustrating the operation of a multi-signal encoder according to another embodiment of the present disclosure.

[0021] FIG. 6 is a schematic diagram showing the configuration of a multi-signal decoder according to one embodiment of the present disclosure.

[0022] FIG. 7 is a timing diagram illustrating the operation of a multi-signal decoder according to one embodiment of the present disclosure.

[0023] FIG. 8 is a schematic diagram showing the configuration of an analog-to-digital converter according to one embodiment of the present disclosure.

[0024] FIG. 9 is a schematic diagram showing the configuration of a pulse detection circuit according to one embodiment of the present disclosure.

[0025] FIG. 10 is a waveform diagram showing the operation of a pulse detection circuit according to one embodiment of the present disclosure.

[0026] FIG. 11 is a waveform diagram showing multiple input signals and multiple output signals of a signal insulation circuit according to one embodiment of the present disclosure.

[0027] Hereinafter, some embodiments of the present disclosure will be described in detail using exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings. Furthermore, when describing the present disclosure, detailed descriptions of related known structures or functions will be omitted if they are deemed to obscure the gist of the present disclosure.

[0028] In describing components of embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated otherwise.

[0029] The detailed description set forth below, together with the accompanying drawings, is intended to explain exemplary embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced.

[0030] FIG. 1 is a schematic diagram showing the configuration of a signal insulation circuit according to one embodiment of the present disclosure.

[0031] The signal isolation circuit (10) is a circuit that transmits multiple signals generated in a first domain to a second domain. The first domain and the second domain may have different power levels or may be domains with separate power sources. The signal isolation circuit (10) may include all or part of a multi-signal encoder (100), a transceiver (120), and a multi-signal decoder (140). The components illustrated in Fig. 1 represent functionally distinct elements, and at least one of the components may be implemented in an integrated form in an actual physical environment.

[0032] A multi-signal encoder (100) encodes multiple input signals (SCP_HV, TSPWM_HV, and RDY_HV) generated in the first domain into one signal (TX_IN).

[0033] The encoded signal (TX_IN) is modulated into a high-frequency signal in the transmitter (122) of the transceiver (120), then transmitted to the second domain through an isolation channel (or isolation barrier) (124), and restored through demodulation in the receiver (126). The transmitter (122) and the receiver (126) can modulate or demodulate the signal based on an on-off keying (OOK) topology. The isolation channel (124) may use a micro transformer, a capacitor, a magneto-resistor (giant magneto-resistor), or an opto-electric device, but is not limited to these examples, and the present disclosure does not limit it in any particular manner.

[0034] The multi-signal decoder (140) decodes the demodulated signal (RX_OUT) into multiple output signals (SCP_LV, TSPWM_LV, and RDY_LV).

[0035] For convenience of explanation, in the present disclosure, it is assumed that the first domain is a high voltage (HV) domain, the second domain is a low voltage (LV) domain, and the multiple input / output signals include a short-circuit protection signal (SCP signal), an external temperature sensing signal (TSPWM signal), and a power supply-and-internal temperature sensing signal (RDY signal), respectively. The SCP signal is a short-circuit detection signal of the first domain, and may be a signal output from a DESAT (DESATuration Sensing) protection circuit or an OCP (Over Current Protection) protection circuit. The TSPWM signal is a square wave signal representing the temperature of an external switching element, module, or PCB, and is generated using a pulse width modulation method in which the duty ratio of the signal varies depending on the detected temperature. The RDY signal is a signal representing the power supply and internal temperature of the integrated circuit. For example, the RDY signal may have a logic high level when the power supply and internal temperature are suitable for the operation of the integrated circuit, and the RDY signal may have a logic low level when the power supply or internal temperature is not suitable for the operation of the integrated circuit.

[0036] However, it should be noted that the domains to which the signal insulation circuit (10) according to the present disclosure is applied and the types of input / output signals are not limited to these examples, and that the technical idea of ​​the present disclosure can be applied even when it is desired to transmit different types of signals between different domains through one transceiver.

[0037] Fig. 2 is a schematic diagram illustrating the configuration of a multi-signal encoder according to one embodiment of the present disclosure. Fig. 3 is a timing diagram illustrating the operation of a multi-signal encoder according to one embodiment of the present disclosure.

[0038] As illustrated in FIG. 2, the multi-signal encoder (100) may include all or part of a pulse generator (200) that generates a first pulse signal (L_PW) based on an SCP signal (SCP_HV), a first pulse train generator (220) that generates a second pulse signal (M_PW) based on a combination of a TSPWM signal (TSPWM_HV) and an RDY signal (RDY_HV), a second pulse train generator (240) that generates a third pulse signal (S_PW) based on a combination of the TSPWM signal (TSPWM_HV) and an RDY signal (RDY_HV), and a merging circuit (260) that merges the first to third pulse signals (L_PW, M_PW, and S_PW) into one signal (TX_IN).

[0039] The pulse generator (200) can be activated during a time period in which the SCP signal (SCP_HV) has a first logic level (e.g., logic high). The first logic level can be, for example, a logic level output when a short circuit is detected. The first pulse signal (L_PW) can include one pulse during a time period in which the SCP signal (SCP_HV) has the first logic level.

[0040] The first pulse train generator (220) can detect the on-pulse of the TSPWM signal (TSPWM_HV) to generate the second pulse signal (M_PW). For example, the first pulse train generator (220) can be activated in a time period in which the TSPWM signal (TSPWM_HV) has a first logic level (e.g., logic high). The number of pulses included in the second pulse signal (M_PW) can vary depending on the length of the on-pulse period of the TSPWM signal (TSPWM_HV).

[0041] The second pulse train generator (240) can detect the off-pulse of the TSPWM signal (TSPWM_HV) and generate the third pulse signal (S_PW). For example, the second pulse train generator (240) can be activated in a time period in which the TSPWM signal (TSPWM_HV) has a second logic level (e.g., logic low). The number of pulses included in the third pulse signal (S_PW) can vary depending on the length of the off-pulse period of the TSPWM signal (TSPWM_HV). The second pulse train generator (240) is implemented with the same circuit as the first pulse train generator (220), and can receive an inverted TSPWM signal (TSPWMB) to detect an off-pulse instead of an on-pulse.

[0042] The RDY signal (RDY_HV) may serve to control the transmission of the TSPWM signal (TSPWM_HV) to the second domain. To this end, the TSPWM signal (TSPWM_HV) and the inverted TSPWM signal (TSPWMB), which are input to the first pulse train generator (220) and the second pulse train generator (240), respectively, may be AND-gated by the RDY signal (RDY_HV). When the RDY signal (RDY_HV) is at a logic low level (i.e., when the supply power or internal temperature is not appropriate for the operation of the integrated circuit), the operations of the first pulse train generator (220) and the second pulse train generator (240) are disabled, so that information about the TSPWM signal (TSPWM_HV) is not transmitted to the second domain side. In another example, if the RDY signal (RDY_HV) is implemented to have a logic high level when the supply power or internal temperature is not appropriate, the TSPWM signal (TSPWM_HV) and the inverted TSPWM signal (TSPWMB) may be AND gated by the inverted RDY signal (not shown).

[0043] Referring to FIG. 3, the first to third pulse signals (L_PW, M_PW, and S_PW) may each have different pulse widths. For example, the first pulse signal (L_PW) may have a first pulse width (t) that is relatively long compared to the other pulse signals (M_PW and S_PW). L _ PW ), and the second pulse signal (M_PW) has a second pulse width (t) of an intermediate level. M _ PW ), the third pulse signal (S_PW) has a relatively short third pulse width (t) compared to the other pulse signals (L_PW and M_PW). S_ PW ) can have.

[0044] The merging circuit (260) can merge the second pulse signal (M_PW) and the third pulse signal into a fourth pulse signal (MS_PW) by OR-gating the second pulse signal (M_PW) and the third pulse signal, and can selectively output the first pulse signal (L_PW) or the fourth pulse signal (MS_PW) through a 2×1 multiplexer (MUX: MUltipleXer). The 2×1 MUX can receive the first pulse signal (L_PW) as a selection signal. That is, the signal (TX_IN) output by the 2×1 MUX can be selected based on the logic level of the first pulse signal (L_PW). For example, the 2×1 MUX can output the first pulse signal (L_PW) in a time section in which the first pulse signal (L_PW) has a logic high level, and output the fourth pulse signal (MS_PW) in a time section in which the first pulse signal (L_PW) has a logic low level. In another example, the merging circuit (260) may be implemented as a 3×1 MUX (not shown) that selectively outputs any one of the first to third pulse signals (L_PW, M_PW, and S_PW). In another example, the merging circuit (260) may generate an output signal (TX_IN) by OR-gating the first pulse signal (L_PW) and the fourth pulse signal (MS_PW).

[0045] Fig. 4 is a schematic diagram illustrating the configuration of a multi-signal encoder according to another embodiment of the present disclosure. Fig. 5 is a timing diagram illustrating the operation of a multi-signal encoder according to another embodiment of the present disclosure.

[0046] The multi-signal encoder (100) may further include an edge detection circuit (400) that detects the edge of the TSPWM signal (TSPWM_HV) and generates an edge detection signal (ED).

[0047] The edge detection circuit (400) may include a first detection circuit (402) that detects an on-pulse edge (typically, a rising edge) of a TSPWM signal (TSPWM_HV) and a second detection circuit (404) that detects an off-pulse edge (typically, a falling edge) of the TSPWM signal (TSPWM_HV). The first detection circuit (402) and the second detection circuit (404) are triggered at the on-pulse edge and the off-pulse edge of the TSPWM signal (TSPWM_HV), respectively, and may generate a single pulse having a predetermined pulse width. The first detection circuit (402) and the second detection circuit (404) may be implemented by, for example, a combination of delay cells and logic gates, but are not limited thereto.

[0048] The signals output from the first detection circuit (402) and the second detection circuit (404) can be NOR gated to form an edge detection signal (ED). The edge detection signal (ED) can have a logic low level only for a certain period of time from the edge of the TSPWM signal (TSPWM_HV), and can maintain a logic high level for the remaining time intervals.

[0049] Fig. 5 shows output signals (TX_IN) that can be generated when a multi-signal encoder (100) includes and does not include an edge detection circuit (400). In this example, for simplicity of explanation, it is assumed that the SCP signal (SCP_HV) is fixed to a logic low level.

[0050] Referring to FIG. 5, depending on the length of the on-pulse period or the off-pulse period of the TSPWM signal (TSPWM_HV), a case may occur where the pulse of the second pulse signal (M_PW) and the pulse of the third pulse signal (S_PW) are connected to each other at the edge of the TSPWM signal (TSPWM_HV). For example, if the off-pulse edge of the TSPWM signal (TSPWM_HV) occurs before (or simultaneously with) the pulse of the second pulse signal (M_PW) is normally terminated and the pulse of the third pulse signal (S_PW) starts, the third pulse width (t S_PW ) longer pulse width (t a + t S_PW ) may appear in the fourth pulse signal (MS_PW) and the output signal (TX_IN). Similarly, when the on-pulse edge of the TSPWM signal (TSPWM_HV) occurs before (or simultaneously with) the pulse of the third pulse signal (S_PW) is normally terminated and the pulse of the second pulse signal (M_PW) starts, the second pulse width (t M _ PW ) with a pulse width (t) longer than b + t M _ PW ) can appear in the fourth pulse signal (MS_PW) and the output signal (TX_IN). The pulse width (t) of the connected pulse a + t S_ PW or t b + t M _ PW ) is the first pulse width (t L _ PW ), the edge timing of the TSPWM signal (TSPWM_LV) is incorrectly recognized as the edge timing of the SCP signal (SCP_LV) in the multi-signal decoder (140) described later, thereby generating incorrect signals.

[0051] To prevent such malfunction, the multi-signal encoder (100) can use the edge detection signal (ED) to clearly define the boundary between the on-pulse section and the off-pulse section of the TSPWM signal (TSPWM_HV) in the fourth pulse signal (MS_PW) and the output signal (TX_IN). The multi-signal encoder (100) can mask the fourth pulse signal (MS_PW) using the edge detection signal (ED). For example, the fourth pulse signal (MS_PW) can be input to a 2×1 MUX (264) after being AND-gated with the edge detection signal (ED).

[0052] Fig. 6 is a schematic diagram illustrating the configuration of a multi-signal decoder according to one embodiment of the present disclosure. Fig. 7 is a timing diagram illustrating the operation of a multi-signal decoder according to one embodiment of the present disclosure.

[0053] As illustrated in FIG. 6, the multi-signal decoder (140) may include all or part of a charge pump circuit (600), an analog-to-digital converter (ADC) (620), latches (640 and 660), and a pulse detection circuit (680).

[0054] The charge pump circuit (600) generates an analog signal (CP_OUT) whose potential varies depending on the pulse width of the input signal (RX_OUT). For example, referring to FIG. 7, the longer the pulse width of each pulse in the input signal (RX_OUT), the higher the potential the analog signal (CP_OUT) can have. The structure of the charge pump circuit (600) may adopt the structure of a typical charge pump circuit, and the present disclosure is not limited thereto to a specific structure.

[0055] The analog-to-digital converter (620) converts the analog signal (CP_OUT) output by the charge pump circuit (600) into a plurality of digital signals (SCP_Flag, TSPWM_ON, TSPWM_OFF, and RDY_Flag). The analog-to-digital converter (620) can compare the analog signal (CP_OUT) with a plurality of reference voltages (VREF1, VREF2, and VREF3) to generate a plurality of digital signals. The plurality of digital signals may include a first flag signal (SCP_Flag) indicating an edge timing (on-pulse or off-pulse edge timing) of an SCP signal (SCP_LV), a second flag signal (TSPWM_ON) indicating an on-pulse edge timing of a TSPWM signal (TSPWM_LV), a third flag signal (TSPWM_OFF) indicating an off-pulse edge timing of the TSPWM signal (TSPWM_LV), and a fourth flag signal (RDY_Flag) indicating both the on-pulse edge timing and the off-pulse edge timing of the TSPWM signal (TSPWM_LV). The first flag signal (SCP_Flag), the second flag signal (TSPWM_ON), ​​and the third flag signal (TSPWM_OFF) may be expressed as a one-hot code in which only one signal may have a logic high level in the same time interval.

[0056] FIG. 8 is a schematic diagram showing the configuration of an analog-to-digital converter according to one embodiment of the present disclosure.

[0057] Referring to FIG. 8, the analog-to-digital converter (620) may include a plurality of comparators (800, 802, and 804) and a masking circuit (820).

[0058] Comparators (800, 802, and 804) compare the analog signal (CP_OUT) with respective reference voltages (VREF1, VREF2, and VREF3). For example, a first comparator (800) may compare the analog signal (CP_OUT) with a first reference voltage (VREF1), a second comparator (802) may compare the analog signal (CP_OUT) with a second reference voltage (VREF2), and a third comparator (804) may compare the analog signal (CP_OUT) with a third reference voltage (VREF3).

[0059] The first reference voltage (VREF1) is the first pulse width (t L _ PW ) is set considering the length and a predetermined margin, and the second reference voltage (VREF2) is set considering the second pulse width (t M _ PW ) is set by considering the length and a certain margin, and the third reference voltage (VREF3) is set by considering the third pulse width (t S_ PW ) can be set by considering the length and a predetermined margin. For example, the first reference voltage (VREF1) can have the highest voltage, and the third reference voltage (VREF3) can have the lowest voltage.

[0060] The outputs (T1 to T3) of the comparators (800, 802, and 804) can be expressed as thermometer codes. For example, when the analog signal (CP_OUT) has a voltage higher than the first reference voltage (VREF1), the outputs (T1 to T3) of the first to third comparators can all have a logic high level. As another example, when the analog signal (CP_OUT) has a voltage lower than the first reference voltage (VREF1) and higher than the second reference voltage (VREF2), the output (T1) of the first comparator can have a logic low level, and the outputs (T2 and T3) of the second and third comparators can both have a logic high level. As another example, when the analog signal (CP_OUT) has a voltage lower than the second reference voltage (VREF2) and higher than the third reference voltage (VREF3), the outputs (T1 and T2) of the first and second comparators may have a logic low level, and the output (T3) of the third comparator may have a logic high level. As another example, when the analog signal (CP_OUT) has a voltage lower than the third reference voltage (VREF3), the outputs (T1 to T3) of the first to third comparators may all have a logic low level. The comparators (800, 802, and 804) may be enabled at the falling edge of the input signal (RX_OUT). Each of the comparators (800, 802, and 804) may be reset by its own output (T1 to T3).

[0061] The masking circuit (820) converts the outputs (T1 to T3) of the first to third comparators expressed as a 3-bit thermometer code into the first to third flag signals (SCP_Flag, TSPWM_ON and TSPWM_OFF) expressed as a 3-bit one-hot code.

[0062] For example, the first flag signal (SCP_Flag) can be generated by directly using the output (T1) of the first comparator, the second flag signal (TSPWM_ON) can be generated by NOR-gating the output (T1) of the first comparator, the inverted output (T2) of the second comparator, and the inverted output (T3) of the third comparator, and the third flag signal (TSPWM_OFF) can be generated by NOR-gating the output (T2) of the second comparator and the inverted output (T3) of the third comparator. Accordingly, as illustrated in FIG. 7, when a pulse having a pulse width longer than the first threshold pulse width appears in the input signal (RX_OUT), the first flag signal (SCP_Flag) has a logic high level, when a pulse having a pulse width shorter than the first threshold pulse width and longer than the second threshold pulse width appears in the input signal (RX_OUT), the second flag signal (TSPWM_ON) has a logic high level, and when a pulse having a pulse width shorter than the second threshold pulse width and longer than the third threshold pulse width appears in the input signal (RX_OUT), the third flag signal (TSPWM_OFF) may have a logic high level. Here, the first to third threshold pulse widths may be values ​​determined according to the first to third reference voltages (VREF1, VREF2, and VREF3) and / or the boost ratio of the charge pump circuit (600).

[0063] Meanwhile, the fourth flag signal (RDY_Flag) can be generated by OR-gating the second flag signal (TSPWM_ON) and the third flag signal (TSPWM_OFF). Accordingly, as illustrated in Fig. 7, when a pulse having a pulse width shorter than the first threshold pulse width and longer than the third threshold pulse width appears in the input signal (RX_OUT), the fourth flag signal (RDY_Flag) can have a logic high level.

[0064] Referring back to FIG. 6, each of the outputs of the analog-to-digital converter (620) may be input to any one of the first latch (640), the second latch (660), and the pulse detection circuit (840). For example, the first flag signal (SCP_Flag) corresponding to the most significant bit among the 3-bit one-hot codes generated by the masking circuit (820) may be input to the first latch (640), and the second flag signal (TSPWM_ON) and the third flag signal (TSPWM_OFF) corresponding to the remaining lower bits may be input to the second latch (660). In addition, the fourth flag signal (RDY_Flag) corresponding to the logical sum of the lower bits may be input to the pulse detection circuit (840).

[0065] The first latch (640) can generate an SCP signal (SCP_LV) based on the timing indicated by the first flag signal (SCP_Flag). The first latch (640) may be an RS latch. The first latch (640) may receive the first flag signal (SCP_Flag) as a set input or a reset input. For example, referring to FIG. 7, the SCP signal (SCP_LV) may be set by the first flag signal (SCP_Flag) and reset by a reset signal (RESET) input from the outside.

[0066] The second latch (660) can generate the TSPWM signal (TSPWM_LV) based on the timing indicated by the second flag signal (TSPWM_ON) and the third flag signal (TSPWM_OFF). The second latch (660) may be an RS latch. The second latch (660) may receive the second flag signal (TSPWM_ON) and the third flag signal (TSPWM_OFF) as a set input or a reset input, respectively. For example, referring to FIG. 7, the TSPWM signal (TSPWM_LV) may be set by the second flag signal (TSPWM_ON) and reset by the third flag signal (TSPWM_OFF). The TSPWM signal (TSPWM_LV) may be generated by AND-gating an output signal of the second latch (660) and an RDY signal (RDY_LV).

[0067] The pulse detection circuit (840) can output an RDY signal (RDY_LV) having a logic level when the fourth flag signal (RDY_Flag) is not applied for a period longer than a preset time.

[0068] Fig. 9 is a schematic diagram showing the configuration of a pulse detection circuit according to one embodiment of the present disclosure. Fig. 10 is a waveform diagram showing the operation of a pulse detection circuit according to one embodiment of the present disclosure.

[0069] Referring to FIG. 9, a pulse detection circuit (840) according to an embodiment of the present disclosure may include all or part of a switching element (SW), a capacitor (C), and a hysteresis comparator (900). Normally, when the fourth flag signal (RDY_Flag) is not applied, the capacitor (C) is charged by a power source, and when the fourth flag signal (RDY_Flag) is applied, the capacitor (C) is discharged as the switching element (SW) is turned on. The hysteresis comparator (900) may output an RDY signal (RDY_LV) having a logic low level when the voltage (Vc) of the capacitor (C) increases above a predetermined threshold voltage. For example, referring to FIG. 10, when the fourth flag signal (RDY_Flag) is repeatedly applied at a predetermined interval, the capacitor (C) may be repeatedly discharged, so that the voltage (Vc) of the capacitor (C) may be maintained below the threshold voltage (Vth). On the other hand, if the fourth flag signal (RDY_Flag) is not applied for a period longer than the preset time (tc), the voltage (Vc) of the capacitor (C) may become greater than the threshold voltage (Vth).

[0070] FIG. 11 is a waveform diagram showing multiple input signals and multiple output signals of a signal insulation circuit according to one embodiment of the present disclosure.

[0071] Referring to FIG. 11, assuming that the delay time due to the operation of the transceiver (120) is negligibly small, the delay time (t) between the SCP signal (SCP_HV) of the first domain and the SCP signal (SCP_LV) of the second domain SCP ) is the first pulse width (t L _ PW ), and the delay time (t) between the on-pulse of the TSPWM signal (TSPWM_HV) of the first domain and the on-pulse of the TSPWM signal (TSPWM_LV) of the second domain TSPWM_ON ) is the second pulse width (t M _PM) and the delay time (t) between the off-pulse of the TSPWM signal (TSPWM_HV) of the first domain and the off-pulse of the TSPWM signal (TSPWM_LV) of the second domain TSPWM_OFF ) is the third pulse width (t S_PM ) can be confirmed.

[0072] As described above, the multi-signal encoder (100) according to various embodiments of the present disclosure encodes the SCP signal (SCP_HV), the on-pulse of the TSPWM signal (TSPWM_HV), and the off-pulse of the TSPWM signal (TSPWM_HV) into one output signal (TX_IN) by specifying different pulse widths, and the multi-signal decoder (140) can decode the SCP signal (SCP_LV) and the TSPWM signal (TSPWM_LV) from the input signal (RX_OUT) based on the pulse widths of the individual pulses of the input signal (RX_OUT). In addition, the multi-signal encoder (100) may transmit a series of pulses (e.g., pulses having a pulse width specified for an on-pulse and an off-pulse of a TSPWM signal (TSPWM_HV)) to the second domain side when the RDY signal of the first domain is at a first logic level (e.g., logic high), and may not transmit the corresponding pulse train to the second domain side when the RDY signal is at a second logic level (e.g., logic low). The multi-signal decoder (140) may recognize whether the corresponding pulse trains are received and decode the RDY signal (RDY_LV).

[0073] Various implementations of the systems and techniques described herein can be realized in analog electronic circuits, digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and / or combinations thereof.

[0074] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

[0075] (CROSS-REFERENCE TO RELATED APPLICATION)

[0076] This patent application claims priority to Korean Patent Application No. 10-2023-0159804, filed on November 17, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A signal isolation circuit for transmitting multiple signals from a first domain to a second domain, A multi-signal encoder configured to encode first to third signals in the first domain into one fourth signal, wherein the pulse width of the fourth signal of the first domain is adjusted based on the first signal and the second signal of the first domain, and whether or not a pulse corresponding to the second signal of the first domain is generated based on the third signal of the first domain; a transceiver configured to transmit the fourth signal from the first domain to the second domain; and A signal isolation circuit comprising a multi-signal decoder configured to decode the first to third signals from the fourth signal in the second domain, generate the first signal and the second signal of the second domain based on the pulse width of the fourth signal of the second domain, and generate the third signal of the second domain based on the time interval between pulses of the fourth signal of the second domain.

2. In paragraph 1, The above multi-signal encoder, A pulse generator for generating a first pulse signal having a first pulse width based on a first signal of the first domain; A first pulse train generator that generates a second pulse signal having a second pulse width different from the first pulse width based on the second signal of the first domain having a first logic level, and is selectively deactivated based on the logic level of the third signal of the first domain; A second pulse train generator that generates a third pulse signal having a third pulse width different from the first pulse width and the second pulse width based on the second signal of the first domain having a second logic level, but is selectively deactivated based on the logic level of the third signal of the first domain; and A merging circuit that generates a fourth signal of the first domain by merging the first pulse signal, the second pulse signal, and the third pulse signal A signal isolation circuit including:

3. In paragraph 2, The pulse generator generates the first pulse signal having one pulse in a time interval in which the first signal of the first domain has a predetermined logic level, The first pulse train generator generates the second pulse signal having one or more pulses according to the length of the time interval during which the second signal of the first domain has the first logic level, A signal isolation circuit in which the second pulse train generator generates the third pulse signal having one or more pulses according to the length of the time interval in which the second signal of the first domain has the second logic level.

4. In paragraph 2, The second pulse width is smaller than the first pulse width, A signal isolation circuit wherein the third pulse width is smaller than the second pulse width.

5. In paragraph 2, The above merge circuit is, A logic gate for merging the second pulse signal and the third pulse signal; and A multiplexer that outputs one of the first pulse signal and the merged signal as a fourth signal of the first domain based on the first pulse signal A signal isolation circuit including:

6. In paragraph 5, The above multi-signal encoder further includes an edge detection circuit that detects rising edges and falling edges of the second signal of the first domain to generate an edge detection signal, The above merged signal is a signal isolation circuit masked by the edge detection signal.

7. In paragraph 1, The above multi-signal decoder, A pulse detection circuit that generates a third signal of the second domain based on whether a subsequent pulse occurs within a predetermined threshold time from the time when a preceding pulse occurs in the fourth signal of the second domain. A signal isolation circuit including:

8. In paragraph 1, The above multi-signal decoder, A first latch that generates a first signal of the second domain based on a time point at which a first pulse having a length longer than a first threshold pulse width is detected in the fourth signal of the second domain; and A second latch that generates a second signal of the second domain based on a time point at which a second pulse having a length shorter than the first threshold pulse width and longer than the second threshold pulse width is detected in the fourth signal of the second domain and a time point at which a third pulse having a length shorter than the second threshold pulse width and longer than the third threshold pulse width is detected. A signal isolation circuit including:

9. In paragraph 8, The above first latch receives a first flag signal, the edge of which is formed corresponding to the time at which the first pulse is detected, as a set input or a reset input, The second latch is a signal isolation circuit that receives a second flag signal, an edge of which is formed corresponding to the time when the second pulse is detected, and a third flag signal, an edge of which is formed corresponding to the time when the third pulse is detected, as one of a set input and a reset input, respectively.

10. In paragraph 8, The above multi-signal decoder, A charge pump circuit that converts the fourth signal of the second domain into a signal having a potential corresponding to the pulse width; and Further comprising an analog-to-digital converter for generating one-hot codes by comparing the potential of the converted signal with a plurality of reference potentials, The above first latch receives the most significant bit of the one-hot code, The second latch is a signal isolation circuit that receives bits other than the most significant bit.

11. In paragraph 10, The above analog-to-digital converter, A plurality of comparators for generating a thermometer code by comparing the potential of the converted signal with each of the plurality of reference potentials; and A masking circuit that converts the above thermometer code into the above one-hot code. A signal isolation circuit including:

12. In paragraph 1, The first signal of the first domain is a short-circuit protection signal (SCP) output by a short-circuit protection circuit provided in the first domain, The second signal of the first domain is a pulse-width modulated signal based on a temperature sensed from an external switch element, module, or PCB. A signal isolation circuit wherein the third signal of the first domain is a power supply-and-internal temperature sensing signal (RDY) indicating whether the power supply and internal temperature of the first domain are normal.

13. A multi-signal encoder that encodes multiple input signals into a single output signal, A pulse generator for generating a first pulse signal having a first pulse width based on a first input signal; A first pulse train generator that generates a second pulse signal having a second pulse width different from the first pulse width based on a second input signal having a first logic level, and is selectively deactivated based on the logic level of a third input signal; A second pulse train generator that generates a third pulse signal having a third pulse width different from the first pulse width and the second pulse width based on the second input signal having a second logic level, and is selectively deactivated based on the logic level of the third input signal; and A merging circuit that generates the output signal by merging the first pulse signal, the second pulse signal, and the third pulse signal A multi-signal encoder comprising:

14. In paragraph 13, The pulse generator generates the first pulse signal having one pulse in a time interval in which the first input signal has a predetermined logic level, The first pulse train generator generates the second pulse signal having one or more pulses according to the length of the time interval during which the second input signal has the first logic level, A multi-signal encoder, wherein the second pulse train generator generates the third pulse signal having one or more pulses according to the length of the time interval during which the second input signal has the second logic level.

15. In paragraph 13, The second pulse width is smaller than the first pulse width, A multi-signal encoder wherein the third pulse width is smaller than the second pulse width.

16. In paragraph 13, The above merge circuit is, A logic gate for merging the second pulse signal and the third pulse signal; and A multiplexer that outputs one of the first pulse signal and the merged signal as the output signal based on the first pulse signal A multi-signal encoder comprising:

17. A multi-signal decoder that decodes one input signal into multiple output signals, A first latch that generates a first output signal based on a point in time when a first pulse having a length longer than a first threshold pulse width is detected in the input signal; A second latch that generates a second output signal based on a time point at which a second pulse having a length shorter than the first threshold pulse width and longer than the second threshold pulse width is detected in the input signal and a time point at which a third pulse having a length shorter than the second threshold pulse width and longer than the third threshold pulse width is detected; and A multi-signal decoder comprising a pulse detection circuit that generates a third output signal based on whether a subsequent pulse occurs within a predetermined threshold time from the time when a preceding pulse occurs in the input signal.

18. In paragraph 17, The above first latch receives a first flag signal, the edge of which is formed corresponding to the time at which the first pulse is detected, as a set input or a reset input, A multi-signal decoder, wherein the second latch receives, as one of a set input and a reset input, a second flag signal whose edge is formed corresponding to the time when the second pulse is detected and a third flag signal whose edge is formed corresponding to the time when the third pulse is detected.

19. In Article 17, A charge pump circuit that converts the above input signal into a signal having a potential corresponding to a pulse width; and Further comprising an analog-to-digital converter for generating one-hot codes by comparing the potential of the converted signal with a plurality of reference potentials, The above first latch receives the most significant bit of the one-hot code, The second latch is a multi-signal decoder that receives bits other than the most significant bit.

20. In paragraph 19, The above analog-to-digital converter, A plurality of comparators for generating a thermometer code by comparing the potential of the converted signal with each of the plurality of reference potentials; and A masking circuit that converts the above thermometer code into the above one-hot code. A multi-signal decoder comprising:

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