Driver and control of line power extension circuit for ac-DC converter

Abstract

A line power extension circuit and corresponding driving and control methods are proposed to reduce a capacitor requirement (e.g., size) of AC-DC converters. In particular, a low-side line power extension circuit is proposed (e.g., having a MOSFET switch Q), along with approaches for providing a sensing and control circuit to decide when to turn on and to turn off the switch Q. Relative to an alternate circuit, the Low-Side Line Power Extension Circuit (LS-LPEC) provides different technical characteristics that can be benefit in various scenarios as described herein.

Description

DRIVER AND CONTROL OF LINE POWER EXTENSION CIRCUIT FOR AC-DC CONVERTERCROSS-REFERENCE

[0001] This application is a non-provisional of, and claims all benefit, including priority to, US Application Nos. 63 / 602442 and 63 / 556988, filed 23-Nov-2023 and 23-Feb-2024, respectively, incorporated herein by reference in their entireties. Both applications are entitled: DRIVER AND CONTROL OF LINE POWER EXTENSION CIRCUIT FOR AC-DC CONVERTER.FIELD

[0002] Embodiments of the present disclosure generally relate to the field of electronics, and more specifically, embodiments relate to devices, systems and methods for operating an AC-DC converter, and in particular, a line power extension circuit thereof.INTRODUCTION

[0003] Since 2012, the USB Power Delivery (USB PD) specification has standardized the charging protocols for a majority of consumer electronic devices. USB PD facilitates charger reusability across different devices and minimizes electronic waste. USB PD enables negotiation between the load and power source for multiple levels of power delivery. It proves to be highly advantageous in providing power to multiple devices, including smartphones, tablets, and laptops.

[0004] For USB-PD power adapters without PFC stage, it is common to adopt a single- stage architecture. The full-bridge diode rectifier converts the AC input Vacinto a stable bus voltage Vbuswith the assistance of C,n. The subsequent DC-DC converter serves the purpose of delivering adjustable output voltages to the load.

[0005] USB-PD power adapters have significantly reduced in size over time to meet consumers’ needs. Due to the implementations of fast-switching nature of wide-band-gap semiconductors, the size of the magnetic components within these adapters has been reduced significantly.

[0006] The input capacitor C / n, which occupies roughly a quarter of the converter volume, barely reduces its size as compared to decades ago.SUMMARY

[0007] While many size aspects of the LISB-PD power adaptors have been reduced significantly, the input capacitor C / n, which occupies roughly a quarter of the converter volume has barely reduced in size as compared to decades ago. Accordingly, a proposed circuit is provided, which is adapted to reduce the required capacitance for C / nand improve the power density of the whole converter system.

[0008] The proposed circuit is denoted as a Low-Side Line Power Extension Circuit (LS- LPEC), and its accompanying driving and control method are described herein. It is important to note that each of these (extension circuit and driving I control approach) can be considered separate independent inventive aspects, and in some embodiments, are combined together for interoperation. Independent operation is also possible.

[0009] The circuit is denoted as a "low-side" line power extension circuit to differentiate from a "high-side" line power extension circuit.

[0010] The line power extension circuit is a power converter circuit that includes a rectifier circuit having first and second input terminals that receive an AC input voltage and first and second output terminals that output a DC bus voltage. There is a series circuit comprising a switch connected in series with an input capacitor connected across the first and second output terminals. A controller controls the switch so that the switch is on at least during a period when a magnitude of the AC input voltage is less than a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage. Power adapters incorporating these features benefit from low component count, reduced component voltage stress, reduced size and weight, and low cost, making then suitable for a range of portable devices such as laptop computers and cellphones.

[0011] “Low-side” refers to the proposed positioning of the switch and the capacitor, Cin, which is modified, and this modification includes connecting a drain terminal of the switch Q to the ground point, which is the negative terminal of the input diode bridge (anode terminal of diodes D3 and D4). The source terminal of MOSFET Q is connected to the negative terminal of the input capacitor, Cin. The positive terminal of the input capacitor, Cin, is connected to the positive terminal of the diode bridge (cathode of D1 , D2).

[0012] Structurally, the circuit can include a number of diodes, D1-D4, similar to a fullbridge rectifier, and additionally, a switch (e.g., a N-channel MOSFET, but can also be a BJT, IGBT) is added in series with Cm, positioned below it. This configuration allows for strategic adjustment of the AC power conduction angle, thereby maximizing the utilization of AC input power and reducing the required capacitance for Cm.

[0013] Corresponding driver and controller circuits are also proposed. The driver and controller circuits are configured to regulate the switching states of Q.

[0014] The control circuit is configured to decide the time instant when the MOSFET should be turned and the time instant when the MOSFET should be turned off. Its output is a logic signal (high and low). The drive circuit is used to convert the logic signal to the gatesource terminal of the MOSFET Q. As described herein, there are proposed a number of different variations of control circuits and a couple of driver circuits, and it is important to note the innovative features of these circuits and their corresponding control logic.

[0015] The voltage of gate (QG) is set to a high level with respect to the voltage of source (Qs) to turn ON Q. Conversely, when Q needs to be turned OFF, the voltage of QG is set to a low level with respect to the voltage of Qs. The ON or OFF logic of Q is determined by the controller circuit (the circuit is configured for determining whether Q should be in an ON or OFF state).

[0016] The underlying objective of line power extension control is to maximize the utilization of AC input power, as for a given minimum bus voltage Vbus_min , line power extension control can effectively reduce the required capacitance of Cm, and for a predetermined capacitance of Cm, line power extension control enables the boost of the minimum bus voltage Vbus_mln- The approach is directed to an improved AC power conduction angle, and thus the total AC power conduction angle can be extended. During this extended angle, the DC-DC converter draws power directly from the AC input through the rectifier diodes, thereby significantly reducing the required discharge energy from the input capacitance C,n.

[0017] The line voltage and / or bus voltage is sensed in either analog or digital format, and this is used to determine an operational mode (i.e., whether LS-LPEC is required). LS-LPECis activated when the magnitude of the AC voltage is low, i.e., below Vbus_min, such as 100 Vac.

[0018] In operation, the circuit imparts different control approaches during a number of different time periods, described herein, where different power conduction and extension angles are provided (States A, B, C), controlling operation in respect of different powering periods. To support these approaches, four sensing and control logic circuits are proposed in an embodiment, but it is important to note that other variations are possible. It is important to note that timing control variations are also described, including a simpler sensing circuit if a less accurate timing is acceptable in the practical usage scenario. The simpler sensing circuit utilizes a proposed delay circuit.

[0019] In operation, the approach includes turning off the switch Q when the input AC voltage is at peak, and it can be noted that Q can be turned off any time during State B.

[0020] Performance comparison results are provided, and improvements are described in relation to a simulation. In particular, reduction is possible either in a capacitor size (e.g., less Farads required), or if a capacitor size is held the same, then other parameters can be advantageously adjusted. In some embodiments, reduction in both capacitor size and other parameters are possible. From a practical perspective, these improvements allow for a reduction in cost or complexity, and these savings can then be utilized to improve other performance aspects of the circuit, or power adapter. For example, the circuit proposed herein can be used to improve the power adapter, which includes the DC-DC converter.

[0021] The circuit can be provided in different practical formats, such as a power adapter circuit module, such as one configured for USB type-C power delivery, having a reduced buffering capacitor or increased performance, or both. The accompanying circuits can be coupled together as part of or together as a single package.

[0022] The line power extension circuit can also be contemplated as a standalone circuit, and the accompanying driver and circuit circuits can also be contemplated as standalone circuits. In another embodiment, a plurality of line power extension circuits can be controlled by a central set of driver and control circuits.

[0023] The specific driver and control circuits may include on-board or be coupled with machine interpretable instructions, such as gate control instructions, stored thereon in the form of non-transitory computer readable media or instructions which are executed by a gating control microprocessor to perform the gating control methods.

[0024] Circuit control, for example, can be generated through pulse waveforms generated by a pulse width modulator device that are utilized to control gate operation through changing a voltage at a gate terminal of the switch.DESCRIPTION OF THE FIGURES

[0025] In the figures, embodiments are illustrated by way of example. It is to be expressly understood that the description and figures are only for the purpose of illustration and as an aid to understanding.

[0026] Embodiments will now be described, by way of example only, with reference to the attached figures, wherein in the figures:

[0027] FIG. 1 is a schematic diagram showing a conventional full bridge rectifier without a power factor correction (PFC) in accordance with the prior art.

[0028] FIG. 2 is a two-dimensional graph showing the waveform of the conventional full bridge rectifier shown in FIG. 1 in accordance with the prior art.

[0029] FIG. 3A is a schematic diagram showing an exemplary line power extension circuit, in which an N-channel MOSFET Q is added to the full bridge rectifier.

[0030] FIG. 3B is a schematic diagram showing an isolated view of the MOSFET Q in accordance with the prior art.

[0031] FIG. 4 is a two-dimensional graph showing the waveforms of the line power extension circuit. It is important to note that in the proposed approach, similar performance can be achieved, but the low side approach is able to simplify and improve control and operational aspects.

[0032] FIG. 5A is a schematic diagram showing the power flow in the exemplary line power extension circuit at a State A.

[0033] FIG. 5B is a schematic diagram showing the power flow in the exemplary line power extension circuit at a State B.

[0034] FIG. 5C is a schematic diagram showing the power flow in the exemplary line power extension circuit at a State C.

[0035] FIG. 6 is a schematic diagram highlighting the line extension circuit together with its driver and the sensing circuit.

[0036] FIG. 7 is a two-dimensional graph showing the simulation results of the required capacitance for both the line power extension method and conventional full bridge for different Vbus_min designs and 60 W load.

[0037] FIG. 8 is a two-dimensional graph showing the comparison of the minimum bus voltage between the conventional full bridge and the line extension circuit for different C / nvalues.

[0038] FIG. 9 is a schematic diagram of a conventional full-bridge diode rectifier.

[0039] FIG. 10 illustrates two-dimensional graphs showing the key waveforms of the conventional full-bridge diode rectifier shown in FIG. 9.

[0040] FIG. 11A is a schematic diagram showing an exemplary low-side line power extension circuit.

[0041] FIG. 11B is a schematic diagram showing the complete control and driving architecture of the low-side line power extension circuit shown in FIG. 11 A.

[0042] FIG. 12 is a schematic diagram showing a conventional high-side line power extension circuit.

[0043] FIG. 13 illustrates two-dimensional graphs showing the key waveforms of the low- side line power extension circuit shown in FIGS. 11A and 11B.

[0044] FIG. 14 is a schematic diagram showing a driver circuit #1 for MOSFET Q.

[0045] FIG. 15 illustrates two-dimensional graphs showing the waveforms of the driver circuit #1 shown in FIG. 14.

[0046] FIG. 16 is a schematic diagram showing a driver circuit #2 for MOSFET Q.

[0047] FIG. 17 illustrates two-dimensional graphs showing the waveforms of the driver circuit #2 shown in FIG. 16.

[0048] FIG. 18 is a schematic diagram of an exemplary controller circuit #1.

[0049] FIG. 19 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 18.

[0050] FIG. 20 is a schematic diagram of an exemplary controller circuit #2.

[0051] FIG. 21 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 20.

[0052] FIG. 22 is a schematic diagram of an exemplary controller circuit #3.

[0053] FIG. 23 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 22.

[0054] FIG. 24 is a schematic diagram of an exemplary controller circuit #4.

[0055] FIG. 25 illustrates two-dimensional graphs showing the waveforms of the controller circuit shown in FIG. 24.

[0056] FIG. 26 is a two-dimensional graph showing the simulation results of the required capacitance for both LS-LPEC and conventional full bridge for different Vbus_min designs and 60 W load.

[0057] FIG. 27 is a two-dimensional graph comparing the minimum bus voltage between the conventional full bridge and LS-LPEC for different Cin values.

[0058] FIG. 28 is a two-dimensional graph showing the simulated dynamic performance of LS-LPEC when input AC voltage transitions from 190 Vac to 100 Vac under a constant load power of 65 W.

[0059] FIG. 29 is a two-dimensional graph showing the simulated dynamic performance of LS-LPEC when input AC voltage transitions from 100 Vac to 190 Vac under a constant load power of 65 W.DETAILED DESCRIPTION

[0060] The present application relates to a line power extension circuit and its driving and control method to reduce a capacitor requirement (e.g., size) of AC-DC converters. In particular, a low-side line power extension circuit is proposed (e.g., having a MOSFET switch Q), along with approaches for providing a sensing and control circuit to decide when to turn on and to turn off the switch Q. Relative to an alternate circuit, the Low-Side Line Power Extension Circuit (LS-LPEC) provides different technical characteristics that can be benefit in various scenarios as described herein.

[0061] As shown in FIG. 1 , a diode bridge 100 plus a buffering capacitor is commonly used for AC-DC conversion with no power factor correction requirement. The circuit could be connected to a following stage of DC-DC converter as needed to have a regulated DC voltage. In such case, Cin value is a key design factor because it determines the input voltage range for the DC-DC converter. With a larger capacitor, the bus voltage will be higher, and the operation of DC-DC converter will be more optimized.

[0062] FIG. 2 is a plot 200 that illustrates the waveform of the conventional full bridge rectifier. |vac| is the absolute value of the AC line voltage. VbUSis the voltage on the input capacitor Cin, which is also the bus voltage for the following DC-DC converter. |iacis the absolute value of the input current from the AC line.

[0063] When VbUSis lower than the line voltage, the capacitor will be charged to the peak line voltage. After the peak, Cin will be discharged to power the load before its voltage drops below the line again in the next half line cycle.

[0064] It is noted that in the conventional circuit, the AC line provides power only before its peak, despite the fact that the line voltage remains sufficiently high for usability even after the peak. If the power after the peak can be used, effectively the capacitor discharging time is reduced. Therefore, the required capacitor value can be reduced as well as the size. Alternatively, with the same capacitor value, Vbus_min can be increased, from which the operation of DC-DC converter can benefit.

[0065] An Embodiment of Line Power Extension and its Driver Circuit

[0066] FIG. 3A shows one embodiment of the proposed line power extension circuit 300A, in which an N-channel MOSFET Q 302 is added to the conventional full bridge rectifier.

[0067] In a prior approach, MOSFET Q 302 is connected to the positive end of the bus, and the capacitor is connected to the negative end of the bus, as shown in FIG. 3B. With the connection as shown in FIG. 3B, the source of switch Q (S, as shown in FIG. 3B) is connected to the output of the diode bridge and the drain of switch S (D as shown in FIG. 3B) is connected to the positive terminal of the input capacitor, Cin.

[0068] It is observed that the source terminal of Q (S, as shown in FIG. 3B) is at the highest voltage potential. In order to turn on switch Q, the gate voltage of MOSFET Q 302 (G as shown in FIG. 3B) should be higher than the highest DC voltage. For a typical AC to DC application, this voltage would be close to 400V. Therefore, high voltage, such as 400V, is needed from the control circuit. This increases the circuit complexity and cost.

[0069] This present application contemplates using the circuit as shown in FIG. 3A instead to achieve the same objective with several benefits, as described below, yielding a different set of technical characteristics.

[0070] As shown in FIG. 3A, the positive terminal of input capacitor, Cin, is connected to the output of the diode bridge, (cathode of diode D1 and diode D2), the negative terminal of Cin is connected to the source terminal of Q (S as shown in FIG. 3A). The drain terminal of Q (D as shown in FIG. 3A) is connected to the ground (negative voltage), or the anode of diode D3, and diode D4. Comparing FIG. 3A and FIG. 3B, the difference is that the MOSFET Q 302 is moved from the positive terminal of the input capacitor Cin to the negative terminal of the input capacitor Cin. Therefore, these two circuits will produce the same effect to the overall operation of the AC to DC rectifier, such as shown in FIG. 9, FIG. 11 A.

[0071] In other words, the proposed circuit shown in FIG. 3A will achieve the same performance as the circuit shown in FIG. 3B. However, a core advantage of the circuit of FIG. 3A is that this change will significantly simplify the turn-on and turn-off circuit (also called driver circuit) for MOSFET Q 302, and this is a non-trivial change that yields specifictechnical benefits, improving the performance and operation of the circuit relative to the circuit of FIG. 3B.

[0072] It is noted that in the present application, a MOSFET is used as an example for the switch. Other switches, such as BJT with an anti-parallel diode, an IGBT with an antiparallel diode, etc., can also be used.

[0073] An embodiment of a driver circuit 104 for Q is proposed as well consisting of two resistors Ri and R2, two Zener diodes Dziand DZ2, a low voltage low current switch, shown as MOSFET Q1 in FIG. 3A. A BJT can also be used as Q1 . In other embodiments, R2and Dzican be optional, and Q1 can be other types of switching devices, including but not limited to an NPN BJT, etc.

[0074] FIG. 4 shows the key waveforms 400 of the line power extension circuit as shown in FIG. 3. Vbus is the output voltage of the line power extension circuit, as well as the input voltage for the next stage DC-DC stage, which is well known and is not shown in FIG. 3. |vac| is the absolute value of the AC input. iacis the AC input current. VQgis the gate-source voltage of switch Q. VQigis the gate-source voltage switch Q1.

[0075] The detailed operation in the positive half line cycle is shown in FIG. 5A, FIG. 5B, and FIG. 5C, at 500A, 500B, and 500C. The operation waveforms are shown in FIG. 4. The negative half cycle has a similar operation. In operation, the approach includes turning off the switch Q when the input AC voltage is at peak (t1 in FIG. 13), and it can be noted that Q can be turned off any time during State B.

[0076] State A [to, ti]: Di and D4start to conduct at to, at which time vac rises to equal of Vbus_min (as shown in FIG. 4). From t0to ti, the capacitor voltage will increase with vac. During this process, S is preferred to be turned on to reduce the conduction loss. In an ideal case, MOSFET Q 302 should be turned off at ti , at which the capacitor voltage reaches the peak value. However, in practical implementation, MOSFET Q 102 can be turned off any time between to and ti to avoid late turn-off. Even when MOSFET Q 102 is turned off, the input capacitor, Cin, can still be charged through body diode of MOSFET Q 102 to the peak value of the AC line voltage. The power flow is shown in FIG. 5A as a solid line. The AC current flows through diode Di and D4. Part of the AC current charges Cin and part of the AC current- 10 -RECTIFIED SHEET (RULE 91.1)flows to the input of the DC-DC converter, which is not shown in FIG. 5A, but shown in FIG. 11 B.

[0077] During this state, the gate of Q1 should remain low so that Q1 is off. The gate capacitor of MOSFET Q 102, Cgs, as shown in FIG. 5A, will be charged by the bus voltage through Ri, Zener diode Dz2, and the channel of MOSFET Q 302 (if the MOSFET Q 302 is turned on), or through the body diode of MOSFET Q 302 (Ds, if MOSFET Q 302 is not turned on yet). The gate voltage of MOSFET Q 302 should be clamped by R2and / or Dzi. In case of startup or other cases that S is not conducting, Cgs will be charged through the body diode Ds, and eventually turn on MOSFET Q 302.

[0078] State B [ti, t2]: At ti, MOSFET Q1 302 is turned on so that the gate capacitor of MOSFET Q 302, Cgs, will be discharged through Qi and the channel of Q as long as Q conducts current. When the gate source voltage of Q, Vgs, reaches its threshold voltage, MOSFET Q 302 will be off. Then the gate capacitor will be discharged through R2. When MOSFET Q is turned off at ti , the capacitor is disconnected from the load, thus the capacitor voltage will remain at the peak value of the AC line voltage. The load is powered by the AC line voltage directly during ti to t2, and the AC current equals to the input current drawn by the DC-DC converter, Ide, as shown in FIG. 11 A. Due to this extended conduction time of the line power, iacis lower than the conventional full bridge. During ti to t2, the body diode of S is reverse-biased. The peak voltage stress on MOSFET Q 102 is reached at t2, whose value equals VbUS_max - VbUS_min. The VbUS_max equals to the peak AC line voltage. In practical designs, the voltage stress is below 60 V. Therefore, the voltage rating of MOSFET Q 102 can be as low as 100V or 150V. The voltage stress is much less than 400V, the maximum DC voltage.

[0079] State C [t2, fe]: After t2, vac reduces below the designed Vbus_min. Qi is turned off at t2, so that Cgs is charged again to turn on MOSFET Q 102, and the capacitor energy in Cin is released to load. As the capacitor voltage is maintained at the peak line voltage, Di and D4will be reverse-biased after t2. The capacitor voltage will reduce until equal to vac again at t3, as shown in FIG. 4. In this case, the capacitor value is selected such that the minimum capacitor voltage at t3is equal to the line voltage at t2, both at VbUS_min.

[0080] The operation will be repeated. MOSFET Q 102 is turned off again when the AC line voltage reaches its peak value at t4, as shown in FIG. 4.

[0081] Sensing and Control Logic

[0082] To operate the line extension circuit, it is required to sense the line voltage and / or bus voltage in either analog or digital format. As an example, the sensing circuit 600 shown in FIG. 6 is used to explain the sensing and control strategies. A resistor divider circuit consists of Rsiand Rs2can detect the instantaneous Vusvoltage. With Dsi, Rs3(» Rs2) and Csi, it can be used to detect the peak of the line voltage. The time constant can be as slow as 100ms because the circuit generally does not require fast reaction.

[0083] With the sensed voltage information, the line extension functionality can be enabled when the AC voltage is low, e.g., 100 VAC. For normal operation at 120 VAC, the bus voltage should always be higher than the designed Vbus_min. Thus, there is no need to perform the control. The switch should remain as on, and the circuit is equivalent to the conventional full bridge rectifier.

[0084] While it is straightforward to implement with discrete components, a portion or the entire line extension circuit together with its driver 102, 104 and the sensing circuit, as shown in the box in FIG. 6, can be packaged into an IC with low cost to further improve the simplicity of applications. In practical implementation, there are different approaches, such as using an external MOSFET switch and integrated circuit can be used for all the other circuits.

[0085] Performance Comparison

[0086] With the AC line providing more power, the capacitor does not need to store as much energy as that in the conventional full bridge case, as shown in FIG. 1. Thus, the capacitor value can be reduced while achieving the same bus voltage range. FIG. 7 shows the simulation results 700 of the required capacitance for both the line power extension method 100 and conventional full bridge for different Vbus_min designs and 60 W load.

[0087] If the Vbus min is designed at 50 V, then 37 pF capacitance should be used for conventional full bridge rectifier, while only 15 pF is needed with the line power extension 100. Thus, 59% of capacitor reduction can be achieved for 50 V design. The capacitor reduction ratio will reduce with the VbUS_min increases, as the AC power conduction angle isreduced. In practice, a typical VbUS_min design is 90 V-100 V, at which 1 / 3 of capacitance can be saved with the line extension method.

[0088] If the same capacitance is used, then the VbUS_min can be increased to relieve the wide gain requirement for the following stage. FIG. 8 is a diagram 800 that shows the comparison of the minimum bus voltage between the conventional full bridge rectifier and the line extension method for different Cjnvalues. In some extreme case with a 39 pF capacitor used, then the Vbus_min for the full bridge is only 55 V, while that for the line power extension method is 86 V. Referring to the same VbUS_max of 340 V, the normalized voltage gain requirement is reduced from 6.2 to 4. In other words, the gain requirement reduces to only 64% of that in the full bridge. With the applied Cjnincreases, the conduction angle reduces, thus the line power shows less significance.

[0089] In a practical case, if an 82 pF capacitor is used, then the Vus_min can be increased from 99 V in conventional full bridge to 108 V with the line power extension circuit, which is -10% of improvement. In some topologies, e.g. series resonant converter, this 10% voltage improvement indicates the same amount of current stress reduction. Then, the conduction loss can be reduced to only -80% (= 0.92) of the that in the full bridge case.

[0090] Operation of Conventional Full-Bridge Diode Rectifier

[0091] FIG. 10 is a diagram 1000 that illustrates the key waveforms of the conventional full-bridge diode rectifier 900 shown in FIG. 9. It can be observed that the AC input current conducts only during a portion of the AC half line cycle before it reaches the peak value, which is denoted by 0 in rad. 0 represents the AC power conduction angle. During [cp1 , <p2], the input AC voltage simultaneously provides the power for the DC-DC converter and charges Cin. During [cp2, cp3], the power of the DC-DC converter is supplied by Cin only and the discharging energy of Cin can be described as the following equation:where Facis the AC line frequency (50Hz in Europe, China, and 60Hz in Canada, US) and Pin is the input power of the DC-DC converter, which is also the is the discharging power of C / n. By defining the voltage ratio h asQ can be calculated byThe energy change in C / nwithin half line cycle of the AC voltage isCm can be calculated by

[0092] It can be observed that the required capacitance for C / nis related to the values of maximum and minimum bus voltages (Vbus_max and Vbus_min), AC line frequency Fac, input power Pm, and AC power conduction angle Q. Given a specific voltage ripple, increasing Q lead to a reduced capacitance requirement for C / n. Based on this conclusion, the Low-Side Line Power Extension Circuit (LS-LPEC) is proposed, which modifies the topology of the conventional full-bridge diode rectifier. Specifically, an N-channel MOSFET is added in series with Cm, positioned below it, forming LS-LPEC. This configuration allows for strategic adjustment of the AC power conduction angle, thereby maximizing the utilization of AC input power and reducing the required capacitance for Cm. Corresponding driver and controller circuits are also proposed, aiming to harness the potential of LS-LPEC in a simple, economical, and efficient manner.

[0093] Low-Side Line Power Extension Circuit (LS-LPEC)

[0094] Architecture of LS-LPEC

[0095] FIG. 11A shows the proposed low-side line power extension circuit (LS-LPEC) 1100A. In this figure, an N-channel MOSFET Q is added to the conventional full bridge diode rectifier. The drain terminal of MOSFET Q (D, as shown in FIG. 11 A) is connected to the ground point, which is the negative terminal of the input diode bridge (anode terminal of D3 and D4). The source terminal of MOSFET Q (S, as shown in FIG. 11 A) is connected to the negative terminal of the input capacitor, Cin. The positive terminal of the input capacitor, Cin, is connected to the positive terminal of the diode bridge (cathode terminal of D1 , D2).

[0096] Furthermore, to achieve optimal operation of MOSFET Q, a complete control and driving architecture is also proposed, as depicted in 1100B in FIG. 11B.

[0097] The LS-LPEC and the control and driving architecture are not necessarily provided together in a package, and in a variant, they are provided as standalone circuit packages that can be coupled together. In a further variation, there may be a plurality of interconnected LS-LPEC modules being coupled together with a single control and driving circuit modules. For example, in a first implementation case, the MOSFET switch, control circuit, driver circuit are all integrated into an IC. In a second implementation case, the MOSFET switch is separate, and the control circuit and drivers are integrated into one IC.

[0098] As depicted, a non-isolated driver circuit, powered by the bus voltage (\4US), is employed to regulate the switching states of Q. The voltage of gate (QG) is set to a high level with respect to the voltage of source (Qs) to turn ON Q. Conversely, when Q needs to be turned OFF, the voltage of QG is set to a low level with respect to the voltage of Qs. The ON or OFF logic of Q is determined by the controller circuit. By sampling the input AC voltage (Vac_p and Vac_n) and Vbus, the controller circuit processes this information through logical operations and outputs control signal Vdtv to the driver circuit, thereby determining whether Q should be in an ON or OFF state.

[0099] In a prior approach, MOSFET Q is connected to the positive end of the bus, and the capacitor is connected to the negative end of the bus, as shown in 1200 at FIG. 12. With the connection as shown in FIG. 12, the source of Q (S, as shown in FIG. 12) is connected to the output of the diode bridge and the drain of Q (D, as shown in FIG. 12) is connected to the positive terminal of the input capacitor, Cm. It is observed that the source terminal of Q (S, as shown in FIG. 12) is at the highest voltage potential. In order to turn ON Q, the gatevoltage of Q (G as shown in FIG. 12) should be higher than the highest DC voltage. For a typical AC to DC application, this voltage would be close to 400 V. Therefore, high voltage, such as 400 V, is needed from the driver circuit of MOSFET Q. This increases the circuit complexity and cost.

[0100] One object of the present invention is to use LS-LPEC as shown in FIG. 11A to achieve the same objective described above. It is noted that in the present application, a MOSFET is used as an example for the switch Q. Other switches, such as a BJT with an anti-parallel diode, an IGBT with an anti-parallel diode, etc., can also be used. Comparing FIG. 11A and FIG. 12, the difference is that Q is moved from the positive terminal of the input capacitor C,nto the negative terminal of the input capacitor C / n. Therefore, the operation of these two circuits will be the same. In other words, the proposed circuit shown in FIG. 11A will achieve the same performance as the circuit shown in FIG. 12.

[0101] In practical applications, the maximum value of the drain-source voltage of MOSFET Q in FIG. 11A is typically less than 50 V, representing a reduction from 400V to 50V, or a reduction of 87.5%. This change will significantly simplify the turn-on and turn-off circuit (i.e., driver circuit) for Q.

[0102] Operation Principle and Driver circuit

[0103] FIG. 13 shows the key waveforms 1300 of LS-LPEC as shown in FIG. 11. Vhusis the output voltage of LS-LPEC, as well as the input voltage for the subsequent DC-DC converter. |vac| is the absolute value of the AC input voltage. Van is the voltage across the input capacitor Cm. VQS is the voltage of the source terminal of MOSFET Q. Since the drain terminal of Q is connected to the ground, VQS indicates the voltage stress of Q. irec is the output current of the full bridge diode rectifier. Vgs_Q is the gate-source voltage of Q.

[0104] State A [fa, fi].' Before to, the input AC voltage rises from 0V (at tx, the AC voltage is zero). AC voltage rises from zero (0) at tx, as shown in FIG. 13. Di and O4start to conduct at fa, at which time vacrises to equal of Vbus_min (as shown in FIG. 13). From fa to fa, the input capacitor voltage (Vcin) will increase with vac. During this interval, MOSFET Q is preferred to be turned ON to reduce the conduction loss. In ideal case, Q should be turned OFF at fa, at which the AC voltage and Van reaches its peak value. However, in practical implementation, Q can be turned OFF any time between fa and fa to avoid late turn-off. Even when Q is turnedOFF, the input capacitor, Cm, can still be charged through body diode of Q to the peak value of the AC line voltage. In this specification, the ideal condition is assumed. In other words, MOSFET Q is turned off at t1 , when the AC voltage and Cin voltage reach peak value.

[0105] State B [ti, fe].' When MOSFET Q is turned OFF at ti, when the input AC voltage is at its peak value, the input capacitor is disconnected from the DC-DC converter, thus the capacitor voltage will remain as the peak value of the AC line voltage. The DC-DC converter is powered by the AC line voltage directly during [ , t2], and the AC current equals to the input current of DC-DC converter. Due to this extended conduction angle of the AC input power, irec is lower than the conventional full bridge diode rectifier. During [ , t2], the body diode of Q is reverse-biased. The peak voltage stress across MOSFET Q (the drain to source voltage of Q) is reached at t2, whose value equals Vbus_max - Vbus_mm. Vbus_max equals the peak AC line voltage. In practical designs, the voltage stress is below 50 V. Therefore, the voltage rating of Q can be as low as 100 V or 150 V. The voltage stress is much less than 400 V, the maximum DC voltage.

[0106] State C [t2, f3].‘ At t2, the AC voltage equals to Vbus_min, MOSFET Q is turned ON again. As the input capacitor voltage is maintained at the peak AC line voltage, Di and D4 will be reverse biased after t2. The input capacitor, Cin, will provide the energy to DC-DC converter, and the input capacitor voltage will reduce until equal to vac. At t3, when the input capacitor voltage, Vein equals to the rectified AC voltage, as shown in FIG. 13. In this case, the capacitor value is selected such that the minimum capacitor voltage at fe is equal to the line voltage at t2, both at Vbus_mm. It is noted that the best time (or the most optimal time) to turn on MOSFET Q again is at t2 when the rectified AC voltage value equals Vbus_mm. In practical implementation, MOSFET Q will be turned on again before t2, but close to t2. For example, the MOSFET Q can be turned on 10 to 100 micro-seconds before t2. To summarize, the MOSFET Q will be turned off between to and t1. It is desired that MOSFET Q be turned off at t1 or just before t1 , such as 10 to 100 micro-seconds before t1. MOSFET Q will be turned on again at t2, or just before t2, such as 10 to 100 micro-seconds before t2.

[0107] The operation will be repeated. MOSFET Q is turned OFF again when the AC line voltage reaches its peak value , as shown in FIG. 13.

[0108] The above operation will be repeated at half the AC line cycles, which is 100Hz for 50Hz AC frequency, or 120Hz for 60H AC frequency.

[0109] It can be observed from conventional diode rectifier plus input capacitor circuit, as shown in FIG. 9 and its operating waveforms shown in FIG. 10, that when the magnitude of the instantaneous AC input voltage is higher than the voltage across the input capacitor, Vbus, input diode bridge (D1 , D2, D3, and D4) will be forward biased and the input AC voltage will charge the input capacitor (Cin) and provide all the power drawn by the DC-DC converter. For the conventional full bridge diode rectifier circuit (as shown in FIG. 9), this AC powering period is from <?i to <p2, as shown FIG. 10. At <p2, the input AC voltage reaches its peak value and the input capacitor voltage Vbus also reaches the peak AC voltage value. After <p2, the capacitor voltage Vbus will be higher than the instantaneous AC voltage and therefore, the diode bridge is turned off. Therefore, between <p2and q>3, the power drawn by the DC-DC converter comes from the input capacitor and its voltage reduces, as shown FIG. 10. In other words, the input capacitor discharges during the time period between <p2and q>3.

[0110] The underlying principle of line power extension control is to maximize the utilization of AC input power. For a given minimum bus voltage Vbus_mln, the line power extension control can effectively reduce the required capacitance of Cm. For a predetermined capacitance of Cm, line power extension control enables the boost of the minimum bus voltage Vbus_mm. As shown in FIG. 13, Q represents AC power conduction angle without using line power extension control, while represents the line power extension angle, introduced by the proposed line power extension control. With the help of the proposed technique, the total AC power conduction angle can be extended from Q to Q +During this extended angle (0 + ), the DC-DC converter draws power directly from the AC input through the rectifier diodes, thereby significantly reducing the required discharge energy from the input capacitance C,n. Ideally, the value of should be equal to that of Q, maximizing the energy extracted by the DC-DC converter from the AC input during a half line cycle. In practical applications, the value of may be slightly less than that of Q, depending on the specific implementation of the line power extension circuit.

[0111] It is normally required that an AC to DC power supply should operate normally when the input AC voltage is at 90V rms. The peak value for an 90Vrms AC voltage is 90 x 1.414 = 127V. Therefore, in this case, Vbus_max is 127V. For a typical design case, the valueOf Vbus_min is varied between 85V to 100V. If we assume the VbUS_min value is set at 95V. This means that the DC-DC converter as shown in FIG. 9 should be designed to meet minimum input voltage of 95V.

[0112] As discussed earlier, the angle at t1 is 90 degrees, when the AC voltage reaches peak value. With the above example, when the input voltage reaches to 95V (if we neglect the forward voltage drop of the input diode bridge to simplify the analysis), the diode bridge will be turned on. For 90V rms AC voltage, when <?i equals to 48 degree, its instantaneous AC voltage value is 95V, = 127V x sin (49 degree) = 95.8V, which is very close to 95V. In other words, with the conventional diode bridge + rectifier circuit, as shown in FIG. 9, the input diode bridge will be turned on from 49 degree to 90 degree. The conduction time of the diode bridge is 90 - 49 = 41 degree. After < 2. The diode bridge will be turned off because they are reverse biased. The input capacitor, Cin, will be discharged to provide the power for DC-DC converter. The discharging time is 180 - 41 = 139 degree. In other words, for conventional circuit as shown in FIG. 9, the input capacitor discharges for 139 degree / 180 degree = 77% of the half AC line period. In this case, 180 degree is equivalent to half the AC line cycle.

[0113] As discussed earlier, with the proposed LS-LPEC circuit as shown in FIG. 11 A, FIG. 11 B, the diode bridge will be turned on from to to t2. Comparing between FIG. 10 and FIG. 13, tO in FIG. 13 is equivalent to <pi in FIG. 10 and t1 in FIG. 13 is equivalent to q>2 in FIG. 10.

[0114] If we assume that the minimum bus voltage, Vbus_mm value is still set at 95V, tO corresponds to 49 degree and t1 corresponds to 90 degree. Since at t2, the AC voltage is at Vbus_min which is 95V, t2 corresponds to 131 degree. It is noted that 127V x sin( 131 degree) = 95.8V, which is very close to 95V. Therefore, the (line power extension angle) value is 131 - 90 = 41 degrees. Therefore, with the LS-LPEC circuit, the diode bridge will be turned on from 49 degree to 131 degree. The conduction time of the diode bridge will be 131 - 49 = 82 degrees. From t2 to t3, the diode bridge will be off and input capacitor, Cin, will be discharged to provide power to DC-DC converter. The discharging time is 180 - 82 = 98 degrees, as shown in FIG. 13 (from t2 to t3). In other words, for LS-LPEC circuit as shown in FIG. 11 A, 11 B, the input capacitor discharges for 98 degree / 180 degree = 54% of the half AC line period.

[0115] From the comparison using the above example, discharging time for the LS-LPEC circuit is 98 degrees / 139 degrees = 70% of the conventional diode bridge circuit. Since with same discharging voltage (from Vbus_max = 127V to Vbus_mm = 95V in the above example), the capacitor value depends on the discharging time. It can be concluded that with the LS-LPEX circuit, the input capacitor value, Cin, can be reduced to 70% of the original value when the conventional diode bridge circuit (FIG. 9) is used. In other words, the input capacitor value can be reduced by 30%.

[0116] Similar analysis can be performed for a different Vbus_mm value, such as 90V. In this case, tO in FIG. 13, corresponds to 45 degree and t2 corresponds to 135 degree. This means that with conventional diode bridge, the diode bridge conduction time is 45 degrees (90 - 45) and input capacitor discharging time is 135 degrees (180 - 45). With LS-LPEC circuit (FIG. 11), diode bridge conduction time is 90 degree (135 - 45) and input capacitor discharging time is 90 degrees (180 - 90). Therefore, with LS-LPEC technology proposed in this specification, the capacitor discharging time is 90 degrees / 135 degree = 67% of the conventional diode bridge circuit or the input capacitor value can be reduced by 33%.

[0117] Please note that the above analysis is approximate since it assumes that the capacitor reduction ratio is proportional to the capacitor discharging time. More accurately, the capacitor reduction ratio also depends on the absolute capacitor voltage value.

[0118] From the above discussion I analysis, it is demonstrated that with LS-LPEC technology, as shown in FIG. 11 A, 11B, the conduction time of the diode bridge can be roughly doubled, and the input capacitor value can be reduced by 30 to 35%.

[0119] The term “AC Power Time Interval” is described as the time duration when the DC- DC converter receives the power from input AC voltage through diode bridge, not from the discharging of the input capacitor. For conventional diode bridge rectifier, as shown in FIG. 9, the AC Power Time Interval is shown as angle 0 (Conventional AC Power Conduction Angle) in FIG. 10. While for the proposed LS-LPEC technology, as proposed in this application shown in FIG. 11 , the AC Power Time Interval is shown as angle 0 + <|), as shown in FIG. 13. Considering that <|) (Line Power Extension Angle) is roughly same as the 0, it can be observed that with LS-LPEC technology, the AC Power Time Interval is much longer than the conventional diode bridge rectifier. When AC Power Time Interval is increased the timeinterval that the DC-DC converter receives power from input capacitor, Cin, is significantly reduced. This is another understanding that the value of the input capacitor, Cin, can be significantly reduced with the proposed LS-LPEC technology.

[0120] Another observation from the above analysis I discussion is that when the rms value of the input AC voltage is higher than 90V, such as when the rms value of the AC voltage is 120V. With 120V rms value, the peak voltage is 120 x 1.414 = 170V. In this condition, VbUs_max = 140 x 1.414 = 170V. With conventional diode bridge circuit, as shown in FIG. 9, The Vbus_mm is estimated at around 140V, which is higher than minimum input voltage of the DC-DC converter (90V or 95V in the above discussion). In other words, when input AC voltage is higher, LS-LPEC circuit is not needed. In this case, the MOSFET Q is turned on all the time. This will simplify the design and operation of the LS-LPEC circuit.

[0121] Therefore, one strategy in the practical operation is to disable the operation LS- LPEC circuit when the input AC voltage is higher, such as the input AC voltage is above 110V. Equivalently, when input AC voltage is higher than a design value, the MOSFET Q is turned on all the time.

[0122] The present application contemplates two major technology advancements and their corresponding sub-developments and variations.

[0123] The first technology is to move the MOSFET (Q) that is connected in series with the input capacitor from above the capacitor Cin to below Cin. With the new connection, the drain terminal of MOSFET Q (D, as shown in FIG. 11 A) is connected to the ground point, which is the negative terminal of the input diode bridge (anode terminal of D3 and D4). The source terminal of MOSFET Q (S, as shown in FIG. 11 A) is connected to the negative terminal of the input capacitor, Cin. The positive terminal of the input capacitor, Cin, is connected to the positive terminal of the diode bridge (cathode terminal of D1 , D2). As discussed above, the major benefit is that we do not need a voltage higher than the peak value of the input AC voltage to turn on MOSFET Q. This can significantly reduce the complexity and cost of the driver circuit. In the present application, two possible driver circuits for MOSFET Q have been proposed. None of these two circuits requires a voltage higher than peak value AC voltage. Other similar driver circuits can be developed to achieve the same objective.

[0124] The second technology proposed is the method to generate the gate driver signal for MOSFET Q. Four sensing and control logic circuits are proposed in the present application. In order to achieve the optimal (desired) operation, the MOSFET Q (as shown in FIG. 11) is turned on for most of the AC line cycles. As shown in FIG. 12, it is optimal (desired) that the MOSFET Q is turned off at 90 degrees (t1 as shown in FIG. 13), when the AC voltage reaches the peak value. Under this condition, Cin is charged to the peak value of the AC voltage. It is also optimal (desired) that MOSFET Q is turned on again at t2 (as shown in FIG. 13), when the instantaneous AC voltage value falls to Vbus_min. These four sensing and control logic circuits proposed in the present application use the information of the AC voltage value and DC bus voltage value (Vbus) to find the optimal (or near optimal) turn off and turn on time instant for MOSFET Q.

[0125] An embodiment including a driver circuit #1 for MOSFET Q is shown in circuit 1400 of FIG. 14. Terminal connections of QG, QS, Vbus, GND, and \4 / ,v Can be found in FIG. 11. In this embodiment, the driver circuit includes two resistors F?i and F?2, two Zener diodes Dzi and DZ2, and a low-voltage low-current switch, shown as N-channel MOSFET Qi in FIG. 14. A BJT can also be used as Qi. In other embodiments, R2 and Dzi can be optional, and Qi can be other types of switching devices, including but not limited to an NPN BJT, etc.

[0126] Turn-Off operation of Q in driver circuit #1 : The ON and OFF states of MOSFET Q are controlled by the driver input signal dn, which is also the gate-source signal of MOSFET Qi. As shown in the waveforms 1500 of FIG. 15, during [to, ti], dn is set to high level to turn OFF Q. In this case, Qi is turned ON, and the gate capacitor of Q, Cgs, will be discharged through Qi and the channel of Q as long as Q conducts current. When the gatesource voltage of Q,gs_Q, falls below its threshold voltage, Q will be switched OFF. During [to, fi], VQSand VQGincrease in the reverse direction, indicating that DZ2is reverse-biased when Qi is turned ON (i.e. , Q is turned OFF). The voltage stress of DZ2reaches its maximum value at fi as shown in FIG. 15, which isbus_max -bUs_min- Hence, to ensure the reliable turnoff of Q, the minimum clamp voltage of DZ2, denoted by V z2_min, should meet the following relationship:

[0127] For example, if b us_max " Vbus_min is 50V, the breakdown voltage of Zener diode Dz2 should be higher than 50V, such as 55V.

[0128] Turn-On operation of Q in driver circuit #1 : As shown in FIG. 15, during [fi, fe], Vdrv is set to low level to turn ON MOSFET Q. The gate-source capacitor of Q, Cgs, as shown in FIG. 14, will be charged by the bus voltage through F?i, Dzi, and the channel of Q (if Q is turned ON), or through the body diode of Q {Db, if Q is not turned ON yet). The gate-source voltage of Q should be clamped by R2and / or DZi. FIG. 15, corresponds to the operating scenario where the gate-source voltage of Q is clamped by Dzi. In case of startup or other cases where Q is not conducting, Cgswill be charged through the body diode Db, and eventually turn ON Q. To ensure the reliable turn-on of Q, the maximum clamp voltage of DZ2, denoted by Vbz2_max, should meet the following relationship:When MOSFET Qi is in the OFF state, the voltage stress applied to Qi can be calculated as follows:^gl=^gs_Q+^Dz2 (8)

[0129] In practical designs, the clamp voltage of Dzi is typically selected to be slightly higher than Vozi mn. For a 65 W LISB-PD adapter, the maximum difference between \ / bus_max and / bus_min is below 50 V. Hence, a 60 V Dzi can be employed to ensure the reliable turnon and -off of MOSFET Q. In(8), the maximum value of Vgs_Q is determined by the clamp voltage of Dzi, which is typically less than 15 V. Hence, the voltage rating of MOSFET Qi can be as low as 100 V or 150 V for a 65 W LISB-PD adapter.

[0130] An embodiment including a driver circuit #2 for MOSFET Q 1600 is shown in FIG. 16. In this embodiment, the driver circuit includes two resistors, F?i and R2, a Zener diode Dzi, a low-voltage low-current diode O5, and two low-voltage low-current switches represented by the N-channel MOSFET Q2and the P-channel MOSFET Q3. In other embodiments, R2and Dzi may be optional components, and Q2and Q3can be substituted with other types of switching devices, including but not limited to a BJT, etc.

[0131] Turn-Off operation of Q in driver circuit #2 FIG. 17 showing waveforms 1700 is used to help the explanation of this paragraph. The ON and OFF states of MOSFETs Q2 and Q3 are controlled by the driver input signal Vdtv. Due to the N-channel property of MOSFET Q2, it will conduct when Vdtv is set to a high level. Conversely, the P-channel nature of MOSFET Q3 causes it to conduct when Vdtv is set to a low level. In other words, a high- level dt corresponds to the turning-on of Q2and the turning-off of Q3. Conversely, a low- level dtv corresponds to the turning-off of Q2and the turning-on of Q3. As shown in FIG. 17, during [fo, fi], dt is set to high level to turn OFF Q. In this case, Q2 is kept ON while Q3 is kept OFF. The gate capacitor of Q, Cgs, will be discharged through Qi and the channel of Q as long as Q conducts current. When the gate source voltage of Q, Vgs_Q, reaches its threshold voltage, Q will be switched OFF. As shown in FIG. 16, the Anode of D5is connected to VQG, while its cathode is connected to VQ2. Hence, during [to, fi], Ds is reverse- biased. The voltage stress of 5 reaches its maximum value at fi, which is Vb us_max ~ Vbus_min ■ As mentioned earlier, the voltage stress is below 50 V in practical designs. Therefore, the voltage rating of 5 can be as low as 100V or 150V. The voltage rating of MOSFET Q3 is dominated by Vbus_max, which is around 141 V when the AC input voltage is 100 Vac. As it is desired that LS-LPEC is only activated when the AC input voltage is low (e.g., 100 Vac), the voltage rating of Q3 can be as low as 200 V.

[0132] Turn-On operation of Q in driver circuit #2. As shown in FIG. 17, during [ , fe], Vdtv is set to low level to turn ON MOSFET Q. In this case, MOSFET Q2 is kept in the OFF state, while MOSFET Q3 is kept in the ON state. The gate capacitor of Q, Cgs, as shown in FIG. 16, will be charged by the bus voltage through F?i, Q3, and the channel of Q (if Q is turned ON), or through the body diode of Q (Dft, if Q is not turned ON yet). The gate voltage of Q should be clamped by R2and / orZi. FIG. 17 corresponds to the operating scenario where the gate-source voltage of Q is clamped byZi. In case of startup or other cases where Q is not conducting, Cgswill be charged through the body diode Db, and eventually turn ON Q. The peak voltage stress on Q2is dominated by the gate-source voltage of Q (Vgs_Q), which is less than 15 V. Hence, the voltage rating of Q2can be as low as 40 V or 60 V.

[0133] SENSING AND CONTROL LOGIC

[0134] To operate LS-LPEC, it is required to sense the line voltage and / or bus voltage in either analog or digital format. FIG. 18 gives the schematic diagram 1800 of the proposed controller circuit #1. In this figure, the circuit A in the controller circuit is used to determine the operation mode of the control circuit, i.e., whether LS-LPEC is required.

[0135] By sampling the bus voltage Vbus and comparing it with a preset value Vre / 3, the enable signal VENfor LS-LPEC is generated. Employing a low-bandwidth low-pass filter enables the detection of the peak of the line voltage. If an RC circuit is employed to implement the low-pass filter, the time constant can be as slow as 100 ms, as the circuit typically does not necessitate fast reactions. For normal operation at, e.g., 120 Vac, the bus voltage should always be higher than the designed Vbus_min- Thus, there is no need to activate LS-LPEC. In this scenario, the VENsignal is set high, maintaining MOSFET Q in the ON state, and the circuit functions identically to a conventional full-bridge diode rectifier.

[0136] LS-LPEC is activated when the magnitude of the AC voltage is low, i.e., below Vbus_min , such as 100 Vac. In this case, the VENsignal is set low, and circuit B in FIG. 18 is utilized to determine the ON / OFF timing of MOSFET Q. In other words, the output signal (Vdnz) of the controller circuit is solely determined by Vctri signal. FIG. 19 illustrates the conceptual waveforms 1900 of circuit B shown in FIG. 18.

[0137] The instantaneous value of AC input voltage, denoted as Vacjnst, is sensed and compared with two reference values Vreri and V The outputs of two comparators are fed to a rising-edge-triggered RS flip-flop. As shown in FIG. 19, right after to, Vac_inst exceeds Vref2, triggering the Reset of the flip-flop (V2). This results in a low level of Vcw and a high level of the controller output VW With the help of the proposed driver circuit, MOSFET Q is turned OFF, allowing for an extended AC power conduction time until ti. Right after , Vacjnst falls below \ / ren, and the Set of the flip-flop (Vi) is triggered, leading to high level of \ / cw and low level of the controller output Vdrv. With the help of the proposed driver circuit, MOSFET Q is turned ON, and the DC-DC converter is provided by input capacitor only until t2, at which point MOSFET Q is turned OFF once again.

[0138] Ideally, Q should be turned OFF at the line voltage peak (i.e., VW_max), after which the line will power the DC-DC converter directly. Hence, Vre / 2 should be selected as close to the peak value of Vacjnst as possible while ensuring an adequate margin. The turn-on timingof Q occurs when the magnitude of the line voltage decreases to a predetermined Vbus_min, which can be adjusted by modifying the value of VW

[0139] FIG. 20 gives the schematic diagram 2000 of the proposed controller circuit #2. In this figure, the controller includes circuit A, which is the same as the one shown in FIG. 18. The difference between FIG. 20 and FIG. 18 in the controller circuit lies in the implementation of circuit B. The basic idea of circuit B in FIG. 20 involves estimating the moment when the AC input voltage equals its peak voltage and subsequently generating a fixed delay time to control the activation time of MOSFET Q (refer to fe in FIG. 13).

[0140] FIG. 21 illustrates the conceptual waveforms 2100 of circuit B shown in FIG. 20. \ / ii represents the output signal of the AC voltage sensing circuit, which reflects the instantaneous absolute value of the AC input voltage. After a peak detector circuit PD1 , Vu is fed to the negative input of comparator 111 , represented by W Simultaneously, it is also fed to the positive input of comparator 111. At to, both \ / i2 and Vu reach their maximum values.

[0141] Due to the voltage drop introduced by the diode within PD1 , the maximum value of \ / i2 is slightly lower than that of Vu. After to, Vu follows Vac, decreasing sinusoidally. Meanwhile, \ / i2 decreases very slowly due to the delay effect introduced by PD1. Typically, the RC circuit within PD1 should have a large time constant to effectively function as a sample and hold circuit. The time constant should be 3 to 5 times 1 I 120 Hz. At , Vu reaches VW

[0142] The delay time from to to fi is denoted as tdeiayu Right after fi, Vu becomes lower than VW resulting in the low level of W (output signal of comparator 111). Following another peak detector circuit PD2, W is fed to the positive input of comparator LI2, represented by Vu- By comparing Vu with a fixed reference voltage VW a fixed delay time, denoted as tdeiay2, is generated. After tdeiay2, at t2, Vdrvis set to a low level, turning ON MOSFET Q, and the bus voltage is boosted to its maximum value Vbus-max. MOSFET Q remains ON until t3, from which time \Zi2and Vu both begin to rise until t4when t / 12and Vu reach their maximum values once again. The time duration of t4- t3, as well as tdeiayu can be considered equal due to the sample and hold nature of PD1 . In practice, this time duration should be minimized soas to minimize the conduction time of MOSFET Q’s body diode, thereby increasing circuit efficiency.

[0143] To make sure that MOSFET Q can be turned ON at the designed minimum bus voltage Vbus_mm, tdeiayi and tdeiay2 should be carefully addressed as the turn-on timing of Q is determined by fde / ayi+ tdeiay2- tdeiay can be minimized by selecting a low forward voltage drop diode within PD1. tdeiay2 can be adjusted by altering the time constant of the RC circuit within PD2 or by modifying the value of Vref4-

[0144] While it is straightforward to implement with discrete components, the entire line extension circuit together with its driver and the controller can be packaged into an IC with low cost to further improve the simplicity of applications.

[0145] It is noted that the above two sensing and control logic circuits use the actual AC voltage value and the actual DC bus voltage value (VbUS) to determine the turn on and turn off time instant for MOSFET Q. They can achieve very accurate control of the timing. If a less accurate timing is acceptable, a third and much simpler sensing and control logic circuit can be proposed as shown in diagram 2200 of FIG. 22. In this figure, circuit B includes three control units: a peak detect circuit, a delay circuit, and a NOT gate. VPk represents the output signal of the peak detect circuit, indicating the moment when the input AC voltage reaches its peak value. VPk is typically a narrow pulse lasting from nanoseconds to microseconds. After passing through the delay circuit, the high-level duration of VPk is extended to the millisecond range. The specific delay time can be pre-set according to the requirements. VPk_deiay represents the output signal of the delay circuit, which is used to generate the Vctd signal after passing through a NOT gate. FIG. 23 illustrates the conceptual waveforms 2300 of circuit B shown in FIG. 22. The working principle can be summarized as follows:

[0146] Step 1 : At t0, the peak value of the AC voltage is detected. At this moment, Vpkand VPk_deiay are set to high level, while Vctn is set to low level. MOSFET Q is turned OFF at t0.

[0147] Step 2: From t0to fi, the delay circuit extends the high-level duration of Vpkto the millisecond range, which is represented by the predetermined delay time shown in FIG. 23.

[0148] Step 3: At fi, Vpk_deiay returns to the low level. At this point, the Vctn signal is set to high level, and the Vdrvsignal is set to low. The driving signal Vgs_Q of MOSFET Q is set high,and MOSFET Q is turned on again. Because MOSFET Q remains OFF state during the delay time (from to to t1) generated by the delay circuit, line power extension can be achieved. The delay time generated by the delay circuit can be adjusted as needed, such as setting it to 2 milliseconds for a 60 Hz AC system.

[0149] In some cases, the NOT gate of circuit B in FIG. 22 can be removed, as shown in circuit 2400 of FIG. 24. FIG. 25 illustrates the conceptual waveforms 2500 of circuit B shown in FIG. 24. In this scenario, the falling edge of the Vpksignal is utilized to signify the moment when the input AC voltage reaches its peak value. The duration of the Vpksignal's low level typically ranges from nanoseconds to microseconds. The delay circuit is employed to prolong the low level duration of the Vpksignal to the millisecond range (such as 1 millisecond to 3 millisecond), thereby generating the Vctrisignal. As MOSFET Q remains OFF during the delay time generated by the delay circuit, line power extension can be achieved.

[0150] Simulation Verification

[0151] Performance Comparison Between Circuits with and without LS-LPEC

[0152] With the AC line providing more power, the capacitor does not need to store as much energy as that in the full bridge case. Thus, the capacitor value can be reduced while achieving the same bus voltage range. FIG. 26 shows the simulation results 2600 of the required capacitance for both LS-LPEC and conventional full bridge for different Vbus_mm designs and 60 W load.

[0153] If the Vbus_min is designed at 50 V, then 37 pF capacitance should be used for full bridge, while only 15 pF is needed with LS-LPEC. Thus, 59% of capacitor reduction can be achieved for 50 V design. The capacitor reduction ratio will reduce with the Vbus_mm increases, as the AC power conduction angle is reduced. In practice, a typical Vbus_mm design is 90 V- 100 V, at which 1 / 3 of capacitance can be saved with LS-LPEC.

[0154] If the same capacitance is used, then the VbUs_min can be increased to relieve the wide gain requirement for the following DC-DC converter. FIG. 27 shows the comparison plot 2700 of the minimum bus voltage between the conventional full bridge and LS-LPEC for different C / nvalues. In some extreme case with a 39 pF capacitor used, then the VbUs_min for the conventional full bridge is only 55 V, while that for LS-LPEC is 86 V. Referring to thesame Vbus_max of 340 V, the normalized voltage gain requirement is reduced from 6.2 to 4. In other words, the gain requirement reduces to only 64% of that in the full bridge. With the applied C / nincreases, the conduction angle reduces, thus the line power shows less significance.

[0155] In a practical case, if an 82 pF capacitor is used, then the Vbus_min can be increased from 99 V in the conventional full bridge to 108 V with LS-LPEC, which is around 10% of improvement. In some topologies, e.g. series resonant converter, this 10% voltage improvement indicates the same amount of current stress reduction. Then, the conduction loss can be reduced to roughly 80% (= 0.922) of the that in the full bridge case.

[0156] Dynamic Simulation of LS-LPEC

[0157] FIG. 28 is a plot 2800 that illustrates the simulated dynamic performance of LS- LPEC when the input AC voltage transitions from 190 Vac to 100 Vac under a constant load power of 65 W. In this figure, to represents the moment when the AC input voltage undergoes a step-down change. At to, Vbus starts to decrease. By fi, Vbus equals vac, from which point the circuit operates as a conventional full-bridge diode rectifier until time fe. After fe, LS-LPEC is activated, allowing for an increase in the minimum bus voltage from 85 V to 100 V.

[0158] FIG. 29 is a plot 2900 that gives the simulated dynamic performance of LS-LPEC when the input AC voltage jumps from 100 Vac to 190 Vac at a constant load power of 65 W. In this figure, txrepresents the moment when the AC input voltage undergoes a step-up change. After tx, circuit A shown in FIG. 18 (or FIG. 20) operates to disable LS-LPEC. The circuit then operates equivalently to a conventional full-bridge diode rectifier.

[0159] Applicant notes that the described embodiments and examples are illustrative and non-limiting. Practical implementation of the features may incorporate a combination of some or all of the aspects, and features described herein should not be taken as indications of future or existing product plans. Applicant partakes in both foundational and applied research, and in some cases, the features described are developed on an exploratory basis.

[0160] The term “connected” or "coupled to" may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

[0161] Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification.

[0162] As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0163] As can be understood, the examples described above and illustrated are intended to be exemplary only.

Claims

WHAT IS CLAIMED IS:

1. A power converter circuit, comprising: a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch Q, and a drain terminal of the switch Q is connected to the second output terminal.

2. The power converter circuit of claim 1 , wherein the series circuit extends a total AC power conduction angle to Q + where the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein Q is defined as an AC power conduction angle, and is defined as the line power extension angle introduced through switched control of the series circuit.

3. The power converter circuit of claim 2, wherein the value of is approximately equal to e.

4. The power converter circuit of claim 1 , further comprising a controller circuit that controls the switch so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch is turned off, and then decreases to the selected DC bus voltage when the switch is turned on; and wherein the switch has a gate terminal controlled by the controller circuit, the controller circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

5. The power converter circuit of claim 4, wherein the controller circuit is configured to establish at least three different control approaches during a number of correspondingtime periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is at an on state during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus_min.

6. The power converter circuit of claim 5, wherein the first, second, and third state of operation are repeated during operation.

7. The power converter circuit of claim 5, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

8. The power converter circuit of claim 5, wherein during the second state of operation, a line power extension angle is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

9. The power converter circuit of claim 8, wherein the line power extension angle is approximately equal to a AC power conduction angle Q.

10. The power converter circuit of claim 5, further comprising a voltage sensing circuit configured to track an AC voltage value and a DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.11 . A controller device configured for operation with one or more power converter circuits each including a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; and a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminalof the switch, and a drain terminal of the switch is connected to the second output terminal; the controller device including a: a logic circuit that is configured to control the switch so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch Q is turned on, and then decreases to the selected DC bus voltage.

12. The controller device of claim 11 , wherein the series circuit extends a total AC power conduction angle to Q + when the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein Q is defined as an AC power conduction angle, and is defined as the line power extension angle introduced through switched control of the series circuit.

13. The controller device of claim 12, wherein the value of is approximately equal to Q.

14. The controller device of claim 1 , wherein the switch has a gate terminal controlled by the logic circuit, the logic circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

15. The controller device of claim 11 , wherein the logic circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is switched on during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus_min.

16. The controller device of claim 15, wherein the first, second, and third state of operation are repeated during operation.

17. The controller device of claim 15, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

18. The controller device of claim 15, wherein during the second state of operation, a line power extension angle is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

19. The controller device of claim 15, further comprising a voltage sensing circuit configured to track an actual AC voltage value and an actual DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.

20. The controller device of claim 19, further comprising a voltage sensing circuit configured to track an estimated AC voltage value and an estimated DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation, the estimated AC voltage value and the estimated DC voltage value detected using a peak detection circuit, a delay circuit, and a NOT gate operating in concert.

21. A method for power conversion, comprising: operating a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; and operating a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch Q, and a drain terminal of the switch Q is connected to the second output terminal.

22. The method of claim 21 , wherein the series circuit extends a total AC power conduction angle to Q + where the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein Q is defined as an AC power conductionangle, and is defined as the line power extension angle introduced through switched control of the series circuit.

23. The method of claim 22, wherein the value of is approximately equal to 0.

24. The method of claim 21 , further comprising controlling the switch, using a controller circuit, so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch is turned off, and then decreases to the selected DC bus voltage when the switch is turned on; and wherein the switch has a gate terminal controlled by the controller circuit, the controller circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

25. The method of claim 24, wherein the controller circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is at an on state during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus_min.

26. The method of claim 25, wherein the first, second, and third state of operation are repeated during operation.

27. The method of claim 25, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

28. The method of claim 25, wherein during the second state of operation, a line power extension angle is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

29. The method of claim 28, wherein the line power extension angle is approximately equal to a AC power conduction angle Q.

30. The power converter circuit of claim 25, further comprising tracking, by a voltage sensing circuit, an AC voltage value and a DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.31 . A control method configured for operation with one or more power converter circuits each including a rectifier circuit having first and second input terminals that receive an AC input voltage from an AC input (Vac), and first and second output terminals that output a DC bus voltage (Vbus) to a DC-DC converter circuit; and a series circuit connected across the first and second output terminals, the series circuit consisting of a switch Q and a capacitor, wherein a first terminal of the capacitor is connected to the first output terminal, and a second terminal of the capacitor is connected to a source terminal of the switch, and a drain terminal of the switch is connected to the second output terminal; the method including a: controlling, by a logic circuit, the switch so that the switch is turned on when a magnitude of the AC input voltage decreases to a selected DC bus voltage, and the switch is off during a period when the magnitude of the AC input voltage is greater than the selected DC bus voltage and less than a peak value of the AC input voltage; wherein the DC bus voltage increases to a maximum magnitude of the AC input voltage when the switch Q is turned on, and then decreases to the selected DC bus voltage.

32. The method of claim 31 , wherein the series circuit extends a total AC power conduction angle to Q + when the DC-DC converter circuit draws power directly from the AC input through diodes of the rectifier circuit; wherein Q is defined as an AC power conduction angle, and is defined as the line power extension angle introduced through switched control of the series circuit.

33. The method of claim 32, wherein the value of is approximately equal to 0.

34. The method of claim 31 , wherein the switch has a gate terminal controlled by the logic circuit, the logic circuit configured for controlling the operation of the switch through a series of control signals that control a state of a gate corresponding to the gate terminal of the switch.

35. The method of claim 31 , wherein the logic circuit is configured to establish at least three different control approaches during a number of corresponding time periods, including a first state of operation (State A), a second state of operation (State B), and a third state of operation (State C), the first state of operation (State A) where the switch Q is switched on during a portion of or an entirety of a first time period when Vac is rising to equal a minimum Vbus, Vbus_min, and the input capacitor voltage is also rising, the second state of operation (State B) where the switch Q is switched off any time during a second time period following the first time period; and the third state of operation (State C) where the switch Q is switched on during a third time period following the second time period triggered by Vbus reaching the Vbus_min.

36. The method of claim 35, wherein the first, second, and third state of operation are repeated during operation.

37. The method of claim 35, wherein the switch Q is switched off when an AC line voltage reaches its peak value.

38. The method of claim 35, wherein during the second state of operation, a line power extension angle is imparted such that the power converter draws power directly from the AC input through the rectifier diodes of the rectifier circuit.

39. The method of claim 35, further comprising a voltage sensing circuit configured to track an actual AC voltage value and an actual DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation.

40. The method of claim 39, further comprising a voltage sensing circuit configured to track an estimated AC voltage value and an estimated DC bus voltage value for determining switch transition times for switching between the first state of operation, the second state of operation, and the third state of operation, the estimated AC voltage value and theestimated DC voltage value detected using a peak detection circuit, a delay circuit, and a NOT gate operating in concert.

41. The power converter circuit of any one of claims 1-10 further comprising a DC-DC converter.

42. The controller device circuit of any one of claims 11-20 further comprising a DC-DC converter.

43. A non-transitory machine readable medium storing machine interpretable instructions, which when executed by a processor, cause the processor to perform a method according to any one of claims 21-40.

Images