Distributed quantum chip detection method and apparatus, terminal, and storage medium

Abstract

Disclosed are a distributed quantum chip detection method and apparatus, a terminal, and a storage medium. According to the method, by means of establishing a distributed quantum chip architecture, incomplete sensing of cosmic ray events by a single-chip structure is avoided, ensuring the feasibility of small-flux cosmic ray event detection. Cascade encoding is performed on quantum bits in different chips within the quantum chip architecture on the basis of quantum error correction codes, and detection is performed in view of the distributed quantum chip structure, so that the source of chip-level global errors can be effectively determined, thereby avoiding the disadvantage in conventional methods that quantum error correction codes cannot detect and correct chip-level globally correlated errors, and ensuring the effectiveness of the quantum error correction codes. At the current technological level, the invention effectively solves the problem of how to ensure the accuracy of large-scale quantum computing tasks when the scale and operational accuracy level requirements of a quantum chip system cannot be reduced.

Description

A distributed quantum chip detection method, device, terminal and storage medium Technical Field

[0001] The present invention relates to the fields of quantum detection and quantum error correction, and in particular to a distributed quantum chip detection method, device, terminal and storage medium. Background Art

[0002] Superconducting quantum computers usually require extremely low temperatures and extremely high vacuum environments to maintain the stability and coherence of quantum bits. In practical applications, superconducting quantum computers need to operate in a highly controlled laboratory environment to reduce external noise and interference. The system inevitably requires coupling the quantum system with an external system in order to control or measure the quantum system. Quantum error correction technology is a method used to detect and correct errors in quantum bits, thereby improving the accuracy and stability of quantum computing. It encodes the original quantum bit information into a large Hilbert space and uses check bits to detect and correct physical errors of limited density. It is one of the necessary technologies for realizing large-scale quantum computing in the future. However, quantum error correction codes usually make the following assumptions about the error model:

[0003] 1. Physical quantum bits will be disturbed by local noise with a certain probability, but this interference only affects a single or multiple quantum bits within a short range.

[0004] 2. Quantum error correction codes need to use the entanglement between quantum bits to encode and protect quantum information. Quantum error correction can only be used normally if the quantum entanglement between bits is not destroyed.

[0005] Recent research has found that the effects of cosmic rays and background radiation from environmental materials can affect most or all qubits on a single chip, causing non-local correlation errors across the entire chip. These errors cannot be effectively detected and corrected by common error-correcting codes, which can have a catastrophic impact on the performance of quantum error-correcting codes. For example, studies have shown that cosmic ray events can significantly accelerate qubit energy relaxation and can also cause frequency jumps in two-level systems across the entire chip, leading to phase decay of the qubits. Research speculates that qubit sensitivity to radiation may be related to factors such as experimental materials, packaging, and system architecture.

[0006] An existing distributed quantum error correction scheme employs hierarchical encoding across a distributed chip network. Errors in the first-level surface code reveal the location of cosmic rays, which are then corrected by a second-level quantum error correction code. This approach mitigates the destructive effects of catastrophic chip-level errors and protects quantum information. However, this approach places extremely high demands on the scale and operational capabilities of quantum chip systems, requiring implementation on the basis of fault-tolerant quantum computing. Another approach currently exists, which involves preparing all bits in excited states and detecting them by their energy relaxation time. However, this approach is limited in the types of errors it can detect and cannot clearly establish correlations. Therefore, in the noisy, medium-scale quantum era, fault-tolerant quantum error correction in multi-qubit systems remains challenging due to the limited fidelity of gate sequences and the size constraints of quantum chips.

[0007] Therefore, the existing technology still needs to be improved and developed.

[0008] Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a distributed quantum chip detection method, device, terminal and storage medium in response to the above-mentioned defects of the existing technology, aiming to solve the problem in the existing technology that it is impossible to ensure the accuracy of large-scale quantum computing task detection while reducing the scale and operation level requirements of the quantum chip system.

[0010] The technical solutions adopted by the present invention to solve the problem are as follows:

[0011] In a first aspect, an embodiment of the present invention provides a distributed quantum chip detection method, wherein the method includes:

[0012] Establishing a distributed quantum chip architecture, wherein each chip in the quantum chip architecture includes a number of qubits, including computational qubits and signal qubits;

[0013] Obtaining a plurality of quantum error correction codes, and repeatedly cascading encoding the computational qubits in different chips in the quantum chip architecture according to each of the quantum error correction codes;

[0014] Detecting the encoded signal qubits in the quantum chip architecture to determine the amplitude damping channel measurement results and the phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code;

[0015] A detection result of the chip is determined according to the quantum error correction code, the amplitude damping measurement result, and the phase damping channel measurement result.

[0016] In one implementation method, detecting the encoded signal qubits in the quantum chip architecture to determine the amplitude damping channel measurement results and the phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code includes:

[0017] Constructing a plurality of target stabilizers according to the quantum error correction code and the signal qubit on the chip, wherein any target stabilizer corresponds to a plurality of the signal qubits on different chips;

[0018] Non-destructive measurement is performed on each target stabilizer to determine the amplitude damping channel measurement result and the phase damping channel measurement result corresponding to each quantum circuit of the quantum error correction code.

[0019] In one implementation method, determining a detection result of the chip according to the quantum error correction code, the amplitude damping measurement result, and the phase damping channel measurement result includes:

[0020] Determine an error feature table corresponding to the quantum error correction code according to the quantum error correction code;

[0021] Comparing the amplitude damping channel measurement result and the phase damping channel measurement result with the error feature table respectively to determine the detection result of the chip;

[0022] In one implementation method, comparing the amplitude damping channel measurement result and the phase damping channel measurement result with the error signature table to determine the chip detection result includes:

[0023] The amplitude damping channel measurement results and the phase damping channel measurement results are respectively compared with the error feature table to determine whether an error occurs in each of the calculation quantum bits. If no error occurs in the calculation quantum bit, it is determined that the detection result of the chip is that there is no cosmic ray event.

[0024] In one implementation, the method further includes:

[0025] If an error occurs in the calculation quantum bit, obtaining the chip position corresponding to the calculation quantum bit;

[0026] Determining the number of erroneously calculated quantum bits corresponding to each chip according to the chip position;

[0027] If the number of erroneously calculated quantum bits corresponding to any of the chips is greater than or equal to a preset number, it is determined that the detection result of the chip is that a cosmic ray event exists.

[0028] In one implementation, the method further includes:

[0029] If the number of erroneously calculated quantum bits corresponding to any of the chips is less than the preset number, the chip corresponding to the erroneously calculated quantum bit is initialized, and the detection result of the chip is determined to be that there is no cosmic ray event.

[0030] In one implementation, the method further includes:

[0031] When the detection result of the chip is that there is no cosmic ray event, the step of detecting the signal quantum bits in the encoded quantum chip architecture is continued after each preset time interval until the detection result of the chip is that there is a cosmic ray event.

[0032] In a second aspect, an embodiment of the present invention further provides a distributed quantum chip detection device, wherein the distributed quantum chip detection device includes:

[0033] A quantum chip architecture building module, configured to establish a distributed quantum chip architecture, wherein each chip in the quantum chip architecture includes a number of qubits, including computational qubits and signal qubits;

[0034] a computational quantum bit encoding module, configured to obtain a plurality of quantum error correction codes and repeatedly concatenate and encode the computational quantum bits in different chips in the quantum chip architecture according to each of the quantum error correction codes;

[0035] A signal qubit detection module is used to detect the signal qubits in the encoded quantum chip architecture and determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code;

[0036] A detection result determination module is used to determine the detection result of the chip according to the quantum error correction code, the amplitude damping measurement result and the phase damping channel measurement result.

[0037] In a third aspect, an embodiment of the present invention further provides a terminal, characterized in that the terminal includes a memory and one or more processors; the memory stores one or more programs; the program includes instructions for executing any of the distributed quantum chip detection methods described above; and the processor is used to execute the program.

[0038] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium on which a plurality of instructions are stored, wherein the instructions are suitable for being loaded and executed by a processor to implement any of the above-mentioned distributed quantum chip detection methods.

[0039] Beneficial effects of the present invention: The embodiments of the present invention avoid the incompleteness of the single-chip structure in sensing cosmic ray events by establishing a distributed quantum chip architecture, ensuring the feasibility of detecting small-flux cosmic ray events. By cascading the quantum bits in different chips in the quantum chip architecture according to the quantum error correction code and combining it with the distributed quantum chip structure for detection, the source of chip-level global errors can be effectively determined, avoiding the disadvantage of quantum error correction codes in conventional methods that cannot detect and correct chip-level global correlation errors, ensuring the effectiveness of quantum error correction codes, and effectively solving the problem of how to ensure the accuracy of large-scale quantum computing tasks when the scale and operational accuracy requirements of the quantum chip system cannot be reduced under the existing technical level. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] FIG1 is a schematic flow chart of a distributed quantum chip detection method provided in an embodiment of the present invention.

[0042] FIG2 is a general schematic diagram of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0043] FIG3 is a flowchart of an execution of a distributed quantum chip detection method provided in an embodiment of the present invention.

[0044] FIG4 is a schematic diagram of a specific implementation of a dual-chip single [[2,0,2]] code of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0045] FIG5 is an actual quantum circuit diagram of a dual-chip single [[2,0,2]] code detection method of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0046] FIG6 is a diagram showing measurement results of an amplitude (AD) damping channel (|Q2Q0>) of a dual-chip single [[2,0,2]] code quantum circuit of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0047] FIG7 is a diagram showing measurement results of an amplitude damping channel (|Q5Q4>) of a dual-chip single [[2,0,2]] code quantum circuit of a distributed quantum chip detection method provided in an embodiment of the present invention.

[0048] FIG8 is a diagram showing the measurement results of the phase damping (PD) channel (|Q2Q0>) of the dual-chip single [[2,0,2]] code quantum circuit of the distributed quantum chip detection method provided by an embodiment of the present invention.

[0049] FIG9 is a diagram showing measurement results of a phase damping channel (|Q5Q4>) of a dual-chip single [[2,0,2]] code quantum circuit of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0050] FIG10 is a schematic diagram showing a specific implementation of a dual-chip dual [[2,0,2]] code of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0051] FIG11 is a diagram showing the calculation results of the Fisher information amount of the [[2,0,2]] code for different types of errors in the distributed quantum chip detection method provided by an embodiment of the present invention.

[0052] FIG12 is a schematic diagram showing a specific implementation of a three-chip dual [[2,0,2]] code in an actual system of a distributed quantum chip detection method provided by an embodiment of the present invention.

[0053] FIG13 is a measurement result of the amplitude damping channel of the actual system of the distributed quantum chip detection method provided by the embodiment of the present invention (|Q 10 Q7Q4Q1>)Figure.

[0054] FIG14 is a measurement result of a phase damping channel of a three-chip dual [[2,0,2]] code quantum circuit in a practical system of a distributed quantum chip detection method provided by an embodiment of the present invention (|Q 10 Q7Q4Q1>)Figure.

[0055] FIG15 is a schematic diagram of the internal modules of a distributed quantum chip detection device provided in an embodiment of the present invention.

[0056] FIG16 is a functional block diagram of a terminal provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The present invention discloses a distributed quantum chip detection method, device, terminal, and storage medium. To clarify the objectives, technical solutions, and effects of the present invention, the present invention is further described below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention.

[0058] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0059] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0060] Recent research has found that the effects of cosmic rays and background radiation from environmental materials can affect most or all qubits on a single chip, causing non-local correlation errors across the entire chip. These errors cannot be effectively detected and corrected by common error-correcting codes, which can have a catastrophic impact on the performance of quantum error-correcting codes. For example, studies have shown that cosmic ray events can significantly accelerate qubit energy relaxation and can also cause frequency jumps in two-level systems across the entire chip, leading to phase decay of the qubits. Research speculates that qubit sensitivity to radiation may be related to factors such as experimental materials, packaging, and system architecture.

[0061] An existing distributed quantum error correction scheme employs hierarchical encoding across a distributed chip network. Errors in the first-level surface code reveal the location of cosmic rays, which are then corrected by a second-level quantum error correction code. This approach mitigates the destructive effects of catastrophic chip-level errors and protects quantum information. However, this approach places extremely high demands on the scale and operational capabilities of quantum chip systems, requiring implementation on the basis of fault-tolerant quantum computing. Another approach currently exists, which involves preparing all bits in excited states and detecting them by their energy relaxation time. However, this approach is limited in the types of errors it can detect and cannot clearly establish correlations. Therefore, in the noisy, medium-scale quantum era, fault-tolerant quantum error correction in multi-qubit systems remains challenging due to the limited fidelity of gate sequences and the size constraints of quantum chips.

[0062] In response to the above-mentioned shortcomings of the prior art, the present invention provides a distributed quantum chip detection method. By establishing a distributed quantum chip architecture, the method avoids the incompleteness of the single-chip structure in sensing cosmic ray events, ensuring the feasibility of detecting small-flux cosmic ray events. By cascading the quantum bits in different chips in the quantum chip architecture according to quantum error correction codes and combining them with the distributed quantum chip structure for detection, the source of chip-level global errors can be effectively determined. This avoids the disadvantage of quantum error correction codes in conventional methods that they cannot detect and correct chip-level global correlation errors, ensuring the effectiveness of quantum error correction codes. Under the existing technical level, the method effectively solves the problem of how to ensure the accuracy of large-scale quantum computing tasks when the scale and operational accuracy requirements of the quantum chip system cannot be reduced.

[0063] Exemplary Methods

[0064] As shown in FIG1 , the method includes:

[0065] Step S100: Establish a distributed quantum chip architecture, wherein each chip in the quantum chip architecture includes a number of quantum bits, and the quantum bits include computing quantum bits and signal quantum bits.

[0066] Specifically, since cosmic ray events are small-flux events, the errors they generate, when confined to a single chip, are global errors correlated in time and space. Therefore, a distributed quantum chip architecture is established, comprising multiple chips with good connectivity between them, with only one connection between every two chips. Each chip contains several qubits, including computational qubits for encoding and signal qubits for detecting errors in computational qubits. By utilizing a distributed quantum chip architecture, the incompleteness of a single-chip structure in sensing cosmic ray events is avoided, ensuring the feasibility of detecting small-flux cosmic ray events.

[0067] Step S200: Acquire a plurality of quantum error correction codes, and repeatedly concatenate and encode the computational quantum bits in different chips in the quantum chip architecture according to each of the quantum error correction codes.

[0068] Specifically, multiple sets of quantum error-correcting codes need to be encoded on the chips within a quantum chip architecture. For each quantum error-correcting code, the encoded computational qubits are distributed across different chips and encoded using repeated concatenation. For example, a qubit is taken from each of n chips and encoded into a [[n, 0, d]] quantum error-correcting code. Repeating this step yields m quantum error-correcting codes. This repeated concatenation of quantum error-correcting codes overcomes the conventional inability of quantum error-correcting codes to correct globally correlated errors, ensuring their effectiveness within the solution and improving the accuracy of global error determination. This allows for effective identification of the source of global errors in conjunction with a distributed architecture.

[0069] In one implementation, the quantum error-correcting code can be a graphical quantum error-correcting code. Compared to other quantum error-correcting codes, graphical quantum error-correcting codes are easier to encode in a distributed structure and are simpler to verify their error-correcting capabilities, thus improving the error-correcting efficiency of quantum error-correcting codes.

[0070] Step S300: Detect the encoded signal quantum bits in the quantum chip architecture to determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code.

[0071] Specifically, the signal qubits in the quantum chip architecture are detected, and based on the measurement results of the signal qubits, the amplitude damping channel measurement results and phase damping measurement results corresponding to each quantum circuit in the quantum chip architecture are determined. In this embodiment, the quantum chip architecture is a distributed quantum chip architecture, which does not require the detection of a large number of signal qubits and can be run on existing intermediate-scale noisy quantum computers (NISQs), with relatively low equipment requirements.

[0072] In one implementation, detecting signal qubits in a quantum chip architecture specifically includes: constructing several target stabilizers based on the quantum error correction code and the signal qubits on the chip, wherein any target stabilizer corresponds to multiple signal qubits on different chips; and performing non-destructive measurement on each target stabilizer to determine the amplitude damping channel and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code. Because cosmic rays can generate global errors, which can lead to errors including in signal qubits, to mitigate the effects of cosmic rays on stabilizer measurements, each stabilizer corresponds to multiple signal qubits distributed across different chips. In other words, the same stabilizer is measured using multiple signal qubits on multiple chips, thereby ensuring accurate error signatures from the measurement results. By using multiple groups of stabilizers distributed across different chips for measurement, the reliability of the measurement results and the necessary fault tolerance of the quantum error correction scheme are ensured. In addition, this embodiment uses a periodic detection method to detect the signal quantum bits in the quantum chip architecture, determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code, and can timely detect and discover chip-level global noise that may be caused by high-energy rays during the quantum computing process.

[0073] Step S400: determining a detection result of the chip according to the quantum error correction code, the amplitude damping measurement result, and the phase damping channel measurement result.

[0074] Specifically, the error signature table corresponding to the quantum error correction code is first determined based on the quantum error correction code. The amplitude damping channel and phase damping channel measurement results are then compared with the error signature table to determine the chip's detection result. When comparing the amplitude damping channel and phase damping channel measurement results with the error signature table, the comparison results determine whether errors have occurred in the computational qubits. If no errors have occurred, the chip's detection result is determined to be the absence of a cosmic ray event. If the comparison results indicate that errors have occurred in the computational qubits, the chip locations corresponding to the computational qubits are obtained. Based on the chip locations, the number of erroneous computational qubits corresponding to each chip is determined. If the number of erroneous qubits corresponding to any chip is greater than or equal to a preset number, the chip's detection result is determined to be the presence of a cosmic ray event. The preset number is determined based on the number of chips, the number of qubits on each chip, and other factors. Since the characteristic of a cosmic ray event is that it affects most or all of the quantum bits on the chip, causing non-local global correlation errors at the chip level, by detecting whether most of the quantum bits with errors are located on one chip, it is possible to accurately infer that a global correlation error event has occurred, thereby determining that a cosmic ray event has occurred in the distributed quantum chip architecture.

[0075] In one implementation, the method further includes:

[0076] If the number of erroneously calculated quantum bits corresponding to any of the chips is less than the preset number, the chip corresponding to the erroneously calculated quantum bit is initialized, and the detection result of the chip is determined to be that there is no cosmic ray event.

[0077] Simply put, when the number of erroneous calculation quantum bits corresponding to each chip in the quantum chip architecture is less than the preset number, it means that a global correlation error event did not occur, but a random error may have occurred. In this case, the random error is ignored, and the erroneous quantum bits on the chip are initialized for state preparation.

[0078] The method further comprises:

[0079] When the detection result of the chip is that there is no cosmic ray event, the step of detecting the signal quantum bits in the encoded quantum chip architecture is continued after each preset time interval until the detection result of the chip is that there is a cosmic ray event.

[0080] Simply put, when the chip's detection result shows that there is no cosmic ray event, a periodic measurement method of the signal quantum bits is adopted, that is, the signal quantum bits in the encoded quantum chip architecture are continued to be detected after each preset time interval to determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the preset quantum error correction code; the chip's detection result is determined based on the preset quantum error correction code, the amplitude damping measurement results, and the phase damping channel measurement results, thereby realizing the detection of whether an error has occurred in the calculation quantum bit and the type of error.

[0081] Example 1:

[0082] 4 to 9 , this embodiment explains the above content in more detail. This embodiment is a special case in a general structural style, namely, the minimum verification unit—a dual-chip single [[2,0,2]] code structure.

[0083] This embodiment consists of two interconnected chips, with only one connection between the chips. The two ends of the connection correspond to the two computational qubits on the two chips. The designed chip structure and simulation circuit are shown in Figures 4 and 5. The two computational qubits distributed on the two chips are encoded into a [[2,0,2]] quantum error correction code. On each chip, there are two signal qubits for stable sub-measurement, corresponding to the two stable sub-quanta X of [[2,0,2]]. a Z b and Z a X bAfter the encoding is completed, assuming that a cosmic ray event occurs on the left chip, resulting in a global correlation error at the chip level, non-destructive stable quantum measurement is performed according to the circuit, that is, these signal quantum bits are measured.

[0084] Because the simulation method used in this example is Qiskit programming simulation, based on relevant experimental research, the error models in this example all use the amplitude damping channel and phase damping channel included in Qiskit. The following table shows the error characteristics of the [[2,0,2]] quantum error correction code used in this example. Table 1 shows the corresponding errors in the measurement results.

[0085] Table 1: Error characteristics of the [[2,0,2]] quantum error correction code connected between two chips

[0086] The global amplitude damping channel on the simulated chip occurs with different probabilities. The predicted measurement results for the auxiliary bit are as follows: For a chip hypothetical cosmic ray event, when the error probability is very low, based on the designed quantum circuit, the signal qubit is likely to be in its error-free state, |1>. The probability of an error-prone measurement being in the |0> state also gradually increases. When the error probability on the chip approaches 1, the result is very likely to be in the |0> state.

[0087] For the unaffected signal qubit on the right chip, when the error probability is low, the probability of the result being the |1> state is high. However, as the error probability increases, according to Table 1, the probability of one of the signal qubits measuring the |0> and |1> quantum states gradually converges toward the average distribution. That is, the probabilities of the two signal qubits measuring |00>, |01>, |10>, and |11> quantum states gradually converge toward the average distribution. As the error probability approaches 1, each signal qubit has an equal probability of being the |0> and |1> states, resulting in a probability of approximately 0.25 for each of the four quantum states. This corresponds to the corresponding calculated results of 0.5 and 0.5 in the error signature table. Qiskit is used for encoding and measurement, and the quantum gate and measurement operations in the circuit are ideal, assuming their fidelity to be 1. Finally, the statistical histograms of the quantum state results obtained from multiple measurements of the signal qubits are shown in Figures 6 and 7.

[0088] From the results, we can see that for chips with chip-level errors:

[0089] When the error probability is very small, the results of the two signal qubits are almost all in the |1> state, that is, almost no error occurs;

[0090] As the error probability increases, the probability that the quantum bit on the chip will measure the |0> state also gradually increases due to the signal quantum bit's own errors.

[0091] When the error probability is close to 1, almost all quantum bits on the chip have errors and become |0> state.

[0092] For chips without errors:

[0093] When the error probability is very small, the measurement results of the signal qubits on it mostly correspond to the situation in Table 1, that is, the vast majority are in the |1> state;

[0094] Similarly, as the error probability increases, the measurement results of the signal quantum bit show that the probabilities of the four quantum state results gradually converge to the average distribution, which is the same as expected;

[0095] Finally, when the error probability is close to 1, the measurement results show the results of the amplitude damping channel in Table 1, that is, the four results of |00>, |01>, |10>, and |11> have similar distributions, so the simulation shows the same results as the theoretical analysis.

[0096] For a simulated chip with a global phase damping channel occurring under different probabilities, the predicted measurement results for the signal qubit are as follows: For a chip hypothetical to experience a phase damping error, when the error probability is low, based on the designed quantum circuit, the auxiliary bit is likely to be in the |1> state. As the probability increases, the probability of the signal qubit being in a superposition of |0> and |1> states also gradually increases. When the error probability approaches 1, the measurement result is likely to show similar probabilities for the |0> and |1> states. For the unaffected signal qubit on the right chip, when the error probability is low, the probability of the error-free |1> state is high. However, as the error probability increases, as shown in Table 1, the correct measurement results for the two signal qubits are that the probabilities of the |0> and |1> quantum states for the first auxiliary bit gradually approach an even distribution, while the probability of the second auxiliary bit being in the |1> state remains high. As the error probability approaches 1, the probability of each quantum state in |01> and |11> should be approximately 0.5, which is consistent with the corresponding results of 0.5 and 1 in Table 1. Simulations using Qiskit were also performed, with ideal quantum gate and measurement operations in the circuit. Finally, statistical histograms of the quantum state results obtained by multiple measurements of the signal qubit are shown in Figures 8 and 9.

[0097] From the results, we can see that for the chip with chip-level errors added:

[0098] When the error probability is very small, the measurement results of the two auxiliary bits are almost all |1> states, which means that almost no error occurs;

[0099] As the error probability increases, due to the errors in the auxiliary bits themselves, the probability of the two auxiliary bits on the chip measuring the two quantum states |0> and |1> gradually approaches the average distribution;

[0100] When the error probability is almost 1, since the quantum bits on the chip are also likely to have errors, the probability of each quantum state |00>, |01>, |10>, |11> in the result is about 0.25.

[0101] For chips without errors:

[0102] When the error probability is very small, the measurement results of the auxiliary qubits on it mostly correspond to the situations in the error characteristic table, that is, the vast majority are in the |1> state;

[0103] Similarly, as the error probability increases, the auxiliary qubit's measurement results show that the probability of one of the two quantum states, |0> and |1>, gradually approaches the average distribution, while the other measurement result is always |1>, which is the same as expected.

[0104] Finally, when the error probability is close to 1, the measurement results show that the |01> and |11> states have similar distributions, which is the result of the phase damping error shown in Table 1. Therefore, the simulation shows the same results as the theoretical analysis.

[0105] According to the theoretical and simulation results in Example 1, only one set of quantum error correction codes can only detect the occurrence of an error on the chip, and cannot fully explain the difference between a single event and a correlated error, or whether the error is global. Therefore, in actual use, more error correction codes should be integrated as much as possible at different locations on the chip to ensure the completeness of error detection.

[0106] Example 2:

[0107] Besides the relatively idealized design and verification process of Example 1, existing distributed quantum systems still have some limitations (the following is an example): Each chip has four qubits distributed on it; only one connection can be achieved between chips; and universal two-bit quantum gates cannot be implemented between chips, only state transfer operations between any quantum state and the ground state can be performed. Therefore, the multiple inter-chip connections and universal inter-chip quantum gates required by the chip system designed in Example 1 are currently difficult to implement. Therefore, based on the existing chip structure, a compromise solution is considered, as shown in Figure 12 (due to system limitations, the signal qubit needs to be transferred to the chip where the computational qubit is located to complete the stabilizer measurement. Therefore, the upper and lower figures respectively show the positions of the system quantum state after state preparation and before the stabilizer measurement). Three chips are connected, each connection corresponding to a computational qubit on two adjacent chips. Two [[2,0,2]] quantum error correction codes are distributed across the chip system, each of which corresponds to two signal qubits used for the stabilizer measurement.

[0108] Assume that a cosmic ray event occurs on the middle chip in Figure 12. This means that one computational qubit in each of the two [[2,0,2]] codes should have an error. This is a global, chip-level error and a correlated error. Table 2 shows the specific error characteristics for this chip structure. Table 2 indicates the correct result that the signal qubit should measure if an error occurs in the computational qubit, as well as the corresponding result if an error occurs in the signal qubit.

[0109] Table 2: Error characteristics of the [[2,0,2]] quantum error correction code connected to three chips

[0110] However, since the positions of the two types of quantum bits are changing during the operation of the line, especially the signal quantum bit will be affected by cosmic rays when it is exchanged to the intermediate chip, causing errors in both the computing quantum bit and the signal quantum bit, so there will be slight deviations in the measurement results.

[0111] If an amplitude damping error occurs, it can be roughly analyzed from Table 2 that the signal qubit located in the normal chip should correspond to the results in the AD column, and the corresponding stabilizer measurement results should theoretically be 0.5 and |0> states respectively. Specifically, they are Q1 and Q 10 The measurement result is 0.5 as shown in Table 2, while the measurement results of Q4 and Q7 themselves cause the |0> state, which is the auxiliary bit |Q 10Q7Q4Q1> should have four states: |0000>, |0001>, |1000>, and |1001>. During simulation, the simulation parameters must be adjusted based on the fidelity of quantum state preparation, gate fidelity, and measurement fidelity in the actual experimental system, and the resulting measurement results will also have certain errors.

[0112] According to the simulation results in Figure 13, we can see that:

[0113] When the error probability is small, most of the measurement results of the signal qubit correspond to I in Table 2, that is, most of them are in the |1> state;

[0114] However, as the error probability increases, the measurement results of the signal quantum bit show that the probabilities of the four quantum state results mentioned above gradually approach the average distribution;

[0115] Finally, when the error probability approaches 1, the measurement results show that the probabilities of the four states |0000>, |0001>, |1000>, and |1001> are similar. Therefore, the simulation results are roughly consistent with the theoretical analysis.

[0116] If a phase damping error occurs, it can be roughly analyzed from Table 2 that the signal qubit located in the normal chip should correspond to the result in the PD column, and the corresponding stabilizer measurement results should theoretically be 0.5 and 0.5 respectively. Specifically, the signal qubit |Q 10 Q7Q4Q1> should have: |0000> to |1111>, a total of 16 quantum states.

[0117] As shown in the simulation results of Figure 14, we can see that:

[0118] When the error probability is small, most measurement results of the signal quantum bit are in the |1> state;

[0119] As the error probability increases, the measurement results of the signal quantum bit show that the probabilities of the 16 quantum states mentioned above gradually approach the average distribution;

[0120] When the error probability is close to 1, the measurement results show that the probabilities of the 16 states are similar.

[0121] Based on theoretical calculations and simulation results, we can generally conclude that if the error signatures obtained from measuring the stabilizers of multiple quantum error-correcting codes encoded in a distributed system all indicate a cosmic ray event on a specific chip, this data can be used to infer the occurrence of the cosmic ray event in the system and also to deduce its location. Therefore, when cosmic rays occur in a distributed system, analyzing the results of measuring the stabilizers of multiple quantum error-correcting codes can be used to detect and locate the event.

[0122] Based on the above embodiment, the present invention further provides a distributed quantum chip detection device, as shown in FIG15 , comprising:

[0123] Quantum chip architecture building module 01 is used to establish a distributed quantum chip architecture, wherein each chip in the quantum chip architecture includes a number of quantum bits, including computing quantum bits and signal quantum bits;

[0124] The computational quantum bit encoding module 02 is configured to obtain a plurality of quantum error correction codes and repeatedly concatenate the computational quantum bits in different chips in the quantum chip architecture according to each of the quantum error correction codes;

[0125] The signal qubit detection module 03 is used to detect the signal qubits in the encoded quantum chip architecture and determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code;

[0126] The detection result determination module 04 is used to determine the detection result of the chip according to the quantum error correction code, the amplitude damping measurement result and the phase damping channel measurement result.

[0127] Based on the above embodiment, the present invention also provides a terminal, whose principle block diagram can be shown in Figure 16. The terminal includes a processor, a memory, a network interface, and a display screen connected via a system bus. The processor of the terminal is used to provide computing and control capabilities. The memory of the terminal includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The network interface of the terminal is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a distributed quantum chip detection method is implemented. The display screen of the terminal can be a liquid crystal display or an electronic ink display.

[0128] Those skilled in the art will understand that the principle block diagram shown in Figure 16 is only a block diagram of a partial structure related to the solution of the present invention, and does not constitute a limitation on the terminal to which the solution of the present invention is applied. The specific terminal may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0129] In one implementation, the terminal has one or more programs stored in its memory, and is configured to be executed by one or more processors, wherein the one or more programs include instructions for performing a distributed quantum chip detection method.

[0130] Those skilled in the art will appreciate that all or part of the processes in the above-described embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-described embodiments. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAM bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0131] In summary, the present invention discloses a distributed quantum chip detection method, device, terminal and storage medium. The method avoids the incompleteness of the single-chip structure in sensing cosmic ray events by establishing a distributed quantum chip architecture, ensuring the feasibility of detecting small-flux cosmic ray events. By cascading the quantum bits in different chips in the quantum chip architecture according to quantum error correction codes and combining them with the distributed quantum chip structure for detection, the source of chip-level global errors can be effectively determined. This avoids the disadvantage of quantum error correction codes in conventional methods that they cannot detect and correct chip-level global correlation errors, ensuring the effectiveness of quantum error correction codes. Under the existing technical level, it effectively solves the problem of how to ensure the accuracy of large-scale quantum computing tasks when the scale and operational accuracy requirements of the quantum chip system cannot be reduced.

[0132] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A distributed quantum chip detection method, characterized in that: The method comprises: Establishing a distributed quantum chip architecture, wherein each chip in the quantum chip architecture includes a number of quantum bits, wherein the quantum bits include computing quantum bits and signal quantum bits; Acquire a plurality of quantum error correction codes, and perform repeated cascade encoding on the computing quantum bits in different chips in the quantum chip architecture according to each of the quantum error correction codes; Detecting the encoded signal quantum bits in the quantum chip architecture to determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code; The detection result of the chip is determined according to the quantum error correction code, the amplitude damping measurement result and the phase damping channel measurement result.

2. The distributed quantum chip detection method according to claim 1, characterized in that: The detecting of the signal quantum bits in the encoded quantum chip architecture to determine the amplitude damping channel measurement results and the phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code includes: Constructing a plurality of target stabilizers according to the quantum error correction code and the signal quantum bits on the chip, wherein any of the target stabilizers corresponds to a plurality of the signal quantum bits on different chips; Non-destructive measurement is performed on each of the target stabilizers to determine the amplitude damping channel measurement result and the phase damping channel measurement result corresponding to each quantum circuit of the quantum error correction code.

3. The distributed quantum chip detection method according to claim 1, characterized in that: Determining the detection result of the chip according to the quantum error correction code, the amplitude damping measurement result and the phase damping channel measurement result, including: Determine an error feature table corresponding to the quantum error correction code according to the quantum error correction code; The amplitude damping channel measurement result and the phase damping channel measurement result are respectively compared with the error feature table to determine the detection result of the chip.

4. The distributed quantum chip detection method according to claim 3, characterized in that: The comparing the amplitude damping channel measurement result and the phase damping channel measurement result with the error feature table to determine the detection result of the chip includes: The amplitude damping channel measurement result and the phase damping channel measurement result are respectively compared with the error feature table to determine whether an error occurs in each of the calculation quantum bits. If no error occurs in the calculation quantum bit, it is determined that the detection result of the chip is that there is no cosmic ray event.

5. The distributed quantum chip detection method according to claim 4, characterized in that: The method further comprises: If an error occurs in the calculation quantum bit, obtaining the chip position corresponding to the calculation quantum bit; Determining the number of erroneously calculated quantum bits corresponding to each chip according to the chip position; If the number of erroneously calculated quantum bits corresponding to any of the chips is greater than or equal to a preset number, it is determined that the detection result of the chip is that a cosmic ray event exists.

6. The distributed quantum chip detection method according to claim 5, characterized in that: The method further comprises: If the number of erroneously calculated quantum bits corresponding to any of the chips is less than the preset number, the chip corresponding to the erroneously calculated quantum bits is initialized, and the detection result of the chip is determined to be that there is no cosmic ray event.

7. The distributed quantum chip detection method according to claim 6, characterized in that: The method further comprises: When the detection result of the chip is that there is no cosmic ray event, the step of detecting the encoded signal quantum bits in the quantum chip architecture continues after each preset time interval until the detection result of the chip is that there is a cosmic ray event.

8. A distributed quantum chip detection device, characterized in that: The device comprises: A quantum chip architecture building module, used to establish a distributed quantum chip architecture, wherein each chip in the quantum chip architecture includes a number of quantum bits, and the quantum bits include computing quantum bits and signal quantum bits; A computational quantum bit encoding module, used to obtain a plurality of quantum error correction codes, and to repeatedly cascade encode the computational quantum bits in different chips in the quantum chip architecture according to each of the quantum error correction codes; A signal quantum bit detection module, used to detect the signal quantum bits in the encoded quantum chip architecture, and determine the amplitude damping channel measurement results and phase damping channel measurement results corresponding to each quantum circuit of the quantum error correction code; A detection result determination module is used to determine the detection result of the chip according to the quantum error correction code, the amplitude damping measurement result and the phase damping channel measurement result.

9. A terminal, characterized in that: The terminal includes a memory and one or more processors; the memory stores one or more programs; the program contains instructions for executing the distributed quantum chip detection method as described in any one of claims 1 to 7; and the processor is used to execute the program.

10. A computer-readable storage medium having a plurality of instructions stored thereon, characterized in that: The instructions are suitable for being loaded and executed by a processor to implement the steps of the distributed quantum chip detection method described in any one of claims 1 to 7 above.

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