Clock synchronization method, device, and computer readable storage medium

Abstract

The present application belongs to the technical field of communications, and discloses a clock synchronization method, a device, and a computer readable storage medium. The method comprises: selecting a master clock source inside of a base station to be a clock synchronization source of a fusion control system; on the basis of the clock synchronization source, constructing a wired synchronous master clock message and an air interface synchronous master clock message; and sending the wired synchronization master clock message to a wired connection device, and sending the air interface synchronization master clock message to a wireless connection device.

Description

Clock synchronization method, device and computer-readable storage medium

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202311584833.2 filed on November 23, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a clock synchronization method, device, and computer-readable storage medium. Background Art

[0004] Clock synchronization refers to the process of synchronizing the clocks of the sending and receiving devices in a communication system to ensure data accuracy and consistency.

[0005] Because wired and wireless networks differ in their communication methods and transmission media, different methods are required for clock synchronization. When using a mixed wired and wireless network, based on the principle of independent wireless and wired synchronization, network-wide synchronization requires the following steps: Synchronize the wired controller and its directly connected actuators using an external clock synchronization source; synchronize wireless base stations with each other using an external clock synchronization source; and synchronize wireless base stations and terminals using over-the-air synchronization signals.

[0006] After the wired and wireless networks have independently synchronized, they use data packets to identify services. However, wireless typically processes data in frames. When receiving wired data packets, the clock synchronization sources of the wireless and wired frames differ, resulting in slight differences in clock frequency and phase. These minor discrepancies can cause the wireless and wired frames to misalign, impacting real-time data processing and factory production.

[0007] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art.

[0008] Summary of the Invention

[0009] The main purpose of this application is to provide a clock synchronization method, device and computer-readable storage medium, aiming to solve the technical problem of low reliability of clock synchronization in wired and wireless converged control systems.

[0010] To achieve the above-mentioned objectives, the present application provides a clock synchronization method, which is applied to a base station of a fusion control system. The fusion control system further includes a controller, an actuator, and a terminal device. The first side of the controller is connected to the actuator via a wired connection, and the second side is connected to the base station via a wired connection. The actuator is connected to the actuator or the base station via a wired connection, and the terminal device is connected to the base station via a wireless connection. The clock synchronization method includes the following steps:

[0011] Selecting a master clock source within the base station as a clock synchronization source for the integrated control system;

[0012] Constructing a wired synchronization master clock message and an air interface synchronization master clock message according to the clock synchronization source;

[0013] The wired synchronization master clock message is sent to the wired connection device, and the air interface synchronization master clock message is sent to the wireless connection device.

[0014] In one embodiment, the step of constructing a wired synchronization master clock message and an air interface synchronization master clock message according to the clock synchronization source includes:

[0015] Distributing the clock signal corresponding to the clock synchronization source to the clock divider and the phase-locked loop;

[0016] Dividing the clock signal by the clock divider to generate corresponding second pulses and time information;

[0017] Eliminate jitter on the clock signal through the phase-locked loop to generate a master timestamp working clock;

[0018] generating the wired synchronous master clock message according to the second pulse and the time information; and

[0019] The air interface synchronization master clock message is generated according to the master timestamp working clock, the second pulse and the time information.

[0020] In one embodiment, the step of selecting the master clock source within the base station as the clock synchronization source of the integrated control system includes:

[0021] When the base station is a primary base station, obtaining a wireless system design requirement of the integrated control system, and determining a crystal oscillator frequency deviation index according to the wireless system design requirement;

[0022] A target crystal oscillator selected according to the crystal oscillator frequency deviation index is used as the clock synchronization source.

[0023] In one embodiment, before the step of selecting the master clock source within the base station as the clock synchronization source of the converged control system, the following steps are included:

[0024] When the base station is set as a slave base station, receiving the wired synchronous master clock message sent by the master base station;

[0025] Performing a synchronous clock recovery action according to the wired synchronous master clock message;

[0026] The step of selecting the master clock source inside the base station as the clock synchronization source of the integrated control system includes:

[0027] The restored synchronous clock is used as the clock synchronization source.

[0028] In one embodiment, after the steps of sending the wired synchronization master clock message to the wired connection device and sending the air interface synchronization master clock message to the wireless connection device, the method further includes:

[0029] Calculate the data sending time period of the controller through the service control cycle parameter;

[0030] According to the second pulse corresponding to the clock synchronization source, timing information is sent to the controller during the data sending time period.

[0031] To achieve the above objectives, the present application provides a clock synchronization method, which is applied to a controller of a fusion control system. The clock synchronization method includes the following steps:

[0032] Receive the wired synchronization master clock message sent by the base station;

[0033] A synchronous clock recovery action is performed according to the wired synchronous master clock message.

[0034] In one embodiment, after the step of performing a synchronous clock recovery action according to the wired synchronous master clock message, the following steps are included:

[0035] Receive the timing information sent by the base station and handle the service within the specified time corresponding to the timing information.

[0036] To achieve the above objectives, the present application provides a clock synchronization method, which is applied to an actuator of a fusion control system. The clock synchronization method includes the following steps:

[0037] Receive wired synchronization master clock message sent by base station or controller;

[0038] A synchronous clock recovery action is performed according to the wired synchronous master clock message.

[0039] To achieve the above objectives, the present application provides a clock synchronization method, which is applied to a wireless connection device of a fusion control system. The clock synchronization method includes the following steps:

[0040] Receive the air interface synchronization master clock message sent by the base station;

[0041] Obtaining the master timestamp working clock associated with the air interface synchronization master clock message and the slave timestamp working clock used locally;

[0042] A synchronous clock recovery action is performed according to the master timestamp working clock and the master timestamp working clock.

[0043] In one embodiment, before the step of performing a synchronous clock recovery action based on the master timestamp working clock and the master timestamp working clock, the step includes:

[0044] Sending a delayed message to the base station and determining a sending time of the delayed message;

[0045] receiving a reception time of the delayed message sent by the base station;

[0046] The step of performing a synchronous clock recovery action according to the master timestamp working clock and the master timestamp working clock comprises:

[0047] A synchronous clock recovery action is performed according to the master timestamp working clock and the master timestamp working clock, as well as the sending time and the receiving time of the delayed message.

[0048] In addition, to achieve the above-mentioned purpose, the present application also provides a base station, which includes: a memory, a processor, and a clock synchronization program stored on the memory and runnable on the processor, and the clock synchronization program is configured to implement the steps of the clock synchronization method.

[0049] In addition, to achieve the above-mentioned purpose, the present application also provides a controller, which includes: a memory, a processor, and a clock synchronization program stored on the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method.

[0050] In addition, to achieve the above-mentioned purpose, the present application also provides an executor, which includes: a memory, a processor, and a clock synchronization program stored on the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method.

[0051] In addition, to achieve the above-mentioned purpose, the present application also provides a wireless connection device, which includes: a memory, a processor, and a clock synchronization program stored in the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method.

[0052] In addition, to achieve the above-mentioned purpose, the present application also provides a computer-readable storage medium, on which a clock synchronization program is stored. When the clock synchronization program is executed by a processor, the steps of the clock synchronization method are implemented.

[0053] In one technical solution provided by this application, the master clock source within the base station is used as the clock synchronization source for the converged control system. Corresponding wired synchronization master clock messages and air interface synchronization master clock messages are constructed and then sent to wired and wireless devices, respectively. This ensures that the reference clock source used by the next-level devices is the same, and thus the clock synchronization results of wired and wireless devices remain consistent. This effectively resolves the time deviation problem between the two and ensures the reliability of the clock synchronization results of the entire converged control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a schematic diagram of clock synchronization in a wired system;

[0055] FIG2 is a schematic diagram of clock synchronization in a wireless system;

[0056] Figure 3 is a schematic diagram of clock synchronization in a fusion control system;

[0057] FIG4 is a flow chart of a first embodiment of a clock synchronization method of the present application;

[0058] FIG5 is a schematic diagram of a joint control system in a first embodiment of a clock synchronization method of the present application;

[0059] FIG6 is a signaling flow chart of the first embodiment of the clock synchronization method of the present application;

[0060] FIG7 is a flow chart of step S11 in the first embodiment of the clock synchronization method of the present application;

[0061] FIG8 is a flow chart of step S12 in the first embodiment of the clock synchronization method of the present application;

[0062] FIG9 is a schematic diagram of a wireless system with enhanced determinism in the first embodiment of the clock synchronization method of the present application;

[0063] FIG10 is a schematic diagram of the process before step S11 in the first embodiment of the clock synchronization method of the present application;

[0064] FIG11 is a schematic diagram of the flow chart after step S13 in the first embodiment of the clock synchronization method of the present application;

[0065] FIG12 is a flow chart of a second embodiment of a clock synchronization method of the present application;

[0066] FIG13 is a schematic diagram of the flow chart after step S22 in the second embodiment of the clock synchronization method of the present application;

[0067] FIG14 is a flow chart of a third embodiment of a clock synchronization method of the present application;

[0068] FIG15 is a schematic diagram of the process before step S33 in the third embodiment of the clock synchronization method of the present application;

[0069] FIG16 is a signaling flow chart of the third embodiment of the clock synchronization method of the present application;

[0070] FIG17 is a schematic diagram of an example of a combined control system of a clock synchronization method of the present application;

[0071] FIG18 is a schematic diagram of a simplified flow chart of an example of a combined control system for a clock synchronization method of the present application;

[0072] FIG19 is a schematic diagram of timing synchronization of an example of a combined control system using a clock synchronization method according to the present application;

[0073] FIG20 is a schematic diagram of the structure of the equipment in the hardware operating environment involved in the embodiment of the present application.

[0074] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0075] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0076] Conventional industrial wired systems use clock synchronization sources from controllers or actuators, or from external clock synchronization sources. Figure 1 shows an example of a controller with an external clock synchronization source, a controller as the clock synchronization source, and an actuator as the clock synchronization source. Examples of external synchronization sources include GNSS (Global Navigation Satellite System) and clock servers, while actuators include servos and motors.

[0077] Conventional industrial wireless systems generally use 3GPP (3rd Generation Partnership Project) 4 / 5G (Generation Mobile Communication Network) standards and Wi-Fi devices for wireless communication.

[0078] In particular, TDD (Time Division Duplexing) systems face difficulties in coordinating clock synchronization between devices from different operators, or between different standards or networking systems within the same operator. To prevent interference between different base stations and uplink and downlink interference between different terminals, clock synchronization is typically derived from a common standard clock source, such as a GNSS satellite clock source or clock server connected to a wireless base station. Figure 2 shows an application example where a base station is connected to an external synchronous clock source and then synchronizes clocks with wirelessly connected devices such as industrial CPE (Industrial Customer Premise Equipment) and gateways.

[0079] When wired and wireless networks are mixed, network-wide synchronization becomes crucial and prone to errors, as each has its own synchronization method. If there are any issues with network-wide synchronization, it will affect the control of the entire industrial network and, in turn, the entire business process.

[0080] In a wired-wireless converged control system, independent synchronization of wired and wireless systems is often used. As shown in the networking diagram in Figure 3, network-wide synchronization includes the following steps:

[0081] 1) Synchronization between wired master and slave controllers and their directly connected actuators. The master controller is connected to an external clock synchronization source, and the slave controllers and actuators are synchronized with the master controller. Alternatively, the controllers can also use a local clock source as the clock source for synchronization;

[0082] 2) Wireless base stations maintain synchronization through an external clock synchronization source, such as 1588;

[0083] 3) Synchronization is completed between the wireless base station and the terminal through the air interface.

[0084] However, the above solution has the following problems:

[0085] 1) Wireless networks typically process data in frames. When receiving wired data packets, the clock synchronization sources of wireless and wired frames are different, meaning there may be slight differences in clock frequency and phase. These minor differences can cause the wireless frames and wired data packets to misalign, impacting real-time data processing and factory production.

[0086] 2) If the clock source is derived from a local clock source in the controller or actuator, it typically cannot meet the clock frequency deviation accuracy requirements. For example, the clock frequency deviation of wired Ethernet must not exceed ±100ppm, far exceeding the WiFi standard's clock frequency deviation requirements of <±25ppm (802.11b) and <±20ppm (802.11g / a / n). For industrial wireless communications that adhere to the 3GPP standard, the air interface clock frequency deviation requirement is less than ±0.05ppm.

[0087] 3) GNSS satellite synchronization has the disadvantages of low reliability, susceptibility to interference, and difficulty in installation and construction. The time server or other external clock source corresponding to the 1588 protocol has the disadvantages of large initial workload, difficult fault location, and high cost.

[0088] This application provides a new clock synchronization method, which uses the main clock source inside the base station as the clock synchronization source of the integrated control system, and then synchronizes the clocks of various wired and wireless connection devices according to the clock synchronization source to ensure the reliability of the clock synchronization of the entire system.

[0089] To better understand the above technical solutions, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0090] An embodiment of the present application provides a clock synchronization method, which is applied to a master base station in a converged control system. Referring to FIG4 , FIG4 is a flow chart of a first embodiment of a clock synchronization method of the present application.

[0091] In this embodiment, the clock synchronization method includes:

[0092] Step S11: selecting a master clock source inside the base station as a clock synchronization source for the integrated control system;

[0093] Step S12: constructing a wired synchronization master clock message and an air interface synchronization master clock message according to the clock synchronization source;

[0094] As shown in Figure 5, the joint control system primarily consists of several base stations, controllers, actuators, and terminal devices. One of the base stations is designated as the master, and the remaining base stations are slaves. The controller's first side is wired to the actuators, and its second side is wired to the base station. The actuators are wired to either the actuator or the base station (the diagram shows only one connection method). Terminal devices connect to the base station wirelessly.

[0095] It can be understood that the base station is the core device in the system, responsible for managing and controlling various connected devices, providing services and resource allocation to them, and coordinating communication and data transmission between different devices; wired connection devices refer to devices connected to the base station through wired connections, such as optical fibers, cables, etc., and usually include controllers, actuators and other devices; wireless connection devices refer to devices connected to the main base station through wireless connections, such as smartphones, servos, motors and other terminal devices.

[0096] The master clock source within a base station refers to the main clock device used to provide the internal time of the base station. The master clock source is crucial to the base station and even the entire integrated control system. It provides the clock reference for the entire system and ensures synchronization and coordination between various devices.

[0097] In one embodiment, a master clock source inside the base station is selected. The master clock source may be a local crystal oscillator, an external clock device, etc., which is not specifically limited in this embodiment. The master clock source is then used as the clock synchronization source for the entire integrated control system.

[0098] 6 , a wired synchronization master clock message and an air interface synchronization master clock message are constructed according to the clock synchronization source, wherein the wired synchronization master clock message is used to realize clock synchronization between the base station and the wired connection device, and the air interface synchronization master clock message is used to realize clock synchronization between the base station and the wireless connection device.

[0099] In one embodiment, referring to FIG. 7 , step S11 includes:

[0100] Step S111: When the base station is a primary base station, obtaining a wireless system design requirement of the integrated control system, and determining a crystal oscillator frequency deviation index according to the wireless system design requirement;

[0101] Step S112: using the target crystal oscillator selected according to the crystal oscillator frequency deviation index as the clock synchronization source.

[0102] It is understandable that when the current base station is the main base station, its internal master clock source is the most basic clock synchronization source for the entire joint control system, and the main base station may include multiple local crystal oscillator clock sources. In this case, one of them needs to be selected as the main clock source.

[0103] In one embodiment, wireless system design requirements for the integrated control system are obtained, including frequency synchronization requirements, frequency deviation accuracy requirements, time phase synchronization requirements, and temperature range. Crystal oscillator frequency deviation indicators, such as crystal oscillator aging rate, crystal oscillator initial frequency deviation, and full temperature range frequency deviation, are then determined based on the wireless system design requirements.

[0104] Exemplary crystal oscillator types include quartz crystal oscillator (OSC), temperature-compensated crystal oscillator (TCXO), voltage-controlled crystal oscillator (VCXO), and oven-controlled crystal oscillator (OCXO). Based on wireless system design requirements and the device lifecycle, crystal oscillator frequency deviation indicators are determined. Specifically, these indicators include the crystal oscillator aging rate over a 10-year time span, the crystal oscillator's initial frequency deviation, and the frequency deviation over the full temperature range. Based on these crystal oscillator frequency deviation indicators, a maximum spectrum superposition analysis is performed on all crystal oscillator types. Based on wireless system design requirements, such as a frequency synchronization requirement of ≤10PPM or ≤20PPM, suitable target crystal oscillators are selected as clock synchronization sources.

[0105] This solution selects a suitable target crystal from multiple local crystal oscillators within the master base station based on the crystal's frequency deviation indicator and uses it as the clock synchronization source. This local crystal oscillator generates clock signals without relying on an external clock source. This means the master base station can still generate accurate time information without an external network connection and is less susceptible to external environmental influences, resulting in greater independence and stability.

[0106] In one embodiment, referring to FIG8 , step S12 includes:

[0107] Step S121: distributing the clock signal corresponding to the clock synchronization source to the clock divider and the phase-locked loop;

[0108] It is understandable that a crystal oscillator is an electronic oscillator that generates a stable frequency through crystal oscillation. The frequency of the clock signal it generates is fixed and may not meet the synchronization requirements. Therefore, its frequency needs to be adjusted.

[0109] In one embodiment, after connecting the target crystal oscillator to the driver, an appropriate power supply is provided to the crystal oscillator driver to ensure that the voltage and current meet the driver's requirements, and then the clock signal corresponding to the clock synchronization source is measured and obtained through testing equipment such as an oscilloscope.

[0110] Step S122: dividing the clock signal by the clock divider to generate corresponding second pulses and time information;

[0111] It can be understood that a clock divider is a circuit used to divide an input high-frequency clock signal according to a certain division multiple to obtain a lower frequency signal for use in a digital system.

[0112] In one embodiment, the clock signal generated by the driver has a relatively high frequency. Therefore, the clock signal needs to be input into a clock divider. A programmable device, such as a complex programmable logic device (CPLD) or field programmable gate array (FPGA), counts and divides the input clock signal before outputting it to generate a frame header pulse signal. The frame header pulse signal is essentially a short pulse signal, such as 1ms or 10ms, that marks the time domain starting point of a wireless frame.

[0113] A counter circuit is designed in an FPGA or CPLD to count the number of frame header pulse signals. Each time a frame header pulse signal is detected, the counter increments by 1. When the counter value reaches a preset value, a short pulse signal, known as a pulse per second (PP1S), is generated. For example, if the frame header pulse signal is 10ms, a PP1S is generated when the counter reaches 100.

[0114] Using the frame header pulse signal as an interrupt trigger signal, the current reference time, such as the reference time provided by a local real-time clock or an external clock reference source, can be read. Combined with the count value of the frame header pulse signal, the current time information (Time of Day, TOD) can be calculated. For example, when the frame header pulse signal is detected, the reference time provided by the real-time clock is 10:30:25, and the count value of the frame header pulse signal is 8. Therefore, the TOD can be calculated as 10:30:25+80ms.

[0115] Step S123: Eliminate jitter on the clock signal through the phase-locked loop to generate a master timestamp working clock;

[0116] This solution uses a timestamp tagging method to enhance the transmission certainty between the base station and the wireless connection device.

[0117] It is understood that a phase-locked loop (PLL) is a common circuit used to generate a stable clock signal. It can eliminate jitter in the clock signal and provide a stable clock signal as a working clock of the system.

[0118] In one embodiment, a clock signal is input into a phase-locked loop circuit, and after jitter elimination, a stable, low-jitter clock signal is output. The clock signal generated by the phase-locked loop is then connected to the clock input port of a device such as a processor, a switching chip, and a network port PHY chip to form a stable working clock.

[0119] Since these devices usually have built-in clock modules, the above working clock can be used to timestamp data packets or events. These timestamps can be used to record the time when the event occurred, that is, to form the main timestamp working clock.

[0120] Step S124: generating the wired synchronous master clock message according to the second pulse and the time information; and

[0121] It is understandable that the pulse per second signal is generally used for synchronizing clocks and timing, and can be used as a reference time to trigger a processor to perform a specific operation.

[0122] In this solution, the second pulse is used as a write signal. When a specific second pulse is detected, the processor encodes the current time information into a specific format, such as binary, based on this signal, for easy transmission and parsing. Then, according to the protocol and format requirements, the time information in the specific format is written into a blank message to generate a wired synchronous master clock message.

[0123] Step S125: Generate the air interface synchronization master clock message according to the master timestamp working clock, the second pulse and the time information.

[0124] In one embodiment, as shown in Figure 9, the application adaptation layer generates a master clock message to be stamped based on the second pulse and time information, using the same method as step S124. Based on this, a master timestamp tag is added to the deterministic timestamp location of the master clock message to be stamped, such as at the physical layer or data link layer, based on the master timestamp working clock, thereby generating an air interface synchronization master clock message. This master timestamp tag serves as a time information tag, helping downstream wireless connection devices adjust their own clocks to maintain synchronization with the base station's clock.

[0125] In this solution, a master clock message is generated based on second pulses and time information. Since the second pulse is a time signal generated in real time, it will not be affected by network delays and transmission time, nor will it be affected by the network or external servers. Therefore, it helps to improve the independence and stability of clock synchronization. In addition, this solution sets up a wireless system with enhanced determinism, that is, the base station will mark the master clock message with a master timestamp tag at the deterministic timestamp position. In this way, after receiving the master clock message, the wireless connection device can also mark it with a slave timestamp tag accordingly. At this point, the clock can be synchronized based on the two tags. This setting takes into account the impact of network delays and fluctuations on message transmission. The timestamp synchronization adopted in this solution can help the receiving end better understand the sending time of the data message, thereby resisting the impact of network delays and fluctuations on the accuracy of clock synchronization.

[0126] Step S13: sending the wired synchronization master clock message to the wired connection device, and sending the air interface synchronization master clock message to the wireless connection device.

[0127] It is understandable that, as a master device, the base station needs to send a master clock message to the next-level device so that the next-level device can restore the synchronous clock.

[0128] In one embodiment, the wired synchronization master clock message is sent to the wired connection device via network port transmission. In addition, the air interface synchronization master clock message is sent to the wireless connection device via air interface transmission.

[0129] The transmission of messages between the base station and wired devices through the network port mainly involves the following two types of clock synchronization protocols:

[0130] The first category: 802.1as, PTCP (Path MTU Discovery Protocol), and CIP sync (Common Internet Protocol Signaling Synchronization) are clock synchronization protocols derived from 1588.

[0131] 802.1as provides more specific regulations and restrictions for 1588, PTCP cuts out 1588 functions, and CIP sync uses the ETE measurement method of the 1588 protocol and expands the time step detection function.

[0132] Taking the master and slave base stations as an example, this type of synchronization requires the master station to use independent messages to transmit information to the slave station, and the slave station also responds through independent messages. The core algorithm needs to be implemented in both the master station and the slave station.

[0133] The second category: Powerlink (Powerlink Communication, power line communication), SercosIII (Siemens Real-Time Communication Protocol, Siemens real-time communication protocol), EtherCAT (ethernet for Control Automation Technology, Ethernet control automation technology).

[0134] Features: Logical ring structure simplifies the calculation mechanism of link delay. The calculation of link delay and residence time needs to be implemented at the master station.

[0135] Wired PTP clock synchronization accuracy: Taking IEEE 802.1as as an example, IEEE 802.1AS is a simplified and adjusted version of IEEE1588. This protocol operates at the link layer, inserting time information into data frames and transmitting it to each network node. In a network environment with a maximum of 7 hops, it can ensure clock synchronization error within 1 μs.

[0136] In addition, referring to FIG10 , before step S11, the following steps are included:

[0137] Step S14: When the base station is set as a slave base station, receiving the wired synchronous master clock message sent by the master base station;

[0138] Step S15: performing a synchronous clock recovery action according to the wired synchronous master clock message;

[0139] It is understandable that when the current base station is a slave base station, it does not need to perform operations such as frequency division and jitter elimination on the local crystal oscillator. It only needs to synchronize the clock according to the message sent by the upper-level master base station.

[0140] In one embodiment, according to the port information of the primary base station sending the message, the corresponding port is monitored to receive the wired synchronization master clock message sent by the primary base station in real time. After receiving the message, the following operations are performed:

[0141] On the one hand, according to the communication protocol used by the main base station to send the message, the location and format of the time information in the message is determined, and then the field or data structure containing the main clock source time information is found, and it is parsed and processed to obtain readable time information.

[0142] On the other hand, the current local time of the local clock is obtained by calling the interface.

[0143] At this point, the time information of the master base station and the local time information can be compared to calculate the time offset between them. The time offset can be calculated by a simple subtraction operation, that is, subtracting the local time from the time of the master base station.

[0144] After calculating the time offset, you need to apply the calculated time offset to the local device's clock to adjust the local clock for clock synchronization. Specific adjustment methods include time counter adjustment, clock frequency adjustment, and clock reset. For example, in some devices, the clock's counter is used to record time. Therefore, you can change the clock time by adjusting the counter value. For example, if the counter value is one second ahead of the actual time, you can adjust the clock by subtracting one second from the counter value.

[0145] Step S11 includes:

[0146] Step S16: Using the recovered synchronous clock as the clock synchronization source.

[0147] In one embodiment, after the slave base station completes the synchronous clock recovery operation, the clock of the slave base station is consistent with the clock of the master base station. At this point, the clock source inside the slave base station can be used as a new clock synchronization source to synchronize the clock of the next-level device.

[0148] In the process of clock synchronization of the next-level device from the base station, the second pulse and time information used can continue to use the previous second pulse and time information to improve the overall efficiency of time synchronization.

[0149] In addition, referring to FIG11 , after step S13, the following steps are further included:

[0150] Step S17: Calculating the data sending time period of the controller according to the service control cycle parameter;

[0151] It is understandable that after the base station and the controller complete clock synchronization, this solution also proposes a timing control method between the base station and the controller to support the implementation of service functions between the two.

[0152] Service control cycle parameters refer to the time parameters that control the implementation of service functions, usually including frame structure, transmission timing, access control cycle, scheduling cycle, etc. Among them, the frame structure defines the time slot and duration of each communication frame so that the main base station and controller can transmit data and exchange control signaling within a specific time; the transmission timing determines the timing and sequence of data transmission to ensure that data can be transmitted and processed in the correct order and timing; the access control cycle is used to control the access and departure of user equipment to ensure the reasonable allocation and management of network resources; the control cycle is used to schedule and allocate wireless resources to meet different service requirements and optimize network performance.

[0153] In one embodiment, the base station calculates the application layer data sending time period provided by the controller through the above parameters, and determines information such as the timing, sequence, and transmission duration of data transmission.

[0154] For example, assuming the base station needs to send actuator feedback data to the controller, the base station first calculates the application layer data delivery time period provided by the controller based on service control cycle parameters, such as frame structure and transmission timing. This may determine that a frame of actuator feedback data needs to be sent to the controller every 10ms.

[0155] Step S18: sending timing information to the controller during the data sending time period according to the second pulse corresponding to the clock synchronization source.

[0156] In one embodiment, the base station sends timing information to the controller at the corresponding time point based on its own interrupt, that is, the second pulse corresponding to the clock synchronization source, to notify the controller to complete service operations such as data collection, processing, and distribution within the specified time.

[0157] For example, the base station will send timing information to the controller every 10ms based on the second pulse, which may include a timestamp, time interrupt, and packet transmission time zone. In this way, after receiving the timing information sent by the base station, the controller will schedule the transmission of application layer data every 10ms.

[0158] In this way, base stations and controllers can communicate and collaborate at predetermined time points to support the implementation of business functions and the reliability of data transmission, thereby ensuring the stability and performance of the communication system and improving the user experience.

[0159] In one technical solution provided in this embodiment, the master clock source within the base station is used as the clock synchronization source for the converged control system. Corresponding wired and air interface master clock synchronization messages are constructed and sent to wired and wireless devices, respectively. This ensures that the reference clock source used by the next-level devices is the same, and thus the clock synchronization results of wired and wireless devices remain consistent. This effectively resolves the time deviation issue between the two and ensures the reliability of the clock synchronization results of the entire converged control system.

[0160] An embodiment of the present application provides a clock synchronization method, which is applied to a controller in a fusion control system. Referring to FIG. 12 , FIG. 12 is a flow chart of a second embodiment of a clock synchronization method of the present application.

[0161] In this embodiment, the clock synchronization method includes:

[0162] Step S21: receiving a wired synchronization master clock message sent by a base station;

[0163] Step S22: Execute a synchronous clock recovery action according to the wired synchronous master clock message.

[0164] Optionally, the second side of the controller in the integrated control system is connected to the base station via a wired connection, so the controller receives a wired synchronization master clock message sent by the base station through the network port.

[0165] On the one hand, the time information of the base station is determined according to the wired synchronous master clock message. On the other hand, the local time information of the controller is obtained, the two time information are compared, and the executor is synchronized and recovered according to the comparison result. The specific principle is the same as the synchronous clock recovery action from the base station in the first embodiment, and will not be repeated here.

[0166] In addition, referring to FIG13 , after step S22, the following steps are included:

[0167] Step S23: Receive the timing information sent by the base station, and handle the service within the specified time corresponding to the timing information.

[0168] It is understandable that after the base station and the controller complete clock synchronization, this solution also proposes a timing control method between the base station and the controller to support the implementation of service functions between the two.

[0169] In one embodiment, when the controller receives the timing information sent by the base station, the controller will handle services, such as data collection, processing, and distribution, within a specific time period according to the timing information.

[0170] For example, after the controller receives the timing information sent by the base station, it will cooperate at a predetermined time point, such as arranging the delivery of application layer data every 10ms to support the transmission and playback of actuator feedback data, ensuring the reliability and real-time performance of data transmission.

[0171] As for the actuators in the converged control system, they are connected to the actuator or base station via a wired connection. Therefore, they receive wired synchronization master clock messages from the base station or controller through the network port. They then perform synchronization clock recovery based on these wired synchronization master clock messages. The specific principles are similar to those of the actuators and are not detailed here.

[0172] In one technical solution provided in this embodiment, upon receiving a wired master clock synchronization message from a base station, a wired device performs clock synchronization recovery based on the message. This means that the wired device uses the base station's internal master clock source as a reference for synchronization, and the wireless device does the same. This means that the reference clock source for both the wired and wireless devices is the same, resulting in consistent clock synchronization. This effectively resolves time deviation issues and ensures the reliability of the clock synchronization results for the entire converged control system.

[0173] An embodiment of the present application provides a clock synchronization method, which is applied to a wireless connection device in a fusion control system. Referring to FIG. 14 , FIG. 14 is a flow chart of a third embodiment of a clock synchronization method of the present application.

[0174] In this embodiment, the clock synchronization method includes:

[0175] Step S31: receiving an air interface synchronization master clock message sent by a base station;

[0176] Step S32: Obtain the master timestamp working clock associated with the air interface synchronization master clock message and the slave timestamp working clock used locally;

[0177] Step S33: Perform a synchronous clock recovery action according to the master timestamp working clock and the master timestamp working clock.

[0178] In one embodiment, as shown in Figure 9, the entire base station is considered the physical layer, and air interface synchronization master clock messages are transmitted to wireless connection devices via the deterministic enhanced wireless system air interface. Accordingly, the wireless connection device receives the wireless signal carrying the air interface synchronization master clock message from the base station and obtains a digital data stream through steps such as signal conversion and digital demodulation.

[0179] The digital data stream then passes through the physical layer for processing, including channel decoupling, channel estimation, and equalization, to restore the original data information. The processed data at the physical layer is then sent to the data link layer for further processing, including parsing the message header information and extracting valid data.

[0180] After the above processing, the master timestamp working clock associated with the air interface synchronization master clock message can be obtained, and the slave timestamp working clock used locally by the wireless connection device can also be obtained.

[0181] At this point, the time offset between the base station and the wireless connection device can be determined based on the master timestamp working clock and the master timestamp working clock, and then a synchronous clock recovery action can be performed based on the time offset.

[0182] Exemplarily, a deterministic timestamp location is set, including but not limited to a physical layer, data link layer, or other location. A master timestamp tag, stamped by a master timestamp working clock, and a slave timestamp tag, stamped by a slave timestamp working clock, are then determined at the deterministic timestamp location. The master timestamp tag represents the time the message was sent, and the slave timestamp tag represents the time the message was received. The time offset between the base station and the wireless connection device is then calculated based on the master timestamp tag and the slave timestamp tag, i.e., the time of sending and receiving. Based on this time offset, the wireless connection terminal can calibrate its own time to synchronize it with the time of the master base station.

[0183] After that, the PTP protocol stack (Precision Time Protocol) can be run to recover the second pulse and time information so as to synchronize the clock of the next level device of the wireless connection device.

[0184] In addition, referring to FIG15 , before step S33, the following steps are also included:

[0185] Step S34: sending a delayed message to the base station and determining a sending time of the delayed message;

[0186] Step S35: receiving the reception time of the delayed message sent by the base station;

[0187] Step S33 includes:

[0188] Step S36: Execute a synchronous clock recovery action according to the master timestamp working clock and the master timestamp working clock, as well as the sending time and the receiving time of the delayed message.

[0189] It is understood that the base station, as the master clock source, synchronizes wireless devices by transparently transmitting timestamp information from the processor, switch chip, network port PHY chip, etc. over the air interface, thus synchronizing the timestamp information of the wireless devices with the timestamp of the base station. Furthermore, as shown in Figure 16, air interface resource reservation can also be used to ensure the determinism of air interface transmission.

[0190] In one embodiment, a master clock message sent by a base station is received, which can be understood as a Sync message (Synchronization message), and the time t1 when the base station sends the Sync message and the time t2 when the wireless connection device receives the Sync message are determined, which can be specifically determined based on the master timestamp tag and the slave timestamp tag.

[0191] In one embodiment, the wireless connection device sends a Delay Request message (hereinafter referred to as a Delay_Req message) to the base station. The wireless connection device determines the sending time t3 of the Delay_Req message. Upon receiving the Delay_Req message, the base station sends the receipt time t4 to the wireless connection device.

[0192] Through the above message transmission process, the wireless connection device obtains four time points, t1, t2, t3, and t4, and uses these four time points to calculate the path delay and time deviation between the base station and the wireless connection device. The formula is as follows:

[0193] Total round-trip link delay between the base station and the wireless connection device = [(t2-t1)+(t4-t3)]

[0194] One-way link delay between base station and wireless connection device = [(t2-t1)+(t4-t3)] / 2

[0195] The clock offset of the wireless connection device relative to the base station is Offset = (t2-t1)-[(t2-t1)+(t4-t3)] / 2 = [(t2-t1)-(t4-t3)] / 2

[0196] The wireless connection device adjusts the local time according to the time deviation obtained by the above calculation, so as to achieve clock synchronization with the base station.

[0197] Based on the air interface synchronization master clock message, this solution obtains the sending and receiving times of the delayed message and calculates them into the time deviation. This compensates for the uncertainty of transmission time caused by various factors to a certain extent, thereby more accurately calibrating the local clock, ensuring that the clocks of wireless connection devices remain synchronized with the base station, and improving accuracy and reliability.

[0198] In one technical solution provided in this embodiment, upon receiving an air interface synchronization master clock message from a base station, a wireless device compares its associated master timestamp working clock with the locally used slave timestamp working clock, and then performs a synchronization clock recovery operation. In other words, the wireless device synchronizes using the base station's internal master clock source as a reference, and the wired device does the same. That is, the wireless and wired devices share the same reference clock source, ensuring consistent clock synchronization results. This effectively resolves the time deviation issue between the two and ensures the reliability of the clock synchronization results for the entire converged control system.

[0199] For example, the wired-wireless converged control system shown in FIG17 includes several base stations, controllers, actuators, and wireless terminals. As shown in FIG18 , one of the base stations is selected as the main base station and set as the clock synchronization source for the entire system, and then the controllers, actuators, wireless terminals and other devices on the link nodes are synchronized.

[0200] Step 1: Set base station 0 as the main base station;

[0201] Step 2: Complete the synchronization between base station 0 and base station 1;

[0202] Step 3: Complete the synchronization between base station 0 and controller 0;

[0203] Step 4: Complete the synchronization between base station 1 and controller 1;

[0204] Step 5: Complete the synchronization between controller 0 and its directly connected actuator;

[0205] Step 6: Complete the synchronization between controller 1 and the actuator it is directly connected to;

[0206] Step 7: Complete synchronization between base station 0 and its directly connected terminal;

[0207] Step 8: Complete synchronization between base station 1 and its directly connected terminal;

[0208] In addition, after the clocks of the industrial wireless base station are synchronized with those of the wired controller and actuator, the following timing control alignment is designed as an example to achieve synchronous timing between the industrial wireless and wired systems, as shown in Figure 19.

[0209] The frame structure of the base station has a 1ms period and a total of 8 slots. Slots 0 to 3 are D slots with a timing length of 0.5ms, corresponding to D in the figure. Slots 4 to 7 are U slots with a timing length of 0.5ms, corresponding to U in the figure.

[0210] Wireless transmission needs to be sent two slots in advance, that is, the application layer data of the controller needs to be sent to the base station 250us in advance.

[0211] The wireless receiving process needs to be delayed by two slots, that is, the data decoded by the wireless terminal needs to be delayed by 250us before being sent to the driver.

[0212] The entire wireless processing takes 1ms, including two slots for sending, two slots for receiving, and four slots for air interface transmission.

[0213] The controller's interrupt is 250us earlier than the base station's interrupt, and the time it takes to receive data, process, and send application layer data packets is 1ms.

[0214] The time it takes for the driver to receive data, process and send feedback data packets is also 1ms. The feedback it provides is the current loop, position loop and other data of the previous control cycle.

[0215] In Figure 19:

[0216] △t1 PLC The time it takes for the PLC to receive data, perform calculations, and send data, and the execution cycle begins;

[0217] △t1 PLC_MS The time it takes for PLC data to be transmitted to MS via wire

[0218] △t1 MS_SLAVE The wireless transmission time from the MS to the slave after receiving the data packet from the wired station and processing it wirelessly

[0219] △t1 SLAVE The execution time after the servo receives the PLC data packet + the current loop and position loop sampling data packaging time

[0220] △t1 SLAVE_MS The wireless transmission time from the TS to the PLC after receiving the data packet from the servo and processing it wirelessly

[0221] △t1 MS_PLC The time it takes for the servo data packet to be transmitted from the MS to the PLC via the wire

[0222] △t1 PLC’ The time it takes for the PLC to receive data, perform calculations, and send data. The execution cycle ends

[0223] △t1 PLC_Send The absolute time when the PLC data packet is sent, including year, month, day, hour, minute, and second

[0224] △t1PLC_Receive is the absolute time when the servo data packet is received by the PLC, including year, month, day, hour, minute and second.

[0225] △t1PLC_Receive=△t1 PLC_Send +△t1 PLC +△t1 PLC_MS +△t1 MS_SLAVE +△t1 SLAVE +△t1 SLAVE_MS +△t1 MS_PLC +△t1 PLC’

[0226] Refer to Figure 20, which is a schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present application.

[0227] As shown in Figure 20, the device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to implement connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and optionally the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (WI-FI) interface). The memory 1005 may be a high-speed random access memory (RAM) memory, or a stable non-volatile memory (NVM), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0228] Those skilled in the art will understand that the structure shown in FIG20 does not constitute a limitation on the device, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0229] As shown in FIG. 20 , the memory 1005 as a storage medium may include an operating system, a data storage module, a network communication module, a user interface module, and a clock synchronization program.

[0230] In the device shown in Figure 20, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the device of this application can be set in the device, and the device calls the clock synchronization program stored in the memory 1005 through the processor 1001, and executes the clock synchronization method provided in the embodiment of this application.

[0231] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps in any one of the embodiments of the above-mentioned clock synchronization method are implemented.

[0232] Since the embodiments of the computer-readable storage medium part correspond to the embodiments of the method part, the embodiments of the computer-readable storage medium part refer to the description of the embodiments of the method part and are not repeated here.

[0233] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0234] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0235] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0236] The above are merely optional embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A clock synchronization method is applied to a base station of a fusion control system, wherein the fusion control system further comprises a controller, an actuator and a terminal device, wherein a first side of the controller is connected to the actuator by a wired connection, a second side of the controller is connected to the base station by a wired connection, the actuator is connected to the actuator or the base station by a wired connection, and the terminal device is connected to the base station by a wireless connection, wherein the clock synchronization method comprises the following steps: Selecting a master clock source inside the base station as a clock synchronization source for the fusion control system; According to the clock synchronization source, construct a wired synchronization master clock message and an air interface synchronization master clock message; The wired synchronization master clock message is sent to the wired connection device, and the air interface synchronization master clock message is sent to the wireless connection device.

2. The clock synchronization method according to claim 1, wherein: The step of constructing a wired synchronization master clock message and an air interface synchronization master clock message according to the clock synchronization source comprises: Distributing the clock signal corresponding to the clock synchronization source to the clock divider and the phase-locked loop; Divide the clock signal by the clock divider to generate corresponding second pulses and time information; Eliminate jitter of the clock signal through the phase-locked loop to generate a master timestamp working clock; generating the wired synchronous master clock message according to the second pulse and the time information; and The air interface synchronization master clock message is generated according to the master timestamp working clock, the second pulse and the time information.

3. The clock synchronization method according to claim 1, wherein: The step of selecting the master clock source inside the base station as the clock synchronization source of the fusion control system comprises: When the base station is a main base station, obtaining a wireless system design requirement of the integrated control system, and determining a crystal oscillator frequency deviation index according to the wireless system design requirement; The target crystal oscillator selected according to the crystal oscillator frequency deviation index is used as the clock synchronization source.

4. The clock synchronization method according to claim 1, wherein: Before the step of selecting the master clock source inside the base station as the clock synchronization source of the fusion control system, the method includes: When the base station is set as a slave base station, receiving the wired synchronous master clock message sent by the master base station; Execute a synchronous clock recovery action according to the wired synchronous master clock message; The step of selecting the master clock source inside the base station as the clock synchronization source of the fusion control system comprises: The restored synchronous clock is used as the clock synchronization source.

5. The clock synchronization method according to any one of claims 1 to 4, wherein: After the step of sending the wired synchronization master clock message to the wired connection device and sending the air interface synchronization master clock message to the wireless connection device, the method further includes: Calculate the data sending time period of the controller through the service control cycle parameter; According to the second pulse corresponding to the clock synchronization source, timing information is sent to the controller during the data sending time period.

6. A clock synchronization method, applied to a controller of a fusion control system, the clock synchronization method comprising the following steps: Receive the wired synchronization master clock message sent by the base station; A synchronous clock recovery action is performed according to the wired synchronous master clock message.

7. The clock synchronization method according to claim 6, wherein: After the step of performing a synchronous clock recovery action according to the wired synchronous master clock message, the method further comprises: Receive the timing information sent by the base station, and handle the service within the specified time corresponding to the timing information.

8. A clock synchronization method, applied to an actuator of a fusion control system, the clock synchronization method comprising the following steps: Receive wired synchronization master clock message sent by base station or controller; A synchronous clock recovery action is performed according to the wired synchronous master clock message.

9. A clock synchronization method, applied to a wireless connection device of a fusion control system, the clock synchronization method comprising the following steps: Receive the air interface synchronization master clock message sent by the base station; Obtain the master timestamp working clock associated with the air interface synchronization master clock message, and the slave timestamp working clock used locally; A synchronous clock recovery action is performed according to the master timestamp working clock and the master timestamp working clock.

10. The clock synchronization method according to claim 9, wherein: Before the step of performing a synchronous clock recovery action according to the master timestamp working clock and the master timestamp working clock, the method includes: Sending a delayed message to the base station, and determining a time to send the delayed message; Receiving a receiving time of the delayed message sent by the base station; The step of performing a synchronous clock recovery action according to the master timestamp working clock and the master timestamp working clock comprises: A synchronous clock recovery action is performed according to the master timestamp working clock and the master timestamp working clock, as well as the sending time and the receiving time of the delayed message.

11. A base station, comprising: A memory, a processor, and a clock synchronization program stored in the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method according to any one of claims 1 to 5.

12. A controller comprising: A memory, a processor, and a clock synchronization program stored in the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method according to any one of claims 6 to 7.

13. An actuator, comprising: A memory, a processor, and a clock synchronization program stored in the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method according to claim 8.

14. A wireless connection device, comprising: A memory, a processor, and a clock synchronization program stored in the memory and executable on the processor, wherein the clock synchronization program is configured to implement the steps of the clock synchronization method according to any one of claims 9 to 10.

15. A computer-readable storage medium, wherein: The computer-readable storage medium stores a clock synchronization program, and when the clock synchronization program is executed by a processor, the steps of the clock synchronization method according to any one of claims 1 to 10 are implemented.

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