Anti-fatigue ferroelectric capacitor, ferroelectric storage circuit, ferroelectric memory, and chip

Abstract

The present invention relates to the field of memories, and in particular to an anti-fatigue ferroelectric capacitor, a ferroelectric storage circuit, a ferroelectric memory, and a chip. The ferroelectric capacitor comprises: an upper electrode layer, a top electrode layer, a ferroelectric dielectric layer and a bottom electrode layer. The ferroelectric dielectric layer is made of ZrO2, HfO2 or HfxZr1-xO2; an amorphous protective layer is further provided between the top electrode layer and the ferroelectric dielectric layer; the amorphous protective layer uses the same matrix as the ferroelectric dielectric layer and is doped with a preset amount of element Al, Si, La, Y, Nb, Ce or Er to enable the amorphous protective layer to reach an amorphous state; and the thickness of the amorphous protective layer is 10%-40% of the thickness of the ferroelectric dielectric layer. The ferroelectric capacitor can be used for preparing devices such as FeFET and FRAM. The amorphous protective layer in the present invention blocks the connection of a grain boundary, reduces the overall electric leakage, and inhibits the formation of oxygen vacancy conductive filaments, thereby overcoming the defect of insufficient fatigue resistance of conventional devices and prolonging the storage life of the ferroelectric memory.

Description

Fatigue-resistant ferroelectric capacitor, ferroelectric storage circuit, ferroelectric memory and chip Technical Field

[0001] The present invention belongs to the field of memory, and in particular relates to a fatigue-resistant ferroelectric capacitor, a ferroelectric storage circuit, a ferroelectric memory and a non-volatile memory chip. Background Art

[0002] With the development of big data, cloud computing, the Internet of Things, and AI, memory is playing an increasingly important role in the entire internet ecosystem. However, traditional memory devices such as dynamic random access memory (DRAM) and flash memory (NAND Flash) face significant challenges in the face of explosive data growth. Semiconductor technology, based on Moore's Law, faces the challenge of reaching the limit of geometric miniaturization, increasing manufacturing costs, and slowing improvements in storage performance. Traditional memory devices are limited by process limitations in power consumption, data access speed, and storage density, hindering their ability to keep pace with the times. Against this backdrop, a variety of new memory technologies have emerged, such as ferroelectric field-effect transistors (FeFETs). These devices utilize the ferroelectric properties of ferroelectric materials—the ability to retain polarization even after power is removed—to store and retrieve information.

[0003] Among ferroelectric memories, hafnium zirconium oxide (HZO) FeFETs have the advantages of fast read and write speed, non-volatility, low power consumption, and ease of CMOS integration, making them the ideal choice for new memory breakthroughs. Compared with traditional perovskite oxide ferroelectric materials such as Pb(Zr,Ti)O3 (PZT), HZO systems have several advantages: high scalability, meaning that they can still have sufficient ferroelectric properties even at thicknesses below 10 nm; a suitable coercive field (E c ), which can optimize the switching voltage under the ultra-thin limit; and compatibility with CMOS manufacturing technology. Therefore, HZO-based ferroelectric capacitors show broad application potential in related devices such as FeFETs and ferroelectric random access memories (FRAM).

[0004] Writing data into a ferroelectric capacitor involves applying an external electric field (E work ) to switch the polarization of the ferroelectric domain. E work It is necessary to use a coercive field much higher than twice the E c ), to accommodate E c Uneven distribution in different devices, and E due to wake-up effect and fatigue effect c However, the high E c Lead to E workClose to the breakdown voltage, it leads to high failure rate and material degradation, that is, fatigue effect, which affects the product life and hinders its industrialization. Previously, scientists from various countries have tried many methods to improve the fatigue effect of HZO films, such as defect control, phase control, capping effect and interface layer control, but none of them have produced a completely satisfactory solution to overcome the high E work Reliability issues caused by this. Among them, the capping technology is to add a thin insulating Al2O3 layer at the contact interface between the HZO film and the top electrode to improve the fatigue resistance of the sample. This solution has a certain effect on improving fatigue, but it will also increase the equivalent oxide thickness of the medium, and a certain thickness is required to be effective. The increase in the thickness of Al2O3 will affect the ferroelectricity of the sample, and a thicker Al2O3 layer requires a longer atomic layer deposition production time, which is not conducive to scale miniaturization and large-scale mass production. On the other hand, there is an extra interface between the capping layer and the HZO layer, which poses the risk of an extra layer of interface defects. Summary of the Invention

[0005] In order to solve the defect of short storage life of hafnium zirconium oxide ferroelectric memory due to insufficient fatigue resistance of the thin film structure, the present invention provides a fatigue-resistant ferroelectric capacitor, a high-reliability ferroelectric memory circuit, a high-reliability ferroelectric memory and a non-volatile memory chip.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] A fatigue-resistant ferroelectric capacitor comprises, in order from top to bottom, an upper electrode layer, a top electrode layer, a ferroelectric dielectric layer and a bottom electrode layer. The material of the ferroelectric dielectric layer is ZrO2, HfO2 or Hf x Zr 1-x O2; in particular, an amorphous protective layer is included between the top electrode layer and the ferroelectric dielectric layer. The amorphous protective layer uses the same substrate as the ferroelectric dielectric layer and is doped with a predetermined amount of Al, Si, La, Y, Nb, Ce, or Er to achieve an amorphous state. The thickness of the amorphous protective layer is 10%-40% of the thickness of the ferroelectric dielectric layer.

[0008] As a further improvement of the present invention, the amorphous protective layer is generated by atomic layer deposition technology; the doping material and the ferroelectric dielectric layer material are alternately deposited in a preset order and proportion to obtain the amorphous protective layer of the desired preset thickness.

[0009] As a further improvement of the present invention, the growth method of the amorphous protective layer is as follows:

[0010] First, 2-3 cycles of doping material are deposited directly on the bottom base layer, followed by 8 cycles of ferroelectric dielectric layer material, and finally 2-3 cycles of doping material are deposited.

[0011] As a further improvement of the present invention, the materials of the top electrode layer and the bottom electrode layer are both TiN, and are generated by a plasma enhanced atomic deposition process.

[0012] Furthermore, the thickness of the top electrode layer is 10-20 nm; the thickness of the bottom electrode layer is 5-10 nm.

[0013] As a further improvement of the present invention, the material of the upper electrode layer is SiGe.

[0014] Furthermore, the upper electrode layer is grown by electron beam evaporation technology.

[0015] Furthermore, the thickness of the upper electrode layer is 270-300 nm.

[0016] As a further improvement of the present invention, the ferroelectric dielectric layer is formed by atomic layer deposition technology and has a thickness of 5 nm.

[0017] The present invention also includes a ferroelectric memory circuit, which includes a silicon substrate and a circuit structure on the silicon substrate using the aforementioned fatigue-resistant ferroelectric capacitor. The ferroelectric memory circuit includes two types: FeFET and FRAM.

[0018] The present invention also includes a ferroelectric memory, which is a large-scale integrated circuit composed of the aforementioned ferroelectric memory circuit as a unit circuit. The preparation method of the ferroelectric memory is as follows:

[0019] (1) Clean the silicon substrate and use plasma-enhanced atomic layer deposition technology to grow a whole layer of TiN as the bottom electrode on the surface of the silicon substrate with a thickness of 10-20 nm.

[0020] (2) Atomic layer deposition technology is used to grow a whole layer of ferroelectric dielectric film with a thickness of 5 nm on the surface of the TiN bottom electrode.

[0021] (3) Using atomic layer deposition technology, 2-3 cycles of doping material are deposited on the thin film of the ferroelectric dielectric layer, followed by 8 cycles of ferroelectric layer material, and finally 2-3 cycles of doping material are deposited to obtain the desired amorphous protective layer with a thickness of 1-1.5 nm.

[0022] (4) TiN is grown on the amorphous protective layer using plasma-enhanced atomic layer deposition to obtain a top electrode layer with a thickness of 5-10 nm.

[0023] (5) Use electron beam evaporation equipment to continue growing a 270-300 nm SiGe layer on the top electrode to obtain the required top electrode layer.

[0024] (6) The multilayer structure is patterned using a photolithography process and etched using an inductively coupled plasma (ICP) device to obtain a metal-ferroelectric layer-metal circuit structure.

[0025] As a further improvement of the present invention, the material of the ferroelectric dielectric layer is ZrO2, HfO2 or Hf x Zr 1-x O2. Doping materials are selected from Al, Si, La, Y, Nb, Ce or Er.

[0026] The present invention also includes a non-volatile memory chip, which is formed by packaging the aforementioned ferroelectric memory.

[0027] The technical solution provided by the present invention has the following beneficial effects:

[0028] The present invention provides a novel thin-film structure for ferroelectric capacitors. This structure utilizes HZO thin films doped with elements such as Al, Si, La, Y, Nb, Ce, and Er to create an amorphous protective layer of a certain thickness. This layer disrupts the longitudinal grain boundaries of conventional ferroelectric capacitors, blocks oxygen vacancy migration, and slows the formation of conductive filaments, thereby improving the fatigue resistance of the capacitor. Furthermore, the doping of the amorphous protective layer in the novel structure eliminates unnecessary interfaces, ensuring the stability of the ferroelectric dielectric layer. It also improves the dielectric breakdown performance over time and reduces capacitor leakage.

[0029] The present invention is an improved hafnium zirconium oxy-ferroelectric capacitor. From a product perspective, the thin film structure of the present invention helps to increase the number of polarization reversals of the hafnium zirconium oxy-FeFET device, enhance the fatigue characteristics of the device, and ensure the reliability of data storage within the device. From a process perspective, the solution only needs to change a small link in the growth of the dielectric material and adjust some recipes of the ALD equipment; therefore, it is compatible with existing production lines. The ferroelectric memory provided by the present invention can be produced using existing DRAM production process lines, without the need to design new production lines or explore new processes. It is very easy to put into production and application, and can reduce the production and manufacturing costs of new products while improving performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a thin film structure of a fatigue-resistant ferroelectric capacitor provided in Example 1 of the present invention.

[0031] FIG2 is a schematic diagram of a state of a substrate before deposition in a method for preparing a ferroelectric memory according to embodiment 2 of the present invention.

[0032] FIG3 is a schematic diagram of the state after the bottom electrode layer is formed in the method for preparing the ferroelectric memory according to the second embodiment of the present invention.

[0033] FIG4 is a schematic diagram of the state after the ferroelectric dielectric layer is formed in the method for preparing the ferroelectric memory according to the second embodiment of the present invention.

[0034] FIG5 is a schematic diagram of the state after the amorphous protective layer is formed in the method for preparing a ferroelectric memory according to embodiment 2 of the present invention.

[0035] FIG6 is a schematic diagram of the state after the top electrode layer is formed in the method for preparing the ferroelectric memory according to the second embodiment of the present invention.

[0036] FIG7 is a schematic diagram of the state after the upper electrode layer is formed in the method for preparing the ferroelectric memory according to the second embodiment of the present invention.

[0037] FIG8 is a schematic diagram of the state of the ferroelectric memory after photolithography and development are completed in the method for preparing the ferroelectric memory according to Example 2 of the present invention.

[0038] FIG9 is a structural comparison diagram of three devices in the experimental group and the control group in the performance test.

[0039] FIG10 shows the remnant polarization intensity curves obtained from the high electric field cycling experiment of the three device samples in the performance test.

[0040] FIG11 is a schematic diagram showing the principle of the invention's solution for enhancing anti-fatigue properties. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] Explanation of some technical terms involved in the present invention:

[0043] Fluorite structure: In solid-state chemistry, the fluorite structure refers to a common motif in compounds with the molecular formula MX2. X ions occupy eight tetrahedral interstitial sites, while M ions occupy regular sites in a face-centered cubic structure. The hafnium zirconium oxide ferroelectric layer in the present invention exhibits a fluorite structure.

[0044] Perovskite structure: Perovskite is any material with a crystal structure that follows the formula ABX3, where A and B are two positively charged ions (i.e., cations), typically of very different sizes, and X is a negatively charged ion (anion, usually an oxide) that combines with the two cations. While the ferroelectric dielectric in traditional ferroelectric capacitors uses perovskite structure materials, the new technology provided in this embodiment utilizes a hafnium zirconium-based fluorite structure. Hafnium zirconium-based ferroelectric materials are formed from oxides of Zr and Hf, including ZrO2, HfO2, or HfO2. x Zr 1-x O2.

[0045] Amorphous layer: In condensed matter physics and materials science, amorphous solids are solids lacking the long-range order characteristic of crystals. In this invention, hafnium zirconium oxide ferroelectric dielectric materials are doped with elements such as Al, La, Si, Y, Nb, Ce, and Er to render them amorphous, thus forming an amorphous protective layer. With industrial development and scaling, traditional perovskite-structured ferroelectric systems have faced a series of challenges, including the inability to maintain adequate ferroelectric properties in films smaller than 10 nm and an excessively small and difficult-to-control correction field (approximately 0.1 MV / cm). Emerging fluorite-structured HZO thin films are gradually replacing perovskite materials as the material for ferroelectric memory capacitors. However, the introduction of HZO thin films has also introduced certain fatigue issues. This invention aims to alleviate these fatigue issues in HZO materials using a doped protective layer.

[0046] Example 1

[0047] Traditional perovskite materials have disadvantages such as too low switching voltage (±0.1 V) in FeFET applications. However, with the application of fluorite structure HZO material films, this problem has been effectively improved. However, while HZO material films increase the switching voltage in ferroelectric capacitors, they also bring higher coercive field E. c As the coercive field (±0.8-2 V) increases, the fatigue characteristics of the HZO film are greatly weakened. This results in: the ferroelectric memory prepared by the ferroelectric capacitor of the conventional perovskite material flips about 10 under the working voltage. 15 The device fails after 10 cycles, while the ferroelectric memory prepared by the ferroelectric capacitor using HZO film flips about 10 cycles under the working voltage. 10 The short lifespan of ferroelectric memory devices, caused by the insufficient fatigue resistance of HZO thin films, is becoming a major obstacle to their industrialization.

[0048] The main reason for the failure of hafnium zirconium oxide ferroelectric memory devices is that when voltage is applied, oxygen vacancies are generated inside the dielectric. After long-term use, excessive oxygen vacancies form conductive filaments in the film, forming conductive paths, which lead to device failure. In order to overcome this problem, this embodiment provides a new fatigue-resistant ferroelectric capacitor, as shown in Figure 1. In order from top to bottom, it includes: an upper electrode layer, a top electrode layer, a ferroelectric dielectric layer and a bottom electrode layer. The material of the ferroelectric dielectric layer is ZrO2, HfO2 or Hf x Zr 1-xO2. In particular, an amorphous protective layer is further included between the top electrode layer and the ferroelectric dielectric layer. The amorphous protective layer uses the same substrate as the ferroelectric dielectric layer and is doped with a predetermined amount of Al, Si, La, Y, Nb, Ce, or Er to achieve an amorphous state. The newly added amorphous protective layer in this embodiment can interrupt the longitudinal grain boundaries, block the migration of oxygen vacancies, and slow the generation of conductive filaments, thereby achieving an anti-fatigue effect.

[0049] In this embodiment, both the amorphous protective layer and the ferroelectric dielectric layer are grown using atomic layer deposition (ALD). The thickness of the ferroelectric dielectric layer is 5 nm, and the thickness of the amorphous protective layer is 10%-40% of the thickness of the ferroelectric dielectric layer. By alternately depositing the doping material and the ferroelectric dielectric layer material in a predetermined order and proportion, an amorphous protective layer of the desired predetermined thickness can be obtained. Specifically, the amorphous protective layer growth method in this embodiment is as follows:

[0050] First, 2-3 cycles of doping material are deposited directly on the bottom base layer, followed by 8 cycles of ferroelectric dielectric layer material, and finally 2-3 cycles of doping material are deposited.

[0051] In this embodiment, the top and bottom electrode layers are both made of TiN and deposited using plasma-enhanced atomic layer deposition (PEALD). The top electrode layer has a thickness of 10-20 nm, while the bottom electrode layer has a thickness of 5-10 nm. The top electrode layer is made of SiGe and deposited using electron beam evaporation (Ebeam) technology, with a thickness of 270-300 nm.

[0052] Example 2

[0053] Based on the novel ferroelectric capacitor thin film structure proposed in Example 1, this embodiment further provides a ferroelectric memory circuit comprising a silicon substrate and a circuit structure employing the aforementioned fatigue-resistant ferroelectric capacitor located on the silicon substrate. In actual production applications, this ferroelectric memory circuit includes both FeFET and FRAM types.

[0054] At the same time, this embodiment also provides a ferroelectric memory, which is a large-scale integrated circuit composed of the above-mentioned ferroelectric memory circuit as a unit circuit. The preparation method of the ferroelectric memory is as follows:

[0055] Prepare a silicon substrate, as shown in Figure 2, and clean it. Then, use plasma-enhanced atomic layer deposition (PEAD) to grow a full layer of TiN (10-20 nm thick) on the silicon substrate as a bottom electrode. The resulting bottom electrode, shown in Figure 3, completely covers the silicon substrate.

[0056] Next, an atomic layer deposition technique was used to grow a complete ferroelectric dielectric thin film on the TiN bottom electrode surface at a rate of approximately 0.78-1 Å / cycle, or 50-65 cycles. The resulting ferroelectric dielectric layer, shown in Figure 4, was approximately 5 nm thick. At this point, the ferroelectric dielectric completely covered the bottom electrode.

[0057] Next, the atomic layer deposition technique is used to deposit 2-3 cycles of doping material on the thin film of the ferroelectric dielectric layer, and then 8 cycles of ferroelectric dielectric layer material are deposited, and finally 2-3 cycles of doping material are deposited. At this point, a ferroelectric dielectric layer with an amorphous protective layer as shown in Figure 5 can be obtained, wherein the thickness of the amorphous protective layer is 1-1.5 nm. In this stage, the material of the ferroelectric dielectric layer is selected from ZrO2, HfO2 or Hf x Zr 1-x O2, and the ferroelectric dielectric layer and the amorphous protective layer are made of the same material. The doping material can be selected from: Al, Si, La, Y, Nb, Ce or Er.

[0058] It should be noted that in this stage, the doping material and the ferroelectric layer material are alternately deposited on the ferroelectric layer thin film. Each cycle is relatively short, and the amount of doping material deposited is limited, insufficient to form a complete thin film of a single material. Therefore, the amorphous protective layer formed in this stage is actually a composite material in which the doping material is uniformly doped into the ferroelectric layer substrate. Furthermore, in the actual processing flow, the deposition method of the doping material and the ferroelectric material is not limited to the sequence and number of cycles mentioned above, as long as the doping amount is sufficient to make the deposited layer reach an amorphous state and the thickness of the resulting amorphous protective layer meets the requirements.

[0059] After this, TiN is grown on the amorphous protective layer using plasma-enhanced atomic layer deposition, as shown in Figure 6. This results in a top electrode layer with a thickness of 5-10 nm. The top and bottom electrodes are made of the same material, but the top electrode is slightly thinner than the bottom electrode. The top electrode layer serves to maintain the crystalline phase of the thin film. After the top electrode is formed, an electron beam evaporation (Ebeam) system is used to grow a 270-300 nm thick SiGe layer on top of the top electrode, resulting in the upper electrode layer shown in Figure 7.

[0060] Finally, the multilayer structure is patterned using a photolithography and development process, and is etched using an inductively coupled plasma (ICP) device to obtain a metal-ferroelectric layer-metal circuit structure as shown in FIG8 .

[0061] In the ferroelectric memory provided in this embodiment, a highly reliable HZO material is achieved by inserting an AZA layer (an amorphous protective layer doped with a ferroelectric dielectric material). This approach neither increases the overall thickness of the HZO film nor affects the ferroelectric properties of the HZO film, ensuring stability and reliability. Furthermore, doping does not introduce unnecessary interfaces, achieving three goals at once.

[0062] The ferroelectric memory provided in this embodiment can also be marketed in the form of a packaged integrated circuit chip. Therefore, this embodiment also provides a non-volatile memory chip, which is formed by packaging the aforementioned ferroelectric memory.

[0063] Performance Testing

[0064] To demonstrate the advantages of the technical solution provided by this invention, researchers conducted a validation experiment using 6 nm alumina-doped zirconium oxide and hafnium zirconium oxide devices as the experimental group, and undoped alumina devices as the control group. High-field cycling of 6 MV / cm was performed on the experimental (ZAZA and HZO-AZA) and control (ZrO2) samples, respectively. This demonstrated the feasibility and superiority of the present invention's solution in the HZO system.

[0065] Figure 9 shows a schematic diagram comparing the structures of a control group of pure zirconia devices without aluminum oxide doping, an experimental group of zirconia devices with an aluminum-doped protective layer, and a device combining an AZA protective layer with a HZO film. Based on the experimental data from the high-field cycling test for these three groups of samples, the remanent polarization intensity curves shown in Figure 10 were plotted. Analysis of the data in Figure 10 shows that:

[0066] The ZAZA film in the experimental group has a significant anti-fatigue effect, while the ZrO2 device in the control group 7 Fatigue occurs within the number of cycles, while ZAZA 7 There is no fatigue trend within the number of cycles, and the fatigue stage of the HZO-AZA film is also somewhat delayed. This shows that the AZA protective layer added to the traditional HZO type device has a significant effect on improving the reliability of the device. At the same time, it can be found from the data that the addition of Al doping does not significantly damage the ferroelectric properties of the device, and the remanent polarization intensity is still 10μC / cm 2 Therefore, the experimental data proves that the scheme of the present invention not only improves the anti-fatigue characteristics of the device, but also does not damage the ferroelectric characteristics of the device, and has very superior performance.

[0067] Figure 11 illustrates the principle behind the superior performance of the present invention. The primary failure mechanism of conventional HZO thin films under high-field cycling is that the electric field causes an increase in oxygen vacancies within the film. For polycrystalline HZO thin films, oxygen vacancies are distributed along the grain boundaries, gradually increasing and forming conductive filaments, leading to device failure. However, the present invention incorporates an additional amorphous protective layer, which blocks the connectivity of the grain boundaries, reducing overall leakage and thus suppressing the formation of oxygen vacancy conductive filaments.

[0068] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fatigue-resistant ferroelectric capacitor, comprising, in order from top to bottom: The upper electrode layer, the top electrode layer, the ferroelectric dielectric layer and the bottom electrode layer are characterized in that the material of the ferroelectric dielectric layer is a fluorite structure material ZrO2, HfO2 or Hf x Zr 1-x O2; an amorphous protective layer is also included between the top electrode layer and the ferroelectric dielectric layer; the amorphous protective layer adopts the same fluorite structure matrix as the ferroelectric dielectric layer, and is doped with a preset amount of Al, Si, La, Y, Nb, Ce, or Er elements to make the amorphous protective layer reach an amorphous state; the thickness of the amorphous protective layer is 10%-40% of the thickness of the ferroelectric dielectric layer.

2. The fatigue-resistant ferroelectric capacitor according to claim 1, wherein: The amorphous protective layer is generated by atomic layer deposition technology; the doping material and the ferroelectric dielectric layer material are alternately deposited in a preset order and proportion to obtain the amorphous protective layer with the required preset thickness.

3. The fatigue-resistant ferroelectric capacitor according to claim 2, wherein: The growth method of the amorphous protective layer is as follows: First, 2-3 cycles of doping material are directly deposited on the bottom base layer, followed by 8 cycles of ferroelectric dielectric layer material, and finally 2-3 cycles of doping material are deposited again.

4. The fatigue-resistant ferroelectric capacitor according to claim 1, wherein: The materials of the top electrode layer and the bottom electrode layer are both TiN, and are generated by a plasma enhanced atomic deposition process.

5. The fatigue-resistant ferroelectric capacitor according to claim 4, characterized in that: The thickness of the top electrode layer is 10-20 nm; the thickness of the bottom electrode layer is 5-10 nm.

6. The fatigue-resistant ferroelectric capacitor according to claim 1, wherein: The material of the upper electrode layer is SiGe.

7. The fatigue-resistant ferroelectric capacitor according to claim 1, wherein: The upper electrode layer is formed by electron beam evaporation technology.

8. The fatigue-resistant ferroelectric capacitor according to claim 1, wherein: The thickness of the upper electrode layer is 270-300 nm.

9. The fatigue-resistant ferroelectric capacitor according to claim 1, wherein: The ferroelectric dielectric layer is generated by atomic layer deposition technology and has a thickness of 5 nm.

10. A ferroelectric memory circuit, characterized in that: It comprises a silicon substrate, and a circuit structure located on the silicon substrate and using the fatigue-resistant ferroelectric capacitor as claimed in any one of claims 1 to 9; the ferroelectric storage circuit comprises FeFET and FRAM.

11. A ferroelectric memory, characterized in that: This is a large-scale integrated circuit composed of the ferroelectric memory circuit according to claim 10 as a unit circuit.

12. The ferroelectric memory according to claim 11, wherein: The preparation method of the ferroelectric memory is as follows: (1) Clean the silicon substrate and use plasma enhanced atomic layer deposition technology to grow a whole layer of TiN on the surface of the silicon substrate as the bottom electrode; (2) Using atomic layer deposition technology to grow a whole layer of ferroelectric dielectric thin film on the surface of the TiN bottom electrode; (3) using atomic layer deposition technology to deposit 2-3 cycles of doping material on the thin film of the ferroelectric dielectric layer, then depositing 8 cycles of material of the ferroelectric dielectric layer, and finally depositing 2-3 cycles of doping material to obtain the desired amorphous protective layer; (4) using plasma enhanced atomic layer deposition to grow TiN on the amorphous protective layer to obtain a top electrode layer; (5) Use electron beam evaporation equipment to continue growing the SiGe layer on the top electrode to obtain the required upper electrode layer: (6) The multilayer structure is patterned using a photolithography process and etched using an inductively coupled plasma (ICP) device to obtain a metal-ferroelectric layer-metal circuit structure.

13. The ferroelectric memory according to claim 12, wherein: The material of the ferroelectric dielectric layer is ZrO2, HfO2 or Hf x Zr 1-x O2; the doping material is selected from Al, Si, La, Y, Nb, Ce or Er.

14. A non-volatile memory chip, characterized in that: It is packaged by the ferroelectric memory as described in any one of claims 11 to 13.

Images