Light detection device and electronic apparatus

Abstract

The present disclosure pertains to a light detection device and an electronic apparatus in which reduction in drain-induced barrier can be inhibited. This light detection device comprises: a photoelectric conversion unit that is provided on a semiconductor substrate and that generates electric charges corresponding to the amount of received light; a gate electrode of a transfer transistor that controls transfer of the electric charges; an electric charge accumulation unit that accumulates the electric charges transferred by the control of the transfer transistor; and a first semiconductor region that is in contact with the charge accumulation unit in the depth direction and a horizontal direction, is of the same first conductivity type as that of a substrate region of the semiconductor substrate, and has an impurity concentration higher than that of the substrate region. The present disclosure is applicable to, for example, a light detection device or the like that has a pixel array unit in which pixels are two-dimensionally arranged in a matrix, and performs photoelectric conversion on incoming light to output a pixel signal corresponding to the amount of the received light.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to a photodetector and an electronic device, and more particularly to a photodetector and an electronic device that are capable of suppressing drain-induced barrier lowering.

[0002] Conventionally, a vertical transistor with a gate electrode structure in which a portion of the gate electrode is embedded in a semiconductor substrate has been used as a pixel transfer transistor in a solid-state imaging device (see, for example, Patent Document 1). By using a vertical transistor as a pixel transfer transistor, it is possible to form a channel between the photodiode and the floating diffusion (FD) even when the photodiode is positioned deep below the transistor formation surface of the semiconductor substrate. This is expected to facilitate the transfer of signal charge, enabling pixel size miniaturization without reducing the saturation charge (Qs) or sensitivity.

[0003] Japanese Patent Application Laid-Open No. 2005-223084

[0004] However, there is a concern that the potential near the channel is not modulated near the on-voltage of the transfer transistor, which is called drain-induced barrier lowering (DIBL).

[0005] The present disclosure has been made in view of the above circumstances, and aims to make it possible to suppress drain-induced barrier lowering.

[0006] A photodetector according to a first aspect of the present disclosure includes: a photoelectric conversion unit provided on a semiconductor substrate, which generates charges according to an amount of received light; a gate electrode of a transfer transistor which controls the transfer of the charges; a charge accumulation unit which accumulates the charges transferred under the control of the transfer transistor; and a first semiconductor region which is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate and which is in contact with the charge accumulation unit in a depth direction and horizontal direction, and has an impurity concentration higher than that of the substrate region.

[0007] An electronic device according to a second aspect of the present disclosure comprises a photodetector device including: a photoelectric conversion unit provided on a semiconductor substrate, which generates charges according to the amount of light received; a gate electrode of a transfer transistor which controls the transfer of the charges; a charge accumulation unit which accumulates the charges transferred under the control of the transfer transistor; and a first semiconductor region which is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate and which is in contact with the charge accumulation unit in the depth direction and horizontal direction and has an impurity concentration higher than that of the substrate region.

[0008] In first and second aspects of the present disclosure, a photodetector device is provided with: a photoelectric conversion unit provided in a semiconductor substrate, which generates charges according to the amount of light received; a gate electrode of a transfer transistor which controls the transfer of the charges; a charge accumulation unit which accumulates the charges transferred under the control of the transfer transistor; and a first semiconductor region which is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate and which is in contact with the charge accumulation unit in the depth direction and horizontal direction, and has an impurity concentration higher than that of the substrate region.

[0009] The photodetector and electronics may be stand-alone devices or may be modules that are incorporated into other devices.

[0010] 1 is a diagram showing a schematic configuration of a photodetection device to which the technology of the present disclosure is applied; FIG. 2 is a diagram showing an equivalent circuit of a pixel of the photodetection device; FIG. 3 is a cross-sectional view and a plan view showing a pixel structure as a comparative example; FIG. 4 is a diagram explaining potential during charge transfer in a pixel structure of the comparative example; FIG. 5 is a diagram showing a first pixel structure adopted as a pixel of the photodetection device; FIG. 6 is a diagram showing potential during charge transfer in the second pixel structure; FIG. 7 is a diagram showing a modified example of the second pixel structure; FIG. 8 is a diagram showing a third pixel structure adopted as a pixel of the photodetection device; FIG. 9 is a diagram showing a fourth pixel structure adopted as a pixel of the photodetection device; FIG. 10 is a diagram showing a sixth pixel structure adopted as a pixel of the photodetection device; FIG. 11 is a diagram showing a seventh pixel structure adopted as a pixel of the photodetection device; FIG. 12 is a diagram showing eighth and ninth pixel structures adopted as pixels of the photodetection device; FIG. 13 is a diagram showing a tenth pixel structure adopted as a pixel of the photodetection device; FIG. 14 is a diagram showing an eleventh pixel structure adopted as a pixel of the photodetection device; FIG. 15 is a diagram showing an example of the schematic configuration of a photodetection device configured with a stacked structure of three substrates. FIG. 1 is a diagram showing an example of the configuration of a sensor pixel and a readout circuit. FIG. 2 is a block diagram showing an example of the configuration of an electronic device. FIG. 3 is a diagram explaining an example of the use of an image sensor. FIG. 4 is a diagram showing an example of the schematic configuration of an endoscopic surgery system. FIG. 5 is a block diagram showing an example of the functional configuration of a camera head and a CCU. FIG. 6 is a block diagram showing an example of the schematic configuration of a vehicle control system. FIG. 7 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0011] Modes for carrying out the technology of the present disclosure (hereinafter referred to as embodiments) will be described below with reference to the accompanying drawings. The description will be given in the following order: 1. Schematic configuration example of a photodetector 2. Equivalent circuit of a pixel 3. Pixel structure as a comparative example 4. First pixel structure of the present disclosure 5. Second pixel structure of the present disclosure 6. Third pixel structure of the present disclosure 7. Fourth pixel structure of the present disclosure 8. Fifth pixel structure of the present disclosure 9. Sixth pixel structure of the present disclosure 10. Seventh pixel structure of the present disclosure 11. Eighth and ninth pixel structures of the present disclosure 12. Tenth pixel structure of the present disclosure 13. Eleventh pixel structure of the present disclosure 14. Summary of pixel structures of the present disclosure 15. Example of stacked configuration using multiple substrates 16. Example of configuration of electronic device 17. Example of use of image sensor 18. Example of application to an endoscopic surgery system 19. Example of application to a moving body

[0012] In the drawings referred to in the following description, identical or similar parts are denoted by identical or similar reference numerals to avoid repetitive explanation. The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios.

[0013] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted.

[0014] In the following description, the "+" and "-" attached to P-type and N-type indicate that the semiconductor region has a relatively high or low impurity concentration compared to the semiconductor region without the "+" or "-" attached. However, even if the semiconductor region is attached with the same symbol containing P or N, it does not mean that the impurity concentration of each semiconductor region is strictly the same.

[0015] The technology disclosed herein can be applied to photodetection devices in general that have a pixel array in which pixels are arranged two-dimensionally in a matrix, perform photoelectric conversion on incident light, and output pixel signals corresponding to the amount of received light. The light detected by the photodetection device for photoelectric conversion may be light in the visible light range including wavelengths such as R (Red), G (Green), and B (Blue), or light in the non-visible light range such as infrared light. Alternatively, light in both the visible and non-visible light ranges may be used. The photodetection device can be used as a solid-state imaging device that generates and outputs an image signal corresponding to the amount of incident light, or as a light receiving device (ranging sensor) in a ranging system that receives infrared light irradiated as active light and measures the distance to a subject using a direct ToF or indirect ToF method.

[0016] 1. Schematic Configuration Example of Photodetector FIG. 1 is a diagram showing a schematic configuration of a photodetector to which the technology of the present disclosure is applied.

[0017] 1 is configured to include a pixel array section 3 in which pixels 2 are arranged two-dimensionally in a matrix on a semiconductor substrate 21 made of, for example, silicon (Si) as a semiconductor, and a peripheral circuit section around the pixel array section 3. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc.

[0018] The pixel 2 includes a photodiode, which is a photoelectric conversion unit, and a plurality of pixel transistors, each of which is made up of, for example, a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is made up of a MOS transistor (MOS FET).

[0019] The pixels 2 may also have a shared pixel structure. This shared pixel structure is composed of multiple photodiodes, multiple transfer transistors, one shared floating diffusion, and one other pixel transistor that is also shared. That is, in the shared pixel structure, each pixel 2 has a photodiode and a transfer transistor, and the other pixel transistors are shared by multiple pixels 2.

[0020] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0021] The vertical drive circuit 4 is configured by, for example, a shift register, selects a predetermined pixel drive wiring 10, supplies a pulse for driving the pixels 2 to the selected pixel drive wiring 10, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 selects and scans each pixel 2 of the pixel array unit 3 row by row in the vertical direction, and supplies a signal based on a signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 9.

[0022] The column signal processing circuits 5 are arranged for each column of pixels 2, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 2. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to each pixel and AD conversion.

[0023] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0024] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0025] The photodetector 1 configured as described above has a structure known as a column AD system, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged for each column. The photodetector 1 generates a signal corresponding to the amount of light received by each pixel 2 in the pixel array section 3 and outputs the signal to the outside. The photodetector 1 can be used, for example, as a solid-state imaging device that detects the distribution of incident light amounts of infrared light or visible light and captures an image, or as a light receiving device in a distance measurement system that receives infrared light and measures the distance to a subject using a direct ToF system or an indirect ToF system.

[0026] 2. Equivalent Circuit of Pixel> FIG. 2 shows an equivalent circuit of the pixel 2.

[0027] The pixel 2 includes, for example, a photodiode PD as a photoelectric conversion unit, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG. The pixel 2 also includes a reset transistor RST, a switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, the switching transistor FDG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, configured as N-type MOS transistors.

[0028] The photodiode PD photoelectrically converts incident light and generates an electric charge (signal charge) according to the amount of incident light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TG, and the anode is electrically connected to a reference potential line (e.g., ground).

[0029] The transfer transistor TG controls the transfer of charges generated in the photodiode PD. When the transfer transistor TG is turned on, it transfers the charges generated in the photodiode PD to the floating diffusion FD. The drain of the transfer transistor TG is electrically connected to the floating diffusion FD, and the gate is electrically connected to a pixel drive wiring. This pixel drive wiring is part of the pixel drive wiring 10 described in FIG. 1.

[0030] The floating diffusion FD is a charge storage unit that temporarily stores the charge transferred from the photodiode PD, and a charge-voltage converter that generates a voltage according to the amount of charge. The floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the switching transistor FDG.

[0031] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive wiring supplied to its gate, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. This pixel drive wiring is part of the pixel drive wiring 10 described in FIG. 1. When the potential of the floating diffusion FD is reset, the switching transistor FDG is also controlled to the on state at the same time.

[0032] The switching transistor FDG is used to change the gain of the charge-to-voltage conversion in the floating diffusion FD. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, the V when converted to a voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, the pixel signal is large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, to prevent V from becoming too large (in other words, to reduce V) when converted to a voltage by the amplifier transistor AMP, the FD capacitance C must be large. Taking these factors into consideration, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor FDG on and off, the FD capacitance C can be varied, thereby changing the conversion efficiency. The pixel drive wiring connected to the gate of the switching transistor FDG is part of the pixel drive wiring 10 described in Figure 1.

[0033] The amplification transistor AMP generates a pixel signal having a voltage corresponding to the level of charge accumulated in the floating diffusion FD. The amplification transistor AMP is connected to a vertical signal line 9 via a selection transistor SEL. The amplification transistor AMP forms a source follower together with a load circuit section in a column signal processing circuit 5 connected to the vertical signal line 9. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit 5 via the vertical signal line 9. The drain of the amplification transistor AMP is connected to a power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.

[0034] The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to a vertical signal line 9, and the gate of the selection transistor SEL is connected to a pixel drive line. When the selection transistor SEL is turned on by the pixel drive line supplied to its gate, it outputs the pixel signal from the amplification transistor AMP to the vertical signal line 9. This pixel drive line is part of the pixel drive line 10 described in FIG. 1.

[0035] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP. The source of the amplification transistor AMP (the output terminal of the pixel 2) is electrically connected to the vertical signal line 9, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0036] The pixel 2 configured as above photoelectrically converts incident light under the control of the vertical drive circuit 4 and outputs a pixel signal according to the amount of received light to the column signal processing circuit 5 via the vertical signal line 9 .

[0037] It is also possible to configure the pixel 2 without the switching transistor FDG, in which case the pixel 2 is configured with four pixel transistors, for example, a transfer transistor TG, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST.

[0038] 3. Pixel Structure as a Comparative Example Below, a pixel structure (pixel structure of the present disclosure) employed in pixel 2 of photodetector 1 will be described, which is a pixel structure near transfer transistor TG and floating diffusion FD, which are portions that transfer charges generated in photodiode PD to floating diffusion FD.

[0039] Before describing the pixel structure of the present disclosure, a pixel structure as a comparative example for comparing the effects of the pixel structure of the present disclosure will be described with reference to Fig. 3. In Fig. 3, for simplicity and ease of understanding, the reference numerals of the pixel structure of the present disclosure will be appropriately quoted.

[0040] FIG. 3 is a cross-sectional view and a plan view showing a pixel structure as a comparative example.

[0041] Fig. 3A is a cross-sectional view showing the pixel structure near the transfer transistor TG and floating diffusion FD of pixel 2', which is a comparative example of pixel 2 of the photodetector device 1. Fig. 3B is a plan view of pixel 2', which is a comparative example. The cross-sectional view of Fig. 3A corresponds to the cross-sectional view taken along line X-X' of Fig. 3B.

[0042] In the pixel 2′ of the comparative example, a PN junction photodiode PD is formed by forming an N-type semiconductor region 42 (hereinafter referred to as the N-type semiconductor region 42) of a second conductivity type in a substrate region 41 (hereinafter referred to as the P-type substrate region 41) of a semiconductor substrate 21 formed of a P-type semiconductor region of a first conductivity type. The P-type substrate region 41 is formed in a region near the interface between the front and back surfaces of the semiconductor substrate 21, and the N-type semiconductor region 42 is formed within the substrate at a position a predetermined distance deeper than both the front and back surfaces of the semiconductor substrate 21. The P-type substrate region 41 facing both the front and back surfaces of the semiconductor substrate 21 also serves as a hole charge accumulation region for suppressing dark current. Examples of P-type impurities introduced into the P-type substrate region 41 include elements belonging to Group 3 of the periodic table, such as boron (B), gallium (Ga), and indium (In). Examples of N-type impurities that can be introduced into the N-type semiconductor region 42 include elements belonging to Group 5 of the periodic table, such as phosphorus (P), arsenic (As), and antimony (Sb). The P-type substrate region 41 and the N-type semiconductor region 42 can be formed by, for example, ion implantation, which implants P-type or N-type impurities.

[0043] The transfer transistor TG of the pixel 2′ is formed on the front surface of the semiconductor substrate 21 opposite the light incident surface (light incident surface), with the back surface being the surface of the semiconductor substrate 21 on which light to be photoelectrically converted is incident. The transfer transistor TG has a vertical gate electrode 51 composed of a planar gate electrode portion 51P formed above the front surface of the semiconductor substrate 21 (hereinafter also referred to as the substrate surface) and a buried gate electrode portion 51V buried inside the semiconductor substrate 21 (hereinafter also referred to as the substrate interior). A gate insulating film 52 of the transfer transistor TG is formed between the vertical gate electrode 51 and the P-type substrate region 41 and the N-type semiconductor region 42. Therefore, the transfer transistor TG is a vertical transistor having a gate electrode structure in which a portion of the vertical gate electrode 51 is buried in the semiconductor substrate 21. The vertical transfer transistor TG has the buried gate electrode portion 51V, which enables easy readout of charges from the photodiode PD formed at a predetermined depth from the substrate surface. The vertical gate electrode 51 is made of, for example, polysilicon, and the gate insulating film 52 is made of, for example, a silicon oxide film (SiO2).

[0044] Hereinafter, the direction parallel to the surface of the semiconductor substrate 21 (X and Y directions) will be referred to as the horizontal direction, and the direction perpendicular to the surface of the semiconductor substrate 21 (Z direction) will be referred to as the depth direction.

[0045] As shown in the plan view of FIG. 3B, the pixel 2' is formed in a square or rectangular region, and the vertical gate electrode 51 of the transfer transistor TG is located in the center of the pixel 2'. FIG. 3B illustrates an example in which the pixel 2' is formed in a square rectangular region. The planar shape of the vertical gate electrode 51 may be circular, elliptical (oval), or rectangular. A pixel separator 54 is formed around the periphery of the pixel 2', forming the boundary between adjacent pixels. The pixel separator 54 separates the photodiode PD, which serves as the photoelectric conversion unit, from adjacent pixels. The pixel separator 54 is formed as a full trench structure that penetrates the semiconductor substrate 21 in the thickness direction, or as a trench structure dug to a predetermined depth into the semiconductor substrate 21. The pixel separator 54 is formed by embedding an insulating film such as SiO2 inside the full trench structure or trench structure. The pixel separator 54 may also be configured by further embedding a metal material such as tungsten, aluminum, silver, or copper inside the insulating film. Alternatively, the pixel separating section 54 may be formed from a P-type semiconductor region and grounded.

[0046] A floating diffusion FD formed of an N-type semiconductor region 53 of the second conductivity type is disposed at one predetermined corner of the pixel 2' formed in a rectangular region. This N-type semiconductor region 53 corresponds to the drain region of the transfer transistor TG. The floating diffusion FD is connected to the gate electrode of the amplification transistor AMP (not shown) via a contact wiring 55.

[0047] In the pixel 2' configured as described above, the symmetry of the pixel structure means that the PD potential at the center of the pixel tends to be deepest in the planar direction. Therefore, placing the vertical gate electrode 51 at the center of the pixel is expected to shorten the transfer time. Furthermore, by using a vertical transfer transistor TG with a buried gate electrode portion 51V embedded in the substrate, even when the photodiode PD is located deep in the pixel, it is possible to form a channel between the photodiode PD and the floating diffusion FD, as shown by the arrow in Figure 3A. This is expected to facilitate signal charge transfer, enabling pixel size miniaturization without reducing the saturation charge (Qs) or sensitivity.

[0048] On the other hand, in pixel 2', the floating diffusion FD is disposed at a corner (pixel corner) of the rectangular pixel region away from the vertical gate electrode 51. Pixel 2', which has the same equivalent circuit as pixel 2 shown in FIG. 2, is in a state where a positive voltage is applied to the floating diffusion FD during charge transfer from the photodiode PD. When a positive voltage is applied to the floating diffusion FD, the region between the N-type semiconductor region 53 and the P-type substrate region 41 of the floating diffusion FD is depleted, and the potential of the floating diffusion FD enters the channel near the vertical gate electrode 51. This raises the concern that the potential near the channel may not be modulated near the on-voltage of the transfer transistor TG, resulting in drain-induced barrier lowering (DIBL).

[0049] 4A is a cross-sectional view using contour lines showing the potential during charge transfer of the photodiode PD in pixel 2′. The potential is highest around region 62 near the floating diffusion FD and lowest around region 63.

[0050] Fig. 4B is a graph analyzing the potential near the channel by changing the gate voltage of the transfer transistor TG. In the graph of Fig. 4B, the potential near a point 5 nm away from the buried gate electrode portion 51V in the X direction (the horizontal direction of the semiconductor substrate 21), which is indicated by point 61 in the potential diagram of Fig. 4A, was analyzed by changing the gate voltage of the transfer transistor TG.

[0051] In Figure 4B, the region of gate voltage on the horizontal axis between 0.6 and 1.0 corresponds to the on-voltage of the transfer transistor TG. In the graph of Figure 4B, a state in which the potential does not change can be seen once the gate voltage exceeds about 0.5.

[0052] Fig. 4C is a graph analyzing the relationship between the gate voltage of the transfer transistor TG and the transconductance gm. In the graph of Fig. 4C, the transconductance gm, which represents the driving force relative to the gate voltage, also decreases from gmMax at a gate voltage of around 0.5, which is thought to lengthen the average transfer time of the signal charge.

[0053] Furthermore, in pixel 2', punch-through occurs due to depletion of the region between the N-type semiconductor region 53 of the floating diffusion FD and the P-type substrate region 41, and the P-type substrate region 41 acts as an extra-gate resistance due to the vertical gate electrode 51 of the transfer transistor TG and the floating diffusion FD being spaced apart. A large switching voltage is required to counteract the adverse effects of the current (leakage current) Ioff when the transfer transistor TG is off and the decrease in the current Ion when the transfer transistor TG is on, which is thought to increase power consumption.

[0054] The following describes a pixel structure of the present disclosure that suppresses drain-induced barrier lowering (DIBL), which is a concern in pixel 2′, reduces electrode consumption, and achieves high-speed imaging.

[0055] 4. First Pixel Structure of the Present Disclosure FIG. 5 shows a first pixel structure employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0056] Fig. 5A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the first pixel structure. Fig. 5B is a plan view of the pixel 2 according to the first pixel structure. The cross-sectional view of Fig. 5A corresponds to the cross-sectional view of Fig. 5B along line X-X'.

[0057] In FIG. 5, parts corresponding to the pixel structure of the pixel 2' according to the comparative example shown in FIG. 3 are given the same reference numerals, and the description of those parts will be omitted as appropriate.

[0058] The first pixel structure shown in FIG. 5 differs from the pixel structure of pixel 2′ according to the comparative example shown in FIG. 3 in that a semiconductor region 71 (hereinafter referred to as the P-type semiconductor region 71) of the same conductivity type (i.e., P-type) as the P-type substrate region 41 but with a higher impurity concentration than the P-type substrate region 41 is further formed in the peripheral region of the N-type semiconductor region 53 that constitutes the floating diffusion FD. The P-type semiconductor region 71 is formed in contact with the bottom and side surfaces of the N-type semiconductor region 53 so as to be in contact with the N-type semiconductor region 53 in the depth direction and horizontal direction. However, as shown in the plan view of FIG. 5B, the side surfaces of the N-type semiconductor region 53 on which the P-type semiconductor region 71 is formed are the two side surfaces on the vertical gate electrode 51 side of the transfer transistor TG. The “P+” indicated on the P-type semiconductor region 71 in FIG. 5 indicates that the impurity concentration is higher than the “P” indicated by the P-type substrate region 41. The P-type semiconductor region 71 can be formed, for example, by ion implantation, in which P-type impurities are implanted.

[0059] The first pixel structure in FIG. 5 is similar to the pixel structure according to the comparative example shown in FIG. 3 except that a P-type semiconductor region 71 is further provided.

[0060] According to the first pixel structure, a P-type semiconductor region 71 is provided between the vertical gate electrode 51 of the transfer transistor TG and the N-type semiconductor region 53 constituting the floating diffusion FD, in a region in contact with the bottom and side surfaces of the N-type semiconductor region 53. This makes it possible to suppress the intrusion of the positive potential of the floating diffusion FD into the channel. As a result, the contribution of the on-voltage of the transfer transistor TG to potential modulation near the channel is improved, and the occurrence of drain-induced barrier lowering (DIBL) can be suppressed. Furthermore, the provision of the P-type semiconductor region 71 makes it possible to reduce the leakage current Ioff when the transfer transistor TG is off.

[0061] 5. Second Pixel Structure of the Present Disclosure FIG. 6 shows a second pixel structure employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0062] Fig. 6A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the second pixel structure. Fig. 6B is a plan view of the pixel 2 according to the second pixel structure. The cross-sectional view of Fig. 6A corresponds to the cross-sectional view of Fig. 6B along line X-X'.

[0063] In FIG. 6, the same parts as those in the first pixel structure shown in FIG. 5 are denoted by the same reference numerals, and the description of those parts will be omitted as appropriate.

[0064] In the second pixel structure shown in FIG. 6 , similar to the first pixel structure shown in FIG. 5 , a P-type semiconductor region 71 is formed in a region in contact with the bottom and side surfaces of the N-type semiconductor region 53 that constitutes the floating diffusion FD. Furthermore, a semiconductor region 72 (hereinafter referred to as the N-type semiconductor region 72) of the same conductivity type (i.e., N-type) as the N-type semiconductor region 53 is formed above the P-type semiconductor region 71 in the peripheral region of the N-type semiconductor region 53. The N-type semiconductor region 72 is formed in a region shallower in the depth direction than the P-type semiconductor region 71, in a region near the substrate surface between the N-type semiconductor region 53 and the vertical gate electrode 51. As shown in the cross-sectional view of A in FIG. 6 , the bottom surface of the N-type semiconductor region 72 may be in contact with the top surface of the P-type semiconductor region 71. In the cross-sectional view of Fig. 6A, the region end faces of the N-type semiconductor region 72 and the P-type semiconductor region 71 on the vertical gate electrode 51 side are at the same position, but in the plan view of Fig. 6B, in order to clearly show the arrangement of the two, the N-type semiconductor region 72 is formed with an area larger than the P-type semiconductor region 71, and further, the P-type semiconductor region 71 is illustrated above the N-type semiconductor region 72 so that the P-type semiconductor region 71 can be seen. The planar areas of the N-type semiconductor region 72 and the P-type semiconductor region 71 on the vertical gate electrode 51 side may be the same or different.

[0065] The impurity concentration of the N-type semiconductor region 72 is either lower than that of the N-type semiconductor region 53 or the same as that of the N-type semiconductor region 53. The "N-" shown for the N-type semiconductor region 72 in FIG. 6 indicates that the impurity concentration is lower than that of the N-type semiconductor region 53. The N-type semiconductor region 72 can be formed, for example, by ion implantation, in which N-type impurities are implanted. If the impurity concentration of the N-type semiconductor region 72 is the same as that of the N-type semiconductor region 53, the N-type semiconductor region 53 and the N-type semiconductor region 72 appear to be integrated regions. In this case, the N-type semiconductor region 53 and the N-type semiconductor region 72 can be distinguished from each other by the position of the peak of the impurity concentration distribution in the depth direction. The peak position of the impurity concentration distribution of the N-type semiconductor region 72 is shallower than the peak position of the N-type semiconductor region 53.

[0066] The second pixel structure in FIG. 6 is similar to the pixel structure according to the comparative example shown in FIG. 3 except that a P-type semiconductor region 71 and an N-type semiconductor region 72 are further provided.

[0067] According to the second pixel structure, the P-type semiconductor region 71 is provided in a region between the vertical gate electrode 51 of the transfer transistor TG and the N-type semiconductor region 53 constituting the floating diffusion FD, in contact with the bottom and side surfaces of the N-type semiconductor region 53. This makes it possible to suppress the intrusion of the positive potential of the floating diffusion FD into the channel. As a result, the contribution of the on-voltage of the transfer transistor TG to potential modulation near the channel is improved, and the occurrence of drain-induced barrier lowering (DIBL) can be suppressed. Furthermore, the N-type semiconductor region 72 is provided in a region shallower than the P-type semiconductor region 71 near the substrate surface between the N-type semiconductor region 53 and the vertical gate electrode 51, making it possible to reduce extra-gate resistance.

[0068] Fig. 7A is a graph analyzing the potential near the channel by changing the gate voltage of the transfer transistor TG in the second pixel structure. The black circles (●) in the graph in Fig. 7A show the relationship between the gate voltage and the potential in the second pixel structure, and for comparison, the relationship between the gate voltage and the potential in the comparative example shown in Fig. 4B is shown by the white circles (◯).

[0069] 7B is a graph analyzing the relationship between the gate voltage and transconductance gm of the transfer transistor TG in the second pixel structure. The solid line in the graph in Fig. 7B shows the relationship between the gate voltage and transconductance gm in the second pixel structure, and for comparison, the dashed line shows the relationship between the gate voltage and transconductance gm in the comparative example shown in Fig. 4C.

[0070] According to the second pixel structure, even after the gate voltage of the transfer transistor TG exceeds 0.5, increasing the gate voltage modulates the potential and improves the transconductance gm. That is, the contribution of the gate voltage to the potential near the channel is improved, drain-induced barrier lowering (DIBL) is suppressed, and the transconductance gm near the gate voltage is improved. This shortens the average transfer time of signal charges. Furthermore, by providing the N-type semiconductor region 72 near the substrate surface between the N-type semiconductor region 53 and the vertical gate electrode 51 and in a region shallower than the P-type semiconductor region 71, the external resistance of the gate can be reduced. The provision of the P-type semiconductor region 71 reduces the current Ioff when the transfer transistor TG is off, and the provision of the N-type semiconductor region 72 increases the current Ion when the transfer transistor TG is on, thereby increasing the on / off current ratio Ion / Ioff. This allows the transfer transistor TG to be turned on with a smaller boost, thereby reducing power consumption.

[0071] In the second pixel structure shown in FIG. 6 , the region end faces of the N-type semiconductor region 72 and the P-type semiconductor region 71 on the vertical gate electrode 51 side are positioned at the same location, and the bottom surface of the N-type semiconductor region 72 and the top surface of the P-type semiconductor region 71 are in contact. However, as shown in FIG. 8 , for example, the region end faces of the N-type semiconductor region 72 and the P-type semiconductor region 71 on the vertical gate electrode 51 side may be positioned at different locations, and a P-type substrate region 41 may be disposed between the bottom surface of the N-type semiconductor region 72 and the top surface of the P-type semiconductor region 71. The P-type semiconductor region 71 may be disposed so as to cover the bottom surface of the floating diffusion FD (N-type semiconductor region 53) in the depth direction and part of the side surface in the horizontal direction. The N-type semiconductor region 72 may be formed in a region near the substrate surface between the N-type semiconductor region 53 and the vertical gate electrode 51, extending from the side surface of the floating diffusion FD (N-type semiconductor region 53) toward the vertical gate electrode 51.

[0072] 6. Third Pixel Structure of the Present Disclosure FIG. 9 shows a third pixel structure that is employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0073] Fig. 9A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the third pixel structure. Fig. 9B is a plan view of the pixel 2 according to the third pixel structure. The cross-sectional view of Fig. 9A corresponds to the cross-sectional view of Fig. 9B along line X-X'.

[0074] In the third pixel structure shown in FIG. 9 , in addition to the P-type semiconductor region 71 and the N-type semiconductor region 72, a sidewall 81 is newly provided on the side of the vertical gate electrode 51 of the transfer transistor TG on the floating diffusion FD side. The N-type semiconductor region 72 is arranged to extend closer to the vertical gate electrode 51 than the P-type semiconductor region 71. The sidewall 81 can be formed, for example, from a SiO film and a SiN film. Forming the sidewall 81 reduces the electric field between the vertical gate electrode 51 and the N-type semiconductor regions 72 and 53 and brings the N-type semiconductor region 72 closer to the vertical gate electrode 51. This prevents defect noise (e.g., white spots) caused by a strong electric field between the vertical gate electrode 51 and the floating diffusion FD while further suppressing external resistance. When forming the P-type semiconductor region 71 and the N-type semiconductor region 72 by ion implantation, at least one of the P-type semiconductor region 71 and the N-type semiconductor region 72 may be formed in a self-aligned manner using the sidewall 81. In FIG. 9B, the gate insulating film 52 adjacent to the sidewall 81 is omitted.

[0075] In the third pixel structure, by having the P-type semiconductor region 71 and the N-type semiconductor region 72, it is possible to achieve the same effects as the second pixel structure, such as suppressing drain-induced barrier lowering, improving mutual conductance gm, shortening the average transfer time of signal charges, improving the on / off current ratio Ion / Ioff of the transfer transistor TG, and reducing power consumption.

[0076] 7. Fourth Pixel Structure of the Present Disclosure FIG. 10 shows a fourth pixel structure that is employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0077] Fig. 10A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the fourth pixel structure. Fig. 10B is a plan view of the pixel 2 according to the fourth pixel structure. The cross-sectional view of Fig. 10A corresponds to the cross-sectional view of Fig. 10B along line X-X'.

[0078] The fourth pixel structure shown in Figure 10 illustrates a configuration example in which a planar gate electrode is used as the gate electrode structure of the transfer transistor TG. That is, in the transfer transistor TG of Figure 10, the buried gate electrode portion 51V is omitted, and the gate electrode is composed only of a planar gate electrode portion 51P. A gate insulating film 52 is formed between the planar gate electrode portion 51P and the substrate surface of the semiconductor substrate 21. Other components, such as the P-type semiconductor region 71 and the N-type semiconductor region 72, are the same as those of the second pixel structure described above. In the planar transfer transistor TG, a channel is formed between the photodiode PD and the floating diffusion FD below the gate insulating film 52, as indicated by the arrow in Figure 10A.

[0079] In the fourth pixel structure employing the planar transfer transistor TG, by having the P-type semiconductor region 71 and the N-type semiconductor region 72, it is possible to achieve the same effects as the second pixel structure, such as suppression of drain-induced barrier lowering, improvement of the mutual conductance gm, shortening of the average transfer time of the signal charge, improvement of the on / off current ratio Ion / Ioff of the transfer transistor TG, and reduction of power consumption.

[0080] 8. Fifth Pixel Structure of the Present Disclosure FIG. 11 shows a fifth pixel structure that is employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0081] Fig. 11A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the fifth pixel structure. Fig. 11B is a plan view of the pixel 2 according to the fifth pixel structure. The cross-sectional view of Fig. 11A corresponds to the cross-sectional view of Fig. 11B along line X-X'.

[0082] The fifth pixel structure shown in FIG. 11 is a configuration in which a sidewall 81 is added to the fourth pixel structure of FIG. 10 , which employs a planar transfer transistor TG. Specifically, the sidewall 81 is provided on the side surface of the planar gate electrode portion 51P facing the floating diffusion FD. The N-type semiconductor region 72 extends from the side surface of the floating diffusion FD to a region below the sidewall 81 and has a region overlapping the sidewall 81 in a planar view. The other components, such as the P-type semiconductor region 71, are the same as those of the second pixel structure described above. As with the third pixel structure of FIG. 9 , which also includes the sidewall 81, defect noise caused by a strong electric field between the planar gate electrode portion 51P and the floating diffusion FD can be prevented while suppressing external resistance to the gate. When forming the P-type semiconductor region 71 and the N-type semiconductor region 72 by ion implantation, at least one of the P-type semiconductor region 71 and the N-type semiconductor region 72 may be formed in a self-aligned manner using the sidewall 81.

[0083] In the fifth pixel structure, by having the P-type semiconductor region 71 and the N-type semiconductor region 72, it is possible to achieve the same effects as the second pixel structure, such as suppressing drain-induced barrier lowering, improving mutual conductance gm, shortening the average transfer time of signal charges, improving the on / off current ratio Ion / Ioff of the transfer transistor TG, and reducing power consumption.

[0084] 9. Sixth Pixel Structure of the Present Disclosure FIG. 12 shows a sixth pixel structure employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0085] Fig. 12A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the sixth pixel structure. Fig. 12B is a plan view of the pixel 2 according to the sixth pixel structure. The cross-sectional view of Fig. 12A corresponds to the cross-sectional view of Fig. 12B along line X-X'.

[0086] In the sixth pixel structure shown in FIG. 12 , the vertical gate electrode 51 of the transfer transistor TG has a different arrangement and shape from the vertical gate electrode 51 of the second pixel structure shown in FIG. 6 . Specifically, the vertical gate electrode 51 (including the planar gate electrode portion 51P and the buried gate electrode portion 51V) has a triangular planar shape, and one side of the triangle is arranged to contact one side of the rectangular pixel region. As shown in the plan view of FIG. 12B , one side of the triangle of the planar gate electrode portion 51P contacts the outer periphery of the pixel separation portion 54, which forms the boundary with the adjacent pixel, and one side of the triangle of the buried gate electrode portion 51V contacts the inner periphery of the pixel separation portion 54, which forms the boundary with the adjacent pixel. In FIG. 12B , the triangular region of the buried gate electrode portion 51V is indicated by a dashed line. The planar gate electrode portion 51P is formed above the pixel separation portion 54 and above the photodiode PD located inside the pixel separation portion 54, and the buried gate electrode portion 51V is formed inside the pixel separation portion 54. In FIG. 12B, the gate insulating film 52 is not shown.

[0087] The sixth pixel structure, like the second pixel structure shown in FIG. 6 , has a P-type semiconductor region 71 arranged so as to cover the bottom surface in the depth direction and part of the side surface in the horizontal direction of the floating diffusion FD (N-type semiconductor region 53), and an N-type semiconductor region 72 formed in a region near the substrate surface between the N-type semiconductor region 53 and the vertical gate electrode 51 so as to extend from the side surface of the floating diffusion FD toward the vertical gate electrode 51.

[0088] According to the sixth pixel structure, by having the P-type semiconductor region 71 and the N-type semiconductor region 72, it is possible to achieve the same effects as the second pixel structure, such as suppressing drain-induced barrier lowering, improving mutual conductance gm, shortening the average transfer time of signal charges, improving the on / off current ratio Ion / Ioff of the transfer transistor TG, and reducing power consumption.

[0089] Furthermore, by forming the vertical gate electrode 51 of the transfer transistor TG into a triangular planar shape and positioning it so that one side of the triangle is in contact with the pixel separation section 54, the channel between the photodiode PD and the floating diffusion FD is formed in a concentrated manner near the hypotenuse of the triangle, and a transfer path is formed from the center of the pixel, where the PD potential is likely to be deepest, along the hypotenuse of the triangle, which is expected to reduce the transfer path's detouring and suppress variations in transfer time.

[0090] Although the sidewalls 81 are not formed in the sixth pixel structure of Fig. 12, the sidewalls 81 may be provided on the hypotenuse faces of the triangular vertical gate electrode 51, similar to the third pixel structure of Fig. 9 and the fifth pixel structure of Fig. 11. In this case, it is possible to prevent defect noise caused by a strong electric field between the vertical gate electrode 51 and the floating diffusion FD, while further suppressing the external resistance of the gate.

[0091] 10. Seventh Pixel Structure of the Present Disclosure FIG. 13 shows a seventh pixel structure that is employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0092] Fig. 13A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the seventh pixel structure. Fig. 13B is a plan view of the pixel 2 according to the seventh pixel structure. The cross-sectional view of Fig. 13A corresponds to the cross-sectional view of Fig. 13B along line XX'.

[0093] The seventh pixel structure shown in FIG. 13 differs from the vertical gate electrode 51 of the second pixel structure shown in FIG. 6 in the arrangement and shape of the vertical gate electrode 51 of the transfer transistor TG. Specifically, the vertical gate electrode 51 (including the planar gate electrode portion 51P and the buried gate electrode portion 51V) has a rectangular (quadrilateral) planar shape, and one side of the rectangle is arranged to contact one side of the rectangular pixel region. As shown in the plan view of FIG. 13B, one side of the rectangle of the planar gate electrode portion 51P contacts the outer periphery of the pixel separation portion 54, which forms the boundary with the adjacent pixel, and one side of the rectangle of the buried gate electrode portion 51V contacts the inner periphery of the pixel separation portion 54, which forms the boundary with the adjacent pixel. One corner of the rectangle of the buried gate electrode portion 51V coincides with one corner of the rectangle of the inner periphery of the pixel separation portion 54. In FIG. 13B, the rectangular region of the buried gate electrode portion 51V is indicated by a dashed line, and the gate insulating film 52 is not shown. The planar gate electrode portion 51P is formed above the pixel separating portion 54 and above the photodiode PD inside the pixel separating portion 54, and the buried gate electrode portion 51V is formed inside the pixel separating portion 54.

[0094] The seventh pixel structure, like the second pixel structure shown in FIG. 6 , has a P-type semiconductor region 71 arranged so as to cover the bottom surface in the depth direction and part of the side surface in the horizontal direction of the floating diffusion FD (N-type semiconductor region 53), and an N-type semiconductor region 72 formed in a region near the substrate surface between the N-type semiconductor region 53 and the vertical gate electrode 51 so as to extend from the side surface of the floating diffusion FD toward the vertical gate electrode 51.

[0095] According to the seventh pixel structure, by having the P-type semiconductor region 71 and the N-type semiconductor region 72, it is possible to achieve the same effects as the second pixel structure, such as suppressing drain-induced barrier lowering, improving mutual conductance gm, shortening the average transfer time of signal charges, improving the on / off current ratio Ion / Ioff of the transfer transistor TG, and reducing power consumption.

[0096] Furthermore, by forming the vertical gate electrode 51 of the transfer transistor TG into a rectangular shape in plan view and positioning it so that one side of the rectangle is in contact with the pixel separation portion 54, the channel between the photodiode PD and the floating diffusion FD is formed in a concentrated manner near the surface of the long side of the rectangle, and a transfer path is formed along the oblique side of the long side of the vertical gate electrode 51, which is expected to reduce the deflection of the transfer path and suppress variations in transfer time.

[0097] Although the seventh pixel structure in Fig. 13 does not have a sidewall 81, the sidewall 81 may be provided on the long side surface of the rectangular vertical gate electrode 51 on the floating diffusion FD side, as in the third pixel structure in Fig. 9 and the fifth pixel structure in Fig. 11. In this case, it is possible to prevent defect noise caused by a strong electric field between the vertical gate electrode 51 and the floating diffusion FD, while further suppressing the extra-gate resistance.

[0098] 11. Eighth and Ninth Pixel Structures of the Present Disclosure> FIG. 14A is a plan view showing an eighth pixel structure employed as pixel 2 of the photodetector 1, and FIG. 14B is a plan view showing a ninth pixel structure employed as pixel 2 of the photodetector 1.

[0099] The eighth and ninth pixel structures shown in Fig. 14 each show an example of a structure in which a floating diffusion FD is shared by two pixels. In Fig. 14, one pixel 2 of the two pixels sharing the floating diffusion FD is designated pixel 2A, and the other pixel 2 is designated pixel 2B. Pixel 2A and pixel 2B are configured as rectangular pixel regions having long and short sides. The rectangular pixel region may be shaped such that the two pixels, pixel 2A and pixel 2B, form a square, which is advantageous when miniaturizing pixel 2.

[0100] In the eighth pixel structure shown in FIG. 14A, a floating diffusion FD (N-type semiconductor region 53) shared by pixel 2A and pixel 2B is located at one adjacent corner between the rectangular pixels 2A and 2B. A shallow trench isolation (STI) 91 for forming an overflow path is formed on the substrate surface of the pixel isolation section 54 between pixels 2A and 2B at the center of the two-pixel region of pixels 2A and 2B. The overflow path separates pixel 2A from pixel 2B by a predetermined potential barrier (separation potential). Signal charges from pixels 2A and 2B are accumulated independently in their respective photodiodes PD until the amount of signal charge reaches the height of the potential barrier of the overflow path. When the amount of signal charge exceeds the height of the potential barrier of the overflow path, signal charge flows from one of the photodiodes PD of the two pixels to the other via the overflow path.

[0101] The vertical gate electrode 51, P-type semiconductor region 71, and N-type semiconductor region 72 of the transfer transistor TG are arranged symmetrically (bilaterally symmetrically) with respect to the pixel isolation region 54 between pixel 2A and pixel 2B. The vertical gate electrode 51 of the transfer transistor TG is arranged at the end opposite to the end of one side of the pixel isolation region 54 where the floating diffusion FD is arranged, away from the other pixel 2 (pixel 2A or pixel 2B) that shares it. The planar shape of the vertical gate electrode 51 of the transfer transistor TG is triangular, similar to the sixth pixel structure of FIG. 12 . The P-type semiconductor region 71 is arranged to cover the bottom surface of the floating diffusion FD (N-type semiconductor region 53) in the depth direction and part of the side surface in the horizontal direction, and the N-type semiconductor region 72 is arranged to extend from the side surface of the floating diffusion FD toward the vertical gate electrode 51. According to the eighth pixel structure of FIG. 14A , a transfer path is formed along the hypotenuse of the triangle, which is expected to reduce detouring of the transfer path and suppress variation in transfer time. Depending on the pixel sizes of pixel 2A and pixel 2B, the vertical gate electrode 51 may be arranged in the center of one side of the pixel separation section 54, as in the sixth pixel structure of Figure 12, rather than at the end on the opposite side of the side where the floating diffusion FD is arranged.

[0102] The arrangement of the floating diffusion FD and STI 91 in the ninth pixel structure shown in FIG. 14B is the same as that in the eighth pixel structure shown in FIG. 14A. In the ninth pixel structure shown in FIG. 14B, the vertical gate electrode 51 of the transfer transistor TG is disposed between the floating diffusion FD and the STI 91. The vertical gate electrode 51 has a rectangular planar shape, and one side of the rectangular embedded gate electrode portion 51V (not shown) contacts the inner periphery of the pixel isolation portion 54 between the pixel 2A and the pixel 2B. The P-type semiconductor region 71 is disposed so as to cover the bottom surface in the depth direction and part of the side surface in the horizontal direction of the floating diffusion FD (N-type semiconductor region 53), and the N-type semiconductor region 72 is disposed so as to extend from the side surface of the floating diffusion FD toward the vertical gate electrode 51. In the ninth pixel structure, the vertical gate electrode 51 of the transfer transistor TG is disposed near the overflow path (PD potential saddle point), which is expected to reduce the average transfer time.

[0103] 14 , the two pixels, pixel 2A and pixel 2B, may be combined to output one signal, or individual signals may be output from pixel 2A and pixel 2B. When an on-chip lens is formed on the light incident surface of the semiconductor substrate 21, one on-chip lens may be disposed for two pixels, pixel 2A and pixel 2B, or an on-chip lens may be disposed for each pixel, pixel 2A and pixel 2B. When one on-chip lens is disposed for two pixels, pixel 2A and pixel 2B, it becomes possible to detect a phase difference using signals for each pixel, pixel 2A and pixel 2B.

[0104] Although the eighth and ninth pixel structures are examples in which two pixels share a floating diffusion FD, a configuration in which a floating diffusion FD is shared by more than two pixels is also possible. For example, a floating diffusion FD may be disposed in the center of four 2x2 pixels, and the four pixels may share the floating diffusion FD. In this case, too, a photodiode PD, a vertical gate electrode 51, a P-type semiconductor region 71, and an N-type semiconductor region 72 are provided for each pixel.

[0105] 12. Tenth Pixel Structure of the Present Disclosure> FIG. 15 shows a tenth pixel structure employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0106] Fig. 15A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the tenth pixel structure. Fig. 15B is a plan view of the pixel 2 according to the tenth pixel structure. The cross-sectional view of Fig. 15A corresponds to the cross-sectional view taken along line X-X' of Fig. 15B. In Fig. 15B, the gate insulating film 52 is omitted for simplification and clarity.

[0107] The tenth pixel structure shown in FIG. 15 differs from the second pixel structure shown in FIG. 6 in that one pixel has two vertical gate electrodes 51. Assuming that the two vertical gate electrodes 51 formed in one pixel are vertical gate electrodes 51A and 51B, the vertical gate electrodes 51A and 51B are arranged in an L-shape in plan view to surround the floating diffusion FD located at the corner (pixel corner) of the rectangular pixel region. The center of the pixel, where the PD potential is likely to be deepest, corresponds to the corner of the L-shape formed by the vertical gate electrodes 51A and 51B, and the buried gate electrode portions 51V of the vertical gate electrodes 51A and 51B are arranged opposite each other across the P-type substrate region 41 at the pixel center. The arrangement of the floating diffusion FD (N-type semiconductor region 53), P-type semiconductor region 71, and N-type semiconductor region 72 is the same as in the second pixel structure shown in FIG. 6. The planar shape of the buried gate electrode portion 51V may be circular, elliptical (oval), rectangular, or triangular.

[0108] According to the tenth pixel structure, the channel between the photodiode PD and the floating diffusion FD is formed intensively near the opposing surfaces of the two buried gate electrode portions 51V of the vertical gate electrodes 51A and 51B, as indicated by the arrows in Fig. 15, and a transfer path is formed from the center of the pixel, where the PD potential is likely to be deepest, along the vicinity of the opposing surfaces of the buried gate electrode portions 51V, thereby reducing the detour of the transfer path and also reducing the potential influence of other structures such as the floating diffusion FD and pixel separation portion 54. This is expected to suppress variations in transfer time.

[0109] According to the tenth pixel structure, by having the P-type semiconductor region 71 and the N-type semiconductor region 72, it is possible to achieve the same effects as the second pixel structure, such as suppression of drain-induced barrier lowering, improvement of mutual conductance gm, shortening of the average transfer time of signal charges, improvement of the on / off current ratio Ion / Ioff of the transfer transistor TG, and reduction of power consumption.

[0110] 13. Eleventh Pixel Structure of the Present Disclosure> FIG. 16 shows an eleventh pixel structure employed as the pixel 2 of the photodetector device 1. As shown in FIG.

[0111] Fig. 16A is a cross-sectional view of the transfer transistor TG and the floating diffusion FD of a pixel 2 according to the eleventh pixel structure. Fig. 16B is a plan view of the pixel 2 according to the eleventh pixel structure. The cross-sectional view of Fig. 16A corresponds to the cross-sectional view taken along line X-X' of Fig. 16B. In Fig. 16B, the gate insulating film 52 is omitted for simplification and clarity.

[0112] The eleventh pixel structure shown in FIG. 16 differs from the second pixel structure shown in FIG. 6 in that the transfer transistor TG has a gate-all-around (GAA) vertical gate electrode 51AA that completely covers the periphery of the channel. The transfer transistor TG has a vertical gate electrode 51AA consisting of a planar gate electrode portion 51P and a buried gate electrode portion 51VA buried in the substrate. As shown in FIG. 16B, the buried gate electrode portion 51VA is formed to surround the floating diffusion FD (N-type semiconductor region 53) formed in a region near the substrate surface at the center of the pixel. The planar gate electrode portion 51P is connected to a portion of the upper surface of the prismatic or cylindrical buried gate electrode portion 51VA and extends linearly to a predetermined side of the rectangular pixel separation portion 54. As shown in FIG. 16A, the P-type semiconductor region 71 is formed below the floating diffusion FD and in contact with the bottom surface of the floating diffusion FD. The N-type semiconductor region 72 is omitted because the floating diffusion FD and the buried gate electrode portion 51VA are adjacent to each other. A channel is formed near the inner circumferential surface of the buried gate electrode portion 51VA having a substantially octagonal prismatic or cylindrical shape.

[0113] According to the eleventh pixel structure, the channel between the photodiode PD and the floating diffusion FD is formed intensively near the inner circumferential surface of the prismatic or cylindrical buried gate electrode portion 51VA, as indicated by the arrow A in Fig. 16, and a transfer path is formed from the center of the pixel, where the PD potential is likely to be deepest, along the vicinity of the inner circumferential surface of the buried gate electrode portion 51VA, thereby reducing the detour of the transfer path and also reducing the potential influence of other structures such as the floating diffusion FD and pixel separation portion 54. This is expected to suppress variations in transfer time.

[0114] 14. Summary of Pixel Structures of the Present Disclosure The first to eleventh pixel structures described above each include a photoelectric conversion unit (e.g., a photodiode PD) provided on a semiconductor substrate 21 that generates charge in response to the amount of light received; a gate electrode (e.g., a vertical gate electrode 51) of a transfer transistor TG that controls the charge transfer; a charge accumulation unit (a floating diffusion FD formed in an N-type semiconductor region 53) that accumulates the charge transferred by controlling the transfer transistor TG; and a first semiconductor region (P-type semiconductor region 71) that is a semiconductor region of the same first conductivity type as the substrate region (P-type substrate region 41) of the semiconductor substrate 21 and that is adjacent to the charge accumulation unit in the depth direction and horizontal direction, but has a higher impurity concentration than the substrate region. This configuration can suppress the occurrence of drain-induced barrier lowering (DIBL). It also can reduce the leakage current Ioff when the transfer transistor TG is off.

[0115] The second to eleventh pixel structures further include a second semiconductor region (N-type semiconductor region 72) in a region shallower than the first semiconductor region of the semiconductor substrate between the gate electrode and the charge storage region. The second semiconductor region (N-type semiconductor region 72) is a semiconductor region of a second conductivity type opposite to the first conductivity type and the same conductivity type as the charge storage region, and has an impurity concentration lower or equal to that of the charge storage region. This reduces resistance outside the gate. Furthermore, increasing the current Ion when the transfer transistor TG is on increases the on / off current ratio Ion / Ioff, allowing the transfer transistor TG to be turned on with a smaller boost width, thereby reducing power consumption.

[0116] 15. Example of a Stacked Structure Using Multiple Substrates In the above-described embodiment, an example has been described in which the photodetector 1 is configured using one substrate (semiconductor substrate 21). The photodetector 1 may be configured by stacking two or three substrates. With reference to FIG. 17 , a case in which the photodetector 1 is configured with a stacked structure of three substrates will be described.

[0117] Fig. 17 shows a schematic configuration example of the photodetector 1 when configured with a stacked structure of three substrates. In Fig. 17, parts corresponding to those in the configuration described above are given the same reference numerals, and their description will be omitted as appropriate.

[0118] 17 has a three-dimensional structure in which a first substrate 111, a second substrate 112, and a third substrate 113 are bonded together. The first substrate 111, the second substrate 112, and the third substrate 113 are stacked in this order.

[0119] The first substrate 111 has a semiconductor substrate 141 made of, for example, silicon (Si), and a pixel region 212 in which a plurality of sensor pixels 211 are two-dimensionally arranged in a matrix is ​​formed on the semiconductor substrate 141. The sensor pixel 211 includes at least the above-mentioned photodiode PD and transfer transistor TG.

[0120] The second substrate 112 has a semiconductor substrate 142 made of, for example, silicon (Si), and a readout circuit 221 is formed on the semiconductor substrate 142. The readout circuit 221 outputs pixel signals based on charges generated in the sensor pixels 211. The readout circuit 221 corresponds to, for example, the reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL described above, and when a shared pixel structure is adopted, one readout circuit 221 is arranged for multiple sensor pixels 211. A plurality of pixel drive wirings 222 extending in the row direction and a plurality of vertical signal lines 223 extending in the column direction are also formed on the second substrate 112.

[0121] The third substrate 113 has a semiconductor substrate 143 made of, for example, silicon (Si), and a logic circuit 241 that processes pixel signals is formed on the semiconductor substrate 143. The logic circuit 241 includes, for example, a vertical drive circuit 251, a column processing circuit 252, a horizontal drive circuit 253, and a system control circuit 254. The vertical drive circuit 251, the column processing circuit 252, the horizontal drive circuit 253, and the system control circuit 254 have functions similar to those of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the control circuit 8 in FIG. 1, respectively. The horizontal drive circuit 253 sequentially selects the column signal processing circuits in the column processing circuit 252, and pixel signals acquired from each column signal processing circuit are output from an output terminal 255.

[0122] FIG. 18 shows an example of the configuration of the sensor pixels 211 and the readout circuit 221. FIG. 18 describes a case where four sensor pixels 211 share one readout circuit 221. Here, "shared" means that the outputs of the four sensor pixels 211 are input to a common readout circuit 221. When distinguishing between the four sensor pixels 211 that share one readout circuit 221, they are referred to as sensor pixels 211A, 211B, 211C, and 211D, as shown in FIG. 18. The sensor pixels 211A, 211B, 211C, and 211D are formed on the first substrate 111, for example, and the readout circuit 221 is formed on the second substrate 112, for example.

[0123] The sensor pixels 211A, 211B, 211C, and 211D have common components. Hereinafter, when distinguishing between the components of the sensor pixels 211A, 211B, 211C, and 211D, the reference numerals of the components of the sensor pixel 211A will be suffixed with "a," the reference numerals of the components of the sensor pixel 211B will be suffixed with "b," the reference numerals of the components of the sensor pixel 211C will be suffixed with "c," and the reference numerals of the components of the sensor pixel 211D will be suffixed with "d." When it is not necessary to distinguish between the components of the sensor pixels 211A, 211B, 211C, and 211D, the identification symbols "a," "b," "c," and "d" at the end of the reference numerals of the components of the sensor pixels 211A, 211B, 211C, and 211D will be omitted.

[0124] Each sensor pixel 211 includes, for example, a photodiode PD as a photoelectric conversion unit, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG. The cathodes of the photodiodes PD (PDa, PDb, PDc, and PDd) are electrically connected to the sources of the transfer transistors TG (TGa, TGb, TGc, and TGd), and the anodes are electrically connected to a reference potential line (e.g., ground). The photodiodes PD photoelectrically convert incident light and generate signal charges corresponding to the amount of received light. The transfer transistors TG are, for example, N-type MOS transistors. The drains of the transfer transistors TG are electrically connected to the floating diffusions FD (FDa, FDb, FDc, and FDd), and the gates are electrically connected to pixel drive wiring. The pixel drive wiring is part of multiple pixel drive wirings 222 ( FIG. 17 ) connected to a single readout circuit 221. The transfer transistors TG transfer the charges generated by the photodiodes PD to the floating diffusions FD. The floating diffusion FD is composed of, for example, an N-type diffusion layer region formed in a P-type semiconductor region. The floating diffusion FD is a charge storage section that temporarily stores the signal charge transferred from the photodiode PD, and also a charge-voltage conversion section that generates a voltage according to the amount of charge.

[0125] The four floating diffusions FDa, FDb, FDc, and FDd included in one readout circuit 221 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the switching transistor FDG. The drain of the switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the switching transistor FDG is connected to a pixel drive line. This pixel drive line is part of the multiple pixel drive lines 222 connected to one readout circuit 221. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the pixel drive line. This pixel drive line is part of the multiple pixel drive lines 222 connected to one readout circuit 221. The gate of the amplification transistor AMP is connected to the floating diffusions FDa, FDb, FDc, and FDd, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 223, and the gate of the selection transistor SEL is connected to the pixel drive line. This pixel drive wiring is a part of a plurality of pixel drive wirings 222 connected to one readout circuit 221 .

[0126] The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 221. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 223 via the selection transistor SEL. This amplification transistor AMP forms a source follower together with a load circuit section in the column processing circuit 252 connected to the vertical signal line 223. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column processing circuit 252 via the vertical signal line 223. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type MOS transistors.

[0127] The switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffusion FD. The switching transistor FDG switches the conversion efficiency by switching on and off. The switching transistor FDG is, for example, an N-type MOS transistor. Note that a configuration without the switching transistor FDG is also possible. In this case, for example, the readout circuit 221 is composed of three pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST.

[0128] The select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to the pixel drive wiring 222. The source of the amplifier transistor AMP (the output terminal of the readout circuit 221) is electrically connected to the vertical signal line 223, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST.

[0129] Although not shown in the drawings, the number of sensor pixels 211 sharing one readout circuit 221 may be other than four. For example, two or eight sensor pixels 211 may share one readout circuit 221. Alternatively, instead of a configuration in which the readout circuit 221 is shared by a plurality of sensor pixels 211, a readout circuit 221 may be provided for each pixel.

[0130] 16. Configuration Examples of Electronic Devices The above-described photodetector 1 can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0131] FIG. 19 is a block diagram showing an example of the configuration of an electronic device.

[0132] 19 , electronic device 301 includes an optical system 302, a photodetector 303, a DSP (Digital Signal Processor) 304, a display device 305, an operation system 306, a memory 307, a recording device 308, and a power supply system 309. DSP 304, display device 305, operation system 306, memory 307, recording device 308, and power supply system 309 are interconnected via a bus 310. Electronic device 301 is, for example, an imaging device capable of capturing still images and moving images.

[0133] The optical system 302 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 303 , forming an image on the light receiving surface (sensor portion) of the photodetector 303 .

[0134] The photodetector 303 has the same configuration as the photodetector 1 described above. Electrons are accumulated as signal charges in the photodetector 303 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 302. A signal corresponding to the electrons accumulated in the photodetector 303 is then supplied to the DSP 304.

[0135] The DSP 304 performs various signal processing on the signal from the photodetector 303 to generate an image, and temporarily stores the image data in a memory 307. The image data stored in the memory 307 is recorded in a recording device 308 or supplied to a display device 305 to display the image. In addition, an operation system 306 accepts various operations by a user and supplies operation signals to each block of the electronic device 301, and a power supply system 309 supplies the power necessary to drive each block of the electronic device 301.

[0136] In the electronic device 301 configured in this manner, by applying the above-described photodetector 1 as the photodetector 303, it is possible to suppress drain-induced barrier lowering, improve the mutual conductance gm, shorten the average transfer time of the signal charge, improve the on / off current ratio Ion / Ioff of the transfer transistor TG, reduce power consumption, and so on, thereby enabling the generation of high-quality captured images.

[0137] 17. Example of Use of Image Sensor FIG. 20 is a diagram showing an example of use of the above-described photodetector 1 as an image sensor.

[0138] When the above-described photodetector 1 is an image sensor, it can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0139] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0140] 18. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0141] FIG. 21 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0142] 21 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0143] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0144] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0145] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0146] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0147] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0148] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0149] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0150] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0151] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0152] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0153] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0154] FIG. 22 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0155] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0156] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0157] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0158] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0159] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0160] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0161] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0162] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0163] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0164] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0165] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0166] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0167] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0168] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0169] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0170] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0171] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102 in the above-described configuration. Specifically, the above-described light detection device 1 can be used as the imaging unit 11402. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to obtain clearer images of the surgical site while miniaturizing the camera head 11102.

[0172] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0173] 19. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0174] FIG. 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0175] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0176] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0177] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0178] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0179] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0180] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0181] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0182] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0183] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0184] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 23, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0185] FIG. 24 is a diagram showing an example of the installation position of the imaging unit 12031.

[0186] In FIG. 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0187] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0188] 24 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0189] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for detecting a phase difference.

[0190] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0191] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into categories such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0192] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0193] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the image capture unit 12031 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied as the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to obtain a more easily visible captured image and acquire distance information while still reducing the size of the image capture unit 12031. Furthermore, using the obtained captured image and distance information, it is possible to reduce driver fatigue and increase the safety of the driver and the vehicle.

[0194] In the above example, a photodetector in which the first conductivity type is P-type and the second conductivity type is N-type and electrons are used as signal charges has been described, but the present disclosure can also be applied to a photodetector in which holes are used as signal charges. That is, the first conductivity type can be N-type and the second conductivity type can be P-type, and the aforementioned semiconductor regions can be configured with semiconductor regions of opposite conductivity types.

[0195] Furthermore, the present disclosure is not limited to application to photodetection devices that detect the distribution of incident light amount of visible light and capture it as an image, but is also applicable to photodetection devices that capture the distribution of incident amounts of infrared rays, X-rays, particles, etc. as an image, and in a broad sense, to photodetection devices in general (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure or capacitance and capture it as an image.

[0196] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the technology of the present disclosure.

[0197] For example, it is possible to adopt a configuration in which all or part of the first to eleventh pixel structures described above are appropriately combined.

[0198] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0199] The technology disclosed herein may employ the following configurations: (1) A photodetector comprising: a photoelectric conversion unit provided on a semiconductor substrate, the photoelectric conversion unit generating charges according to an amount of received light; a gate electrode of a transfer transistor controlling the transfer of the charges; a charge accumulation unit storing the charges transferred under the control of the transfer transistor; and a first semiconductor region that is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate, the first semiconductor region being in contact with the charge accumulation unit in a depth direction and a horizontal direction, the first semiconductor region having an impurity concentration higher than that of the substrate region. (2) The photodetector described in (1) above, further comprising: a second semiconductor region that is a semiconductor region of a second conductivity type opposite to the first conductivity type and the same conductivity type as the charge accumulation unit, the second semiconductor region having an impurity concentration lower than or equal to that of the charge accumulation unit, in a region shallower than the first semiconductor region of the semiconductor substrate between the gate electrode and the charge accumulation unit. (3) The photodetector described in (1) or (2) above, further comprising a sidewall on a side surface of the gate electrode of the transfer transistor. (4) The photodetector according to any one of (1) to (3), wherein the gate electrode of the transfer transistor is a vertical gate electrode having a buried gate electrode portion buried in a substrate. (5) The photodetector according to any one of (1) to (3), wherein the gate electrode of the transfer transistor is a planar gate electrode. (6) The photodetector according to any one of (1) to (5), wherein the gate electrode of the transfer transistor has a circular, elliptical, or rectangular planar shape and is disposed in the center of the pixel. (7) The photodetector according to any one of (1) to (5), further comprising a pixel isolation portion separating the photoelectric conversion unit from an adjacent pixel, wherein the gate electrode of the transfer transistor has a triangular planar shape, with one side of the triangle being disposed in contact with the pixel isolation portion. (8) The photodetector according to any one of (1) to (5), further comprising a pixel isolation portion separating the photoelectric conversion unit from an adjacent pixel, wherein the gate electrode of the transfer transistor has a rectangular planar shape, with one side of the rectangle being disposed in contact with the pixel isolation portion.(9) The photodetector according to any one of (1) to (5), further comprising a pixel isolation section that isolates the photoelectric conversion section from adjacent pixels, wherein the gate electrode of the transfer transistor is disposed in contact with the pixel isolation section, and a portion of the gate electrode is disposed above the pixel isolation section. (10) The photodetector according to any one of (1) to (9), wherein the photoelectric conversion section, the gate electrode, and the first semiconductor region are provided for each pixel, and the charge accumulation section is shared by a plurality of pixels. (11) The photodetector according to (10), wherein the plurality of pixels that share the charge accumulation section have an overflow path, and the gate electrode of the transfer transistor is disposed between the overflow path and the charge accumulation section. (12) The photodetector according to any one of (1) to (11), wherein one pixel comprises two gate electrodes of the transfer transistor. (13) The photodetector according to (12), wherein the gate electrodes of the two transfer transistors are arranged in a linear L-shape in a plan view, and the charge accumulation portion is arranged at a corner of a pixel region surrounded by the gate electrodes of the two transfer transistors. (14) The photodetector according to any of (1) to (3), wherein the gate electrode of the transfer transistor is a gate-all-around type that surrounds the periphery of a channel in a plan view. (15) An electronic device comprising: a photodetector comprising: a photoelectric conversion portion provided on a semiconductor substrate and generating charges according to an amount of received light; gate electrodes of transfer transistors that control the transfer of the charges; a charge accumulation portion that accumulates the charges transferred by control of the transfer transistor; and a first semiconductor region that is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate and is in contact with the charge accumulation portion in a depth direction and horizontal direction, the first semiconductor region having an impurity concentration higher than that of the substrate region.

[0200] REFERENCE SIGNS LIST 1 Photodetector, 2, 2A, 2B Pixel, 3 Pixel array section, 21 Semiconductor substrate, 41 Substrate region (P-type substrate region), 42 Semiconductor region (N-type semiconductor region), 51 Vertical gate electrode, 51A Vertical gate electrode, 51AA Vertical gate electrode, 51P Planar gate electrode section, 51V Buried gate electrode section, 51VA Buried gate electrode section, 52 Gate insulating film, 53 N-type semiconductor region, 54 Pixel separation section, 55 Contact wiring, 71 Semiconductor region (P-type semiconductor region), 72 Semiconductor region (N-type semiconductor region), 81 Sidewall, PD Photodiode, TG Transfer transistor, RST Reset transistor, AMP Amplifying transistor, FDG Switching transistor, SEL Select transistor, FD Floating diffusion, 301 Electronic device, 302 Photodetector

Claims

1. A photodetection device comprising: a photoelectric conversion unit provided on a semiconductor substrate for generating charges in accordance with an amount of received light; a gate electrode of a transfer transistor for controlling the transfer of the charges; a charge accumulation unit for accumulating the charges transferred under the control of the transfer transistor; and a first semiconductor region that is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate, bordering the charge accumulation unit in the depth direction and horizontal direction, and has an impurity concentration higher than that of the substrate region.

2. The photodetector according to claim 1, further comprising a second semiconductor region in a region of the semiconductor substrate between the gate electrode and the charge accumulation portion that is shallower than the first semiconductor region, the second semiconductor region being a semiconductor region of a second conductivity type opposite to the first conductivity type and the same conductivity type as the charge accumulation portion, the second semiconductor region having an impurity concentration lower than or equal to that of the charge accumulation portion.

3. The photodetector according to claim 1, further comprising a sidewall on a side surface of the gate electrode of the transfer transistor.

4. The photodetector according to claim 1, wherein the gate electrode of the transfer transistor is a vertical gate electrode having a buried gate electrode portion buried in a substrate.

5. The photodetector according to claim 1, wherein the gate electrode of the transfer transistor is a planar gate electrode.

6. The photodetector according to claim 1, wherein the gate electrode of the transfer transistor has a circular, elliptical or rectangular planar shape and is disposed in the center of the pixel.

7. The photodetection device according to claim 1, further comprising a pixel isolation section that isolates the photoelectric conversion section from adjacent pixels, wherein the gate electrode of the transfer transistor has a triangular planar shape, and one side of the triangle is disposed in contact with the pixel isolation section.

8. The photodetection device according to claim 1, further comprising a pixel isolation section that isolates the photoelectric conversion section from adjacent pixels, wherein the gate electrode of the transfer transistor has a rectangular planar shape, and one side of the rectangle is disposed in contact with the pixel isolation section.

9. The photodetection device according to claim 1, further comprising a pixel isolation section that isolates the photoelectric conversion section from adjacent pixels, a gate electrode of the transfer transistor being disposed in contact with the pixel isolation section, and a portion of the gate electrode being disposed above the pixel isolation section.

10. The photodetector according to claim 1, wherein the photoelectric conversion section, the gate electrode, and the first semiconductor region are provided for each pixel, and the charge storage section is shared by a plurality of pixels.

11. The photodetection device according to claim 10, wherein the plurality of pixels sharing the charge storage section have an overflow path, and the gate electrode of the transfer transistor is disposed between the overflow path and the charge storage section.

12. The photodetector according to claim 1, wherein one pixel comprises two gate electrodes of the transfer transistor.

13. The photodetection device according to claim 12, wherein the gate electrodes of the two transfer transistors are arranged in a straight line in an L shape in a plan view, and the charge storage section is arranged at a corner of a pixel region surrounded by the gate electrodes of the two transfer transistors.

14. The photodetector according to claim 1, wherein the gate electrode of the transfer transistor is of a gate-all-around type that surrounds the channel in a plan view.

15. An electronic device comprising a photodetector including: a photoelectric conversion unit provided on a semiconductor substrate for generating charges according to an amount of received light; a gate electrode of a transfer transistor for controlling the transfer of the charges; a charge accumulation unit for accumulating the charges transferred under the control of the transfer transistor; and a first semiconductor region that is a semiconductor region of the same first conductivity type as a substrate region of the semiconductor substrate, bordering the charge accumulation unit in the depth direction and horizontal direction, and has an impurity concentration higher than that of the substrate region.

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