Light-emitting element-thin-film transistor integration structure based on step difference of substrate, and manufacturing method therefor

Abstract

The present invention relates to a light-emitting element-thin-film transistor integration structure. The integration structure according to one embodiment comprises: a first thin-film transistor formed in a first region of a substrate corresponding to a first height; a second thin-film transistor formed in a second region of the substrate corresponding to a second height; and a light-emitting element formed on the second thin-film transistor, wherein, after a thin-film transistor layer and a light-emitting element layer are sequentially formed in the first region and the second region of the substrate, the light-emitting element layer formed in the first region is removed so that the first thin-film transistor can be formed on top of the first region and the second thin-film transistor and the light-emitting element can be formed on top of the second region.

Description

Light-emitting device based on the step of the substrate - Thin film transistor integration structure and manufacturing method thereof

[0001] The present invention relates to an integration structure of a light-emitting element and a thin film transistor, and more specifically, to a technical idea of ​​implementing an integration structure of a light-emitting element and a thin film transistor using a substrate having a step difference.

[0002] The existing integration structure of a light-emitting element and a thin film transistor distinguishes the light-emitting element and the thin film transistor by controlling the manufacturing process of thin films deposited on the substrate rather than controlling the substrate.

[0003] Specifically, the existing integration structure applies an additional process of forming a light shielding wall to prevent light output from the light emitting element from entering the thin film transistor after individually forming a light emitting element and a thin film transistor on a substrate.

[0004] The present invention aims to provide an integration structure and a manufacturing method thereof that can simplify the manufacturing process by using a substrate having a step structure.

[0005] In addition, the present invention aims to provide an integration structure and a manufacturing method thereof that can omit an additional photo process for forming a light blocking structure by using a substrate having a step structure.

[0006] In addition, the present invention seeks to provide an integration structure and a manufacturing method thereof that can easily change the positions of a light-emitting element and a thin film transistor during a manufacturing process as needed.

[0007] An integration structure according to one embodiment of the present invention includes a first thin film transistor formed in a first region of a substrate corresponding to a first height, a second thin film transistor formed in a second region of the substrate corresponding to a second height, and a light-emitting element formed on the second thin film transistor, wherein the substrate may have a thin film transistor layer and a light-emitting element layer sequentially formed in the first region and the second region, and then the light-emitting element layer formed in the first region may be removed to form the first thin film transistor on the first region, and the second thin film transistor and the light-emitting element may be formed on the second region.

[0008] According to one side, each of the thin film transistor layer and the light emitting element layer can be formed simultaneously in the first region and the second region using a collimator of a sputtering device.

[0009] According to one side, the integration structure may further include a first wiring layer connecting the upper electrode of the first thin film transistor and the light emitting element to each other, and a second wiring layer connecting the lower electrode of the second thin film transistor and the light emitting element to each other.

[0010] According to one side, the first wiring layer may include a reflective material when the first height is lower than the second height.

[0011] According to one side, the light-emitting element may include a lower electrode layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and an upper electrode layer.

[0012] According to one side, the substrate may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0013] According to one side, the semiconductor thin film of the light-emitting element can be formed by supplying additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light during a deposition process based on at least one of a physical deposition method and a chemical deposition method.

[0014] A method for manufacturing an integration structure according to one embodiment of the present invention may include a step of forming a thin film transistor layer in a first region of a substrate corresponding to a first height and a second region of the substrate corresponding to a second height, a step of forming a light-emitting element layer on the thin film transistor layer formed on the first region and the second region, and a step of removing the light-emitting element layer formed on the first region to form a first thin film transistor on the first region, and a step of forming a second thin film transistor and a light-emitting element on the second region.

[0015] According to one side, the step of forming a thin film transistor layer in the second region may be performed by simultaneously forming a thin film transistor layer in the first region and the second region using a collimator of a sputtering device, and the step of forming a light emitting element layer on top of the thin film transistor layer may be performed by simultaneously forming a light emitting element layer on top of the thin film transistor layer formed in the first region and the thin film transistor layer formed in the second region using a collimator.

[0016] According to one aspect, the method for manufacturing an integration structure may further include a step of forming a first wiring layer connecting the upper electrode of the first thin film transistor and the light-emitting element to each other, and a second wiring layer connecting the lower electrode of the second thin film transistor and the light-emitting element to each other.

[0017] According to one side, the first wiring layer may include a reflective material when the first height is lower than the second height.

[0018] According to one side, the step of forming a light-emitting element layer on top of a thin film transistor layer may include a step of forming a lower electrode layer on top of the thin film transistor layer, a step of forming an n-type semiconductor layer on top of the lower electrode layer, a step of forming an active layer on top of the n-type semiconductor layer, a step of forming a p-type semiconductor layer on top of the active layer, and a step of forming an upper electrode layer on top of the p-type semiconductor layer.

[0019] According to one side, the substrate may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0020] According to one side, the step of forming the light-emitting element layer may include supplying additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light during the process of depositing a semiconductor thin film of the light-emitting element layer based on at least one of a physical deposition method and a chemical deposition method.

[0021] According to one embodiment, the present invention can simplify the manufacturing process of an integration structure by using a substrate having a step structure.

[0022] In addition, the present invention can omit an additional photo process for forming a light blocking structure by using a substrate having a step structure.

[0023] In addition, the present invention can easily change the positions of the light-emitting element and the thin film transistor during the manufacturing process as needed.

[0024] FIG. 1 is a drawing for explaining an integration structure according to a first embodiment.

[0025] Figure 2 is a drawing for explaining an integration structure according to a second embodiment.

[0026] FIG. 3 is a drawing for explaining a method for manufacturing an integration structure according to an embodiment.

[0027] FIGS. 4A to 4C are drawings for explaining a method for manufacturing an integration structure according to the first embodiment.

[0028] FIGS. 5A to 5C are drawings for explaining a method for manufacturing an integration structure according to a second embodiment.

[0029] Below, various embodiments of this document are described with reference to the attached drawings.

[0030] The examples and terms used herein are not intended to limit the technology described in this document to a particular embodiment, but should be understood to encompass various modifications, equivalents, and / or alternatives of the embodiments.

[0031] In the following description of various embodiments, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the invention, the detailed description will be omitted.

[0032] The terms described below are defined based on their functions in various embodiments, and may vary depending on the intent or custom of the user or operator. Therefore, their definitions should be based on the contents of this specification.

[0033] In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0034] A singular expression may include a plural expression unless the context clearly indicates otherwise.

[0035] In this document, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0036] Expressions such as "first," "second," "first," or "second," may modify the components without regard to order or importance, and are used only to distinguish one component from another, but do not limit the components.

[0037] When it is said that a component (e.g., a first component) is “(functionally or communicatively) connected” or “connected” to another component (e.g., a second component), that component may be directly connected to the other component, or may be connected through another component (e.g., a third component).

[0038] In this specification, “configured to” may be used interchangeably with “suitable for,” “capable of,” “modified to,” “made to,” “capable of,” or “designed to,” depending on the context, for example, in terms of hardware or software.

[0039] In some contexts, the expression "a device configured to" may mean that the device is "capable of" doing something in conjunction with other devices or components.

[0040] For example, the phrase "a processor configured (or set) to perform A, B, and C" may mean a dedicated processor (e.g., an embedded processor) for performing those operations, or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0041] Also, the term 'or' means 'inclusive or' rather than 'exclusive or'.

[0042] That is, unless otherwise stated or clear from context, the expression 'x utilizes a or b' means any one of the natural inclusive permutations.

[0043] In the specific embodiments described above, the components included in the invention are expressed singularly or plurally depending on the specific embodiment presented.

[0044] However, the singular or plural expressions are selected to suit the situation presented for convenience of explanation, and the above-described embodiments are not limited to singular or plural components, and even components expressed in plural may be composed of singular elements, or even components expressed in singular elements may be composed of plural elements.

[0045] Meanwhile, although the description of the invention has described specific embodiments, it is clear that various modifications are possible within the scope that does not depart from the scope of the technical ideas contained in the various embodiments.

[0046] Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims described below but also by equivalents of the claims.

[0047] FIG. 1 and FIG. 2 are drawings for explaining an integration structure according to one embodiment.

[0048] Specifically, FIG. 1 is a drawing for explaining an integration structure according to a first embodiment (where the first height is higher than the second height), and FIG. 2 is a drawing for explaining an integration structure according to a second embodiment (where the first height is lower than the second height).

[0049] An integration structure according to one embodiment can simplify the manufacturing process of the integration structure by using a substrate having a step structure.

[0050] In addition, the integration structure can omit an additional photo process for forming a light-blocking structure by using a substrate having a step structure.

[0051] In addition, the integration structure can easily change the positions of the light-emitting element and the thin film transistor during the manufacturing process as needed, i.e., it can easily implement an integration structure corresponding to either the first embodiment or the second embodiment.

[0052]

[0053] Hereinafter, a first embodiment of an integration structure according to an embodiment will be described through FIG. 1.

[0054] Referring to FIG. 1, an integration structure (100) according to a first embodiment may include a first thin film transistor (120-1) formed in a first region of a substrate (110) corresponding to a first height, a second thin film transistor (120-2) formed in a second region of the substrate (110) corresponding to a second height lower than the first height, and a light emitting element (130) formed on the second thin film transistor (120-2).

[0055] That is, the substrate (110) may be a substrate having a step based on a first height and a second height, and for example, the substrate (110) may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0056] According to one side, if the substrate (110) is a glass substrate, a reflective film may be coated in advance on the side wall of the first region (i.e., the side wall adjacent to the light-emitting element (130)), thereby preventing light output from the light-emitting element (130) from entering the first thin film transistor (120-1).

[0057] Specifically, the substrate (110) may be formed with a thin film transistor layer and a light emitting element layer sequentially formed in a first region and a second region, and then the light emitting element layer formed in the first region may be removed, so that a thin film transistor layer, i.e., a first thin film transistor (120-1), may be formed on the first region, and a thin film transistor layer and a light emitting element layer, i.e., a second thin film transistor (120-2) and a light emitting element (130), may be formed on the second region.

[0058] For example, each of the thin film transistor layer and the light emitting element layer can be formed simultaneously in the first region and the second region using a collimator of the sputtering equipment.

[0059] A collimator is a means that serves to evenly deposit particles of a deposit emitted from a target in a desired area by making the direction of the particles constant. It is located between the target and the path of the deposit, and can make the particles of the deposit emitted from the target evenly proceed at a constant angle and direction.

[0060] For example, each of the first thin film transistor (120-1) and the second thin film transistor (120-2) may mean one thin film transistor, and may also mean a thin film transistor-based driving circuit composed of two or more thin film transistors, wherein the thin film transistor may include a channel layer, a gate electrode, a source electrode, and a drain electrode.

[0061] For a more specific example, each of the gate electrode, source electrode, and drain electrode of the thin film transistor may include at least one of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or silver (Ag), and a metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).

[0062] Additionally, the channel layer of the thin film transistor may include at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon, polycrystalline silicon, InGaZnO, a-IGZO (amorphous-Indium Gallium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), IGO (Indium Gallium Oxide), ITZO (Indium Tin Zinc Oxide), GTO (Gallium Tin Oxide), ZTO (Zinc Tin Oxide), IAZO (Indium Antimony Zinc Oxide), AZO (Antimony Zinc Oxide), ITO (Indium Tin Oxide), ATO (Antimony Tin Oxide), and GZO (Gallium Zinc Oxide).

[0063] According to one side, the light-emitting element (130) may include a lower electrode layer (130-1), an n-type semiconductor layer (130-2), an active layer (130-3), a p-type semiconductor layer (130-4), and an upper electrode layer (130-5).

[0064] The lower electrode layer (130-1) can serve as a metal reflective film by including a metal material with high reflectivity, and through this, the lower electrode layer (130-1) can improve the light extraction efficiency of the light emitting element (130) by reflecting light generated from the light emitting element (130).

[0065] For example, the lower electrode layer (130-1) may include at least one metal material among silver (Ag) and aluminum (Al).

[0066] Preferably, the lower electrode layer (130-1) is implemented as an aluminum (Al) electrode layer, and can simultaneously serve as a buffer layer that induces easier c-axis growth of a semiconductor thin film (i.e., at least one layer among the n-type semiconductor layer (130-2), the active layer (130-3), and the p-type semiconductor layer (130-4)) of a light-emitting element formed on top of the lower electrode layer (130-1).

[0067] The n-type semiconductor layer (130-2) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the n-type semiconductor layer (130-2) may be an n-GaN layer.

[0068] The active layer (130-3) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN).

[0069] In addition, the active layer (130-3) may have a structure in which a quantum well using a material having a small energy band gap and a quantum barrier using a material having a large energy band gap are alternately stacked at least once, and the quantum well may have a single quantum well structure or a multi-quantum well (MQW) structure. Preferably, the active layer (130-3) may include an MQW structure.

[0070] According to one side, the active layer (130-3) may include an InGaN-based red MQW structure, wherein the InGaN-based red MQW structure may be implemented as a stacked structure of a first GaN layer, a first InAlN-based capping layer, an InGaN layer, a second InAlN-based capping layer, and a second GaN layer.

[0071] Specifically, the high indium content InGaN MQW structure applied to nitride-based red light-emitting devices causes the QCSE effect and phase separation due to stress generated by the difference in lattice parameters with the GaN layer, which may cause a decrease in internal quantum efficiency (IQE).

[0072] Accordingly, the active layer (130-3) according to one embodiment can minimize stress due to a difference in lattice constant between the GaN layer and the InGaN layer by applying an InAlN capping layer having a thickness of 1 nm to 2 nm between the GaN layer and the InGaN layer provided in the MQW structure. At this time, doping may be additionally applied to the InAlN capping layer to control conduction band and valence band characteristics.

[0073] The p-type semiconductor layer (130-4) may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the p-type semiconductor layer (130-4) may be a p-GaN layer.

[0074] The upper electrode layer 130-5 includes amorphous-Indium Gallium Zinc Oxide (a-IGZO), Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Indium Tin Zinc Oxide (ITZO), Gallium Tin Oxide (GTO), Zinc Tin Oxide (ZTO), and Indium Tin Oxide (IAZO). It may be a transparent electrode containing at least one of antimony zinc oxide (AZO), antimony zinc oxide (AZO), indium tin oxide (ITO), antimony tin oxide (ATO), and gallium zinc oxide (GZO).

[0075] According to one aspect, the semiconductor thin film of the light-emitting element (i.e., at least one layer among the n-type semiconductor layer (130-2), the active layer (130-3), and the p-type semiconductor layer (130-4)) can be formed by supplying additional energy based on at least one of an ion beam, an electron beam, a plasma, ultraviolet rays, a laser, and LED light during a deposition process based on at least one of a physical deposition method and a chemical deposition method. Preferably, additional energy based on an ion beam can be supplied during the deposition process of the semiconductor thin film of the light-emitting element.

[0076] Specifically, when a glass substrate is used as the substrate (110), in order to grow a thin film directly on the glass substrate without a transfer process, it is necessary to lower the growth temperature of the thin film to a low temperature.

[0077] Accordingly, an integration structure according to one embodiment lowers the temperature for growing a semiconductor thin film of a light-emitting element to a low temperature (for example, a temperature of 700°C or lower) and, in this process, supplies additional energy to the semiconductor thin film being deposited to supplement the energy required for thin film growth, thereby enabling the implementation of a high-quality semiconductor thin film at a low temperature.

[0078] According to one side, the integration structure (100) may further include a first wiring layer (140) that connects the first thin film transistor (120-1) and the upper electrode (130-5) of the light emitting element (130) to each other, and a second wiring layer (150) that connects the second thin film transistor (120-2) and the lower electrode (130-1) of the light emitting element (130) to each other.

[0079] For example, the first wiring layer (140) can connect one of the source electrode and the drain electrode of the first thin film transistor (120-1) to the upper electrode (130-5) of the light emitting element (130), and the second wiring layer (150) can connect one of the source electrode and the drain electrode of the second thin film transistor (120-2) to the lower electrode (130-1) of the light emitting element (130).

[0080] Hereinafter, a second embodiment of an integration structure according to an embodiment will be described with reference to FIG. 2, and any description that overlaps with the description with reference to FIG. 1 among the contents described with reference to FIG. 2 will be omitted.

[0081] Referring to FIG. 2, an integration structure (200) according to a second embodiment may include a first thin film transistor (220-1) formed in a first region of a substrate (210) corresponding to a first height, a second thin film transistor (220-2) formed in a second region of the substrate (210) corresponding to a second height higher than the first height, and a light emitting element (230) formed on the second thin film transistor (220-2).

[0082] Specifically, the substrate (210) may be formed with a thin film transistor layer and a light emitting element layer sequentially formed in a first region and a second region, and then the light emitting element layer formed in the first region may be removed, so that a thin film transistor layer, i.e., a first thin film transistor (220-1), may be formed on the first region, and a thin film transistor layer and a light emitting element layer, i.e., a second thin film transistor (220-2) and a light emitting element (230), may be formed on the second region.

[0083] For example, each of the thin film transistor layer and the light emitting element layer can be formed simultaneously in the first region and the second region using a collimator of the sputtering equipment.

[0084] Additionally, each of the first thin film transistor (220-1) and the second thin film transistor (220-2) may mean one thin film transistor, or may mean a thin film transistor-based driving circuit composed of two or more thin film transistors.

[0085] According to one side, the light emitting element (130) may include a lower electrode layer (230-1), an n-type semiconductor layer (230-2), an active layer (230-3), a p-type semiconductor layer (230-4), and an upper electrode layer (230-5).

[0086] Preferably, the lower electrode layer (230-1) can serve as a metal reflective film by including a metal with high reflectivity, and the upper electrode layer (230-5) can be implemented as a transparent electrode.

[0087] Additionally, the n-type semiconductor layer (230-2) may be an n-GaN layer, the p-type semiconductor layer (230-4) may be a p-GaN layer, and the active layer (230-3) may include a multi-quantum well (MQW) structure.

[0088] According to one side, the integration structure (200) may further include a first wiring layer (240) connecting the first thin film transistor (220-1) and the upper electrode (230-5) of the light emitting element (230) to each other, and a second wiring layer (250) connecting the second thin film transistor (220-2) and the lower electrode (230-1) of the light emitting element (230) to each other, wherein the first wiring layer (240) may further include a reflective material to reflect light output from the light emitting element (230) toward the first thin film transistor (220-1).

[0089] For example, the integration structure (200) may include a reflective film (240-1) based on a reflective material between the first wiring layer (240) and the light emitting element (230) to reflect light output from the light emitting element (230) in the direction of the first thin film transistor (220-1), but is not limited thereto, and the first wiring layer (240) may be implemented with a metal material (i.e., a reflective material) having a high reflectivity of at least one of silver (Ag) and aluminum (Al) to perform the role of a metal reflective film.

[0090] FIG. 3 is a drawing for explaining a method for manufacturing an integration structure according to an embodiment.

[0091] Referring to FIG. 3, in step 310, the manufacturing method can form a thin film transistor layer in a first region of the substrate corresponding to a first height and a second region of the substrate corresponding to a second height.

[0092] That is, the substrate may be a substrate having a step based on a first height and a second height, and for example, the substrate may include at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate.

[0093] According to one side, when the substrate is a glass substrate, a reflective film may be coated in advance on the side wall of the first region (a side wall adjacent to the light-emitting element described below), thereby preventing light output from the light-emitting element from entering the first thin film transistor described below.

[0094] For example, a thin film transistor layer may mean one thin film transistor, or may mean a thin film transistor-based driving circuit composed of two or more thin film transistors, where the thin film transistor may include a channel layer, a gate electrode, a source electrode, and a drain electrode.

[0095] For a more specific example, each of the gate electrode, source electrode, and drain electrode of the thin film transistor may include at least one of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or silver (Ag), and a metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).

[0096] Additionally, the channel layer of the thin film transistor may include at least one of amorphous silicon, nanocrystalline silicon, microcrystalline silicon, polycrystalline silicon, InGaZnO, a-IGZO (amorphous-Indium Gallium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IZO (Indium Zinc Oxide), IGO (Indium Gallium Oxide), ITZO (Indium Tin Zinc Oxide), GTO (Gallium Tin Oxide), ZTO (Zinc Tin Oxide), IAZO (Indium Antimony Zinc Oxide), AZO (Antimony Zinc Oxide), ITO (Indium Tin Oxide), ATO (Antimony Tin Oxide), and GZO (Gallium Zinc Oxide).

[0097] According to one side, in step 310, the manufacturing method can simultaneously form a thin film transistor layer in the first region and the second region using a collimator of a sputtering device.

[0098] In step 320, the manufacturing method can form a light-emitting element layer on top of the thin film transistor layer formed on the first region and the second region.

[0099] According to one side, in step 320, the manufacturing method can simultaneously form a light-emitting element layer on top of a thin film transistor layer formed in a first region and a thin film transistor layer formed in a second region using a collimator of a sputtering device.

[0100] For example, the light-emitting element layer may include a lower electrode layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and an upper electrode layer.

[0101] Specifically, in step 320, the manufacturing method can form a lower electrode layer on top of the thin film transistor layer.

[0102] For example, the lower electrode layer can include a metal material with high reflectivity to serve as a metal reflective film, thereby improving the light extraction efficiency of the light-emitting element by reflecting light generated from the light-emitting element.

[0103] For a more specific example, the lower electrode layer may include at least one highly reflective metal material selected from the group consisting of silver (Ag) and aluminum (Al).

[0104] Next, in step 320, the manufacturing method can form an n-type semiconductor layer on top of the lower electrode layer.

[0105] For example, the n-type semiconductor layer may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the n-type semiconductor layer may be an n-GaN layer.

[0106] Next, in step 320, the manufacturing method can form an active layer on top of the n-type semiconductor layer.

[0107] For example, the active layer may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN).

[0108] In addition, the active layer may have a structure in which a quantum well using a material having a small energy band gap and a quantum barrier using a material having a large energy band gap are alternately stacked at least once, and the quantum well may have a single quantum well structure or a multi-quantum well (MQW) structure. Preferably, the active layer may include an MQW structure.

[0109] According to one side, the active layer may include an InGaN-based red MQW structure, wherein the InGaN-based red MQW structure may be implemented as a stacked structure of a first GaN layer, a first InAlN-based capping layer, an InGaN layer, a second InAlN-based capping layer, and a second GaN layer.

[0110] Next, in step 320, the manufacturing method can form a p-type semiconductor layer on top of the active layer.

[0111] For example, the p-type semiconductor layer may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Preferably, the p-type semiconductor layer (130-4) may be a p-GaN layer.

[0112] Next, in step 320, the manufacturing method can form an upper electrode layer on top of the p-type semiconductor layer.

[0113] For example, the upper electrode layer may be a transparent electrode including at least one of amorphous-indium gallium zinc oxide (a-IGZO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), gallium tin oxide (GTO), zinc tin oxide (ZTO), indium antimony zinc oxide (IAZO), antimony zinc oxide (AZO), indium tin oxide (ITO), antimony tin oxide (ATO), and gallium zinc oxide (GZO).

[0114] According to one side, in the manufacturing method in step 320, in the process of depositing a semiconductor thin film of a light-emitting element layer (at least one layer of an n-type semiconductor layer, an active layer, and a p-type semiconductor layer) based on at least one of a physical vapor deposition method and a chemical vapor deposition method, additional energy based on at least one of an ion beam, an electron beam, plasma, ultraviolet rays, a laser, and LED light can be supplied.

[0115] In step 330, the manufacturing method can form a first thin film transistor (i.e., a thin film transistor layer formed in the first region) on top of the first region by removing the light-emitting element layer formed in the first region, and form a second thin film transistor (i.e., a thin film transistor layer formed in the second region) and a light-emitting element (i.e., a light-emitting element layer formed in the second region) on top of the second region.

[0116] In step 340, the manufacturing method can form a first wiring layer connecting the upper electrode of the first thin film transistor and the light-emitting element to each other, and a second wiring layer connecting the lower electrode of the second thin film transistor and the light-emitting element to each other.

[0117] For example, the first wiring layer may include a reflective material if the first height is lower than the second height.

[0118] FIGS. 4A to 4C are drawings for explaining a method for manufacturing an integration structure according to the first embodiment.

[0119] The manufacturing method described below through FIGS. 4a to 4c can be performed in steps 310 to 340 described through FIG. 3.

[0120] In step 410, the manufacturing method can form a thin film transistor layer (402) and a light emitting element layer (403 to 407) in a first region of the substrate (401) corresponding to a first height and in a second region of the substrate (401) corresponding to a second height lower than the first height.

[0121] For example, the light emitting element layer (403 to 407) may include a lower electrode layer (403), an n-type semiconductor layer (404), an active layer (405), a p-type semiconductor layer (406), and an upper electrode layer (407).

[0122] According to one side, in step 410, the manufacturing method can simultaneously form a thin film transistor layer (402) and a light emitting element layer (403 to 407) in the first region and the second region using a collimator of a sputtering device.

[0123] In step 420, the manufacturing method can form a first thin film transistor (i.e., a thin film transistor layer (402) formed in the first region) on top of the first region by removing the light emitting element layer formed in the first region, and form a second thin film transistor (i.e., a thin film transistor layer (402) formed in the second region) and a light emitting element (i.e., a light emitting element layer (403 to 407) formed in the second region) on top of the second region.

[0124] In step 430, the manufacturing method can form a first wiring layer (408) that connects the upper electrode (407) of the first thin film transistor (i.e., the thin film transistor layer (402) formed in the first region) and the light emitting element (i.e., the light emitting element layer (403 to 407) formed in the second region) to each other, and a second wiring layer (409) that connects the lower electrode (403) of the second thin film transistor (i.e., the thin film transistor layer (402) formed in the second region) and the light emitting element (i.e., the light emitting element layer (403 to 407) formed in the second region) to each other.

[0125] FIGS. 5A to 5C are drawings for explaining a method for manufacturing an integration structure according to a second embodiment.

[0126] The manufacturing method described below through FIGS. 5a to 5c can be performed in steps 310 to 340 described through FIG. 3.

[0127] In step 510, the manufacturing method can form a thin film transistor layer (502) and a light emitting element layer (503 to 507) in a first region of the substrate (501) corresponding to a first height and a second region of the substrate (501) corresponding to a second height higher than the first height.

[0128] For example, the light-emitting element layer (503 to 507) may include a lower electrode layer (503), an n-type semiconductor layer (504), an active layer (505), a p-type semiconductor layer (506), and an upper electrode layer (507).

[0129] According to one side, in step 510, the manufacturing method can simultaneously form a thin film transistor layer (502) and a light emitting element layer (503 to 507) in the first region and the second region using a collimator of a sputtering device.

[0130] In step 520, the manufacturing method can form a first thin film transistor (i.e., a thin film transistor layer (502) formed in the first region) on top of the first region by removing the light-emitting element layer formed in the first region, and form a second thin film transistor (i.e., a thin film transistor layer (502) formed in the second region) and a light-emitting element (i.e., a light-emitting element layer (503 to 507) formed in the second region) on top of the second region.

[0131] In step 530, the manufacturing method may form a first wiring layer (508) that connects the upper electrode (507) of the first thin film transistor (i.e., the thin film transistor layer (502) formed in the first region) and the light emitting element (i.e., the light emitting element layer (503 to 507) formed in the second region) to each other, and a second wiring layer (509) that connects the lower electrode (503) of the second thin film transistor (i.e., the thin film transistor layer (502) formed in the second region) and the light emitting element (i.e., the light emitting element layer (503 to 507) formed in the second region) to each other, wherein the first wiring layer (508) may include a reflective material.

[0132] For example, the integration structure may include a reflective film (508-1) based on a reflective material between the first wiring layer (240) and the light-emitting element (i.e., the light-emitting element layer (503 to 507) formed in the second region), but is not limited thereto, and the first wiring layer (508) may be implemented with a metal material (i.e., a reflective material) having a high reflectivity of at least one of silver (Ag) and aluminum (Al) to perform the function of a metal reflective film.

[0133] Ultimately, by using the present invention, the manufacturing process of an integration structure can be simplified by using a substrate having a step structure.

[0134] In addition, by using the present invention, an additional photo process for forming a light blocking structure can be omitted by using a substrate having a step structure.

[0135] In addition, by using the present invention, the positions of the light-emitting element and the thin film transistor can be easily changed during the manufacturing process as needed.

[0136] Although the embodiments described above have been described with limited drawings, those skilled in the art will recognize that various modifications and variations can be made based on the above description. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0137] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. A first thin film transistor formed in a first area of ​​a substrate corresponding to a first height; A second thin film transistor formed in a second region of the substrate corresponding to the second height, and A light-emitting element formed on top of the second thin film transistor Including, The above substrate is, After a thin film transistor layer and a light emitting element layer are sequentially formed in the first region and the second region, the light emitting element layer formed in the first region is removed, so that the first thin film transistor is formed on the upper part of the first region, and the second thin film transistor and the light emitting element are formed on the upper part of the second region. Integration structure.

2. In paragraph 1, Each of the above thin film transistor layer and the above light emitting element layer, Using a collimator of a sputtering device, the first region and the second region are formed simultaneously. Integration structure.

3. In paragraph 1, A first wiring layer connecting the first thin film transistor and the upper electrode of the light-emitting element to each other, and A second wiring layer connecting the second thin film transistor and the lower electrode of the light emitting element to each other An integration structure that further includes:

4. In paragraph 3, The above first wiring layer is, If the first height is lower than the second height, the reflective material is included. Integration structure.

5. In paragraph 1, The above light emitting element, Comprising a lower electrode layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and an upper electrode layer. Integration structure.

6. In paragraph 1, The above substrate is, Comprising at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate. Integration structure.

7. In paragraph 1, The semiconductor thin film of the above light-emitting element is, In a deposition process based on at least one of a physical deposition method and a chemical deposition method, additional energy based on at least one of an ion beam, an electron beam, a plasma, ultraviolet light, a laser, and an LED light is supplied to form Integration structure.

8. A step of forming a thin film transistor layer in a first region of the substrate corresponding to a first height and a second region of the substrate corresponding to a second height; A step of forming a light-emitting element layer on top of the thin film transistor layer formed on the first region and the second region, and A step of forming a first thin film transistor on top of the first region by removing the light-emitting element layer formed on the first region, and forming a second thin film transistor and light-emitting element on top of the second region. A method for manufacturing an integration structure including:

9. In paragraph 8, The step of forming a thin film transistor layer in the second region is: The thin film transistor layer is formed simultaneously in the first region and the second region using a collimator of a sputtering device, The step of forming a light-emitting element layer on top of the thin film transistor layer is: Using the collimator, the light-emitting element layer is simultaneously formed on top of the thin film transistor layer formed in the first region and the thin film transistor layer formed in the second region. A method for manufacturing an integration structure.

10. In paragraph 8, A step of forming a first wiring layer connecting the upper electrode of the first thin film transistor and the light-emitting element to each other, and a second wiring layer connecting the lower electrode of the second thin film transistor and the light-emitting element to each other. A method for manufacturing an integration structure further comprising:

11. In paragraph 10, The above first wiring layer is, If the first height is lower than the second height, the reflective material is included. A method for manufacturing an integration structure.

12. In paragraph 8, The step of forming a light-emitting element layer on top of the thin film transistor layer is: A step of forming a lower electrode layer on top of the thin film transistor layer; A step of forming an n-type semiconductor layer on top of the lower electrode layer; A step of forming an active layer on top of the n-type semiconductor layer; A step of forming a p-type semiconductor layer on top of the above active layer, and A step of forming an upper electrode layer on top of the above p-type semiconductor layer A method for manufacturing an integration structure including:

13. In paragraph 8, The above substrate is, Comprising at least one of a glass substrate, a stainless steel substrate, a polymer substrate, a sapphire substrate, a silicon (Si) substrate, and a silicon carbide (SiC) substrate. A method for manufacturing an integration structure.

14. In paragraph 8, The step of forming the above light-emitting element layer is: In the process of depositing the semiconductor thin film of the light-emitting element layer based on at least one of a physical deposition method and a chemical deposition method, additional energy based on at least one of an ion beam, an electron beam, a plasma, ultraviolet rays, a laser, and an LED light is supplied. A method for manufacturing an integration structure.

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