Memory management method and apparatus having validation function

Abstract

The present invention relates to a memory management method and apparatus having a validation function, wherein an intermediate checksum is stored in a first non-volatile memory along with a portion of code, and a final checksum for the entire code stored divided between the first non-volatile memory and a second non-volatile memory is stored in the second non-volatile memory along with the remainder of the code.

Description

Memory operating method and device having a validation function

[0001] The present invention relates to a memory operation method and device applicable to an embedded system.

[0002] An embedded system is a computer system implemented with software (or program code) embedded in hardware to perform specific functions. To verify the integrity of software code in embedded systems, checksums can be used when writing or reading code to memory.

[0003] Here's an example of a typical cyclic checksum: First, if the four bytes of data are 0x25, 0x62, 0x3F, and 0x52, adding them all up gives 0x118. Next, by discarding the carry nibble, 0x18 is obtained, and in the third step, the checksum byte 0xE8 is obtained by obtaining the two's complement of 0x18. To test the checksum byte, adding all the bytes in the original group up to the checksum byte gives 0x25 + 0x62 + 0x3F + 0x52 + 0xE8 = 0x200. Again, discarding the carry nibble gives 0x00, which means that there are no errors in the byte data.

[0004] In embedded systems, a checksum is calculated before storing the code in non-volatile memory, and the calculated checksum is stored in the last address of the memory. When the embedded system's MCU (Microcontroller Unit) starts reading the code, the process of calculating the checksum is repeated every time the embedded system is powered on, equal to the size of the program code stored in the memory. Assuming a memory with N addresses, N additions and carry nibbles must be performed to complete the checksum calculation, and when converted to clock cycles, it takes N clock cycles to calculate. In MCUs with slow clock frequencies, the checksum calculation takes a long time before the software (or application code) starts executing, which slows down the code validation time. Embedded systems typically have one checksum corresponding to the code stored in non-volatile memory.

[0005] The present invention provides a memory operation method and device capable of increasing the speed of validation of code stored in non-volatile memory in an embedded system.

[0006] A memory operating method according to one embodiment of the present invention comprises the steps of: storing an intermediate checksum together with a portion of code in a first non-volatile memory; storing a final checksum for the entire code, which is divided and stored in the first non-volatile memory and the second non-volatile memory, together with the remainder of the code in a second non-volatile memory; and reading the intermediate checksum stored in the first non-volatile memory and reading a portion of the code stored in the first non-volatile memory, accumulating a first checksum by real-time calculation, and using the intermediate checksum to accumulate a second checksum by real-time calculation in a process of reading the remainder of the code stored in the second non-volatile memory.

[0007] The codes stored in the first non-volatile memory and the second non-volatile memory can be read simultaneously through parallel processing, and the first checksum and the second checksum can be accumulated through real-time calculation.

[0008] The above second checksum can be accumulated from the above first checksum.

[0009] The above memory operating method may further include a step of comparing the intermediate checksum and the first checksum to verify the integrity of a portion of the code stored in the first non-volatile memory; and a step of comparing the final checksum and the second checksum to verify the integrity of the entire code stored in the first non-volatile memory and the second non-volatile memory.

[0010] At the same time that the intermediate checksum and the first checksum are compared, the final checksum and the second checksum can be compared.

[0011] The above memory operating method may further include a step of writing the intermediate checksum after a portion of the code is sequentially written to the first non-volatile memory; and a step of writing the final checksum after the remaining portion of the code is sequentially written to the second non-volatile memory. The first intermediate checksum may be written to the first non-volatile memory as the intermediate checksum before the final checksum is written to the second non-volatile memory.

[0012] A memory operating device according to one embodiment of the present invention comprises: a first non-volatile memory;

[0013] An Nth nonvolatile memory (N is a positive integer greater than or equal to 2); and a central processing unit, a memory control unit, a communication interface, and a volatile memory connected to the first nonvolatile memory and the Nth nonvolatile memory via a bus. The memory control unit stores an intermediate checksum for a portion of the code together with a portion of the code in the first nonvolatile memory when N is 2, and stores a final checksum for the entire code stored in the first nonvolatile memory and the second nonvolatile memory together with the remainder of the code in the second nonvolatile memory. The memory control unit reads the intermediate checksum from the first nonvolatile memory and accumulates a first checksum through real-time calculation in the process of reading the portion of the code stored in the first nonvolatile memory, and accumulates a second checksum through real-time calculation using the intermediate checksum in the process of reading the remainder of the code stored in the second nonvolatile memory.

[0014] According to an embodiment of the invention, a validation process that compares a real-time calculated checksum with an internally generated and stored intermediate checksum during the storage process in non-volatile memories of an embedded system can be performed in parallel in non-volatile memories, thereby increasing the validation speed of the entire code stored in non-volatile memories. As a result, the present invention can improve the initial integrity check speed of a low-speed MCU, thereby improving the startup speed of the overall application software of the embedded system.

[0015] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0016] FIG. 1 and FIG. 2 are drawings showing the configuration of a memory operating device according to one embodiment of the present invention.

[0017] FIG. 3 is a flowchart showing a writing method of a non-volatile memory according to one embodiment of the present invention.

[0018] Figure 4 is a drawing showing in detail an example of a writing method of nonvolatile memory when the nonvolatile memory is divided into two.

[0019] FIG. 5 is a flowchart showing a method for reading a non-volatile memory according to one embodiment of the present invention.

[0020] Figure 6 is a drawing showing in detail an example of a reading method of nonvolatile memory when the nonvolatile memory is divided into two.

[0021] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0022] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, the same reference numerals designate substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of the present invention.

[0023] In the specification, when “comprises,” “includes,” “has,” and “consists of,” other parts may be added unless “only” is used. When a component is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

[0024] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0025] When the positional relationship and interconnectedness between two components are described as ‘on’, ‘above’, ‘below’, ‘next to’, ‘connect, couple’, crossing, intersecting, etc., one or more other components may be interposed between the components unless there is a mention of ‘directly’ or ‘directly’.

[0026] When the temporal relationship is explained with phrases such as ‘after’, ‘following’, ‘next to’, or ‘before’, it may not be continuous on the time axis unless ‘right away’ or ‘directly’ is used.

[0027] Although first, second, etc. may be used to distinguish components, the function or structure of these components is not limited by the ordinal number or component name attached to the front of the component.

[0028] The following embodiments can be partially or fully combined or combined with one another, enabling various technically diverse interconnections and operations. Each embodiment can be implemented independently of the other, or can be implemented together in a related manner.

[0029] Hereinafter, "code" includes an operating system (OS), application programs, and data that can be stored in memory. Here, the data includes configuration data for peripheral devices connected internally and externally to the embedded system, user data, etc.

[0030] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0031] Figures 1 and 2 are drawings showing a memory operating device according to one embodiment of the present invention. The memory operating device (100) may be an MCU (Microcontroller Unit) of an embedded system.

[0032] Referring to FIGS. 1 and 2, the memory operating device (100) includes a central processing unit (hereinafter referred to as “”) (110), a non-volatile memory (120), a memory control unit (130), a communication interface (140), a volatile memory (150), and a bus (160) that connects components (110 to 150) of the memory operating device (100) to provide a signal transmission path.

[0033] The CPU (110) executes application programs written in code stored in the non-volatile memory (120), processes commands, and performs operations. The communication interface (140) supports a standard interface for data communication between an external peripheral device and the memory operating device (100), for example, a serial communication interface such as a Universal Asynchronous Receiver / Transmitter (UART), a Serial Peripheral Interface (SPI), an I2C, or a Universal Serial Bus (USB). The volatile memory (150) may include a memory that temporarily stores data, for example, a Static Random Access Memory (SRAM).

[0034] The memory operating device (100) includes first and second pins (101, 102) through which code or data is input / output. The first pin (102) may be a JTAG (Joint Test Action Group) pin. The first pin (102) provides code to the CPU (110) in debugging, program upload (Flash Programming), board testing, inter-chip testing, etc. The second pin (102) may be a communication interface pin connected to a peripheral device. Through the pins (101, 102), code to be stored in the non-volatile memory (120) and a final checksum for the entire code may be received, or data read from the non-volatile memory (120) may be transmitted to an external peripheral device. As an example of the checksum, a CRC (Cyclic Redundancy Check) may be used, but is not limited thereto.

[0035] The nonvolatile memory (120) may be, but is not limited to, a flash memory, an EEPROM, etc. The nonvolatile memory (120) stores the code in a divided form, and stores an intermediate checksum and a final checksum for the divided code. The nonvolatile memory (120) may be divided into N or more memories (N is a positive integer greater than or equal to 2) in which writes and reads are distinguished in a software manner or a hardware manner. In the software manner, one nonvolatile memory for reading and writing codes may be divided into N memories. When N is 2, the code of the first data group corresponding to half of the entire code may be read and written to the first memory area of ​​the nonvolatile memory, and the code of the second data group corresponding to the remaining half may be read and written to the second memory area of ​​the nonvolatile memory. The intermediate checksum is a value that can be used to verify whether the code stored in each memory area is not damaged when verifying the integrity of the code stored in each of N non-volatile memories, and can minimize the validation time by enabling parallel processing of the validation to verify the integrity of the code in the process of reading the code stored in non-volatile memories. The hardware method can divide the code into N physically separate non-volatile memories, read and write it, and store the intermediate checksum in at least one (N-1) of the memories.

[0036] In the first non-volatile memory (121), together with the code of the first data group, an intermediate checksum for the code of the first data group, for example, a first checksum (CS1), is generated and stored. In the second non-volatile memory (122), together with the code of the second data group, an accumulated intermediate checksum for the code of the first and second data groups, for example, a second checksum, is generated and stored. In the Nth non-volatile memory (123), together with the code of the third data group, a final checksum (FCS) for the entire code divided and stored in the first to Nth non-volatile memories (121, 122, 123) is stored.

[0037] The memory control unit (130) controls the writing and reading of codes in the non-volatile memory (120), and can calculate and generate intermediate checksums (CS1, CS2) and a final checksum (FCS). The memory control unit (130) can perform reading / writing of memory and checksum calculation in the memory operating methods illustrated in FIGS. 3 to 5. The final checksum (FCS) is a checksum for the entire code stored in the non-volatile memory (120). When the non-volatile memory (120) is a flash memory, it can include N Flash Program IPs (Intellectual Properties) and N checksum calculators (131 to 133) that individually manage N divided non-volatile memories (121, 122, 123). The N divided non-volatile memories can be interpreted as N memory cells included in the flash memory.

[0038] The memory operating device (100) further includes a memory selector (111) as illustrated in FIG. 2 and a plurality of comparators (112 to 115). The memory selector (111) and the comparators (112 to 115) may be physical components controlled by the CPU (110) or the memory control unit (130) or may be part of a function of a program performed by the CPU (110) or the memory control unit (130).

[0039] The memory selector (111) divides the input original code into memory areas of the non-volatile memories (121, 122, 123) and sequentially transmits the divided original code to the non-volatile memories (121, 122, 123). When the original code is divided into the first to Nth data groups, the first data group may be stored in the first non-volatile memory (121), the second data group may be stored in the second non-volatile memory (122), and then the Nth data group may be stored in the Nth non-volatile memory (123).

[0040] When the original code is divided and stored in the first to Nth non-volatile memories (121, 122, 123), an intermediate checksum is calculated for each memory. For example, the first checksum calculator (131) calculates in real time the first checksum for the code of the first data group when the code of the first data group is written and stored in the first non-volatile memory (121). The second checksum calculator (132) calculates in real time the second checksum as an accumulated value for the code of the combined first and second data groups stored in the first and second non-volatile memories (122) when the code of the second data group is written and stored in the second non-volatile memory (122). The Nth checksum calculator (133) calculates the final checksum in real time as an accumulated value for the entire original code divided and stored in the first to Nth nonvolatile memories (121, 122, 123) when the code of the Nth data group is written and stored in the third nonvolatile memory (123).

[0041] The first to Nth comparators (112, 113, 114) can simultaneously compare an intermediate checksum calculated in real time for each memory area of ​​non-volatile memories (121 to 123) with an intermediate checksum read from a corresponding memory (121 to 123) among checksums stored in the non-volatile memories (121 to 123) through parallel processing and output the comparison results simultaneously.

[0042] The first comparator (112) compares the real-time calculated value of the first checksum input from the first checksum calculator (131) with the first checksum (CS1) read from the first non-volatile memory (121). When the first checksum (CS1) read from the first non-volatile memory (121) is identical to the real-time calculated value of the first checksum, the first comparator (112) outputs a first logic value indicating that the code stored in the first non-volatile memory (121) is valid data, whereas when they do not match (or are different), the first logic value may be '1 (or high)', and the second logic value may be '0 (or low)', but is not limited thereto.

[0043] The second checksum calculator (132) calculates the second checksum using the first checksum (CS1) value and the stored value of the second non-volatile memory (122). The second comparator (113) compares the second checksum input from the second checksum calculator (132) with the second checksum (CS2) read from the second non-volatile memory (122). The second checksum output from the second checksum calculator (132) is an intermediate checksum calculated as an accumulated value for the code that combines the first and second data groups that are divided and stored in the first and second non-volatile memories (121, 122). The second comparator (113) outputs a first logic value indicating that the code stored in the second non-volatile memory (122) is valid data when the second checksum (CS2) read from the second non-volatile memory (122) is the same as the real-time calculated value of the second checksum input from the second checksum calculator (132), while outputting a second logic value when they do not match (or are different).

[0044] The Nth comparator (114) compares the final checksum (FCS) read from the Nth non-volatile memory (123) with the final checksum input from the Nth checksum calculator (133). The Nth comparator (114) outputs a first logic value indicating that the code stored in the Nth non-volatile memory (123) is valid data when the final checksum (FCS) read from the Nth non-volatile memory (123) is identical to the real-time calculated value of the final checksum input from the Nth checksum calculator (133), whereas it outputs a second logic value when they do not match (or are different).

[0045] The output signals of the first to Nth comparators (112, 113, 114) can be simultaneously input to the final comparator (115). The final comparator (115) outputs a first logic value indicating that the entire data of the code stored in the first to Nth non-volatile memories (121, 122, 123) is valid data without a defect when all of the output signals of the first to Nth comparators (112, 113, 114) are the first logic value. On the other hand, the final comparator (115) outputs a second logic value indicating that the code read from the first to Nth non-volatile memories (121, 122, 123) has a defect when at least one of the output signals of the first to Nth comparators (112, 113, 114) is the second logic value. The output signal of the final comparator (115) can be transmitted to a component requesting data reading from non-volatile memories (121, 122, 123).

[0046] FIG. 3 is a flowchart showing a writing method of a non-volatile memory according to one embodiment of the present invention.

[0047] Referring to FIG. 3, the final checksum for the entire original code is input to the memory operating device (100) together with the entire original code (W1).

[0048] The memory operating device (100) can divide the non-volatile memory into memories in which the original code is divided and stored (W2).

[0049] The memory operating device (100) stores the original code by dividing it into distinct memory areas in a nonvolatile memory. Each memory area may be a single nonvolatile memory. The memory operating device (100) accumulates the addresses of the nonvolatile memories where the code is written and calculates an intermediate checksum. The process of storing the divided code in a single nonvolatile memory and then storing the intermediate checksum for the divided code is repeated until the entire original code is stored in N nonvolatile memories (W3 to W8). Therefore, before the entire original code is stored in the nonvolatile memories, one or more intermediate checksums can be calculated and stored in the corresponding nonvolatile memories.

[0050] As the original code is stored in N non-volatile memories, the final checksum calculated in real time is compared with the input final checksum. The memory operating device (100) verifies the code stored in the non-volatile memories as integrity data without defects when the final checksum calculated in real time is the same as the input final checksum (W10). If the final checksum comparison result (W9 and W10) determines that the code stored in the non-volatile memories is defective, W3 to W10 are repeated to store the original code in the non-volatile memories again and verify the validity of the stored code.

[0051] FIG. 4 is a drawing showing in detail an example of a writing method of nonvolatile memory when the nonvolatile memory is divided into two. This writing method of nonvolatile memory may be a process of writing code to memory when storing initial code during the production of an embedded system or when updating code during use of the embedded system after product shipment, but is not limited thereto. In FIG. 4, 'Write clock' is a clock used when writing code to nonvolatile memory. 'External communication Read' represents a process in which code is serially input from the outside through pins (101, 102). When the nonvolatile memory is divided into two, 'Write1' is a process in which code is written to the first nonvolatile memory, and 'Write2' is a process in which code is written to the second nonvolatile memory. In FIG. 4, "C1~C(N)" are original codes that are divided and stored in the first and second nonvolatile memories. In this embodiment, it is assumed that the checksum of non-volatile memories is initialized to CS=0 at Write clock '0'.

[0052] Referring to Fig. 4, the original code received from the outside begins to be written to the first non-volatile memory (121) after the first Write clock (1). A checksum is accumulated when the code is written to the first non-volatile memory at each Write clock.

[0053] For example, when C1 is input to the first Write clock (1) through pins (101, 102), the first checksum (CS1) is accumulated as CS1=CS+C1. When C2 is input to the second Write clock (2), and C1 is written to the first non-volatile memory, the first checksum (CS1) is accumulated so that CS1=CS1+C2. Then, when C3 is input to the third Write clock (3), and C2 is written to the first non-volatile memory, the first checksum (CS1) is accumulated so that CS1=CS1+C3. When C(N / 2) is input to the N / 2 Write clock (N / 2), and C(N / 2)-1 is written to the first non-volatile memory, the first checksum (CS1) is accumulated so that CS1=CS1+C(N / 2). When C(N / 2)+1 is input to the (N / 2)+1 Write clock((N / 2)+1) and C(N / 2) is written to the first non-volatile memory, the accumulated value of the first checksum (CS1) CS1=CS1+C(N / 2)+1 is stored in the first non-volatile memory. The first checksum (CS1) is an intermediate checksum used to verify the validity of the code stored in the first non-volatile memory. After half of the original code is stored in the first non-volatile memory, the remaining half of the code is sequentially stored in the second non-volatile memory.

[0054] At the (N / 2)+2 Write clock ((N / 2)+2), C(N / 2)+2 is input and C(N / 2)+1 is written to the second non-volatile memory, and at the same time, the second checksum (CS2) begins to accumulate, so that CS2=CS1+C(N / 2)+2. Then, at the (N / 2)+3 Write clock (omitted in the drawing), C(N / 2)+3 is input and C(N / 2)+2 is written to the second non-volatile memory, and at the same time, the second checksum (CS2) is accumulated, so that CS2=CS2+C(N / 2)+3. At the (N-1) Write clock (N-1), C(N-1) is input and C(N-2) is written to the second non-volatile memory, and at the same time, the second checksum (CS2) is accumulated, so that CS2=CS2+C(N-1). When C(N) is input to the N Write clock (N) and C(N-1) is written to the second non-volatile memory, the second checksum (CS2) is accumulated so that CS2=CS2+C(N).

[0055] At the same time that C(N) is written to the second non-volatile memory without an input code at the N+1 Write clock (N+1), the final checksum (FCS) input to the memory operating device (100) together with the original code and the second checksum (CS2) accumulated through real-time calculation are compared by a comparator. The final checksum (FCS) received together with the original code may be temporarily stored in the volatile memory (150) and then compared with the second checksum (CS2) at the N+1 Write clock (N+1). When the accumulated second checksum (CS2) is identical to the input final checksum (FCS), the integrity of the code divided and stored in the first and second non-volatile memories is verified. At this time, a first logic value may be output from the comparator and the checksum calculation may be terminated. When the second checksum (CS2) does not match the final checksum (FCS), a second logic value may be output from the comparator. The final checksum (FCS) can be stored in the second non-volatile memory at the N+2 Write clock (N+2).

[0056] FIG. 5 is a flowchart showing a method for reading a non-volatile memory according to one embodiment of the present invention.

[0057] Referring to FIG. 5, a memory operating device (100) can simultaneously read N non-volatile memories in parallel processing and execute an application written with code stored in the N non-volatile memories.

[0058] First, the memory operating device (100) reads an intermediate checksum pre-stored in non-volatile memories (R1). Next, the memory operating device (100) simultaneously reads codes stored in N non-volatile memories and accumulates the code values ​​in real time to calculate a checksum (R2).

[0059] Next, the memory operating device (100) compares the checksum calculated in real time with the pre-stored checksum in each of the N non-volatile memories to simultaneously verify the integrity of the code stored in the non-volatile memories, thereby performing validation of the entire code (R3). Once the integrity of the entire code stored in the non-volatile memories is verified, the application program written with this code can be executed (R4).

[0060] FIG. 6 is a diagram showing in detail an example of a method for reading nonvolatile memory when the nonvolatile memory is divided into two. In FIG. 4, 'Read clock' is a clock used when reading code in the nonvolatile memory. When the nonvolatile memory is divided into two, 'Read1' is a process in which code stored in the first nonvolatile memory is read, and 'Read2' is a process in which code stored in the second nonvolatile memory is read. In FIG. 4, "C1~C(N)" are codes that are divided and stored in the first and second nonvolatile memories. "Checksum calculation 1" is an intermediate checksum calculation process that is calculated in real time when code stored in the first nonvolatile memory is sequentially read. "Calculation 2" is an intermediate checksum calculation process that is calculated in real time when code stored in the second nonvolatile memory is sequentially read. The first and second non-volatile memories are accessed in parallel processing, so that the code stored in these non-volatile memories is read simultaneously, and the intermediate checksums of each non-volatile memory are calculated simultaneously in real time.

[0061] Referring to FIG. 6, the memory operating device (100) first reads an intermediate checksum stored in non-volatile memories, for example, a first checksum (CS1) stored in the first non-volatile memory, at the first Read clock (1). At the same time, the first checksum (CS1), which is calculated in real time whenever a code is read, is initialized to CS=0, and the second checksum (CS2) is initialized to the first checksum (CS1) read from the first non-volatile memory (CS2=CS1).

[0062] At the second Read clock (2), as C1 is read from the first non-volatile memory, the first checksum (CS) calculated in real time is accumulated, so that CS=CS+C1. At the second Read clock (2), as C(N / 2)+1 is read from the second non-volatile memory, the second checksum (CS2) calculated in real time is accumulated, so that CS2=CS2+C(N / 2)+1. At the third Read clock (3), as C2 is read from the first non-volatile memory, the first checksum (CS) calculated in real time is accumulated, so that CS=CS+C2. At the third Read clock (3), as C(N / 2)+2 is read from the second non-volatile memory, the second checksum (CS2) calculated in real time is accumulated, so that CS2=CS2+C(N / 2)+2.

[0063] At the N / 2-th Read clock (N / 2), C(N / 2)-1 is read from the first non-volatile memory, and at the same time, the first checksum (CS) calculated in real time is accumulated, so that CS=CS+C(N / 2)-1. At the N / 2-th Read clock (N / 2), C(N-1) is read from the second non-volatile memory, and at the same time, the second checksum (CS2) calculated in real time is accumulated, so that CS2=CS2+C(N-1). At the (N-2)+1-th Read clock ((N-2)+1), C(N / 2) is read from the first non-volatile memory, and at the same time, the first checksum (CS) calculated in real time is accumulated, so that CS=CS+C(N / 2). At the (N-2)+1 Read clock ((N-2)+1), C(N) is read from the second non-volatile memory, and the second checksum (CS2) calculated in real time is accumulated, so that CS2=CS2+C(N / 2).

[0064] At the N / 2+2 Read clock ((N / 2)+2), the first checksum (CS) calculated in real time during the read process is compared with the first checksum (CS1) stored in the first non-volatile memory by a comparator. When the first checksum (CS) calculated in real time is identical to the first checksum stored in the first non-volatile memory, the integrity of the code stored in the first non-volatile memory is verified. At the N / 2+2 Read clock ((N / 2)+2), the second checksum (CS2) calculated in real time during the read process is compared with the final checksum (FCS) stored in the second non-volatile memory by a comparator. The final checksum (FCS) is the final checksum for the entire original code. After the integrity of the entire code stored in the first and second non-volatile memories is confirmed when the second checksum (CS2) calculated in real time is identical to the final checksum (FCS) stored in the second non-volatile memory, the reading of the first and second non-volatile memories may be terminated at the N / 2+3 Read clock ((N / 2)+3). At the N / 2+3 Read clock ((N / 2)+3), a first logic value confirming the integrity of the entire code stored in the first and second non-volatile memories may be output from the comparator, and a second logic value may be output from the comparator when the second checksum (CS2) is not identical to the final checksum (FCS).

[0065] The memory operating device according to the embodiment can be applied to embedded systems such as home appliances, automobiles, medical devices, communication systems, aviation and space systems, smart homes, and IoT devices.

[0066] Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

[0067] While the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

[0068] A memory operating method according to one embodiment of the present invention comprises the steps of: storing an intermediate checksum together with a portion of code in a first non-volatile memory; storing a final checksum for the entire code, which is divided and stored in the first non-volatile memory and the second non-volatile memory, together with the remainder of the code in a second non-volatile memory; and reading the intermediate checksum stored in the first non-volatile memory and reading a portion of the code stored in the first non-volatile memory, accumulating a first checksum by real-time calculation, and using the intermediate checksum to accumulate a second checksum by real-time calculation in a process of reading the remainder of the code stored in the second non-volatile memory.

[0069] An embedded system is a computer system implemented with software (or program code) embedded in hardware to perform specific functions. To verify the integrity of software code in embedded systems, checksums can be used when writing or reading code to memory.

[0070] The memory operating device according to the embodiment can be applied to embedded systems such as home appliances, automobiles, medical devices, communication systems, aviation and space systems, smart homes, and IoT devices.

Claims

1. A step of storing an intermediate checksum together with a part of the code in a first non-volatile memory; A step of storing a final checksum for the entire code divided and stored in the first non-volatile memory and the second non-volatile memory, together with the remainder of the code in the second non-volatile memory; and A memory operating method, comprising the steps of: reading the intermediate checksum stored in the first non-volatile memory, accumulating a first checksum by real-time calculation in the process of reading a part of the code stored in the first non-volatile memory, and accumulating a second checksum by real-time calculation using the intermediate checksum in the process of reading the remaining part of the code stored in the second non-volatile memory.

2. In paragraph 1, A memory operating method, wherein codes stored in the first non-volatile memory and the second non-volatile memory are read simultaneously through parallel processing, and the first checksum and the second checksum are accumulated through real-time calculation in parallel.

3. In paragraph 2, A memory operating method, wherein the second checksum is accumulated from the first checksum.

4. In paragraph 3, A step of comparing the intermediate checksum and the first checksum to verify the integrity of a portion of the code stored in the first non-volatile memory; and A memory operating method further comprising the step of comparing the final checksum with the second checksum to verify the integrity of the entire code stored in the first non-volatile memory and the second non-volatile memory.

5. In paragraph 4, A memory operating method, wherein the intermediate checksum and the first checksum are compared at the same time as the final checksum and the second checksum are compared.

6. In paragraph 1, A step in which the intermediate checksum is written after a part of the code is sequentially written to the first non-volatile memory; and further comprising a step of writing the final checksum after the remainder of the code is sequentially written to the second non-volatile memory; A memory operating method, wherein the first intermediate checksum is written to the first non-volatile memory as the intermediate checksum before the final checksum is written to the second non-volatile memory.

7. First non-volatile memory; Nth (N is a positive integer greater than or equal to 2) nonvolatile memory; and A central processing unit, a memory control unit, a communication interface, and a volatile memory connected to the first non-volatile memory and the Nth non-volatile memory via a bus, The above memory control unit, When the above N is 2, an intermediate checksum for a part of the code together with a part of the code is stored in the first non-volatile memory, and a final checksum for the entire code stored in the first non-volatile memory and the second non-volatile memory together with the remaining part of the code is stored in the second non-volatile memory, A memory operating device that reads the intermediate checksum from the first non-volatile memory, accumulates a first checksum through real-time calculation in the process of reading a part of the code stored in the first non-volatile memory, and accumulates a second checksum through real-time calculation in the process of reading the remaining part of the code stored in the second non-volatile memory.

8. In paragraph 7, The above memory control unit, A memory operating device that simultaneously reads codes stored in the first non-volatile memory and the second non-volatile memory through parallel processing, and accumulates the first checksum and the second checksum through real-time calculation.

9. In paragraph 7, A memory operating device, wherein the second checksum is accumulated from the first checksum.

10. In paragraph 9, The above memory control unit, Compare the intermediate checksum with the first checksum to verify the integrity of a portion of the code stored in the first non-volatile memory, A memory operating device that compares the final checksum and the second checksum to verify the integrity of the entire code stored in the first non-volatile memory and the second non-volatile memory.

11. In Article 10, The above memory control unit, A memory operating device that compares the intermediate checksum with the first checksum and compares the final checksum with the second checksum.

12. In paragraph 7, The above memory control unit, After sequentially storing a portion of the code in the first non-volatile memory, the intermediate checksum is stored, A memory operating device that stores the final checksum after sequentially storing the remaining portion of the code in the second non-volatile memory.

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