Chip antenna manufacturing method

Abstract

The present disclosure provides a technology relating to a chip antenna comprising a plurality of dielectric sheets stacked together, wherein a power supply line of a radiator is formed by stacking via holes formed through drilling, and thereby via holes having the same upper and lower diameters are formed, so that a reduction in the efficiency of power supply through the power supply line is prevented.

Description

Chip antenna manufacturing method

[0001] The present invention relates to a technology for manufacturing a chip antenna in which a plurality of dielectric sheets having conductors formed thereon are laminated.

[0002] Typically, chip antennas are manufactured by laminating multiple dielectric sheets having conductive patterns formed thereon. The conductive patterns formed on the dielectric sheets constitute a radiator, a feed line, a signal line, etc.

[0003] However, if the alignment of the chip antenna is misaligned during the process of stacking the dielectric sheets, problems such as disconnection of the connection between the conductor patterns, reduction of the connection area, change in the resonant frequency, or reduction in the power supply efficiency may occur.

[0004] The matters described in the background art above are intended to help understand the background of the invention and may include matters that are not publicly disclosed prior art.

[0005] The present invention has been proposed in consideration of the above circumstances, and its purpose is to provide a method for manufacturing a chip antenna by stacking via holes formed through drilling during the manufacturing of a chip antenna equipped with a radiator to form a power supply line of the radiator.

[0006] In order to achieve the above object, a method for manufacturing a chip antenna according to an embodiment of the present invention includes the steps of preparing a first sheet in which a radiator connected to a metallized via hole is formed, the step of preparing a second sheet in which a metallized via hole for power supply to the radiator is formed, the step of laminating the first sheet and the second sheet, and the step of firing a laminate in which the first sheet and the second sheet are laminated, wherein in the step of preparing the first sheet and the step of preparing the second sheet, a via hole is formed in the first sheet and the second sheet through drilling.

[0007] The step of preparing the first sheet may include the steps of preparing a first green sheet of a dielectric material, the step of forming a first via hole in the first green sheet through drilling, the step of forming a metallized first via hole by filling the first via hole with a conductor, and the step of forming a first conductive layer as a radiator on an upper surface of the first green sheet. In the step of forming the first via hole, the first via hole penetrating the center point of the first green sheet may be formed through drilling, and in the step of forming the first conductive layer, the first conductive layer may be formed to overlap the metallized first via hole.

[0008] The step of preparing the second sheet may include the steps of preparing a second green sheet of a dielectric material, the step of forming a second via hole in the second green sheet through drilling, the step of forming a metallized second via hole by filling the second via hole with a conductor, and the step of forming a second conductive layer on an upper surface of the second green sheet. The second green sheet prepared in the step of preparing the second green sheet may be of the same dielectric material as the first green sheet of the first sheet, and in the step of forming the second via hole, the second via hole may be formed through drilling to penetrate the center point of the second green sheet, and in the step of forming the second conductive layer, the second conductive layer may be formed to overlap the metallized second via hole.

[0009] In the laminating step, a plurality of second sheets are laminated on the lower side of the first sheet, and the metallized via holes of the first sheet and the metallized via holes of the second sheets are laminated so as to overlap each other, thereby forming a power supply line of a radiator in which the plurality of metallized via holes are connected.

[0010] A method for manufacturing a chip antenna according to an embodiment of the present invention further includes a step of preparing a third sheet of dielectric material prior to the laminating step, and in the laminating step, the third sheet can be laminated on top of the first sheet on which the radiator is formed.

[0011] The metallized via holes are formed to have the same upper and lower diameters within a tolerance range.

[0012] According to the present invention, a method for manufacturing a chip antenna can form a feed line of a radiator by forming a via hole in a sheet through drilling, thereby minimizing the out-of-roundness of the via hole, thereby forming a via hole with almost the same upper diameter and lower diameter.

[0013] In addition, the chip antenna manufacturing method has the effect of preventing a decrease in the power supply efficiency of the power supply line by securing a certain area for connecting via holes even if the alignment of the sheets is partially misaligned when stacking multiple sheets.

[0014] Figure 1 is a flowchart illustrating a method for manufacturing a chip antenna according to an embodiment of the present invention.

[0015] Figures 2 and 3 are flowcharts for explaining the first sheet preparation step of Figure 1.

[0016] FIG. 4 is a drawing for explaining a first sheet prepared through the step of preparing the first sheet of FIG. 1.

[0017] Figures 5 and 6 are flowcharts for explaining the second sheet preparation step of Figure 1.

[0018] FIG. 7 is a drawing for explaining a second sheet prepared through the step of preparing a plurality of second sheets of FIG. 1.

[0019] FIG. 8 is a drawing for explaining a third sheet prepared through the step of preparing the third sheet of FIG. 1.

[0020] Fig. 9 is a drawing for explaining the sheet lamination step of Fig. 1.

[0021] Fig. 10 is a cross-sectional view illustrating a chip antenna manufactured through the firing step of Fig. 1.

[0022] Fig. 11 is a drawing for explaining the via hole formation step of Figs. 2 and 5.

[0023] Figure 12 is a drawing for comparing and explaining the cross-section of a via hole according to a via hole processing method.

[0024] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0025] These examples are provided to more fully illustrate the present invention to those skilled in the art. The following examples may be modified in various ways, and the scope of the present invention is not limited to the examples described below. Rather, these examples are provided to further faithfully and completely convey the spirit of the present invention.

[0026] The terminology used herein is used to describe specific embodiments and is not intended to limit the present invention. In addition, the singular form in this specification may include the plural form unless the context clearly indicates otherwise. It should be understood that the terms "comprise," "include," and "have" in this application are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof of the invention, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0027] In the description of the embodiments, when each layer (film), region, pattern or structure is described as being formed "on" or "under" the substrate, each layer (film), region, pad or pattern, "on" and "under" include both being formed "directly" or "indirectly" through another layer. In addition, the reference for above or below each layer is, in principle, based on the drawing.

[0028] The drawings are intended solely to facilitate understanding of the invention and should not be construed as limiting the scope of the invention. Furthermore, relative thicknesses, lengths, and sizes in the drawings may be exaggerated for convenience and clarity of explanation.

[0029] A chip antenna manufacturing method according to an embodiment of the present invention is configured by stacking dielectric sheets to manufacture a chip antenna of a set frequency band (e.g., UWB). That is, the chip antenna manufacturing method manufactures a chip antenna of a set frequency band by stacking a dielectric sheet on which a conductor, which is a radiator, is formed, a metallized via hole forming a feed line, and a plurality of dielectric sheets on which a conductor is formed.

[0030] Referring to FIG. 1, a chip antenna manufacturing method according to an embodiment of the present invention comprises a first sheet preparation step (S100), a second sheet preparation step (S200), a third sheet preparation step (S300), a sheet lamination step (S400), and a firing step (S500).

[0031] In the first sheet preparation step (S100), a first green sheet (110) having a first conductive layer (140) formed thereon, which acts as a radiator of a chip antenna (1000), is prepared as the first sheet (100). At this time, in the first sheet preparation step (S100), a first green sheet (110) having a metallized via hole connected to the conductive layer formed thereon is prepared as the first sheet (100).

[0032] For example, referring to FIGS. 2 and 3, the first sheet preparation step (S100) includes a first green sheet preparation step (S110), a first via hole formation step (S120), a first via hole filling step (S130), and a first conductor layer formation step (S140).

[0033] In the first green sheet preparation step (S110), a first green sheet (110) made of a dielectric material is prepared. As an example, in the first green sheet preparation step (S110), a ceramic green sheet mainly used in the low-temperature co-firing (LTCC) method is prepared as the first green sheet (110).

[0034] In the first via hole forming step (S120), a first via hole (120) is formed in the first green sheet (110). In the first via hole forming step (S120), a first via hole (120) penetrating the center point of the first green sheet (110) is formed. In the first via hole forming step (S120), a first via hole (120) penetrating vertically the center point of the first green sheet (110) is formed through drilling.

[0035] In the first via hole filling step (S130), a metallized first via hole (130) is formed in the first green sheet (110). In the first via hole filling step (S130), the first via hole (120) formed in the first green sheet (110) is filled with a conductor. In the first via hole filling step (S130), the first via hole (120) formed in the first green sheet (110) is filled with a conductor to form a metallized first via hole (130).

[0036] In the first conductor layer forming step (S140), a first conductor layer (140) that acts as a radiator is formed on the upper surface of the first green sheet (110). In the first conductor layer forming step (S140), the first conductor layer (140) is formed to overlap with the metallized first via hole (130) formed in the first green sheet (110). As an example, in the first conductor layer forming step (S140), the first conductor layer (140) is formed by printing a conductor on the upper surface of the first green sheet (110).

[0037] Referring to FIG. 4, in the first sheet preparation step (S100), a plate-shaped first conductor layer (140) is formed on a first green sheet (110), and a first sheet (100) directly connected to the first conductor layer (140) and the metallized first via hole (130) is prepared.

[0038] In the second sheet preparation step (S200), a second green sheet (210) having a metallized via hole formed therein, which constitutes a feed line (500) of a chip antenna (1000), is prepared as the second sheet (200). In the second sheet preparation step (S200), a second green sheet (210) having a second conductor layer (240) connected to the metallized via hole formed on one surface is prepared as the second sheet (200). Here, as an example, in the second sheet preparation step (S200), a second sheet (200) composed of a second green sheet (210) of the same material as the first green sheet (110) is prepared.

[0039] For example, referring to FIGS. 5 and 6, the second sheet preparation step (S200) includes a second green sheet preparation step (S210), a second via hole formation step (S220), a second via hole filling step (S230), and a second conductor layer formation step (S240).

[0040] In the second green sheet preparation step (S210), a plurality of second green sheets (210) made of a dielectric material are prepared. As an example, in the second green sheet preparation step (S210), a ceramic green sheet made of the same material as the first green sheet (110) is prepared as the second green sheet (210).

[0041] In the second via hole forming step (S220), a second via hole (220) is formed in the second green sheet (210). In the second via hole forming step (S220), a second via hole (220) penetrating the center point of the second green sheet (210) is formed. In the second via hole forming step (S220), a second via hole (220) penetrating vertically the center point of the second green sheet (210) is formed through drilling.

[0042] In the second via hole filling step (S230), a metallized second via hole (230) is formed in the second green sheet (210). In the second via hole filling step (S230), the second via hole (220) formed in the second green sheet (210) is filled with a conductor. In the second via hole filling step (S230), the second via hole (220) formed in the second green sheet (210) is filled with a conductor to form a metallized second via hole (230).

[0043] In the second conductor layer forming step (S240), a second conductor layer (240) that assists in connecting the metallized via holes in the firing step (S600) is formed on the upper surface of the second green sheet (210). In the second conductor layer forming step (S240), a second conductor layer (240) having a larger area than the first via hole (120) and the second via hole (220) is formed. In the second conductor layer forming step (S240), the second conductor layer (240) is formed to overlap the metallized second via hole (230) formed in the second green sheet (210). As an example, in the second conductor layer forming step (S240), a conductor is printed on the upper surface of the second green sheet (210) to form the second conductor layer (240).

[0044] Referring to FIG. 7, in the second sheet preparation step (S200), a plate-shaped second conductor layer (240) is formed on the second green sheet (210), and a second sheet (200) directly connected to the second conductor layer (240) and the metallized second via hole (230) is prepared.

[0045] In the third sheet preparation step (S300), a third sheet (300) forming a protective layer is prepared. In the third sheet preparation step (S300), a third sheet (300) is prepared that is placed on the upper surface of the first sheet (100) and protects the first conductor layer (140) (i.e., radiator) formed on the first sheet (100).

[0046] Referring to FIG. 8, in the third sheet preparation step (S300), as an example, a ceramic green sheet having the same plate shape as the first green sheet (110) and the second green sheet (210) is prepared as the third sheet (300).

[0047] In the sheet stacking step (S400), a first sheet (100), a plurality of second sheets (200) and a third sheet (300) are stacked. In the sheet stacking step (S400), the first sheet (100), a plurality of second sheets (200) and a third sheet (300) are stacked so that the third sheet (300) is placed on the upper surface of the first sheet (100) and the plurality of second sheets (200) are placed on the lower surface of the first sheet (100).

[0048] For example, referring to FIG. 9, in the sheet lamination step (S400), a third sheet (300) is laminated on the upper surface of the first sheet (100) on which the first conductor layer (140) is formed. In the sheet lamination step (S400), a plurality of second sheets (200) are laminated on the lower surface of the first sheet (100). In the sheet lamination step (S400), the first sheet (100) and the plurality of second sheets (200) are laminated so that the first via holes (120) formed in the first sheet (100) and the plurality of second via holes (220) formed in the plurality of second sheets (200) are vertically aligned and overlap each other.

[0049] In the firing step (S500), a laminate (400) in which a first sheet (100), a plurality of first sheets (200) and a third sheet (300) are laminated is fired. In the firing step (S500), the laminate (400) is fired through a low-temperature firing process. As an example, in the firing step (S500), the first sheet (100) to the third sheet (300) made of a ceramic material are fired at a low temperature to manufacture a low-temperature simultaneous firing ceramic chip antenna (1000).

[0050] Referring to Fig. 10, the first sheet (100) to the third sheet (300) form a laminate (400) made of a dielectric material through the above-described chip antenna manufacturing method. At this time, the first conductive layer (140) is arranged inside the laminate (400) to form a radiator that resonates in a set frequency band, and the metallized first via hole (130) and the plurality of metallized second via holes (220) are connected through a firing step (S500) to form a power supply line (500) that supplies power to the first conductive layer (140).

[0051] The alignment of the first via hole (120) and the plurality of second via holes (220) may be misaligned during the process of stacking the first sheet (100) and the plurality of second sheets (200). If the alignment of the first via hole (120) and the second via hole (220) is misaligned, the connection area between the via holes is reduced, thereby lowering the power supply efficiency of the power supply line (500).

[0052] Accordingly, since the second conductor layer (240) is formed with a larger area than the first via hole (120) and the second via hole (220), even if the alignment is partially misaligned, the contact area between the first via hole (120) and the plurality of second via holes (220) can be maintained at a certain level or more, thereby preventing the power supply efficiency of the power supply line (500) from being lowered.

[0053] In a method for manufacturing a chip antenna according to an embodiment of the present invention, via holes forming a power supply line (500) of a radiator are formed by drilling.

[0054] Referring to Fig. 11, in the first via hole formation step (S120) and the second via hole formation step (S220), a via hole is formed in the green sheet through drilling. The drill is placed on top of the green sheet, rotates, and slowly descends to form a via hole penetrating the green sheet.

[0055] In the first via hole forming step (S120) and the second via hole forming step (S220), a via hole is formed through drilling, so a via hole without a taper can be formed.

[0056] In addition, since the via hole is formed through drilling in the first via hole forming step (S120) and the second via hole forming step (S220), the out-of-roundness of the via hole can be minimized, so that a via hole with an upper diameter and a lower diameter that are almost the same can be formed.

[0057] Accordingly, the chip antenna manufacturing method according to an embodiment of the present invention can secure a certain area or more for connecting via holes even if the alignment of the sheets is partially misaligned when stacking a plurality of sheets, thereby preventing a decrease in the power supply efficiency of the power supply line (500).

[0058] Meanwhile, the processing methods mainly used to form via holes include laser processing, punching processing, and drilling processing.

[0059] Referring to Fig. 12, a via hole formed through laser processing has a difference between the upper diameter (R1) and the lower diameter (R1') because the circularity of the via hole is large.

[0060] A via hole formed through punching processing has a difference in the upper diameter (R2) and lower diameter (R2') because a taper is formed at the upper and / or lower portion of the via hole during the punching process.

[0061] Due to this, when a power supply line (500) is formed through a via hole formed through laser processing or punching processing, the area where the via holes are connected cannot be secured above a certain level, so the power supply efficiency of the power supply line (500) is reduced.

[0062] In contrast, via holes formed through drilling have a small circularity, so the upper diameter (R3) and the lower diameter (R3') are formed to be almost identical. Accordingly, the chip antenna manufacturing method according to an embodiment of the present invention forms a via hole in a green sheet through drilling.

[0063] The above description is merely an illustrative illustration of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A step of preparing a first sheet having a radiator formed thereon and connected to a metallized via hole; A step of preparing a second sheet having a metallized via hole formed therein for powering the above-mentioned radiator; A step of laminating the first sheet and the second sheet; and Comprising a step of firing a laminate in which the first sheet and the second sheet are laminated, A chip antenna manufacturing method in which, in the step of preparing the first sheet and the step of preparing the second sheet, via holes are formed in the first sheet and the second sheet through drilling.

2. In paragraph 1, The step of preparing the above first sheet is: A step of preparing a first green sheet of genetic material; A step of forming a first via hole in the first green sheet through drilling; A step of forming a metallized first via hole by filling a conductor into the first via hole; and A method for manufacturing a chip antenna, comprising the step of forming a first conductor layer, which is the radiator, on the upper surface of the first green sheet.

3. In paragraph 2, A chip antenna manufacturing method in which a first via hole is formed through drilling in the step of forming the first via hole, the first via hole penetrating the center point of the first green sheet.

4. In paragraph 2, A chip antenna manufacturing method, wherein in the step of forming the first conductor layer, the first conductor layer is formed to overlap with the metallized first via hole.

5. In paragraph 1, The step of preparing the second sheet is as follows: Step of preparing a second green sheet of genetic material; A step of forming a second via hole in the second green sheet through drilling; A step of forming a metallized second via hole by filling a conductor into the second via hole; and A method for manufacturing a chip antenna, comprising the step of forming a second conductor layer on the upper surface of the second green sheet.

6. In paragraph 5, A method for manufacturing a chip antenna, wherein the second green sheet prepared in the step of preparing the second green sheet is made of the same dielectric material as the first green sheet of the first sheet.

7. In paragraph 6, A chip antenna manufacturing method in which a second via hole is formed through drilling in the step of forming the second via hole, the second via hole penetrating the center point of the second green sheet.

8. In paragraph 6, A chip antenna manufacturing method, wherein in the step of forming the second conductor layer, the second conductor layer is formed to overlap with the metallized second via hole.

9. In paragraph 1, In the above laminating step, A method for manufacturing a chip antenna, wherein a plurality of second sheets are laminated on the lower side of the first sheet, such that the metallized via holes of the first sheet and the metallized via holes of the second sheets overlap each other, thereby forming a feed line of the radiator in which the plurality of metallized via holes are connected.

10. In paragraph 1, Further comprising a step of preparing a third sheet of dielectric material prior to the above laminating step, A chip antenna manufacturing method in which, in the above laminating step, the third sheet is laminated on top of the first sheet on which the radiator is formed.

11. In paragraph 1, A method for manufacturing a chip antenna, wherein the above metallized via hole has the same upper diameter and lower diameter within a tolerance range.

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