Display panel

Abstract

The present application provides a display panel. A first active layer comprises a first channel and a first drain ohmic contact portion; an isolation portion covers the first channel; a first drain comprises a transparent first part and a transparent second part, the first part is arranged on the surface of the side of the isolation portion away from the first active layer, and the second part is arranged on the first drain ohmic contact portion; a pixel electrode is electrically connected to the first part through a first via hole formed in the side of the first part away from the isolation portion.

Description

A display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] With the advancement of display technology, consumer electronics products that rely on display panels, such as mobile phones, televisions, personal digital assistants (PDAs), digital cameras, laptops, desktop computers, virtual reality (VR) displays, and augmented reality (AR) displays, have emerged in an endless stream. The rise of the "metaverse" concept has also attracted widespread consumer attention for VR / AR displays, demonstrating their broad market potential.

[0003] VR / AR display devices are near-eye display devices, which have high requirements for the aperture ratio and display quality of the display panel, and need to minimize manufacturing costs. The display panel includes pixel electrodes and thin-film transistors (TFTs) electrically connected to the pixel electrodes. The TFTs are switching elements that control the pixel electrodes to obtain pixel voltage. The connection method between the TFTs and the pixel electrodes and the structure of the TFTs directly affect the aperture ratio, display quality, and manufacturing costs of the display panel.

[0004] Therefore, how to set the structure of the thin film transistor electrically connected to the pixel electrode, and the connection method between the thin film transistor and the pixel electrode, so that the display panel has a high aperture ratio, high display quality and low production cost, is a problem that technical personnel in this field urgently need to solve. SUMMARY OF THE INVENTION

[0005] The present application provides a display panel that can effectively solve the problem of display panels failing to balance display quality and production costs while achieving a high aperture ratio.

[0006] The present application provides a display panel, which has a display area, and includes: a substrate; a first thin film transistor, arranged on one side of the substrate and located in the display area; a pixel electrode, arranged on a side of the first thin film transistor away from the substrate and located in the display area; wherein the first thin film transistor includes: a first active layer, including a first channel and a first drain ohmic contact portion arranged on one side of the first channel; an isolation portion, arranged on a surface of the first channel away from the substrate and covering the first channel; a first drain, including a transparent first portion and a transparent second portion, the first portion being arranged on a surface of the isolation portion away from the first active layer, and the second portion being arranged on a surface of the first drain ohmic contact portion away from the substrate; wherein the pixel electrode is electrically connected to the first portion through a first via hole arranged on a side of the first portion away from the isolation portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] FIG1 is a schematic plan view of a display panel in the related art.

[0009] FIG. 2 is a schematic cross-sectional view of a display panel in the related art.

[0010] FIG3 is a plan view schematically illustrating a display panel provided in some embodiments of the present application.

[0011] FIG4 is a schematic cross-sectional view of a display panel provided in some embodiments of the present application.

[0012] FIG5 a is a schematic cross-sectional view of an isolation portion provided by some embodiments of the present application when the angle formed between the sidewall of the isolation portion and the bottom surface of the isolation portion is 90°.

[0013] FIG5 b is a schematic cross-sectional view of the isolation portion provided by some embodiments of the present application when the angle formed between the sidewall of the isolation portion and the bottom surface of the isolation portion is 30°.

[0014] FIG6 a is a schematic structural diagram of a display panel corresponding to step S01 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0015] FIG6 b is a schematic structural diagram of a display panel corresponding to step S02 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0016] FIG6 c is a schematic structural diagram of a display panel corresponding to step S03 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0017] FIG6 d is a schematic structural diagram of a display panel corresponding to step S04 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0018] FIG6 e is a schematic structural diagram of a display panel corresponding to step S05 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0019] FIG6 f is a schematic structural diagram of a display panel corresponding to step S06 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0020] FIG6 g is a schematic structural diagram of a display panel corresponding to step S07 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0021] FIG6h is a schematic structural diagram of a display panel corresponding to step S08 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0022] FIG6i is a schematic structural diagram of a display panel corresponding to step S09 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0023] FIG6 j is a schematic structural diagram of a display panel corresponding to step S10 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0024] FIG6 k is a schematic structural diagram of a display panel corresponding to step S11 in the method for manufacturing a display panel provided in an embodiment of the present application.

[0025] Description of reference numerals:

[0026] Display area AA'; non-display area NAA'; substrate 10'; thin film transistor 20'; active layer 21'; channel 211'; drain ohmic contact 212'; first gate 22'; second gate 23'; source 24'; drain 25'; pixel electrode 30'; first via hole 40'; second via hole 50';

[0027] Display area AA; non-display area NAA; substrate 10; first thin film transistor 20; first active layer 21; first channel 211; first drain ohmic contact 212; first source ohmic contact 213; isolation portion 22; sidewall 221 of isolation portion; bottom surface 222 of isolation portion; edge 223 of isolation portion; first drain 23; first portion 231; edge 2311 of first portion; second portion 232; first source 24; first gate 25; image Element electrode 30; first via hole 40; first gate insulating layer 50; first sub-insulating layer 51; second sub-insulating layer 52; second thin film transistor 60; second active layer 61; second gate 62; second source electrode 63; second drain electrode 64; first source conductive portion 70; second via hole 80; second gate insulating layer 90; composite functional layer 100; interlayer dielectric layer 110; first planarizing layer 120; passivation layer 130; second planarizing layer 140; common electrode 150; Modes for Carrying Out the Invention

[0028] The present application provides a display panel, which has a display area, and includes: a substrate; a first thin film transistor, arranged on one side of the substrate and located in the display area; a pixel electrode, arranged on a side of the first thin film transistor away from the substrate and located in the display area; wherein the first thin film transistor includes: a first active layer, including a first channel and a first drain ohmic contact portion arranged on one side of the first channel; an isolation portion, arranged on a surface of the first channel away from the substrate and covering the first channel; a first drain, including a transparent first portion and a transparent second portion, the first portion being arranged on a surface of the isolation portion away from the first active layer, and the second portion being arranged on a surface of the first drain ohmic contact portion away from the substrate; wherein the pixel electrode is electrically connected to the first portion through a first via hole arranged on a side of the first portion away from the isolation portion.

[0029] Optionally, the second portion covers the first drain ohmic contact.

[0030] Optionally, the second portion covers the side wall of the isolation portion, and the angle formed between the side wall of the isolation portion and the bottom surface of the isolation portion is a, 30°≤a≤90°.

[0031] Optionally, in a direction in which the isolation portion moves away from the second portion, an edge of the isolation portion protrudes beyond an edge of the first portion.

[0032] Optionally, the first active layer also includes a first source ohmic contact portion arranged on the other side of the first channel, wherein the first thin film transistor also includes a first source electrode formed integrally with the first drain electrode, and the first source electrode is arranged on the surface of the side of the first source ohmic contact portion facing away from the substrate and covers the first source ohmic contact portion.

[0033] Optionally, the display panel also includes a first gate insulating layer, which is arranged on the side of the first active layer away from the isolation portion, wherein the first gate insulating layer includes a first sub-insulating layer, the first sub-insulating layer is in contact with the first active layer, and the first sub-insulating layer is made of the same material as the isolation portion.

[0034] Optionally, the display panel also includes a second thin film transistor, which is arranged on the side of the substrate facing the first thin film transistor, wherein the second thin film transistor includes a second active layer, which is arranged on the side of the first active layer away from the isolation portion, and the second active layer includes a second channel, and the material of the second channel is different from the material of the first channel.

[0035] Optionally, the first gate insulating layer also includes a second sub-insulating layer, which is arranged on the side of the first sub-insulating layer away from the first active layer, and the second sub-insulating layer and the first sub-insulating layer are made of different materials; the first thin-film transistor includes a first gate, which is arranged on the side of the second sub-insulating layer away from the first sub-insulating layer; the second thin-film transistor also includes a second gate, which is arranged on the side of the second active layer away from the substrate; wherein the first gate and the second gate are arranged in the same layer, and the first gate and the second gate are respectively in contact with the second sub-insulating layer.

[0036] Optionally, the display panel also includes a second gate insulating layer, which is arranged on the side of the second active layer facing the second gate, wherein the first gate insulating layer arranged between the first active layer and the first gate has a first thickness, and the second gate insulating layer arranged between the second active layer and the second gate has a second thickness, and the ratio of the first thickness to the second thickness is less than or equal to 3.

[0037] Optionally, the second thin film transistor further includes a second source and a second drain, and the first thin film transistor further includes a first source conductive portion, the first source conductive portion is arranged in the same layer as the second source and the second drain, and the first source conductive portion is electrically connected to the first source through a second via.

[0038] The present application provides a display panel having a display area, the display panel comprising: a substrate; a first thin film transistor disposed on one side of the substrate and located in the display area; a pixel electrode disposed on a side of the first thin film transistor facing away from the substrate and located in the display area; the first thin film transistor comprising a first active layer, an isolation portion, and a first drain electrode, wherein the first active layer comprises a first channel and a first drain ohmic contact portion disposed on one side of the first channel; the isolation portion is disposed on a surface of the first channel facing away from the substrate and covers the first channel; the first drain electrode comprises a transparent first portion and a transparent second portion, the first portion being disposed on a surface of the isolation portion facing away from the first active layer, and the second portion being disposed on a surface of the first drain ohmic contact portion facing away from the substrate; wherein the pixel electrode is electrically connected to the first portion via a first via hole disposed on a side of the first portion facing away from the isolation portion. The display panel provided by the present application can achieve a high aperture ratio while improving the display quality of the display panel and reducing the production cost of the display panel.

[0039] The specific implementation of the above technical solution is described in detail below with reference to the accompanying drawings.

[0040] FIG1 is a schematic plan view of a display panel in the related art; FIG2 is a schematic cross-sectional view of a display panel in the related art. 1 and 2 , a display panel 100′ in the related art has a display area AA′ and a non-display area NAA′, the display panel 100′ includes a substrate 10′, a thin film transistor 20′ arranged on one side of the substrate 10′, and a pixel electrode 30′ arranged on a side of the thin film transistor 20′ away from the substrate 10′, the thin film transistor 20′ and the pixel electrode 30′ are both located in the display area AA′ of the display panel 100′, wherein the thin film transistor 20′ includes an active layer 21′, a first gate 22′, a second gate 23′, a source 24′ and a drain 25′, the active layer 21′ includes a channel 211′ and a drain ohmic contact portion 212′ located on one side of the channel 211′, the drain 25′ is overlapped with the drain ohmic contact portion 212′ through a first via hole 40′, and the pixel electrode 30′ is overlapped with the drain 25′ through a second via hole 50′. The drain electrode 25' is made of a transparent conductive material, so that the area where the drain electrode 25' overlaps with the drain ohmic contact portion 212' has high light transmittance, which is used to perform the display function, thereby improving the aperture ratio of the display panel 100'. However, due to the presence of the first via hole 40' in the area where the drain electrode 25' overlaps with the drain ohmic contact portion 212', the area where the first via hole 40' is located is prone to uneven display when performing the display function, which reduces the display quality of the display panel 100'. In addition, the first via hole 40' and the second via hole 50' increase the number of process steps for the display panel 100', thereby increasing the production cost of the display panel 100'.

[0041] In order to enable a display panel to achieve a high aperture ratio while improving display quality and reducing production costs, the present application provides a display panel and a method for preparing the same.

[0042] FIG3 is a planar schematic diagram of a display panel provided by some embodiments of the present application; FIG4 is a cross-sectional schematic diagram of a display panel provided by some embodiments of the present application. Referring to FIG3 and FIG4 , in a first aspect, an embodiment of the present application provides a display panel, wherein the display panel has a display area AA and a non-display area NAA, wherein the non-display area NAA surrounds the display area AA, and the display area AA is arrayed with a plurality of display pixels. The display panel includes a substrate 10, a first thin film transistor 20, and a pixel electrode 30, wherein the first thin film transistor 20 is arranged on one side of the substrate 10 and is located in the display area AA; the pixel electrode 30 is arranged on the side of the first thin film transistor 20 facing away from the substrate 10 and is located in the display area AA.

[0043] In some embodiments of the present application, the first thin film transistor 20 includes a first active layer 21, an isolation portion 22 and a first drain 23, wherein the first active layer 21 includes a first channel 211 and a first drain ohmic contact portion 212 arranged on one side of the first channel 211; the isolation portion 22 is arranged on the surface of the first channel 211 away from the substrate 10 and covers the first channel 211; the first drain 23 includes a transparent first portion 231 and a transparent second portion 232, the first portion 231 is arranged on the surface of the isolation portion 22 away from the first active layer 21, and the second portion 232 is arranged on the surface of the first drain ohmic contact portion 212 away from the substrate 10; wherein the pixel electrode 30 is electrically connected to the first portion 231 through a first via 40 arranged on the side of the first portion 231 away from the isolation portion 22.

[0044] In the display panel provided in the present application, since the second portion 232 arranged on the surface of the first drain ohmic contact portion 212 on the side away from the substrate 10 is transparent, the area where the first drain ohmic contact portion 212 is located can have high light transmittance for performing the display function, thereby improving the aperture ratio of the display panel.

[0045] Moreover, since the pixel electrode 30 is electrically connected to the first part 231 through the first via 40 arranged on the side of the first part 231 away from the isolation part 22, and the first part 231 is arranged on the isolation part 22 corresponding to the first channel 211, that is, in the direction perpendicular to the substrate 10, the first via 40 and the first drain ohmic contact part 212 are staggered, the first via 40 will not affect the display function of the area where the first drain ohmic contact part 212 is located.

[0046] In addition, since the first part 231 is arranged on the surface of the isolation part 22 on the side away from the first active layer 21, and the second part 232 is arranged on the surface of the first drain ohmic contact part 212 on the side away from the substrate 10, that is, in the direction perpendicular to the substrate 10, the first part 231 and the second part 232 are separated by only one isolation part 22. Therefore, the first part 231 and the second part 232 do not need to be connected by a via structure when they are formed as one piece, so that there is no need to set a via structure above the second part 232, so that the area where the first drain ohmic contact part 212 is located has a consistent display effect with other display areas AA, thereby improving the display uniformity of the display panel and improving the display quality of the display panel.

[0047] In some embodiments of the present application, a vertical projection of the first via hole 40 on the first active layer 21 overlaps with the first channel 211 .

[0048] In the display panel provided by the present application, a non-transparent gate is often provided in the channel region of the thin film transistor, that is, the display panel does not have a display function in the channel region of the thin film transistor. The present application overlaps the vertical projection of the first via hole 40 on the first active layer 21 with the first channel 211, so that the first via hole 40 does not occupy the area with display function in the display area AA, thereby further improving the aperture ratio of the display panel.

[0049] In some embodiments of the present application, the first thin-film transistor 20 is a metal oxide thin-film transistor, the first channel 211 is made of a metal oxide semiconductor, and the first drain ohmic contact 212 is a transparent conductive structure formed by converting the metal oxide semiconductor material into a conductive material. This enables the display panel to have the advantages of low leakage current, low refresh rate, and high light transmittance.

[0050] In some embodiments of the present application, the second portion 232 covers the drain ohmic contact portion. Optionally, an edge of the second portion 232 protrudes from an edge of the drain ohmic contact portion by 0.5-1 micrometers.

[0051] In the display panel provided in the present application, since the second part 232 covers the first drain ohmic contact portion 212, the second part 232 can protect the first drain ohmic contact portion 212 to avoid damage to the first drain ohmic contact portion 212 during the patterning process of the film layer where the first drain 23 is located.

[0052] In some embodiments of the present application, the second portion 232 covers the sidewall 221 of the isolation portion 22 , and an angle a formed between the sidewall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is 30°≤a≤90°.

[0053] In the display panel provided herein, the end of the second portion 232 adjacent to the first portion 231 covers the sidewall 221 of the isolation portion 22 and is connected to the first portion 231. Therefore, a step structure corresponding to the shape of the sidewall 221 of the isolation portion 22 is formed at the junction of the first portion 231 and the second portion 232. If the angle between the sidewall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is too large, such as an obtuse angle, an undercut structure may be formed between the sidewall 221 of the isolation portion 22 and the first active layer 21, significantly increasing the risk of fracture at the junction of the first portion 231 and the second portion 232. If the angle between the sidewall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is too small, such as less than 30°, the area of ​​the top surface of the isolation portion 22 may be reduced, thereby reducing the area of ​​the first portion 231 and affecting the electrical connection stability between the first drain electrode 23 and the pixel electrode 30. The present application controls the angle between the side wall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 within the range of 30° to 90°, thereby reducing the risk of fracture at the junction of the first portion 231 and the second portion 232, while allowing the top surface of the isolation portion 22 and the first portion 231 to have a larger area, thereby improving the electrical connection stability between the first drain 23 and the pixel electrode 30 and reducing the design difficulty of the first via 40.

[0054] FIG5a is a schematic cross-sectional view of an isolation portion provided in some embodiments of the present application, wherein the angle formed between the sidewall of the isolation portion and the bottom surface of the isolation portion is 90°. As shown in FIG4 and FIG5a , the angle formed between the sidewall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is 90°. This can reduce the risk of fracture at the junction of the first portion 231 and the second portion 232 and the area of ​​the bottom surface of the isolation portion 22 while maximizing the area of ​​the top surface of the isolation portion 22 and the area of ​​the first portion 231, thereby reducing the design difficulty of the first via 40.

[0055] FIG5 b is a schematic cross-sectional view of an isolation portion provided in some embodiments of the present application, wherein the angle formed between the sidewall of the isolation portion and the bottom surface of the isolation portion is 30°. As shown in FIG4 and FIG5 b , the angle formed between the sidewall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is 30°. This can minimize the risk of fracture at the junction of the first portion 231 and the second portion 232 while taking into account the area requirements of the top surface of the isolation portion 22, the area requirements of the first portion 231, and the electrical connection stability between the first drain 23 and the pixel electrode 30, thereby improving the stability of the electrical connection between the first drain 23 and the pixel electrode 30 and the first drain ohmic contact 212.

[0056] In some embodiments of the present application, in the direction in which the isolation portion 22 is away from the second portion 232, the edge 223 of the isolation portion 22 protrudes beyond the edge 2311 of the first portion 231. Optionally, the edge 223 of the isolation portion 22 protrudes beyond the edge 23111 of the first portion 231 by 2 micrometers.

[0057] In the display panel provided in the present application, since the edge 223 of the isolation portion 22 protrudes from the edge 2311 of the first portion 231 in the direction in which the isolation portion 22 moves away from the second portion 232, it is possible to ensure that the first portion 231 does not go beyond the edge 223 of the isolation portion 22, thereby avoiding short circuit between the first portion 231 and other structures (such as the first source 24 of the first thin film transistor 20), thereby improving the stability of the first thin film transistor 20.

[0058] In some embodiments of the present application, the first active layer 21 further includes a first source ohmic contact 213 disposed on the other side of the first channel 211, wherein the first thin film transistor 20 further includes a first source electrode 24 integrally formed with the first drain electrode 23, and the first source electrode 24 is disposed on a surface of the first source ohmic contact 213 facing away from the substrate 10, and covers the first source ohmic contact 213. Optionally, an edge of the first source electrode 24 protrudes from an edge of the first source ohmic contact 213 by 0.5-1 micrometers.

[0059] In the display panel provided by the present application, since the first source electrode 24 and the first drain electrode 23 are integrally formed, the production process of the first thin-film transistor 20 can be simplified. Furthermore, since the first source electrode 24 is disposed on the surface of the first source ohmic contact portion 213 facing away from the substrate 10 and covers the first source ohmic contact portion 213, the first source electrode 24 can protect the first source ohmic contact portion 213, thereby preventing damage to the first source ohmic contact portion 213 during the patterning process of the film layer where the first source electrode 24 is located.

[0060] In some embodiments of the present application, the display panel also includes a first gate insulating layer 50, which is arranged on the side of the first active layer 21 away from the isolation portion 22, wherein the first gate insulating layer 50 includes a first sub-insulating layer 51, the first sub-insulating layer 51 is in contact with the first active layer 21, and the first sub-insulating layer 51 and the isolation portion 22 are made of the same material.

[0061] In the display panel provided in the present application, the isolation portion 22 covering the first channel 211 can protect the first channel 211. Since the first sub-insulating layer 51 is in contact with the first active layer 21, and the first sub-insulating layer 51 and the isolation portion 22 are made of the same material, the first gate insulating layer 50 can provide good protection for the first channel 211 while reducing material costs.

[0062] Optionally, the first insulating layer and the isolation portion 22 are both made of silicon oxide, and the hydrogen content in the silicon oxide film layer is lower than the hydrogen content in the silicon nitride film layer.

[0063] In some embodiments of the present application, the display panel also includes a second thin film transistor 60, which is arranged on the side of the substrate 10 facing the first thin film transistor 20, wherein the second thin film transistor 60 includes a second active layer 61, and the second active layer 61 is arranged on the side of the first active layer 21 away from the isolation portion 22, and the second active layer 61 includes a second channel, and the material of the second channel is different from the material of the first channel 211.

[0064] In the display panel provided in the present application, since the material of the second channel is different from the material of the first channel 211, the type of the second thin-film transistor 60 is different from the type of the first thin-film transistor 20, so that the display panel can have two types of thin-film transistors, thereby further improving the display performance of the display panel.

[0065] In some embodiments of the present application, the second thin-film transistor 60 is disposed in the non-display area NAA of the display panel, for example, in the gate drive circuit of the non-display area NAA. The second channel is made of low-temperature polysilicon, and the second thin-film transistor 60 is a low-temperature polysilicon thin-film transistor, thereby enabling the display panel to have advantages such as high mobility and high response speed. In addition, since the second thin-film transistor 60 is a low-temperature polysilicon thin-film transistor with high mobility and high response speed, the gate drive circuit has a stronger driving capability, thereby enabling the display panel including the second thin-film transistor 60 to drive more pixels, enabling the display panel to have a higher resolution and be used in VR / AR display devices with higher resolution requirements. At the same time, as the resolution of the display panel increases, the number of various wiring types (such as data lines and scan lines) increases, resulting in a decrease in the aperture ratio of the display area AA of the display panel. In the present application, by disposing the second thin-film transistor 60 in the non-display area NAA of the display panel while disposing the first thin-film transistor 20 in the display area AA, the aperture ratio of the display area AA of the display panel can be increased while maintaining high resolution.

[0066] It should be noted that the second thin-film transistor 60 can be disposed in the non-display area NAA and / or the display area AA of the display panel. When the second thin-film transistor 60 is disposed in the non-display area NAA, the display panel may be a liquid crystal display panel; and when at least a portion of the second thin-film transistor 60 is disposed in the display area AA, the display panel may be an organic light-emitting diode display panel.

[0067] In some embodiments of the present application, the first gate insulating layer 50 further includes a second sub-insulating layer 52, which is arranged on a side of the first sub-insulating layer 51 away from the first active layer 21, and the second sub-insulating layer 52 is made of a different material from the first sub-insulating layer 51; the first thin-film transistor 20 includes a first gate 25, which is arranged on a side of the second sub-insulating layer 52 away from the first sub-insulating layer 51; the second thin-film transistor 60 further includes a second gate 62, which is arranged on a side of the second active layer 61 away from the substrate 10; wherein the first gate 25 and the second gate 62 are arranged in the same layer, and the first gate 25 and the second gate 62 are respectively in contact with the second sub-insulating layer 52.

[0068] In the display panel provided in the present application, since the first gate electrode 25 and the second gate electrode 62 are provided in the same layer, the number of film layers of the display panel can be reduced, thereby lowering the production cost.

[0069] Moreover, since the first gate 25 and the second gate 62 are respectively in contact with the second sub-insulating layer 52, and the material of the second sub-insulating layer 52 is different from that of the first sub-insulating layer 51, the second sub-insulating layer 52 can be set to a silicon nitride film layer with a higher hydrogen content, which is beneficial to improving the performance of the second thin film transistor 60.

[0070] In some embodiments of the present application, the display panel also includes a second gate insulating layer 90, which is arranged on the side of the second active layer 61 facing the second gate 62, wherein the first gate insulating layer 50 arranged between the first active layer 21 and the first gate 25 has a first thickness, and the second gate insulating layer 90 arranged between the second active layer 61 and the second gate 62 has a second thickness, and the ratio of the first thickness to the second thickness is less than or equal to 3.

[0071] In the display panel provided in the present application, the first thin film transistor 20 is a metal oxide thin film transistor. Therefore, compared with the second thin film transistor 60 of the low-temperature polycrystalline silicon thin film transistor type, the mobility is relatively low. In the related art, another gate can be set on the side of the first channel 211 away from the first gate 25, thereby forming a double-gate structure to improve the performance of the first thin film transistor 20. However, since the isolation layer, the first drain 23 and the first via 40 are set on the side of the first channel 211 away from the first gate 25 of the present application, a double-gate structure cannot be formed. In order to enable the first thin film transistor 20 to still have a high mobility without having a dual-gate structure, the present application makes the thickness of the first gate insulating layer 50 arranged between the first active layer 21 and the first gate 25 less than three times the thickness of the second gate insulating layer 90 arranged between the second active layer 61 and the second gate 62. As a result, compared with the thin film transistor architecture in the related art in which the thickness of the first gate insulating layer 50 arranged between the first active layer 21 and the first gate 25 is more than five times the thickness of the second gate insulating layer 90 arranged between the second active layer 61 and the second gate 62, the device performance of the first thin film transistor 20 can be significantly improved.

[0072] In some embodiments of the present application, the second thin film transistor 60 further includes a second source 63 and a second drain 64, and the first thin film transistor 20 further includes a first source conductive portion 70, the first source conductive portion 70 is arranged in the same layer as the second source 63 and the second drain 64, and the first source conductive portion 70 is electrically connected to the first source 24 through a second via 80.

[0073] In the display panel provided in the present application, since the first source conductive portion 70 electrically connected to the first source 24 is arranged on the same layer as the second source 63 and the second drain 64, the signal input of the first thin film transistor 20 can be made more convenient without increasing the number of film layers of the display panel, which is beneficial to reducing production costs.

[0074] In some embodiments of the present application, the display panel further includes at least one of a composite functional layer 100 , an interlayer dielectric layer 110 , a first planar layer 120 , a passivation layer 130 , a second planar layer 140 and a common electrode 150 . In which, the composite functional layer 100 is arranged between the second active layer 61 and the substrate 10, and the composite functional layer 100 includes at least one of a buffer layer and a light-shielding layer; the interlayer dielectric layer 110 is arranged on the side of the first drain 23 facing away from the substrate 10; the first planar layer 120 is arranged on the side of the second source 63, the second drain 64, and the first source conductive portion 70 facing away from the substrate 10, the pixel electrode 30 is arranged on the side of the first planar layer 120 facing away from the substrate 10, and the first via 40 passes through the interlayer dielectric layer 110 and the first planar layer 120; the passivation layer 130 is arranged on the side of the pixel electrode 30 facing away from the substrate 10; the second planar layer 140 is arranged on the side of the passivation layer 130 facing away from the substrate 10; and the common electrode 150 is arranged on the side of the second planar layer 140 facing away from the substrate 10.

[0075] In a second aspect, the present application provides a method for preparing a display panel, which includes step S01, step S02, step S03, step S04, step S05, step S06, step S07, step S08, step S09, step S10, and step S11.

[0076] Figure 6a is a schematic diagram of the structure of a display panel corresponding to step S01 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 6a , step S01 includes providing a substrate 10. Optionally, step S01 also includes forming a composite functional layer 100 on the substrate 10. The composite functional layer 100 includes at least one of a buffer layer and a light shielding layer.

[0077] Figure 6b is a schematic diagram of the structure of a display panel corresponding to step S02 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 6b , step S02 includes forming a second active layer 61 of a second thin-film transistor on one side of the substrate 10. The second active layer 61 includes a second channel and second source and drain regions located on either side of the second channel.

[0078] Figure 6c is a schematic diagram of the structure of the display panel corresponding to step S03 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 6c, step S03 includes forming a second gate insulating layer 90 on a side of the second active layer 61 facing away from the substrate 10, and forming the second gate 62 of the second thin-film transistor 60 and the first gate 25 of the first thin-film transistor on a side of the second gate insulating layer 90 facing away from the substrate 10.

[0079] FIG6 d is a schematic structural diagram of a display panel corresponding to step S04 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG6 d , step S04 includes: forming a first gate insulating layer 50 on a side of the second gate insulating layer 90 facing away from the substrate 10, covering the first gate 25 and the second gate 62, the first gate insulating layer 50 including a first sub-insulating layer 51 and a second sub-insulating layer 52, the first sub-insulating layer 51 being disposed on a side of the second sub-insulating layer 52 facing away from the substrate 10, the first sub-insulating layer 51 having a lower hydrogen content than the second sub-insulating layer 52, and hydrogen-activating the second channel; and then forming a first active layer 21 of the first thin film transistor 20 on a side of the first gate insulating layer 50 facing away from the substrate 10, the first active layer 21 including a first channel 211 and a first source ohmic contact and a first drain ohmic contact located on both sides of the first channel 211 without being subjected to conductorization.

[0080] FIG6e is a schematic diagram of the structure of the display panel corresponding to step S05 in the method for preparing a display panel provided in an embodiment of the present application. Referring to FIG6e , step S05 includes: forming an isolation layer on the side of the first channel 211 away from the substrate 10, wherein the isolation layer is made of the same material as the first sub-insulating layer 51, for example, silicon oxide; then, through exposure, development, and etching, the isolation layer is processed to form an isolation portion 22 corresponding to the first channel 211, wherein the thickness of the isolation portion 22 is 50-250 nm, and the sidewall 221 of the isolation portion 22 is substantially the same as the bottom surface 222 of the isolation portion 22; The angle is a, 30°≤a≤90°, and a photoresist is formed on the side of the isolation portion 22 facing away from the first channel 211. Then, the isolation portion 22 and the photoresist are used as masks to perform conductorization on the exposed first source ohmic contact portion and the first drain ohmic contact portion that have not been conductorized. The conductorization process includes boron ion doping or argon plasma treatment, thereby forming the first source ohmic contact portion 213 and the first drain ohmic contact portion 212. Then, the photoresist is stripped off.

[0081] FIG6 f is a schematic structural diagram of a display panel corresponding to step S06 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG6 f , step S06 includes: forming a transparent conductive layer on a side of the isolation portion 22 facing away from the substrate 10, patterning the transparent conductive layer to form a first source electrode 24 and a first drain electrode 23, wherein the first source electrode 24 covers the first source ohmic contact portion 213, and the edge of the first source electrode 24 extends beyond the edge of the first source ohmic contact portion 213 by 0.5-1 micrometers; the first drain electrode 23 includes a first portion 231 and a second portion 232, wherein the second portion 232 of the first drain electrode 23 covers the first drain ohmic contact portion 212, and the edge of the second portion 232 extends beyond the edge of the first drain ohmic contact portion 212 by 0.5-1 micrometers; and the edge 223 of the isolation portion 22 protrudes from the edge 2311 of the first portion 231 of the first drain electrode 23 by 1-2 micrometers.

[0082] FIG6g is a schematic diagram of the structure of the display panel corresponding to step S07 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG6g , step S07 includes forming an interlayer dielectric layer 110 on a side of the transparent conductive layer facing away from the substrate 10, wherein the interlayer dielectric layer 110 is a silicon nitride film layer, a silicon oxide film layer, or a stack of silicon nitride and silicon oxide film layers, and performing a hole-forming process on the interlayer dielectric layer 110 to form a plurality of openings exposing the second source region, the second drain region, and the first source electrode 24, wherein the opening exposing the first source electrode 24 is a second via 80.

[0083] Figure 6h is a schematic diagram of the structure of the display panel corresponding to step S08 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 6h , step S08 includes forming a source-drain metal layer on a side of the interlayer dielectric layer 110 facing away from the substrate 10. The source-drain metal layer may be Ti, Al, Mo, or alloys thereof, or a stacked layer thereof, and patterning the source-drain metal layer to form a second source electrode 63, a second drain electrode 64, and a first source conductive portion 70. The second source electrode 63 is electrically connected to the second source region via an opening that exposes the second source region. The second drain electrode 64 is electrically connected to the second drain region via an opening that exposes the second drain region. The first source conductive portion 70 is electrically connected to the first source electrode 24 via an opening (second via 80) that exposes the first source electrode 24.

[0084] FIG6i is a schematic diagram of the structure of a display panel corresponding to step S09 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG6i , step S09 includes forming a patterned first planar layer 120 including a via hole corresponding to the first portion 231 on the side of the second source electrode 63, the second drain electrode 64, and the first source conductive portion 70 facing away from the substrate 10 using a coating, exposure, and development process. Subsequently, the interlayer dielectric layer 110 is etched using the first planar layer 120 as a mask to form a via hole penetrating the interlayer dielectric layer 110 at a position corresponding to the first portion 231. The via hole penetrating the interlayer dielectric layer 110 and the via hole in the first planar layer 120 together constitute the first via hole 40. Alternatively, a photoresist mask may be formed on the first planar layer 120 to form the first via hole 40 penetrating both the first planar layer 120 and the interlayer dielectric layer 110 in a single etching process.

[0085] Figure 6j is a schematic diagram of the structure of a display panel corresponding to step S10 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 6j , step S10 includes forming a pixel electrode 30 on a side of the first planar layer 120 facing away from the substrate 10 , with the pixel electrode 30 electrically connected to the first portion 231 of the first drain electrode 23 via the first via 40 .

[0086] Figure 6k is a schematic diagram of the structure of the display panel corresponding to step S11 in the method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 6k , step S11 includes sequentially forming a passivation layer 130, a common electrode 150, and a second planarization layer 140 on a side of the pixel electrode 30 facing away from the substrate 10, with the second planarization layer 140 filling the groove formed by the pixel electrode 30 at the first via hole 40.

[0087] In summary, the present application provides a display panel having a display area, the display panel comprising: a substrate; a first thin film transistor disposed on one side of the substrate and located in the display area; a pixel electrode disposed on a side of the first thin film transistor facing away from the substrate and located in the display area; the first thin film transistor comprising a first active layer, an isolation portion, and a first drain electrode, wherein the first active layer comprises a first channel and a first drain ohmic contact portion disposed on one side of the first channel; the isolation portion is disposed on a surface of the first channel facing away from the substrate and covers the first channel; the first drain electrode comprises a transparent first portion and a transparent second portion, the first portion being disposed on a surface of the isolation portion facing away from the first active layer, and the second portion being disposed on a surface of the first drain ohmic contact portion facing away from the substrate; wherein the pixel electrode is electrically connected to the first portion via a first via hole disposed on a side of the first portion facing away from the isolation portion. The display panel provided by the present application can achieve a high aperture ratio while improving the display quality of the display panel and reducing the production cost of the display panel.

[0088] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, in, The display panel has a display area, and the display panel includes: substrate; A first thin film transistor is disposed on one side of the substrate and located in the display area; A pixel electrode, arranged on a side of the first thin film transistor away from the substrate and located in the display area; Wherein, the first thin film transistor comprises: A first active layer including a first channel and a first drain ohmic contact portion disposed on one side of the first channel; an isolation portion, disposed on a surface of the first channel on a side away from the substrate and covering the first channel; a first drain electrode, comprising a transparent first portion and a transparent second portion, wherein the first portion is disposed on a surface of the isolation portion on a side away from the first active layer, and the second portion is disposed on a surface of the first drain electrode ohmic contact portion on a side away from the substrate; The pixel electrode is electrically connected to the first portion through a first via hole provided on a side of the first portion away from the isolation portion.

2. The display panel according to claim 1, in, The second portion covers the first drain ohmic contact.

3. The display panel according to claim 2, in, The second portion covers the side wall of the isolation portion, and an angle formed between the side wall of the isolation portion and the bottom surface of the isolation portion is a, and 30°≤a≤90°.

4. The display panel according to claim 2, in, In a direction in which the isolation portion moves away from the second portion, an edge of the isolation portion protrudes beyond an edge of the first portion.

5. The display panel according to claim 4, in, The first active layer further includes a first source ohmic contact portion disposed on the other side of the first channel. The first thin film transistor further includes a first source electrode formed integrally with the first drain electrode, and the first source electrode is arranged on a surface of the first source ohmic contact portion facing away from the substrate and covers the first source ohmic contact portion.

6. The display panel according to claim 5, in, The display panel also includes a first gate insulating layer, which is arranged on a side of the first active layer away from the isolation portion, wherein the first gate insulating layer includes a first sub-insulating layer, the first sub-insulating layer is in contact with the first active layer, and the first sub-insulating layer and the isolation portion are made of the same material.

7. The display panel according to claim 6, in, The display panel further includes a second thin film transistor, which is disposed on a side of the substrate facing the first thin film transistor. The second thin film transistor includes a second active layer, the second active layer is arranged on a side of the first active layer away from the isolation portion, the second active layer includes a second channel, and a material of the second channel is different from a material of the first channel.

8. The display panel according to claim 7, in, The first gate insulating layer further includes a second sub-insulating layer, the second sub-insulating layer is disposed on a side of the first sub-insulating layer away from the first active layer, and the second sub-insulating layer has a different material from the first sub-insulating layer; The first thin film transistor includes a first gate, the first gate is disposed on a side of the second sub-insulating layer away from the first sub-insulating layer; the second thin film transistor further includes a second gate, the second gate is disposed on a side of the second active layer away from the substrate; Wherein, the first gate and the second gate are disposed in the same layer, and the first gate and the second gate are respectively in contact with the second sub-insulating layer.

9. The display panel according to claim 8, Wherein, The display panel further includes a second gate insulating layer, the second gate insulating layer is disposed on a side of the second active layer facing the second gate. Wherein, the first gate insulating layer disposed between the first active layer and the first gate has a first thickness, the second gate insulating layer disposed between the second active layer and the second gate has a second thickness, and a ratio of the first thickness to the second thickness is less than or equal to 3.

10. The display panel according to claim 7, Wherein, The second thin film transistor further includes a second source electrode and a second drain electrode, the display panel further includes a first source electrode connection portion, the first source electrode connection portion is disposed in the same layer as the second source electrode and the second drain electrode, and the first source electrode connection portion is electrically connected to the first source electrode through a second via hole.

11. The display panel according to claim 1, Wherein, A vertical projection of the first via hole on the first active layer overlaps with the first channel.

12. The display panel according to claim 11, Wherein, The second portion covers the first drain ohmic contact portion.

13. The display panel according to claim 12, Wherein, The second portion covers a sidewall of the isolation portion, and an angle formed by the sidewall of the isolation portion and a bottom surface of the isolation portion is a, 30° ≤ a ≤ 90°.

14. The display panel according to claim 12, Wherein, In a direction away from the second portion of the isolation portion, an edge of the isolation portion protrudes from an edge of the first portion.

15. The display panel according to claim 14, Wherein, The first active layer further includes a first source ohmic contact portion disposed on the other side of the first channel, Wherein, the first thin film transistor further includes a first source electrode integrally formed with the first drain electrode, the first source electrode is disposed on a surface of the first source ohmic contact portion on a side away from the substrate and covers the first source ohmic contact portion.

16. The display panel according to claim 15, Wherein, The display panel further includes a first gate insulating layer, the first gate insulating layer is disposed on a side of the first active layer away from the isolation portion. Wherein, the first gate insulating layer includes a first sub-insulating layer, the first sub-insulating layer is in contact with the first active layer, and the first sub-insulating layer has the same material as the isolation portion.

17. The display panel according to claim 16, wherein, the display panel further includes a second thin film transistor, and the second thin film transistor is disposed on a side of the substrate facing the first thin film transistor, wherein the second thin film transistor includes a second active layer, the second active layer is disposed on a side of the first active layer away from the isolation portion, the second active layer includes a second channel, and a material of the second channel is different from a material of the first channel.

18. The display panel according to claim 17, wherein, the first gate insulating layer further includes a second sub-insulating layer, the second sub-insulating layer is disposed on a side of the first sub-insulating layer away from the first active layer, and a material of the second sub-insulating layer is different from a material of the first sub-insulating layer; the first thin film transistor includes a first gate, the first gate is disposed on a side of the second sub-insulating layer away from the first sub-insulating layer; the second thin film transistor further includes a second gate, the second gate is disposed on a side of the second active layer away from the substrate; wherein the first gate and the second gate are disposed in the same layer, and the first gate and the second gate are respectively in contact with the second sub-insulating layer.

19. The display panel according to claim 18, wherein, the display panel further includes a second gate insulating layer, the second gate insulating layer is disposed on a side of the second active layer facing the second gate, wherein the first gate insulating layer disposed between the first active layer and the first gate has a first thickness, the second gate insulating layer disposed between the second active layer and the second gate has a second thickness, and a ratio of the first thickness to the second thickness is less than or equal to 3.

20. The display panel according to claim 17, wherein, the second thin film transistor further includes a second source electrode and a second drain electrode, the display panel further includes a first source electrode connection portion, the first source electrode connection portion is disposed in the same layer as the second source electrode and the second drain electrode, and the first source electrode connection portion is electrically connected to the first source electrode through a second via hole.

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