Display panel and display device

Abstract

The embodiments of the present invention provide a display panel and a display device. The display panel comprises a substrate, and a plurality of first connection lines, a plurality of data lines, a plurality of pads and a plurality of pixel circuits that are located on one side of the substrate. The first connection lines and the data lines are each located in a display region, and the pads are located in a non-display region; one end of each first connection line is coupled to a data line, and the other end thereof is coupled to a pad; each first connection line comprises a first line segment extending in a first direction and a second line segment extending in a second direction, wherein the first direction and the second direction intersect; the data lines extend in the second direction, and at least one first connection line comprises at least two first line segments spaced apart; the plurality of pixel circuits are arranged in the first direction to form pixel circuit rows; and the first line segments of two adjacent first connection lines each overlap with a different pixel circuit row. The present invention can reduce the number of first connection lines affected by the same scanning line, and can reduce the coupling effect between scanning lines and the first connection lines, thereby improving the display effect.

Description

Display panel and display device

[0001] This invention claims priority to the Chinese patent application filed with the State Intellectual Property Office on November 28, 2023, with application number 202311614126.3 and application name “Display Panel and Display Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] In the prior art, data connection lines are provided within the display area, and some of the data lines are connected to the data terminals via the data connection lines. This eliminates the data connection lines originally provided at the lower corner of the display panel, thereby achieving the goal of reducing the lower bezel of the display panel. However, the current solution of providing data connection lines within the display area has the problem of displaying diagonal lines, which affects the display effect.

[0004] Summary of the Invention

[0005] Embodiments of the present invention provide a display panel and a display device to solve the technical problem of improving display effects.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0007] A substrate, and a plurality of first connection lines, a plurality of data lines, a plurality of pads, and a plurality of pixel circuits located on one side of the substrate;

[0008] A display area and a non-display area, wherein the first connection line and the data line are respectively located in the display area, the pad is located in the non-display area, one end of the first connection line is coupled to the data line, and the other end is coupled to the pad;

[0009] The first connecting line includes a first line segment extending along a first direction and a second line segment extending along a second direction, and the first direction and the second direction intersect; the data line extends along the second direction, and at least one first connecting line includes at least two first line segments spaced apart;

[0010] A plurality of pixel circuits are arranged in a first direction to form pixel circuit rows; first line segments in two adjacent first connecting lines overlap with different pixel circuit rows respectively.

[0011] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0012] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: at least one first connection line is provided in the display panel, including at least two first line segments arranged at intervals, and the first line segments in two adjacent first connection lines overlap with different pixel circuit rows respectively, then the first line segments in the two adjacent first connection lines respectively form coupling capacitors with different scan lines, which can reduce the number of first connection lines affected by the same scan line, thereby reducing the coupling effect between the scan line and the first connection line, and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] FIG1 is a partial schematic diagram of a display panel in the related art;

[0015] FIG2 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0016] FIG3 is a partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0017] FIG4 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0018] FIG5 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0019] FIG6 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] FIG7 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] FIG8 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] FIG9 is a timing diagram of another display panel provided by an embodiment of the present invention;

[0023] FIG10 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0024] FIG11 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] FIG12 is a schematic cross-sectional view of the position of the tangent line AA′ in FIG11;

[0026] FIG13 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0027] FIG14 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0029] It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present invention may be combined with each other unless there is any contradiction.

[0030] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0031] It should be understood that although the terms first and second may be used to describe XX in the embodiments of the present invention, these XX should not be limited to these terms. These terms are only used to distinguish XX from each other.

[0032] FIG1 is a partial schematic diagram of a display panel in the related art. As shown in FIG1 , a data connection line 01 is provided in the display area AA. One end of the data connection line 01 is coupled to the data line 02 and the other end is coupled to the data terminal 03. A multiplexing circuit 04 can be provided in the non-display area NA. The data connection line 01 can be coupled to the data terminal 03 through the multiplexing circuit 04. The multiplexing circuit 04 can include multiple demultiplexers. One demultiplexer can couple at least two data lines 02, that is, there is a demultiplexer coupled to at least two data connection lines 01. The data connection line 01 includes a first line segment 011 extending along a first direction x. The data line 02 extends along a second direction y. A scan line (not shown in FIG1 ) extending along the first direction x is also provided in the display area AA. The first line segment 011 can extend in the same direction as the scan line. During wiring, the distance between the first line segment 011 and the scan line is also relatively close, resulting in a large coupling capacitance between the two. When a signal is provided on a scan line, the adjacent first line segment 011 is coupled by the scan line, causing the data voltage transmitted on the first line segment 011 to fluctuate, resulting in the appearance of diagonal lines on the display. Providing a demultiplexer circuit 04 within the non-display area NA can reduce the number of data terminals 03. However, when the switch in the demultiplexer is closed, the data connection line 01 connected to the switch is in a floating state. At this point, the data connection line 01 is more susceptible to the coupling effect of the scan line, exacerbating the diagonal lines on the display and seriously affecting the display quality.

[0033] To address the problems existing in the related art, an embodiment of the present invention provides a display panel in which first connecting lines are arranged within a display area to achieve electrical connection between a portion of the data lines and the data terminals. At least a portion of the first connecting lines includes at least two first line segments, and the extension direction of the first line segments intersects the extension direction of the data lines. This disperses the coupling between the first connecting lines and the scan lines into couplings between each first line segment and a different scan line. This reduces the degree to which the first connecting lines are coupled to the scan lines each time, thereby reducing the impact of the coupling on the data signal and improving the display effect. In addition, the first line segments of two adjacent first connecting lines are arranged to overlap with different pixel circuit rows, so that the first line segments of the two adjacent first connecting lines are coupled to different scan lines, thereby reducing the number of first connecting lines affected by the same scan line.

[0034] FIG2 is a schematic diagram of a display panel provided in an embodiment of the present invention. As shown in FIG2 , the display panel includes a plurality of first connecting lines 10, a plurality of data lines 20, a plurality of pads 30, and a plurality of pixel circuits 40. The first connecting lines 10 and the data lines 20 are respectively located in the display area AA, and the pads 30 are located in the non-display area NA. One end of the first connecting line 10 is coupled to the data line 20, and the other end is coupled to the pads 30. The display panel also includes a substrate (not shown in FIG2 ), and the pixel circuits 40, pads 30, data lines 20, and the first connecting lines 10 are all located on the same side of the substrate.

[0035] The first connecting line 10 includes a first line segment 11 extending along a first direction x and a second line segment 12 extending along a second direction y, and the first direction x and the second direction y intersect; the data line 20 extends along the second direction y, and at least one first connecting line 10 includes at least two first line segments 11 arranged at intervals.

[0036] Multiple pixel circuits 40 are arranged in a first direction x to form a pixel circuit row 40H. The first line segments 11 of two adjacent first connecting lines 10 overlap with different pixel circuit rows 40H. It will be understood that the pixel circuits 40 are arranged with transistors and signal lines, and the pixel circuits 40 occupy a certain area in both the first direction x and the second direction y. Any overlap between a first connecting line 10 and a transistor or signal line in a pixel circuit 40 is considered to be an overlap between the first connecting line 10 and the pixel circuit row 40H.

[0037] The display panel also includes a scan line 50 extending along a first direction x. Scan line 50 is indicated by a dashed line in FIG2 . The pixel circuit 40 is coupled to scan line 50, and scan line 50 is used to drive pixel circuit row 40H. A first segment 11 of the first connecting line 10 is relatively close to scan line 50, forming a coupling capacitor between the first segment 11 and scan line 50.

[0038] In the display panel provided by the embodiment of the present invention, at least one first connecting line 10 is provided, including at least two first line segments 11 arranged at intervals (for example, two first line segments in the same first connecting line are electrically connected through at least one second line segment), and the first line segments 11 in two adjacent first connecting lines 10 overlap with different pixel circuit rows 40H respectively. Then, the first line segments 11 in two adjacent first connecting lines 10 form coupling capacitors with different scan lines 50 respectively, which can reduce the number of first connecting lines 10 affected by the same scan line 50, thereby reducing the coupling effect between the scan line 50 and the first connecting line 10, and improving the display effect.

[0039] Furthermore, in a first connection line 10 comprising at least two first line segments 11, each first line segment 11 can be arranged to overlap with a different pixel circuit row 40H. This creates a relatively small capacitance between each first line segment 11 and the scan line 50 driving the pixel circuit row 40H. By arranging for the scan lines 50 overlapping with the first line segments 11 in the same first connection line 10 to not provide signals simultaneously, the degree of coupling between the first connection line 10 and the scan line 20 can be reduced. During the display of a single frame, the number of times a first connection line 10 is coupled is equal to the number of first line segments 11 it comprises. The degree of coupling between the first connection line 10 is negligible, and the coupling between the first line segments 11 does not accumulate. This reduces the effect of coupling on the data signal on the first connection line 10, improving the display effect.

[0040] In some embodiments, as shown in FIG2 , a display panel includes at least one cable group 10Z, each of which includes at least two first connecting lines 10 arranged in sequence. The first connecting lines 10 in the cable group 10Z include the same number of first line segments 11. Coupling capacitances are formed between the first line segments 11 and the scan lines 50. When the scan lines 50 provide scan signals, the coupling between the first line segments 11 and the scan lines 50 affects the data signals on the first connecting lines 10. By including the same number of first line segments 11 in the cable group 10Z, each first connecting line 10 in the same cable group 10Z is coupled to the scan lines 50 an equal number of times, and the degree of coupling between each first connecting line 10 is minimal. This minimizes the effect of coupling on the data signals transmitted by each first connecting line 10 in the cable group 10Z, thereby further improving display uniformity.

[0041] FIG2 illustrates two cable assemblies 10Z. In one cable assembly 10Z, each first connecting cable 10 includes two first line segments 11, while in the other cable assembly 10Z, each first connecting cable 10 includes one first line segment 11. For each first connecting cable 10, the first line segment 11 and the second line segment 12 connected thereto may form a step shape.

[0042] In some embodiments, as shown in FIG2 , a cable group 10Z includes a first cable group 10Z1 and a second cable group 10Z2. A first connecting line 10 in the first cable group 10Z1 includes n1 first line segments 11, and a first connecting line 10 in the second cable group 10Z2 includes n2 first line segments 11, where n1 and n2 are both positive integers, and n1>n2. The number of first connecting lines 10 included in different cable groups 10Z can be the same or different. By setting different numbers of first line segments 11 for each first connecting line 10 in different cable groups 10Z, the number of first line segments 11 in the first connecting line 10 can be appropriately set to meet the wiring requirements for connecting the first connecting line 10 to the data line 20. This also ensures that the length of each first line segment 11 is not too long, thereby minimizing the coupling capacitance between each first line segment 11 and the scan line 50.

[0043] As shown in Figure 2, the non-display area NA includes a first non-display area NA1, which is located on one side of the display area AA in the second direction y. A bonding pad 30 is located in the first non-display area NA1. Multiple first line segments 11 in the first wiring group 10Z1 are located on the side of the second wiring group 10Z2 away from the first non-display area NA1. As shown in Figure 2, the intersection point W of the first connecting line 10 with the boundary between the display area AA and the first non-display area NA1 is greater than the distance from the intersection point W of the first connecting line 10 in the first wiring group 10Z1 to the data line 20 connected thereto along the first direction x. Consequently, the total length of the first line segments 11 on a single first connecting line 10 in the first wiring group 10Z1 is greater than the total length of the first line segments 11 on a single first connecting line 10 in the second wiring group 10Z2. By providing a relatively large number of first line segments 11 included in a single first connecting line 10 in the first wiring group 10Z1, the length of each first line segment 11 can be kept short, thereby minimizing the coupling capacitance between each first line segment 11 and the scan line 50. Furthermore, the length difference between the individual first line segments 11 in the first wiring group 10Z1 and the second wiring group 10Z2 can be reduced, thereby minimizing the differences in the effect of the coupling of different first connecting lines 10 with the scan line 50, thereby improving display uniformity.

[0044] Figure 2 illustrates only two cable groups 10Z. The present embodiment does not limit the number of cable groups 10Z that can be formed by arranging multiple first connecting lines 10. Figure 3 is a partial schematic diagram of another display panel provided by an embodiment of the present invention. To clearly illustrate the routing of the first connecting lines 10, structures such as pixel circuits, data lines, and scan lines are not shown in Figure 3. Figure 3 shows four cable groups 10Z. The number of first line segments 11 included in a single first connecting line 10 in a cable group 10Z gradually increases as it moves away from the first non-display area NA1.

[0045] As shown in FIG3 , the first non-display area NA1 may further be provided with a demultiplexing circuit 60, through which the first connection lines 10 are coupled to the pads 30. The demultiplexing circuit 60 includes a first demultiplexer (not shown in FIG3 ), the input end of the first demultiplexer being connected to one data terminal 30 and the output end being connected to at least two first connection lines 10. The provision of the demultiplexing circuit 60 can reduce the number of data terminals 30, thereby reducing the number of pins of the display driver chip, which helps reduce manufacturing costs.

[0046] As shown in Figure 2 , the first cable group 10Z1 and the second cable group 10Z2 are adjacent, with n1-n2=1. That is, the difference in the number of first line segments 11 included in a single first connecting line 10 in two adjacent cable groups 10Z is 1. This arrangement minimizes the length differences between the first connecting lines 10 within adjacent cable groups 10Z, and also minimizes the length differences between the first line segments 11. This ensures that the load on the data lines 20 coupled to the first connecting lines 10 is not abruptly changed, and that the effect of coupling with the scan lines 50 on each first connecting line 10 is minimal, thereby improving display uniformity.

[0047] As shown in FIG2 , at least one first connecting line 10 includes a first first line segment 11-1, which is the first first line segment 11-1 in the first connecting line 10 farthest from the first non-display area NA1. Optionally, the first first line segment 11-1 is electrically connected to the data line 20 via a via (illustrated as a black dot in FIG2 ). The lengths of the multiple first first line segments 11-1 in a cable group 10Z gradually increase in length as they move away from the first non-display area NA1. This arrangement can meet the wiring requirements for connecting the first connecting lines 11 in the cable group 10Z and the corresponding data lines 20. It can also gradually change the length of each first connecting line 11 in the cable group 10Z, preventing sudden changes in length. This reduces the load differences between the data lines 20 connected to the corresponding data lines 20 in the cable group 10Z, thereby improving display uniformity.

[0048] In some embodiments, FIG4 is a schematic diagram of another display panel provided by an embodiment of the present invention. As shown in FIG4 , the non-display area NA includes a first non-display area NA1 and a second non-display area NA2, with the second non-display area NA2 located to one side of the display area AA in the first direction x. The pad 30 is located in the first non-display area NA1. The data lines 20 include a first data line 21 and a second data line 22, with the first data line 21 being closer to the second non-display area NA2 than the second data line 22. Among the first connection lines 10, the first line segment 11 that is farthest from the first non-display area NA1 is a first first line segment 11-1. The first connecting lines 10 in a cable group 10Z include a first-type first connecting line 10-1 and a second-type first connecting line 10-2. The length of the first first line segment 11 in the first-type first connecting line 10-1 is greater than the length of the first first line segment 11 in the second-type first connecting line 10-2. The first-type first connecting line 10-1 is coupled to the first data line 21, and the second-type first connecting line 10-2 is coupled to the second data line 22. This arrangement not only allows the lengths of the first connecting lines 10 within a cable group 20Z to gradually change, but also allows the lengths of multiple first connecting lines 10 arranged in sequence to gradually change. This prevents sudden changes in the lengths of two adjacent first connecting lines 10 belonging to two cable groups 20Z, reduces load differences between the data lines 20, and facilitates improved display uniformity.

[0049] In the embodiment of FIG. 4 , the farther the first line segment 11 of the first connection line 10 is from the first non-display area NA1 , the closer the data line 20 connected to the first connection line 10 is to the second non-display area NA2 .

[0050] In other embodiments, FIG5 is a schematic diagram of another display panel provided by an embodiment of the present invention. As shown in FIG5 , the non-display area NA includes a first non-display area NA1 and a second non-display area NA2. The first non-display area NA1 is located on one side of the display area AA in the second direction y, and the second non-display area NA2 is located on one side of the display area AA in the first direction x. Among the first connection lines 10, the first line segment 11 farthest from the first non-display area NA1 is a first first line segment 11-1. The first connection lines 10 include third-type first connection lines 10-3 and fourth-type first connection lines 10-4. Among the fourth-type first connection lines 10-4, the first first line segment 11-1 is located on the side of the third-type first connection lines 10-3 away from the first non-display area NA1. The data lines 20 include a third data line 23 and a fourth data line 24. The third data line 23 is closer to the second non-display area NA2 than the fourth data line 24. The third type of first connecting line 10-3 is coupled to the third data line 23, and the fourth type of first connecting line 10-4 is coupled to the fourth data line 24. In this embodiment, the farther the first first line segment 11 of the first connecting line 10 is from the first non-display area NA1, the farther the data line 20 connected to the first connecting line 10 is from the second non-display area NA2. This configuration minimizes the difference in the total length of the first connecting lines 10, reduces load differences between the data lines 20, and improves display uniformity.

[0051] In some embodiments, along a direction perpendicular to the plane of the substrate, the first line segment 11 overlaps k pixel circuits in a pixel circuit row 40H, where 5%K≤k≤25%K, k and K are both positive integers, and K is the total number of pixel circuits included in a pixel circuit row 40H. In embodiments of the present invention, the first line segment 11 overlaps dozens or even hundreds of pixel circuits. Since the first line segment 11 overlaps a relatively large number of pixel circuits, the total length of the second line segments 12 in a first connecting line 10 is correspondingly relatively small, thereby reducing the length occupied by a first connecting line 10 in the second direction y. Consequently, the total area occupied by multiple first connecting lines 10 within the display area is relatively small, thereby reserving more wiring space within the display area for other wiring designs.

[0052] In some embodiments, in at least one first connecting line 10, there are at least two first line segments 11 of equal length. It should be noted that there are process errors when manufacturing the display panel, and there will also be measurement errors when measuring the length. The equal length mentioned here in the present invention means that the length is roughly equal when the process error and the measurement error are taken into account. The longer the length of the first line segment 11, the greater the coupling capacitance between it and the adjacent scan line. For first line segments 11 of equal length, the coupling capacitance formed by the first line segment 11 and the scan line is also equal. Including first line segments 11 of equal length in the same first connecting line 10 is conducive to relatively evenly distributing the coupling between the first connecting line 10 and the scan line to different first line segments 11.

[0053] In some embodiments, at least one first connecting line 10 is configured such that the lengths of the first line segments 11 arranged sequentially along its routing direction gradually vary. Each first line segment 11 in the first connecting line 10 overlaps with a different pixel circuit row to form a coupling capacitor. As the length of the first line segment 11 gradually changes along the routing direction, the coupling capacitance formed between each first line segment 11 and the scan line gradually changes. Consequently, during a single frame of image display, the degree of multiple couplings on the first connecting line 10 gradually changes, minimizing the difference in coupling between the previous and subsequent frames, thereby reducing the fluctuation amplitude of the data signal on the first connecting line 10.

[0054] Figure 6 is a schematic diagram of another display panel provided by an embodiment of the present invention, which only illustrates a partial area of ​​the display area AA. As can be seen from Figure 6, for a first connecting line 10, the lengths of the first line segments 11 arranged sequentially from left to right gradually increase.

[0055] FIG7 is a schematic diagram of another display panel provided by an embodiment of the present invention. As shown in FIG7 , a cable group 10Z includes a first first connecting line 101. The first first line segment 11-1 in the first first connecting line 101 is the longest. The lengths of the first line segments 11 arranged sequentially from left to right in the first first connecting line 101 gradually decrease. FIG7 shows that, from top to bottom, the lengths of the first first line segments 11-1 in the cable group 10Z gradually decrease. Some of the first connecting lines 10 in the cable group 10Z meet the requirement that the lengths of the first line segments 11 arranged sequentially from left to right gradually decrease; while the remaining first connecting lines 10 meet the requirement that, except for the first first line segment 11-1, the lengths of the first line segments 11 arranged sequentially from left to right gradually decrease.

[0056] As shown in Figure 3, the second line segment 12 includes a middle line segment 12z, with each end of the middle line segment 12z connected to a first line segment 11. The length of the middle line segment 12z is shorter than the length of the first line segment 11 to which it is connected. This arrangement can reduce the span of a single first connecting line 10 in the second direction y, thereby reducing the total length occupied by multiple first connecting lines 10 in the second direction y and saving wiring space within the display area. This allows more space to be reserved within the display area for dummy lines. Using dummy lines to transmit constant voltage signals (such as power or reset signals required by pixel circuits) can reduce signal voltage drop and improve signal uniformity within the display panel.

[0057] As shown in FIG3 , the second line segments 12 further include a first second line segment 121. The first second line segment 121 is the second line segment 12 extending to the boundary between the display area AA and the first non-display area NA1 in the first connecting line 10. As can be seen in FIG3 , the first second line segments 121 of the plurality of first connecting lines 10 gradually become longer from left to right.

[0058] In some embodiments, the first line segment 11 includes a first sub-line segment and a second sub-line segment, with a second line segment 12 connecting the first sub-line segment and the second sub-line segment. That is, the first sub-line segment and the second sub-line segment belong to the same first connecting line 10. The pixel circuit row 40H that overlaps with the first sub-line segment and the pixel circuit row 40H that overlaps with the second sub-line segment are separated by m pixel circuit rows 40H, where m is an integer and m ≥ 0.

[0059] As shown in FIG2 , in a first connection line 10, m=1, that is, there is one pixel circuit row 40H between the first sub-segment 111 and the second sub-segment 112. In other words, in addition to the pixel circuit row 40H overlapping with the first sub-segment 111 and the pixel circuit row 40H overlapping with the second sub-segment 112, there is also a complete pixel circuit row 40H between the first sub-segment 111 and the second sub-segment 112.

[0060] FIG8 is a schematic diagram of another display panel provided by an embodiment of the present invention. As shown in FIG8 , in a first connecting line 10, there is a gap of zero pixel circuit rows 40H between the first sub-line segment 111 and the second sub-line segment 112. That is, the pixel circuit rows 40H that overlap with the first sub-line segment 111 and the second sub-line segment 112 are adjacent pixel circuit rows 40H. This arrangement shortens the length of the second line segment 12 between the first sub-line segment 111 and the second sub-line segment 112, thereby reducing the total length of the multiple first connecting lines 10 in the second direction y and saving wiring space within the display area.

[0061] When m≥1, there is a certain distance between the first sub-segment 111 and the second sub-segment 112, and wiring can be carried out between them. For example, a dummy line is arranged between the row where the first sub-segment 111 is located and the row where the second sub-segment 112 is located. Transmitting a constant voltage signal using the dummy line can reduce the signal voltage drop and improve the in-plane signal uniformity of the display panel.

[0062] In some embodiments, in the display of one frame of the picture, the signals provided on the scanning lines include q effective-level time periods, where q is an integer and q≥2; the time interval between two adjacent effective-level time periods is t, and the total time for n scanning lines to sequentially output an effective level once is T, where n is an integer and n≥1; among them, m≠n. Taking q = 2 and n = 3 as an example, FIG. 9 is a timing diagram of another display panel provided by an embodiment of the present invention, which shows the signal timings of 5 sequentially arranged scanning lines. The 5 scanning lines are Scan_i, Scan_i+1, Scan_i+2, Scan_i+3, Scan_i+4 respectively, where i is a positive integer. The signals provided on the scanning lines include 2 effective-level time periods (indicated by high level), the time interval between two adjacent effective-level time periods on the same scanning line is t, and within the time t, three scanning lines sequentially output an effective level once. That is to say, an effective-level signal is provided simultaneously by a scanning line and another scanning line that is separated from it by three pixel circuit rows 40H. In the embodiment of the present invention, m≠n is set, that is, m < n or m > n, so as to ensure that the two pixel circuit rows overlapping with the first sub-segment 111 and the second sub-segment 112 respectively are not driven simultaneously, and the first sub-segment 111 and the second sub-segment 112 do not couple with the scanning lines simultaneously, which can reduce the degree of coupling of the first connection line 10 by the scanning lines each time.

[0063] As shown in FIG. 2, a plurality of pixel circuits 40 are arranged in pixel circuit columns 40L along the second direction y; in the direction perpendicular to the plane of the substrate, the second segment 12 overlaps at least part of the pixel circuit columns 40L, and two adjacent second segments 12 among different first connection lines 10 overlap with two adjacent pixel circuit columns 40L respectively. Such a setting can make the adjacent second segments 12 belonging to different first connection lines 10 be closely arranged, which is beneficial to reducing the area occupied by the plurality of first connection lines 10 in the display area, thereby saving the wiring space in the display area. In some embodiments, more space can be reserved in the display area to set dummy lines. Transmitting a constant voltage signal using the dummy line can reduce the signal voltage drop and improve the in-plane signal uniformity of the display panel.

[0064] In other embodiments, FIG10 is a schematic diagram of another display panel provided by an embodiment of the present invention. As shown in FIG10 , a plurality of pixel circuits 40 are arranged into pixel circuit columns 40L along the second direction y, and p pixel circuit columns 40L are spaced between at least partially adjacent second line segments 12 in different first connecting lines 10, where p is an integer and p≥1. FIG10 illustrates that, in addition to the two pixel circuit columns 40L that overlap with the two adjacent second line segments 12, a complete pixel circuit column 40L is spaced between the two adjacent second line segments 12, i.e., p=1. In this embodiment, the arrangement of the two adjacent second line segments 12 belonging to different first connecting lines 10 is relatively sparse, so that there is space between the two adjacent second line segments 12 to arrange a dummy line. After a constant voltage signal is applied to the dummy line, it can act as a shield to prevent signal interference between the adjacent second line segments 12.

[0065] In some embodiments, FIG11 is a schematic diagram of another display panel provided by an embodiment of the present invention, and FIG12 is a schematic cross-sectional view at the position of the tangent line AA′ in FIG11. As shown in FIG11, the display area AA includes a first dummy line 71 extending along the first direction x and a second dummy line 72 extending along the second direction y. The first dummy line 71 is used to transmit a constant voltage signal, and the second dummy line 72 is also used to transmit a constant voltage signal. In some embodiments, the first dummy line 71 and the second dummy line 72 cross and are electrically connected, and the two transmit the same signal. In other embodiments, the first dummy line 71 and the second dummy line 72 cross and are insulated, and the two transmit different signals.

[0066] As shown in Figure 12, the display panel includes a first metal layer M1 and a second metal layer M2 located on one side of the substrate 00. The first line segment 11 is located in the first metal layer M1, and the second line segment 12 is located in the second metal layer M2. Specifically, the first dummy line 71 is located in the first metal layer M1; the second dummy line 72 is located in the second metal layer M2. Figure 12 illustrates that the second metal layer M2 is located on the side of the first metal layer M1 close to the substrate 00. Other metal layers and semiconductor layers may also be provided between the second metal layer M2 and the substrate 00, for example, to form transistors and various signal lines. In other words, the pixel circuit 40 may be located between the second metal layer M2 and the substrate 00.

[0067] In the embodiment of Figure 11 , first dummy lines 71 and first line segments 11 extending in the same direction can be located on the same layer, and second dummy lines 72 and second line segments 12 extending in the same direction can be located on the same layer. After multiple first connection lines 10 are arranged within display area AA, the remaining space can be used to arrange dummy lines. Furthermore, the dummy lines can be used to transmit constant voltage signals, thereby reducing signal voltage drop and improving signal uniformity within the display panel.

[0068] 11 shows that both the first dummy line 71 and the second dummy line 72 are arranged in the display area AA. In other embodiments, only the first dummy line 71 or only the second dummy line 72 may be arranged in the display area AA, as shown in the figure.

[0069] In some embodiments, FIG13 is a schematic diagram of another display panel provided by an embodiment of the present invention. As shown in FIG13 , a second dummy line 72 extending along the second direction y is arranged within the display area AA. The second dummy line 72 includes a first dummy line segment 721. At least one first dummy line segment 721 overlaps with at least two first line segments 11 in a direction perpendicular to the plane of the substrate 00. FIG13 illustrates that at least one first dummy line segment 721 overlaps with multiple first line segments 11 arranged along the second direction y. In this embodiment of the present invention, the first connecting line 10 includes at least one step (the interconnected first and second line segments 11 and 12 form a step-like routing), and some first connecting lines 10 include at least two steps. If a first line segment 11 overlaps with dozens or even hundreds of pixel circuits, there is an arrangement area Q1 for the first line segment 11 as shown in FIG13 . The segment of the second dummy line 72 extending into the arrangement area Q1 is the first dummy line segment 721. Using the design of this embodiment of the present invention, the second dummy line 72 can substantially penetrate the display area in the second direction y.

[0070] As shown in FIG13 , the second dummy line 72 includes a second dummy line segment 722, which is located between adjacent second line segments 12. When at least one pixel circuit column is spaced between two adjacent second line segments 12 in different first connecting lines 10, the second dummy line segment 722 can be provided between adjacent second line segments 12. The second dummy line segment 722 transmits a constant voltage signal and can act as a shield to prevent signal interference between adjacent second line segments 12.

[0071] In some embodiments, the first dummy line 71 includes a third dummy line segment, which overlaps with at least two adjacent second line segments 12. This arrangement allows the dummy line to be provided in the arrangement area of ​​the first connecting line 10. Optionally, the first dummy line 72 includes a fourth dummy line segment, which is located between two adjacent first line segments 11. The fourth dummy line segment can then act as a shield between the two first line segments 11 to prevent signal interference.

[0072] Based on the same inventive concept, embodiments of the present invention further provide a display device. FIG14 is a schematic diagram of a display device provided by an embodiment of the present invention. As shown in FIG14 , the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided by an embodiment of the present invention can be, for example, an electronic product such as a mobile phone, a computer, a television, or a smartwatch.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A substrate, and a plurality of first connection lines, a plurality of data lines, a plurality of pads, and a plurality of pixel circuits located on one side of the substrate; A display area and a non-display area, the first connection line and the data line are respectively located in the display area, the pad is located in the non-display area, one end of the first connection line is coupled to the data line, and the other end is coupled to the pad; The first connecting line includes a first line segment extending along a first direction and a second line segment extending along a second direction, and the first direction and the second direction intersect; the data line extends along the second direction, and at least one of the first connecting lines includes at least two first line segments arranged at intervals; A plurality of the pixel circuits are arranged into pixel circuit rows in the first direction; the first line segments in two adjacent first connecting lines overlap with different pixel circuit rows respectively.

2. The display panel according to claim 1, characterized in that: The display panel includes at least one wiring group, the wiring group includes at least two first connecting wires arranged in sequence, and the first connecting wires in the wiring group include the same number of first line segments.

3. The display panel according to claim 2, characterized in that: The wiring group includes a first wiring group and a second wiring group, one of the first connecting wires in the first wiring group includes n1 first line segments, and one of the first connecting wires in the second wiring group includes n2 first line segments, n1 and n2 are both positive integers, and n1>n2.

4. The display panel according to claim 3, characterized in that: The non-display area includes a first non-display area, the first non-display area is located at one side of the display area in the second direction; the pad is located in the first non-display area; A plurality of the first line segments in the first wiring group are located at a side of the second wiring group away from the first non-display area.

5. The display panel according to claim 3, characterized in that: The first wiring group and the second wiring group are adjacent to each other, and n1-n2=1.

6. The display panel according to claim 2, characterized in that: The non-display area includes a first non-display area, the first non-display area is located at one side of the display area in the second direction; the pad is located in the first non-display area; The first line segments in the first connecting lines include a first first line segment, and the first first line segment is the one of the first connecting lines where the first first line segment is located farthest from the first non-display area; Along the direction away from the first non-display area, the lengths of the plurality of first line segments in one wiring group gradually increase.

7. The display panel according to claim 6, characterized in that: The non-display area further includes a second non-display area, and the second non-display area is located at one side of the display area in the first direction; the data line includes a first data line and a second data line, and the distance between the first data line and the second non-display area is smaller than the distance between the second data line and the second non-display area; The first connecting wires in one of the wiring groups include a first type of first connecting wires and a second type of first connecting wires, the length of the first first line segment in the first type of first connecting wires is greater than the length of the first first line segment in the second type of first connecting wires, the first type of first connecting wires are coupled to the first data lines, and the second type of first connecting wires are coupled to the first data lines. The line is coupled to the second data line.

8. The display panel according to claim 2, characterized in that: The non-display area includes a first non-display area and a second non-display area, the first non-display area is located at one side of the display area in the second direction, and the second non-display area is located at one side of the display area in the first direction; The first line segments in the first connecting lines include a first first line segment, and the first first line segment is the one of the first connecting lines where the first first line segment is located farthest from the first non-display area; The first connection lines include third-type first connection lines and fourth-type first connection lines, and the first first line segment of the fourth-type first connection lines is located at a side of the third-type first connection lines away from the first non-display area; The data lines include a third data line and a fourth data line, and the distance between the third data line and the second non-display area is smaller than the distance between the fourth data line and the second non-display area; The third-type first connection line is coupled to the third data line, and the fourth-type first connection line is coupled to the fourth data line.

9. The display panel according to claim 1, characterized in that: Along a direction perpendicular to the plane of the substrate, the first line segment overlaps with k pixel circuits in a pixel circuit row, 5%K≤k≤25%K, k and K are both positive integers, and K is the total number of pixel circuits included in a pixel circuit row.

10. The display panel according to claim 1, characterized in that: In at least one of the first connecting lines, at least two of the first line segments have the same length.

11. The display panel according to claim 1, characterized in that: In at least one of the first connecting lines, the lengths of the first line segments sequentially arranged along the routing direction thereof gradually change.

12. The display panel according to claim 1, characterized in that: The second line segment includes a middle line segment, and both ends of the middle line segment are respectively connected to one of the first line segments. The length of the middle line segment is smaller than the length of the first line segment connected thereto.

13. The display panel according to claim 1, characterized in that: The first line segment includes a first sub-line segment and a second sub-line segment, and the first sub-line segment and the second sub-line segment are connected by a second line segment; There are m pixel circuit rows between the pixel circuit row overlapping the first sub-line segment and the pixel circuit row overlapping the second sub-line segment, where m is an integer and m≥0.

14. The display panel according to claim 13, characterized in that: The display panel comprises a plurality of scan lines, wherein the scan lines are coupled to the pixel circuit rows; In a frame of picture display, the signal provided on the scan line includes q valid level periods, q is an integer, q≥2; the interval time between two adjacent valid level periods on the same scan line is t, and the total time for n scan lines to output a valid level in sequence is t, n is an integer, n≥1; wherein, m≠n.

15. The display panel according to claim 1, characterized in that: A plurality of the pixel circuits are arranged into a pixel circuit column along the second direction; Along a direction perpendicular to the plane where the substrate is located, the second line segments at least partially overlap with the pixel circuit columns, and two adjacent second line segments in different first connecting lines overlap with two adjacent pixel circuit columns respectively.

16. The display panel according to claim 1, characterized in that: The plurality of pixel circuits are arranged into pixel circuit columns along the second direction, and there are p pixel circuit columns spaced between two second line segments that are at least partially adjacent in different first connecting lines, where p is an integer and p≥1.

17. The display panel according to claim 1, characterized in that: The display panel comprises a first metal layer and a second metal layer located on one side of the substrate, the first line segment is located on the first metal layer, and the second line segment is located on the second metal layer; The display area includes a first dummy line extending along the first direction, and the first dummy line is located in the first metal layer; and / or the display area includes a second dummy line extending along the second direction, and the second dummy line is located in the second metal layer.

18. The display panel according to claim 17, characterized in that: The second imaginary line includes first imaginary line segments; along a direction perpendicular to the plane where the substrate is located, at least one of the first imaginary line segments overlaps with at least two of the first line segments.

19. The display panel according to claim 17, characterized in that: The second imaginary line includes second imaginary line segments, and the second imaginary line segments are located between adjacent second line segments.

20. A display device, characterized in that: A display panel comprising any one of claims 1 to 19.

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