Display panel, driving method, driving circuit, and display device

Abstract

A display panel, a driving method, a driving circuit, and a display device (1000). The display panel comprises: a plurality of pixel circuits (100). Each pixel circuit (100) comprises: a first light-emitting control unit (101) electrically connected between a first node (N1) and a second node (N2); a second light-emitting control unit (102) electrically connected between a third node (N3) and a fourth node (N4); a driving unit (103) separately electrically connected to the second node (N2), the third node (N3), and a fifth node (N5); a first data writing unit (104) electrically connected between the third node (N3) and a sixth node (N6) and comprising an oxide transistor; an isolation unit (105) electrically connected between the fifth node (N5) and the sixth node (N6) and comprising a polycrystalline silicon transistor; and a light-emitting unit (106) having one end electrically connected to the fourth node (N4) and the other end used for receiving a second driving signal (VSS).

Description

Display panel, driving method, driving circuit and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311622386.5 filed on November 30, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving method, a driving circuit, and a display device. Background Art

[0004] With the increasing maturity of semiconductor display technologies, such as AMOLED (Active-matrix organic light-emitting diode) and OLED (Organic Light-Emitting Diode), and in response to today's diverse market demands, higher requirements are being placed on the frame rate, resolution, and durability of display screens.

[0005] Pixel circuits fabricated using a combination of LTPS (Low Temperature Poly-Silicon) and oxide technology are widely used due to their combination of the low leakage of oxide transistors and the high maturity of the LTPS process. However, oxide transistors are sensitive to temperature and voltage fluctuations, making them susceptible to characteristic drift. This can cause variations in the drive current in the pixel circuit, resulting in uneven brightness across the display and degraded visual quality.

[0006] Summary of the Invention

[0007] The display panel, driving method, driving circuit and display device provided by the present disclosure can improve the uneven brightness of the display screen caused by the characteristic deviation of the oxide transistor in the pixel circuit.

[0008] According to a first aspect of an embodiment of the present disclosure, a display panel is provided, including a plurality of pixel circuits, wherein the pixel circuits include:

[0009] a first light emitting control unit, the first light emitting control unit being electrically connected between a first node and a second node, the first node being configured to receive a first driving signal;

[0010] a second light emitting control unit, the second light emitting control unit being electrically connected between the third node and the fourth node;

[0011] a driving unit, wherein the driving unit is electrically connected to the second node, the third node, and the fifth node respectively;

[0012] a first data writing unit, the first data writing unit being electrically connected between the third node and the sixth node, the first data writing unit comprising an oxide transistor;

[0013] an isolation unit, the isolation unit being electrically connected between the fifth node and the sixth node, the isolation unit comprising a polysilicon transistor;

[0014] a light-emitting unit, one end of the light-emitting unit being electrically connected to the fourth node, and the other end of the light-emitting unit being configured to receive a second driving signal;

[0015] There is a first time period in which the first data writing unit and the isolation unit are both turned on, and after the first time period, the isolation unit is turned off before the first data unit.

[0016] In some embodiments, the oxide transistor of the first data writing unit is in a saturation region during the first time period.

[0017] In some embodiments, the oxide transistor of the first data writing unit is N-type;

[0018] The polysilicon transistor of the isolation unit is P-type;

[0019] Wherein, before the first time period, the rising edge of the gate signal of the oxide transistor is located before the falling edge of the gate signal of the polysilicon transistor;

[0020] After the first time period, a falling edge of the gate signal of the oxide transistor is located after a rising edge of the polysilicon transistor.

[0021] In some embodiments, the pixel circuit further includes:

[0022] a first reset unit, the first reset unit being electrically connected to the sixth node and configured to transmit a first reset signal to the sixth node;

[0023] There is a second time period in which the first data writing unit and the first reset unit are turned on at the same time, and before the second time period, the first reset unit is turned on before the first data writing unit, and after the second time period, the first reset unit is turned off before the first data writing unit, and the second time period does not overlap with the first time period.

[0024] In some embodiments, before the second time period, there is at least one third time period in which the isolation unit and the first reset unit are simultaneously turned on, and before the third time period, the first reset unit is turned on before the isolation unit.

[0025] In some embodiments, the pixel circuit further includes:

[0026] a second data writing unit, the second data writing unit being electrically connected to the second node and configured to transmit a data signal to the second node;

[0027] The second data writing unit and the isolation unit have the same switching state.

[0028] In some embodiments, the pixel circuit further includes:

[0029] a second reset unit, the second reset unit being electrically connected to the fourth node and configured to transmit a second reset signal to the fourth node;

[0030] a third reset unit, the third reset unit being electrically connected to the second node and configured to transmit a third reset signal to the second node;

[0031] A capacitor, one end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the fifth node.

[0032] In some embodiments, the first reset unit includes an oxide transistor; and / or,

[0033] The second data writing unit includes a polysilicon transistor; and / or,

[0034] The second reset unit includes a polysilicon transistor; and / or,

[0035] The third reset unit includes a polysilicon transistor; and / or,

[0036] The first light emitting control unit includes a polysilicon transistor; and / or,

[0037] The second light emitting control unit includes a polysilicon transistor; and / or,

[0038] The driving unit includes a polysilicon transistor.

[0039] In some embodiments, when the driving unit is a P-type polysilicon transistor, the potential of the third reset signal is greater than the potential of the first driving signal;

[0040] In a case where the driving unit is an N-type polysilicon transistor, the potential of the third reset signal is lower than the potential of the first driving signal.

[0041] In some embodiments, the first light emitting control unit is turned on for at least one row scanning duration before the second light emitting control unit is turned on.

[0042] A second aspect of the present disclosure provides a method for driving a display panel, which is applied to the display panel according to any one of the first aspects. The method includes:

[0043] controlling the first data writing unit and the isolation unit to be turned on, so that the first data writing unit and the isolation unit are turned on at the same time during the first time period, and transmitting write data to the driving unit;

[0044] After the first time period, controlling to disconnect the isolation unit first and then the first data writing unit;

[0045] The first light emitting control unit and the second light emitting control unit are controlled to be turned on, so that the light emitting unit emits light under the action of the first driving signal and the second driving signal.

[0046] In some embodiments, when the pixel circuit includes a first reset unit, and there is a second time period in which the first data writing unit and the first reset unit are simultaneously turned on, the driving method further includes:

[0047] Before the second time period, controlling the first reset unit to be turned on first;

[0048] After the second time period, controlling the first reset unit to be disconnected first;

[0049] The second time period lasts for at least one row scan duration.

[0050] In some embodiments, before the second time period, the isolation unit and the first reset unit are simultaneously turned on for at least one third time period, and the driving method further includes:

[0051] Before the second time period, controlling the first reset unit to be turned on to transmit a first reset signal to the sixth node;

[0052] After the first reset unit is turned on, the isolation unit is controlled to be turned on for at least one of the third time periods to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one row scan duration.

[0053] In some embodiments, the driving method further includes:

[0054] Before controlling the first light emitting control unit and the second light emitting control unit to be turned on, the first light emitting control unit is controlled to be turned on for at least one row scanning duration compared to the second light emitting control unit.

[0055] A third aspect of the embodiments of the present disclosure provides a driving circuit for use in the method for driving a display panel as described in any one of the second aspects.

[0056] A fourth aspect of the embodiments of the present disclosure provides a display device, comprising the display panel as described in any one of the first aspects; and / or the driving circuit as described in the third aspect.

[0057] In summary, the display panel provided by the present disclosure includes multiple pixel circuits, which include: a first light-emitting control unit, the first light-emitting control unit is electrically connected between a first node and a second node, and the first node is used to receive a first drive signal; a second light-emitting control unit, the second light-emitting control unit is electrically connected between a third node and a fourth node; a driving unit, the driving unit is electrically connected to the second node, the third node, and the fifth node respectively; a first data writing unit, the first data writing unit is electrically connected between the third node and the sixth node, and the first data writing unit includes an oxide transistor; an isolation unit, the isolation unit is electrically connected between the fifth node and the sixth node, and the isolation unit includes a polysilicon transistor light-emitting unit, one end of the light-emitting unit is electrically connected to the fourth node, and the other end is used to receive a second drive signal; wherein the first data writing unit and the isolation unit have a first time period in which they are simultaneously turned on, and after the first time period, the isolation unit is turned off before the first data unit. The present disclosure sets an isolation unit between the first data writing unit and the driving unit, and the isolation unit includes a polysilicon transistor. When it is necessary to stop writing charge to the fifth node, the polysilicon transistor in the isolation unit is first turned off, and then the oxide transistor of the first data writing unit is turned off. Polysilicon transistors, especially low-temperature polysilicon transistors, have a mature manufacturing process. Their semiconductor layers are made of polysilicon, which is more stable, has a stronger electron binding force, and is not easily affected by the external environment. Oxide transistors are less stable. After long-term operation, the device temperature rises, the electron activity intensifies, and the electron binding force is further reduced. Therefore, when the gate-source voltage of the transistor fluctuates, it is particularly easy to cause charge accumulation at the defects between the semiconductor layer and the oxide layer, resulting in charging and discharging, causing the threshold voltage to shift, resulting in a change in the potential of the gate node of the write driver transistor, and ultimately forming uneven brightness of the display screen. Therefore, the present disclosure first turns off the polysilicon transistor in the isolation unit. Taking advantage of the strong stability of the polysilicon transistor, the threshold voltage is not easily shifted when the gate-source voltage fluctuates. Therefore, at the moment of turning off, the potential difference of the gate node of the write driver transistor is greatly reduced, and the driving current generated by the driver transistor is highly restored. The brightness of the light-emitting unit does not dim or brighten, which can improve the technical problem of uneven brightness of the display screen and improve the uniformity of the display image.

[0058] Correspondingly, the driving method, driving circuit and display device provided by the present disclosure also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic structural block diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0060] FIG2 is a diagram showing the relationship between the threshold voltage of an oxide transistor and the brightness of an OLED according to an embodiment of the present disclosure;

[0061] FIG3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0062] FIG4 is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0063] FIG5 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0065] FIG7 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0066] FIG8 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0067] FIG9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0068] FIG10 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0069] FIG11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0070] FIG12 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0071] FIG13 is a schematic flow chart of a driving method provided in an embodiment of the present disclosure;

[0072] FIG14 is a schematic structural block diagram of a driving circuit connection relationship provided by an embodiment of the present disclosure;

[0073] FIG15 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.

[0074] 1, 3, 5, 6, 8, 9, 11, 14, and 15, the corresponding relationship between the component names and reference numerals is as follows: 1000 display device; 100 pixel circuit, 200 light emitting array driving circuit, 300 first gate array driving circuit, 400 Second gate array driving circuit; 101 first light-emitting control unit, 102 second light-emitting control unit, 103 driving unit, 104 first data writing unit, 105 isolation unit, 106 light-emitting unit, 107 first reset unit, 108 second data writing unit, 109 second reset unit, 110 third reset unit; N1 first node, N2 second node, N3 third node, N4 fourth node, N5 fifth node, N6 sixth node, T5 polysilicon transistor, T6 oxide transistor, VDD first driving signal, VSS second driving signal, Vinit1 first reset signal, Vinit2 second reset signal, Vinit3 third reset signal, Data data signal, T5 polysilicon transistor, T4 oxide transistor, Ngate first gate driving signal, Pgate second gate driving signal, Reset_n first reset driving signal, Reset_p second reset driving signal, EM light-emitting control signal, EM1 first light-emitting control signal, EM2 second light-emitting control signal. DETAILED DESCRIPTION

[0075] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments.

[0076] In a first aspect, an embodiment of the present disclosure provides a display panel, including a plurality of pixel circuits. FIG1 is a schematic structural block diagram of a pixel circuit provided by an embodiment of the present disclosure. As shown in FIG1 , the pixel circuit 100 includes: a first light-emitting control unit 101, the first light-emitting control unit 101 is electrically connected between a first node N1 and a second node N2, the first node N1 is used to receive a first drive signal VDD; a second light-emitting control unit, the second light-emitting control unit is electrically connected between a third node N3 and a fourth node N4; a driving unit 103, the driving unit 103 is electrically connected to the second node N2, the third node N3 and the fifth node N5 respectively; a first data The writing unit 104, the first data writing unit 104 is electrically connected between the third node N3 and the sixth node N6, and the first data writing unit 104 includes an oxide transistor; the isolation unit 105, the isolation unit 105 is electrically connected between the fifth node N5 and the sixth node N6, and the isolation unit 105 includes a polysilicon transistor; the light-emitting unit 106, one end of the light-emitting unit 106 is electrically connected to the fourth node N4, and the other end is used to receive the second driving signal VSS; wherein, the first data writing unit 104 and the isolation unit 105 have a first time period in which they are simultaneously turned on, and after the first time period, the isolation unit 105 is disconnected before the first data unit.

[0077] It should be noted that the first light-emitting control unit 101 is configured to control the conduction and cutoff between the first node N1 and the second node N2. When the first node N1 and the second node N2 are conductive, the first drive signal VDD is written to the second node N2. The second light-emitting control unit 102 is configured to control the conduction and cutoff between the third node N3 and the fourth node N4. The drive unit 103 is configured to control the conduction and cutoff between the second node N2 and the third node N3 under the influence of the fifth node N5. When the first light-emitting control unit 101, the second light-emitting control unit 102, and the drive unit 103 are all conductive, the light-emitting unit 106 emits light under the influence of the first drive signal VDD and the second drive signal VSS. The isolation unit 105 is used to control the conduction and cutoff between the fifth node N5 and the sixth node N6, and the first data writing unit 104 is used to control the conduction and cutoff between the third node N3 and the sixth node N6. The first time period represents the time period during which the isolation unit 105 and the first data writing unit 104 are simultaneously turned on. During the first time period, the potential of the third node N3 can be written into the fifth node N5 via the first data writing unit 104 and the isolation unit 105. After the first time period, the isolation unit 105 is first turned off, and then the first data writing unit 104 is turned off. Furthermore, the isolation unit 105 includes a polysilicon transistor, and the first data writing unit 104 includes an oxide transistor.

[0078] It is understandable that oxide transistors such as IGZO (Indium Gallium Zinc Oxide) have low leakage characteristics. In the pixel circuit 100, an oxide transistor can be used as an isolation switch for writing a control signal to the gate of the driving transistor, which can prevent the charge of the gate capacitor from being lost when the driving transistor is in the on state, thereby ensuring the on-state stability of the driving transistor. However, due to the low current process maturity of oxide transistors and the relatively active nature of oxides, the threshold voltage characteristics of oxide transistors are prone to offset, especially when the voltage fluctuates. In this way, at the cut-off moment of the oxide transistor, the threshold voltage will produce a positive offset or a reverse offset. For example, Figure 2 is a relationship diagram between the threshold voltage of an oxide transistor and the brightness of an OLED provided in an embodiment of the present disclosure. The horizontal axis ΔV_th in Figure 2 represents the fluctuation of the threshold voltage of the oxide transistor, in V (volts), and the vertical axis ΔIoled / Ioled represents the percentage change in the brightness of the OLED. As shown in Figure 2, when the oxide transistor is forward-shifted, the oxide transistor threshold voltage increases, resulting in an increase in the amount of charge written to the gate of the driver transistor, a decrease in the absolute value of the gate-source voltage of the driver transistor, a decrease in the drive current generated by the driver transistor, and a darker OLED brightness than normal. Conversely, when the oxide transistor is reverse-shifted, the oxide transistor threshold voltage decreases, resulting in a decrease in the amount of charge written to the gate of the driver transistor, an increase in the absolute value of the gate-source voltage of the driver transistor, an increase in the drive current generated by the driver transistor, and a brighter OLED brightness than normal. Therefore, based on the offset of the oxide transistor threshold voltage, the display screen will produce uneven horizontal stripes.

[0079] In the disclosed embodiment, an isolation unit 105 is provided between the first data writing unit 104 and the driving unit 103. The isolation unit 105 includes a polysilicon transistor. After a first time period, that is, when it is necessary to stop writing charge to the fifth node N5, the polysilicon transistor in the isolation unit 105 is first turned off, followed by the oxide transistor in the first data writing unit 104. Polysilicon transistors, especially low-temperature polysilicon transistors, have a mature manufacturing process. Their semiconductor layers are made of polysilicon, which is more stable and has a stronger electron binding force, making it less susceptible to external environmental influences. Oxide transistors, on the other hand, are less stable. Over long periods of operation, device temperature rises, electron activity intensifies, and the electron binding force is further reduced. Therefore, when the gate-source voltage of the transistor fluctuates, charge accumulation is particularly likely to occur at defects between the semiconductor layer and the oxide layer, resulting in charge and discharge, causing a threshold voltage shift, and causing the potential of the gate node of the write driver transistor to change, ultimately resulting in uneven brightness of the display screen. Therefore, the embodiment of the present disclosure first turns off the polysilicon transistor in the isolation unit 105, and takes advantage of the strong stability of the polysilicon transistor. When the gate-source voltage fluctuates, the threshold voltage is not easily offset, so that at the moment of cutoff, the potential difference of the gate node of the write driver transistor is greatly reduced, and then the driving current generated by the driver transistor is highly restored. The brightness of the light-emitting unit will not have the problem of dimming or brightening, which can improve the technical problem of uneven brightness of the display screen and improve the uniformity of the display image. It should be noted that the first light-emitting control unit 101, the second light-emitting control unit 102, the isolation unit 105 and the first data writing unit 104 can be controlled by the driver chip or processor in the display panel, and the specific control method is not limited.

[0080] For example, FIG3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure. As shown in FIG3 , the first light-emitting control unit 101 includes a transistor T1, the second light-emitting control unit 102 includes a transistor T2, the driving unit 103 includes a transistor T3, the first data writing unit 104 includes an oxide transistor T4, the isolation unit 105 includes a polysilicon transistor T5, and the light-emitting unit 106 includes an OLED. The oxide transistor T4 is an N-type transistor, while the transistors T1, T2, T3, and polysilicon transistor T5 are P-type transistors.

[0081] FIG4 is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present disclosure. As shown in conjunction with FIG3 and FIG4 , when the emission control signal EM is at a high level, transistors T1 and T2 are turned off. When the first gate drive signal Ngate is at a high level, oxide transistor T4 is turned on. When the second gate drive signal Pgate is at a low level, polysilicon transistor T5 is turned on. The first time period during which oxide transistors T4 and polysilicon transistors T5 are simultaneously turned on is period T in FIG4 . During period t, the potential of third node N3 is written to fifth node N5 via sixth node N6, and the potential of fifth node N5 is stored in the gate capacitance of transistor T3. After period t, when the second gate drive signal Pgate is at a low level, polysilicon transistor T5 is turned off. After polysilicon transistor T5 is turned off, oxide transistor T4 can be turned off.

[0082] It is easy to understand that the turn-off interval between the polysilicon transistor T5 and the oxide transistor T4 can be determined according to actual conditions, so as to ensure that the oxide transistor T4 is turned off after the polysilicon transistor T5 is completely turned off.

[0083] According to some embodiments, the oxide transistor of the first data writing unit 104 in FIG. 1 and FIG. 3 is in a saturation region during the first time period.

[0084] It should be noted that when the oxide transistor in the first data writing unit 104 is in the saturation region, the source-drain current is little affected by the gate potential. Therefore, when writing data to the fifth node N5 in the above-mentioned first time period, it is possible to prevent the first gate driving signal Ngate from fluctuating and causing the written data to change, thereby improving the accuracy of the charge amount of the gate capacitance of the driving transistor in the write driving unit 103, and then improving the accuracy of the driving current, so that the brightness of the OLED can be accurately restored.

[0085] According to some embodiments, the oxide transistor of the first data writing unit 104 is N-type; the polysilicon transistor of the isolation unit 105 is P-type; wherein, before the first time period, the rising edge of the gate signal of the oxide transistor is located before the falling edge of the gate signal of the polysilicon transistor; after the first time period, the falling edge of the gate signal of the oxide transistor is located after the rising edge of the polysilicon transistor.

[0086] For example, as shown in conjunction with FIG3 and FIG4 , in a first time period, i.e., before time T in FIG4 , the oxide transistor T4 of the first data unit begins to conduct at the rising edge of the first gate drive signal Ngate, and the polysilicon transistor T5 of the isolation unit 105 begins to conduct at the falling edge of the second gate drive signal Pagate, with the rising edge of the first gate drive signal Ngate preceding the falling edge of the second gate drive signal Pagate. After time T, the polysilicon transistor T5 of the isolation unit 105 is turned off at the rising edge of the second gate drive signal Pagate, and the oxide transistor T4 of the first data unit 104 is turned off at the falling edge of the first gate drive signal Ngate, with the falling edge of the first gate drive signal Ngate following the rising edge of the second gate drive signal Pagate. By staggering the turn-on and turn-off of the oxide transistor T4 and the polysilicon transistor T5, it is possible to avoid a threshold voltage shift of the oxide transistor T4 caused by voltage fluctuations, which could result in a change in the potential of the fifth node N5.

[0087] According to some embodiments, Figure 5 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in Figure 5, the pixel circuit 100 also includes: a first reset unit 107, the first reset unit 107 is electrically connected to the sixth node N6, and the first reset unit 107 is used to transmit a first reset signal to the sixth node N6; wherein, the first data write unit 104 and the first reset unit 107 have a second time period in which they are turned on at the same time, and before the second time period, the first reset unit 107 is turned on before the first data write unit 104, and after the second time period, the first reset unit 107 is turned off before the first data write unit 104, and the second time period does not overlap with the first time period.

[0088] It should be noted that the first reset unit 107 is configured to transmit the first reset signal Vinit1 to the sixth node N6 under the control of a control signal. During the second time period when the first data write unit 104 and the first reset unit 107 are both turned on, the first reset signal Vinit1 is written to the third node N3. Because the first data write unit 104 and the isolation unit 105 are both turned on during the first time period to write the potential of the third node N3 to the fifth node N5, the first reset unit 107 cannot write the first reset signal Vinit1 to the third node N3 during the first time period, and the first time period cannot overlap with the second time period.

[0089] For example, Figure 6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure. As shown in Figure 6, taking the transistor T6 as N-type as an example, the first reset unit 107 includes a transistor T6, the gate of the transistor T6 receives the first reset drive signal Reset_n, one of the source or drain is electrically connected to the sixth node N6, and the other receives the first reset signal Vinit1.

[0090] Figure 7 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in combination with Figures 6 and 7, in the T3 time period, which is the above-mentioned second time period, the first reset drive signal Reset_n is at a high potential, the transistor T6 is turned on, the first gate drive signal Ngate is at a high potential, the oxide transistor T4 is turned on, and the first reset signal Vinit1 is written to the third node N3 to set the third node N3.

[0091] Before the stage t3 , the transistor T6 is turned on to precharge the sixth node N6 , so as to adjust the gate-source voltage of the oxide transistor T4 to remove the influence of residual charge in the previous frame of display.

[0092] After the stage t3 , the transistor T6 is turned off first, so as to prevent the first reset signal Vinit1 from being continuously written into the sixth node N6 , thereby preventing the setting of the fifth node N5 in the subsequent stage.

[0093] It should be noted that since the third node N3 is connected to the transistor T3 in the driving unit 103, setting the third node N3 can adjust the threshold voltage of the transistor T3, eliminating the offset of the threshold voltage of the transistor T3 in the previous frame display image, thereby improving the accuracy of the driving current, and then accurately restoring the brightness of the OLED.

[0094] According to some embodiments, before the second time period, the isolation unit 105 and the first reset unit 107 are simultaneously turned on for at least one third time period, and before the third time period, the first reset unit 107 is turned on before the isolation unit 105 .

[0095] For example, in combination with FIG6 and FIG7 , in the time period t2, the second gate drive signal Pgate is in at least one low potential time period, such as the time period t2' in FIG7 , and in the time period t2' the first reset drive signal Reset_n is in a high potential, the polysilicon transistor T5 in the isolation unit 105 and the transistor T6 in the first reset unit 107 are turned on at the same time, and the first reset signal Vinit1 is written to the fifth node N5 through the polysilicon transistor T5.

[0096] It should be noted that setting the electric potential of the fifth node N5 as the first reset signal Vinit1 can clear the residual charge on the fifth node N5, adjust the gate stress of the transistor T3 in the driving unit 103 to control the threshold voltage of the transistor T3, and eliminate the offset of the threshold voltage of the transistor T3 in the previous frame display image, thereby improving the accuracy of the driving current and the brightness restoration of the OLED, thereby improving the afterimage problem of the display screen.

[0097] The transistor T6 is turned on before the polysilicon transistor T5 and sets the sixth node N6 first, thereby clearing the residual charge in the sixth node N6 and eliminating the influence on the polysilicon transistor T5, thereby improving the accuracy of writing the first reset signal Vinit1.

[0098] There may be multiple third time periods. By setting the potential of the fifth node N5 multiple times, the residual charge on the fifth node N5 can be better cleared, and the threshold voltage of the transistor T3 can be adjusted multiple times to improve the adjustment effect.

[0099] It should be noted that clearing the residual charge at the fifth node N5 can also reduce the impact on the characteristics of the polysilicon transistor T5.

[0100] According to some embodiments, as shown in Figure 5, the pixel circuit 100 further includes: a second data writing unit 108, the second data writing unit 108 is electrically connected to the second node N2, and the second data writing unit 108 is used to transmit the data signal Data to the second node N2; wherein the switching state of the second data writing unit 108 is the same as that of the isolation unit 105.

[0101] It should be noted that the pixel circuit 100 further includes a second data write unit 108, which is electrically connected to the second node N2. After the second data write unit 108 is turned on, the data signal Data is written to the fifth node N5 via the driving unit 103, the first data write unit 104, and the isolation unit 105. Because the second data write unit 108 and the isolation unit 105 are connected in series in the same branch and are functionally bound to each other, the switching states of the second data write unit 108 and the isolation unit 105 can be the same, thereby simplifying the control logic of the display panel and reducing driving power consumption. Moreover, after the first reset unit 107 sets the sixth node N6, the second data write unit 108 is used to write the data signal Data to the fifth node N5. This can prevent the residual charge on the sixth node N6 from affecting the conductive state of the isolation unit 105 and the first data write unit 104, thereby improving the accuracy of the data signal Data writing.

[0102] Exemplarily, as shown in Figure 6, taking a P-type transistor as an example, the second data writing unit 108 includes a transistor T7, the gate of the transistor T7 receives the second gate drive signal Pgate, one of the source and the drain receives the data signal Data, and the other of the source and the drain is electrically connected to the second node N2.

[0103] As shown in Figures 6 and 7 , during the third time period t2' of phase T2, transistor T7 and polysilicon transistor T5 are simultaneously turned on by the low potential of the second gate drive signal Pgate, and transistor T6 is turned on by the first reset drive signal Reset_n, setting the potential of the sixth node N6 to the first reset signal Vinit1. In this phase, the sixth node N6 is first reset to remove any residual charge therein, eliminating the influence of the previous frame displayed.

[0104] In stage t4, under the low potential of the second gate drive signal Pgate, transistor T7 and polysilicon transistor T5 are turned on at the same time in the first time period, and the data signal Data is written into the fifth node N5 through transistor T3, transistor T2 and transistor T9.

[0105] In some examples, the second data writing unit 108 and the isolation unit 105 are both controlled by the same driving circuit, thus saving gate lines in the display panel and reducing the width of the non-display area in the display panel.

[0106] According to some embodiments, Figure 8 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in Figure 8, the pixel circuit 100 also includes: a second reset unit 109, the second reset unit 109 is electrically connected to the fourth node N4, and the second reset unit 109 is used to transmit the second reset signal Vinit2 to the fourth node N4; a third reset unit 110, the third reset unit 110 is electrically connected to the second node N2, and the third reset unit 110 is used to transmit the third reset signal Vinit3 to the second node N2; a capacitor Cst, one end of the capacitor Cst is electrically connected to the first node N1, and the other end is electrically connected to the fifth node N5.

[0107] It should be noted that, when the second reset unit 109 is on, it writes the second reset signal Vinit2 into the fourth node N4. When the third reset unit 110 is on, it writes the third reset signal Vinit3 into the second node N2. The capacitor Cst is electrically connected to the first node N1 and the fifth node N5, respectively, and is used to store charge when the driving transistor T3 is turned on.

[0108] FIG9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in FIG9 , taking a P-type transistor as an example, the second reset unit 109 includes a transistor T8, the gate of which receives the second reset drive signal Reset_p, one of its source and drain is connected to the fourth node N4, and the other of its source and drain receives the second reset signal Vinit2. The third reset unit 110 includes a transistor T9, the gate of which can also receive the second reset drive signal Reset_p, one of its source and drain is connected to the second node N2, and the other receives the third reset signal Vinit3.

[0109] FIG10 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present disclosure. The various working stages of the pixel circuit 100 provided by an embodiment of the present disclosure are described in conjunction with FIG9 and FIG10 .

[0110] In stage t1, the second reset drive signal Reset_p is at a low potential, transistors T8 and T9 are turned on, and the remaining transistors are in the off state. The second reset signal Vinit2 and the third reset signal Vinit3 are written to the second node N2 and the fourth node N4 respectively to clear the residual charge after the previous frame is displayed.

[0111] During the t2 period, the first reset drive signal Reset_n is at a high potential, and transistor T6 is in the on state. During this period, the polysilicon transistor T5, under the action of the second gate drive signal Pgate, can be turned on once or multiple times, such as during the t2' period. During the t2' period, the first reset signal Vinit1 is written to the fifth node N5 via transistor T6 and the polysilicon transistor T5 to clear any residual charge on the fifth node N5. This can adjust the gate stress of transistor T3 in the drive unit 103 to eliminate the influence of the previous frame displayed on its threshold voltage. This improves the accuracy of the drive current and the brightness restoration of the OLED, thereby improving the afterimage problem on the display screen. Providing multiple t2' periods can enhance the effect of adjusting the gate stress of transistor T3.

[0112] In stage t3, the first reset drive signal Reset_n is at a high potential, the first gate drive signal Ngate is at a high potential, the second gate drive signal Pgate is at a high potential, the transistor T6 and the oxide transistor T4 are turned on, the transistor T5 is turned off, and the first reset signal Vinit1 sets the third node N3 to clear the residual charge of the third node N3 and bias the threshold voltage of the transistor T3 to further clear the influence of the display image on its threshold voltage.

[0113] During the t4 period, the first gate drive signal Ngate is at a high level, the first reset drive signal Reset_n is at a low level, oxide transistor T4 is turned on, and transistor T6 is turned off. The second gate drive signal Pgate is at a low level during the t4' period, turning on polysilicon transistors T5 and T7, and transistor T3 is turned on by capacitor Cst. During the t4' period, the data signal Data is written to capacitor Cst through transistors T7, T3, T4, and polysilicon transistor T5.

[0114] During stage t5, the second reset drive signal Reset_p is at a low level, transistors T9 and T8 are turned on, the third reset signal Vinit3 is written to the second and third nodes N2 and N3, and the second reset signal Vinit2 is written to the fourth node N4. During this stage, the third node N3 is set, allowing charge to be quickly transferred to the OLED capacitor after transistor T2 is turned on, thereby increasing the OLED's lighting rate. Setting the second and third nodes N2 and N3 adjusts the threshold voltage of transistor T3, improving the accuracy of the drive current.

[0115] It should be noted that, in the display panel provided in the embodiment of the present disclosure, the duration of the t5 stage can also be set according to actual conditions and is not specifically limited.

[0116] In the t6 phase, the light-emitting control signal EM is at a low level, transistors T1 and T2 are turned on, and transistor T3 is turned on by the capacitor Cst. The OLED emits light under the driving current of transistor T3, and the current flowing into the OLED can be determined by the following formula: I OLED =K(V sg -|V th |) 2 (1)

[0117] Among them, K represents the process design constant related to transistor T3, V sg represents the source-gate voltage of transistor T3, V sg represents the threshold voltage of transistor T3, I OLED Indicates the driving current. V in formula (1) sg Can be transformed into: V sg =V DD -(V data -|V th |) (2)

[0118] Among them, V DD represents the potential of the first drive signal VDD, V data Indicates the potential of the data signal Data.

[0119] Combining formula (1) and formula (2), we can get formula (3): OLED =K(V DD -V data ) 2 (3)

[0120] It should be noted that, after the stages t1 to t6, the display panel provided by the embodiment of the present disclosure completes the driving process of one frame of display image.

[0121] According to some embodiments, as shown in Figure 9, the first reset unit 107 includes an oxide transistor; and / or, the second data writing unit 108 includes a polysilicon transistor; and / or, the second reset unit 109 includes a polysilicon transistor; and / or, the third reset unit 110 includes a polysilicon transistor; and / or, the first light-emitting control unit 101 includes a polysilicon transistor; and / or the second light-emitting control unit 102 includes a polysilicon transistor; and / or, the driving unit 103 includes a polysilicon transistor.

[0122] 9 , transistors T1 , T2 , T3 , T7 , T8 , and T9 may be polysilicon transistors, and transistor T6 may be an oxide transistor.

[0123] It should be noted that the current process of polysilicon transistors is mature, and the semiconductor layer is made of polysilicon material, so the semiconductor layer has a strong binding force on electrons. Therefore, the characteristics of polysilicon transistors are relatively stable, and the threshold voltage is not easily affected by the external environment. However, polysilicon transistors are more prone to leakage than oxide transistors. Therefore, setting transistors T1, transistor T2, transistor T3, transistor T7, transistor T8, and transistor T9, which are not directly connected to capacitor Cst, as polysilicon transistors can avoid the leakage defects of polysilicon transistors. In addition, polysilicon transistors have relatively high electron mobility and good conductivity. They are directly connected to data signals such as VDD and Data, which can reduce losses.

[0124] It should be noted that since the transistor T6 is connected in series to the branch of the polysilicon transistor T5 and the capacitor Cst, there is a risk of leakage. Therefore, the transistor T6 is set as an oxide transistor to reduce the leakage risk.

[0125] According to some embodiments, as shown in Figure 9, when the driving unit 103 is a P-type polysilicon transistor, the potential of the third reset signal Vinit3 is greater than the potential of the first driving signal VDD; when the driving unit 103 is an N-type polysilicon transistor, the potential of the third reset signal Vinit3 is less than the potential of the first driving signal VDD.

[0126] For example, when the driving unit 103 is a P-type polysilicon transistor, its threshold voltage is less than zero. Therefore, in order to ensure that the transistor T3 is turned on, the source or drain potential of the transistor T3 can be adjusted higher, that is, the potential of the third reset signal Vinit3 is greater than the potential of the first driving signal VDD, so that the transistor T3 is in a forward bias, so that both the second node N2 and the third node N3 can be set.

[0127] For example, when the driving unit 103 is an N-type polysilicon transistor, its threshold voltage is greater than zero. Therefore, in order to ensure that the transistor T3 is turned on, the source or drain potential of the transistor T3 can be lowered, that is, the potential of the third reset signal Vinit3 is less than the potential of the first driving signal VDD, so that the transistor T3 is in a forward bias, so that both the second node N2 and the third node N3 can be set.

[0128] According to some embodiments, as shown in FIG. 1 , FIG. 5 , and FIG. 8 , the first light emitting control unit 101 is turned on for at least one row scanning duration before the second light emitting control unit 102 .

[0129] Exemplarily, Figure 11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure. As shown in Figure 11, taking a P-type transistor as an example, the first light-emitting control unit 101 includes a transistor T1, and the second light-emitting control unit 102 includes a transistor T2. The gates of transistor T1 and transistor T2 receive a first light-emitting control signal EM1 and a second light-emitting control signal EM2, respectively.

[0130] FIG12 is a schematic signal timing diagram of another pixel circuit provided in an embodiment of the present disclosure. In combination with FIG11 and FIG12 , during the stages t1 to t5, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at a high potential, and the transistors T1 and T2 are cut off. The rest are the same as those described above and will not be repeated.

[0131] In phase t6 , the first light emitting control signal EM1 is at a low level, the transistor T1 is turned on, the second light emitting control signal EM2 is at a high level, the transistor T2 is turned off, and the second node N2 can be precharged.

[0132] In the stage t7, both transistors T1 and T2 are turned on, and the OLED emits light.

[0133] It should be noted that during stage t6, by precharging the second node N2, the precharged charge at the second node N2 can be quickly transferred to the capacitor of the OLED during the subsequent stage t7, thereby increasing the OLED's light emission rate. Furthermore, stage t6 lasts for at least one line scan duration to ensure sufficient precharging. This line scan duration can be understood as the time interval between displaying adjacent frames.

[0134] It should be noted that the pulse widths of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be the same, and the timing difference is one row scanning time. Therefore, when a driving circuit is used to provide the first light-emitting control signal EM1 and the second light-emitting control signal EM2, every two rows of pixel circuits 100 can share one driving circuit, thereby reducing the width of the non-display area of ​​the display panel.

[0135] A second aspect of the present disclosure provides a method for driving a display panel, which is applied to the display panel according to any one of the first aspects. FIG13 is a schematic flow chart of a driving method provided by an embodiment of the present disclosure. As shown in FIG13 , the driving method includes:

[0136] S110 , controlling the first data writing unit 104 and the isolation unit 105 to be turned on, so that the first data writing unit 104 and the isolation unit 105 are turned on simultaneously for a first time period, and transmitting the write data to the driving unit 103 .

[0137] 1 , the first data write unit 104 and the isolation unit 105 are controlled to be turned on simultaneously during a first time period, thereby transmitting write data to the driver unit 103 via the third node N3, the sixth node N6, and the fifth node. As shown in FIG3 , FIG6 , FIG9 , and FIG11 , the first data write unit 104 includes an oxide transistor T4, the isolation unit 105 includes a polysilicon transistor T5, and the driver unit 103 includes a transistor T3.

[0138] It should be noted that the first time period represents the period when the first data writing unit 104 and the isolation unit 105 are simultaneously turned on, as shown in the t time period in Figure 4, but is not limited to the first data writing unit 104 and the isolation unit 105 being simultaneously turned on and off.

[0139] S120 , after the first time period, controlling the isolating unit 105 to be disconnected first and then the first data writing unit 104 to be disconnected.

[0140] For example, after the first time period has passed and the write data has been transmitted to the driving unit 103 , the branch from the third node N3 to the fifth node N5 may be disconnected.

[0141] It should be noted that the manufacturing process of polysilicon transistors is mature, and the semiconductor layer is made of polysilicon material, which has a strong binding force on electrons. The characteristics of the transistor are relatively stable, and the threshold voltage is not easily affected by the external environment. However, the semiconductor layer of the oxide transistor is made of oxide, and the characteristics are relatively unstable. The threshold voltage is prone to offset, especially in the case of voltage fluctuations. Referring to Figures 3, 6, 9 and 11, after the first time period, the polysilicon transistor T5 in the isolation unit 105 is first disconnected, and then the oxide transistor T4 in the first data writing unit 104 is disconnected. Therefore, the current flowing into the fifth node N5 will not produce a sudden change due to the threshold voltage offset that may occur in the oxide transistor T4, causing the gate-source voltage of the driving transistor in the driving unit 103 to increase or decrease, so that the driving current generated by the driving unit 103 will not change, and the brightness of the OLED will not have the problem of dimming or brightening, thereby improving the technical problem of uneven brightness of the display screen.

[0142] S130 , controlling the first light emitting control unit 101 and the second light emitting control unit 102 to be turned on, so that the light emitting unit 106 emits light under the action of the first driving signal and the second driving signal.

[0143] Exemplarily, after the isolation unit 105 is turned off, the first light emitting control unit 101 and the second light emitting control unit 102 are controlled to be turned on, and the light emitting unit 106 emits light under the action of the first driving signal VDD and the second driving signal VSS.

[0144] It should be noted that the driving method provided in the embodiments of the present disclosure is also applicable to the embodiments of Figures 6 and 7 , the embodiments of Figures 9 and 10 , and the embodiments of Figures 11 and 12 .

[0145] According to some embodiments, as shown in Figure 5, when the pixel circuit 100 includes a first reset unit 107, and there is a second time period in which the first data writing unit 104 and the first reset unit 107 are turned on at the same time, the driving method further includes: before the second time period, controlling the first reset unit to be turned on first; after the second time period, controlling the first reset unit 107 to be turned off first; wherein the second time period lasts for at least one row scan duration.

[0146] For example, as shown in Figures 6 and 7 , the first reset unit 107 includes a transistor T6. The second time period corresponds to stage t3 in Figure 7 . During stage t3, the first reset signal Vinit1 is set to the third node N3 via transistor T6 and oxide transistor T4 to clear residual charge from the previous displayed frame. This allows the threshold voltage of transistor T3 to be adjusted to improve the accuracy of the drive current. The second time period lasts for at least one row scan duration, thereby fully clearing the charge at the third node N3.

[0147] Before the stage t3, the transistor T6 is turned on first, which can preheat the transistor T6 so that the transistor T6 is more fully turned on during the stage t3, in preparation for writing data into the fifth node N5.

[0148] After the stage t3, the transistor T6 is turned off first, which can prevent the threshold voltage of the transistor T6 from shifting due to voltage fluctuations, thereby improving the accuracy of subsequently writing data to the fifth node N5.

[0149] It should be noted that the driving method provided in the embodiment of the present disclosure is also applicable to the embodiments of Figures 9 and 10, and the embodiments of Figures 11 and 12.

[0150] According to some embodiments, before the second time period, the isolation unit 105 and the first reset unit 107 are turned on at the same time for at least one third time period, and the driving method further includes: before the second time period, controlling the first reset unit 107 to be turned on to transmit the first reset signal to the sixth node; after the first reset unit 107 is turned on, controlling the isolation unit 105 to be turned on for at least a third time period to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one row scan duration.

[0151] For example, in conjunction with Figures 6 and 7, the t2' time period represents the aforementioned third time period. During the t2' time period, the first reset drive signal Reset_n is at a high potential, the polysilicon transistor T5 in the isolation unit 105 and the transistor T6 in the first reset unit 107 are simultaneously turned on, and the first reset signal Vinit1 is written to the fifth node N5 via the polysilicon transistor T5. This can clear any residual charge on the fifth node N5 and adjust the gate stress of the transistor T3 in the drive unit 103 to eliminate the influence of the previous frame displayed on its threshold voltage, thereby improving the accuracy of the drive current and, in turn, improving the afterimage problem on the display screen. There can be multiple third time periods. By setting the potential of the fifth node N5 multiple times, the residual charge on the fifth node N5 can be better cleared, thereby further reducing the possibility of a shift in the threshold voltage of the transistor T3.

[0152] It should be noted that the driving method provided in the embodiment of the present disclosure is also applicable to the embodiments of Figures 9 and 10, and the embodiments of Figures 11 and 12.

[0153] According to some embodiments, the driving method further includes: before controlling the first light emitting control unit 101 and the second light emitting control unit 102 to be turned on, controlling the first light emitting control unit 101 to be turned on earlier than the second light emitting control unit 102 for at least one row scanning duration.

[0154] 11 and 12 , the first light emitting control unit 101 may include a transistor T1, the second light emitting control unit 102 may include a transistor T2, the gate of the transistor T1 receives a first light emitting control signal EM1, and the gate of the transistor T2 receives a second light emitting control signal EM2.

[0155] The simultaneous conduction of transistors T2 and T1 corresponds to stage t7 in FIG. 12 , during which the OLED enters a light-emitting state. Prior to stage t7, i.e., stage T6 in FIG. 2 , transistor T1 is turned on by the first light-emitting control signal EM1, while transistor T2 is turned off by the second light-emitting control signal EM2. The first drive signal VDD can be written to the second node N2 and the third node N3, precharging transistor T3 in the drive unit 103.

[0156] It should be noted that during stage t6, by precharging the second node N2, the precharged charge at the second node N2 can be quickly transferred to the capacitor of the OLED during the subsequent stage t7, thereby increasing the OLED's light emission rate. Furthermore, stage t6 lasts for at least one line scan duration to ensure sufficient precharging. This line scan duration can be understood as the time interval between displaying adjacent frames.

[0157] A third aspect of the embodiments of the present disclosure provides a driving circuit for executing the display panel driving method as described in any one of the second aspects.

[0158] For example, FIG14 is a schematic structural block diagram of a driving circuit connection relationship provided in an embodiment of the present disclosure. As shown in FIG14, the driving circuit may include an EOA (Emission gate ON Array) circuit and a GOA (Gate ON Array) circuit. Taking FIG3 as an example, the EOA circuit is the emission array driving circuit 200, which is used to provide the emission control signal EM to the pixel circuit 100. The GOA1 circuit is the first gate array driving circuit 300, which is used to provide the first gate driving signal to the pixel circuit 100, such as Ngate in FIG3. The GOA2 circuit is the second gate array driving circuit 400, which is used to provide the second gate driving signal to the pixel circuit 100, such as Pgate in FIG3.

[0159] It should be noted that the driving circuit may transmit the control signal to the pixel circuit 100 under the control of the driving chip in the display panel, or under other control modes, such as a remote controller, etc., which is not specifically limited.

[0160] A fourth aspect of an embodiment of the present disclosure provides a display device. FIG15 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. As shown in FIG15 , the above-mentioned display device 1000 includes a display panel as in any one of the first aspect; and / or a driving circuit as in the third aspect.

[0161] For example, the display device 1000 provided in the embodiment of the present disclosure can be applied to scenarios such as vehicle-mounted display, smart phone, computer, medical display, television, smart wearable display, etc., and the embodiment of the present disclosure does not make specific limitations.

[0162] It can be understood that the display device 1000 provided in the embodiment of the present disclosure includes any display panel in the first aspect, and therefore also has all the beneficial effects of the above-mentioned display panels, which will not be elaborated.

[0163] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display panel, comprising a plurality of pixel circuits, wherein the pixel circuits include: A first light emitting control unit, the first light emitting control unit is electrically connected between a first node and a second node, and the first node is used to receive a first driving signal; a second light emitting control unit, wherein the second light emitting control unit is electrically connected between the third node and the fourth node; a driving unit, wherein the driving unit is electrically connected to the second node, the third node and the fifth node respectively; A first data writing unit, the first data writing unit is electrically connected between the third node and the sixth node, and the first data writing unit includes an oxide transistor; an isolation unit, the isolation unit being electrically connected between the fifth node and the sixth node, the isolation unit comprising a polysilicon transistor; a light emitting unit, one end of which is electrically connected to the fourth node, and the other end of which is used to receive a second driving signal; There is a first time period in which the first data writing unit and the isolation unit are turned on at the same time, and after the first time period, the isolation unit is turned off before the first data unit.

2. The display panel according to claim 1, wherein: The oxide transistor of the first data writing unit is in a saturation region during the first time period.

3. The display panel according to claim 1, wherein: The oxide transistor of the first data writing unit is of N type; The polysilicon transistor of the isolation unit is of P type; Before the first time period, the rising edge of the gate signal of the oxide transistor is located before the falling edge of the gate signal of the polysilicon transistor; After the first time period, a falling edge of the gate signal of the oxide transistor is located after a rising edge of the polysilicon transistor.

4. The display panel according to claim 1, wherein the pixel circuit further comprises: a first reset unit, the first reset unit being electrically connected to the sixth node, and the first reset unit being configured to transmit a first reset signal to the sixth node; There is a second time period in which the first data writing unit and the first reset unit are turned on at the same time, and before the second time period, the first reset unit is turned on before the first data writing unit, and after the second time period, the first reset unit is turned off before the first data writing unit, and the second time period does not overlap with the first time period.

5. The display panel according to claim 4, wherein: Before the second time period, there is at least one third time period in which the isolation unit and the first reset unit are turned on simultaneously, and before the third time period, the first reset unit is turned on before the isolation unit.

6. The display panel according to claim 4, wherein the pixel circuit further comprises: a second data writing unit, the second data writing unit being electrically connected to the second node, and the second data writing unit being used to transmit a data signal to the second node; The second data writing unit has the same switching state as the isolation unit.

7. The display panel according to claim 6, wherein the pixel circuit further comprises: a second reset unit, the second reset unit being electrically connected to the fourth node, and the second reset unit being used to transmit a second reset signal to the fourth node; A third reset unit is electrically connected to the second node, and is used to reset the first node. The second node transmits a third reset signal; A capacitor, one end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the fifth node.

8. The display panel according to claim 7, wherein: The first reset unit includes an oxide transistor; and / or, The second data writing unit includes a polysilicon transistor; and / or, The second reset unit includes a polysilicon transistor; and / or, The third reset unit includes a polysilicon transistor; and / or, The first light emitting control unit comprises a polysilicon transistor; and / or, The second light emitting control unit comprises a polysilicon transistor; and / or, The driving unit includes a polysilicon transistor.

9. The display panel according to claim 8, wherein: In the case where the driving unit is a P-type polysilicon transistor, the potential of the third reset signal is greater than the potential of the first driving signal; In the case where the driving unit is an N-type polysilicon transistor, the potential of the third reset signal is lower than the potential of the first driving signal.

10. The display panel according to any one of claims 1 to 9, wherein: The first light emitting control unit is turned on for at least one row scanning duration before the second light emitting control unit is turned on.

11. A method for driving a display panel, applied to the display panel according to any one of claims 1 to 10, the method comprising: Controlling the first data writing unit and the isolation unit to be turned on, so that the first data writing unit and the isolation unit are turned on at the same time in the first time period, and transmitting the write data to the driving unit; After the first time period, controlling to disconnect the isolation unit first and then disconnect the first data writing unit; The first light emitting control unit and the second light emitting control unit are controlled to be turned on, so that the light emitting unit emits light under the action of the first driving signal and the second driving signal.

12. The method for driving a display panel according to claim 11, wherein when the pixel circuit comprises a first reset unit, and there is a second time period in which the first data writing unit and the first reset unit are turned on at the same time, the method further comprises: Before the second time period, controlling the first reset unit to be turned on first; After the second time period, controlling the first reset unit to be disconnected first; The second time period lasts for at least one row scanning duration.

13. The method for driving a display panel according to claim 12, wherein before the second time period, the isolation unit and the first reset unit are simultaneously turned on for at least one third time period, and the method further comprises: Before the second time period, controlling the first reset unit to be turned on to transmit a first reset signal to the sixth node; After the first reset unit is turned on, the isolation unit is controlled to be turned on for at least one of the third time periods to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one row scanning duration.

14. The method for driving a display panel according to any one of claims 11 to 13, further comprising: Before controlling the first light emitting control unit and the second light emitting control unit to be turned on, the first light emitting control unit is controlled to be turned on earlier than the second light emitting control unit for at least one row scanning duration.

15. A driving circuit, used for executing the driving method of the display panel according to any one of claims 11 to 14.

16. A display device, comprising the display panel according to any one of claims 1 to 10; and / or, The driving circuit as claimed in claim 15.

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