Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area and a peripheral area surrounding the display area. The peripheral area comprises a first bezel area, a second bezel area, a third bezel area, and a fourth bezel area. The display substrate further comprises at least one first binding electrode group, a first initialization signal bus, a second initialization signal bus, a third initialization signal bus, and a plurality of initialization signal lines. The first binding electrode group is located in the third bezel area; the first initialization signal bus is arranged in the first bezel area; the second initialization signal bus is arranged in the second bezel area; the third initialization signal bus is arranged in the third bezel area; the third initialization signal bus is connected to the first initialization signal bus and the second initialization signal bus, and is connected to the first binding electrode group; the plurality of initialization signal lines are at least arranged in the display area. The display substrate is used for displaying an image.

Description

Display substrate and display device

[0001] This application claims priority to Chinese patent application No. 202311599718.2 filed on November 27, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] With the continuous development of display technology, display devices have become increasingly ubiquitous in people's lives. Organic Light-Emitting Diode (OLED) display panels, in particular, are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response speed, and high contrast. High refresh rates are currently a key development trend for display devices.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first border area, a second border area, a third border area, and a fourth border area. The first border area and the second border area are disposed on either side of the display area along a first direction, and the third border area and the fourth border area are disposed on either side of the display area along a second direction, with the first direction and the second direction intersecting.

[0006] The display substrate further includes at least one first binding electrode group, a first initialization signal bus, a second initialization signal bus, a third initialization signal bus, and a plurality of initialization signal lines. The first binding electrode group is located in the third border area, and each first binding electrode group is used to connect to a driver chip; a first initialization signal bus is provided in the first border area; a second initialization signal bus is provided in the second border area; and a third initialization signal bus is provided in the third border area; the third initialization signal bus is connected to the first initialization signal bus and the second initialization signal bus, and is also connected to the first binding electrode group; and a plurality of initialization signal lines are provided in at least the display area and are connected to the first initialization signal bus, the second initialization signal bus, and the third initialization signal bus.

[0007] In some embodiments, the display substrate further includes a data write transistor, a second reset transistor, a second scan signal line, and a second reset control signal line. The gate of the data write transistor is electrically connected to the second scan signal line, and the gate of the second reset transistor is electrically connected to the second reset control signal line.

[0008] The second scan signal line has a first refresh frequency, the second reset control signal line has a second refresh frequency, and the second refresh frequency is greater than the first refresh frequency.

[0009] In some embodiments, the display substrate further includes at least one initialization signal first connection line group. Each of the initialization signal first connection line groups includes a plurality of initialization signal first connection lines, and the plurality of initialization signal first connection lines are located in the third border region and between the first binding electrode group and the third initialization signal bus, and are configured to connect the first binding electrode group and the third initialization signal bus.

[0010] In some embodiments, the display substrate further includes a first source / drain metal layer and a second source / drain metal layer stacked together. The third initialization signal bus and the first initialization signal connection line group are located in the first source / drain metal layer or the second source / drain metal layer; or, one of the third initialization signal bus and the first initialization signal connection line group is located in the first source / drain metal layer, and the other is located in the second source / drain metal layer.

[0011] In some embodiments, the initialization signal lines include a plurality of first initialization signal lines extending along the second direction and a plurality of second initialization signal lines extending along the first direction. The plurality of first initialization signal lines extend to the third border area and are connected to the third initialization signal bus. The plurality of second initialization signal lines extend to the first border area and the second border area and are connected to the first initialization signal bus and the second initialization signal bus, respectively. The plurality of first initialization signal lines are connected to the plurality of second initialization signal lines.

[0012] In some embodiments, the display substrate further comprises two stacked source / drain metal layers. The third initialization signal bus and the plurality of first initialization signal lines are located in different source / drain metal layers; and the plurality of first initialization signal lines and the plurality of second initialization signal lines are located in different source / drain metal layers.

[0013] In some embodiments, the display substrate further includes a plurality of light-emitting devices, a first voltage signal bus, and a plurality of first voltage signal lines extending along the second direction. The first voltage signal bus is disposed in the third border region and is located on one side of the third initialization signal bus in the second direction; the first voltage signal bus is connected to the cathode of the light-emitting device; the first voltage signal line is disposed at least in the display region and extends to the third border region, the plurality of first voltage signal lines being connected to the first voltage signal bus; and in the third border region, the plurality of first initialization signal lines and the plurality of first voltage signal lines are alternately disposed along the first direction.

[0014] In some embodiments, the display substrate further comprises two stacked source / drain metal layers, wherein the first voltage signal bus and the third initialization signal bus are located in the same source / drain metal layer, and the first voltage signal bus and the plurality of first voltage signal lines are located in different source / drain metal layers.

[0015] In some embodiments, the display substrate further comprises a plurality of pixel circuits, a reference voltage signal bus, and a plurality of reference voltage signal lines extending along the second direction. The pixel circuit comprises a drive transistor, a write transistor, and a first reset transistor, wherein the drive transistor, the write transistor, and the first reset transistor are electrically connected to a first node, and the first reset transistor is configured to transmit a reference voltage signal to the first node; the reference voltage signal bus is disposed in a third border region and is located on one side of a third initialization signal bus along the second direction; the reference voltage signal bus is configured to transmit a reference voltage signal; a plurality of reference voltage signal lines are disposed at least in the display region and extend to the third border region, the plurality of reference voltage signal lines being connected to the reference voltage signal bus; and in the third border region, a plurality of the first initialization signal lines and a plurality of the reference voltage signal lines are alternately disposed along the first direction.

[0016] In some embodiments, the display substrate further comprises two stacked source / drain metal layers. The reference voltage signal bus and the third initialization signal bus are located in the same source / drain metal layer; and the reference voltage signal bus and the plurality of reference voltage signal lines are located in different source / drain metal layers.

[0017] In some embodiments, the display substrate further includes at least one second binding electrode group and a fourth initialization signal bus. The second binding electrode group is located in the fourth border region and is used to connect to a driver chip. The fourth initialization signal bus is located in the fourth border region and is connected to the first initialization signal bus, the second initialization signal bus, and the second binding electrode group. The multiple initialization signal lines are also connected to the fourth initialization signal bus.

[0018] In some embodiments, the display substrate further includes a second initialization signal connection line group. The second initialization signal connection line group includes a plurality of second initialization signal connection lines located in the fourth border region and between the second binding electrode group and the fourth initialization signal bus, and is configured to connect the second binding electrode group and the fourth initialization signal bus.

[0019] In another aspect, a display device is provided, comprising: a display substrate as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0021] FIG1 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0022] FIG2A is an equivalent circuit diagram of a pixel driving circuit provided by some embodiments of the present disclosure;

[0023] FIG2B is a timing signal control diagram of a pixel driving circuit provided by some embodiments of the present disclosure;

[0024] FIG3 is a structural diagram of a display substrate according to some embodiments of the present disclosure;

[0025] FIG4 is a schematic diagram showing horizontal stripes generated on the display substrate in FIG3 ;

[0026] FIG5 is another structural diagram of a display substrate according to some embodiments of the present disclosure;

[0027] FIG6 is another structural diagram of a display substrate according to some embodiments of the present disclosure;

[0028] FIG7 is a partial structural diagram of area B in FIG5 ;

[0029] FIG8 is another structural diagram of a display substrate according to some embodiments of the present disclosure;

[0030] FIG. 9 is another structural diagram of a display substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0032] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0033] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0034] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0035] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0036] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0037] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0038] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0039] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0040] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0041] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0042] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 can be any product or component with a display function, such as a television, a monitor, a laptop computer, a tablet computer, a mobile phone, or a navigator. FIG1 illustrates the display device 1000 as a mobile phone.

[0043] Exemplarily, the display device 1000 may be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0044] For example, the display device 1000 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0045] In some embodiments, the display device 1000 may be a low temperature polycrystalline oxide (LTPO) display device, which can support multiple refresh rates, such as from 120 Hz to 1 Hz.

[0046] In some embodiments, the display device 1000 includes a display substrate 100 .

[0047] The structure of the display substrate 100 is described in detail below.

[0048] As shown in Figures 3 and 5, Figure 3 is a structural diagram of a display substrate 100' provided in some embodiments, and Figure 5 is a structural diagram of a display substrate 100 provided in some embodiments of the present disclosure. The display substrate 100 includes a display area AA and a peripheral area AN surrounding the display area AA. The peripheral area AN includes a first border area 11, a second border area 12, a third border area 13, and a fourth border area 14. The first border area 11 and the second border area 12 are arranged on both sides of the display area AA along the first direction X, and the third border area 13 and the fourth border area 14 are arranged on both sides of the display area AA along the second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y are perpendicular.

[0049] It should be noted that the display area AA of the display substrate 100 is used to display images. In order to realize the image display function of the display substrate 100, a display device is provided in the display area AA.

[0050] The following takes the display substrate 100 as an OLED display substrate as an example to schematically illustrate some embodiments of the present disclosure, but the implementation methods of the present disclosure include but are not limited to this, and any other display substrates can also be considered as long as the same technical concept is applied.

[0051] In some embodiments, a plurality of pixel units are provided in the display area AA, and each pixel unit includes at least three sub-pixels P. The sub-pixel P is the smallest light-emitting unit in the display area AA.

[0052] Exemplarily, the plurality of pixel units are arranged in a plurality of rows and columns.

[0053] In some examples, the multiple sub-pixels P emit light of the same color, and the display area AA may further include a color filter layer disposed on the light-emitting side of the multiple sub-pixels P.

[0054] For example, multiple sub-pixels P emit light of colors such as white light, red light, green light or blue light. In this case, the color light emitted by the sub-pixel P remains the same color light after passing through the color filter layer, or is converted into light of other colors and emitted. Therefore, when multiple sub-pixels P emit light of the same color, the display area AA can achieve multi-color light output.

[0055] In other examples, multiple sub-pixels P emit light of different colors. For example, multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby achieving multi-color light output in the display area AA.

[0056] It should be noted that each pixel unit includes at least three sub-pixels P, that is, each pixel unit may include three, four or more sub-pixels P, and the multiple sub-pixels P included in each pixel unit may be a row, a column or a group of sub-pixels, and a group of sub-pixels P may be a plurality of sub-pixels P adjacent to each other, and the adjacent multiple sub-pixels P are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc.

[0057] At the same time, the light emitting areas of the multiple sub-pixels P included in each pixel unit may be the same or different. The above is only an exemplary description and is not intended to limit the present disclosure. The specific adaptive design can be made according to actual needs.

[0058] In some embodiments, the sub-pixel includes a pixel driving circuit, as shown in FIG2A , which is a schematic diagram of an equivalent circuit of a pixel driving circuit provided in some embodiments of the present disclosure. It should be noted that FIG2A is an example of an 8T1C structure of the pixel driving circuit for illustration, but the structure of the pixel driving circuit in the present disclosure is not limited thereto. For example, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Wherein, T represents a transistor, and the number in front of T represents the number of transistors, and C represents a capacitor, and the number in front of C represents the number of capacitors.

[0059] Continuing to refer to FIG. 2A , the pixel driving circuit may include eight transistors (transistors T1 to T8 ) and one storage capacitor C.

[0060] The pixel driving circuit may further include a first node N1, a second node N2, a third node N3, and a fourth node N4. It should be noted that in the pixel driving circuit provided in the embodiments of the present disclosure, the nodes do not represent actual components, but rather represent the junction points of related electrical connections in the equivalent circuit diagram of the pixel driving circuit. In other words, these nodes are nodes formed by equivalently connecting the junction points of related electrical connections in the equivalent circuit diagram of the pixel driving circuit.

[0061] Among them, the first node N1 is respectively connected to the gate of the driving transistor T3, the first plate of the storage capacitor C and the source of the threshold compensation transistor T2, the second node N2 is respectively connected to the source of the driving transistor T3, the drain of the first light-emitting control transistor T5, the drain of the data writing transistor T4 and the drain of the third reset transistor T8, the third node N3 is respectively connected to the drain of the first reset transistor T1, the source of the threshold compensation transistor T2, the source of the second light-emitting control transistor T6 and the drain of the driving transistor T3, and the fourth node N4 is respectively connected to the drain of the second light-emitting control transistor T6, the drain of the second reset transistor T7 and the light-emitting device D.

[0062] The second plate of the storage capacitor C is electrically connected to the first power voltage line VDD, and the first plate of the storage capacitor C is connected to the first node N1 , that is, the first plate of the storage capacitor C is connected to the gate of the driving transistor T3 .

[0063] The source of the first reset transistor T1 is configured to be electrically connected to the initialization signal line Vinit to receive the initialization signal, the drain of the first reset transistor T1 is electrically connected to the drain of the driving transistor T3, and the gate of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Preset1 to receive the reset control signal.

[0064] The source of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 , the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3 , and the gate of the threshold compensation transistor T2 is configured to be electrically connected to the first scan signal line Ngate to receive the compensation control signal.

[0065] The gate of the driving transistor T3 is connected to the first plate of the storage capacitor C. The source of the driving transistor T3 is connected to the second node N2. The drain of the driving transistor T3 is connected to the third node N3. The driving transistor T3 determines the magnitude of the driving current flowing between the second voltage signal line VDD and the first voltage signal line VSS based on the potential difference between the gate and source of the driving transistor T3.

[0066] The drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected to the data signal line Data to receive the data signal, and the gate of the data writing transistor T4 is configured to be electrically connected to the second scanning signal line Pgate to receive the scanning signal.

[0067] The source of the first light-emitting control transistor T5 is electrically connected to the second voltage signal line (VDD) 91, the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the light-emitting control signal line EM to receive the light-emitting control signal.

[0068] The source of the second light emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light emitting control transistor T6 is electrically connected to the first electrode of the light emitting device D, and the gate of the second light emitting control transistor T6 is configured to be electrically connected to the light emitting control signal line EM to receive the light emitting control signal.

[0069] The source of the second reset transistor T7 is configured to be electrically connected to the initialization signal line Vinit to receive the initialization signal, the drain of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device D, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Preset2 to receive the reset control signal.

[0070] The source of the third reset transistor T8 is configured to be electrically connected to the reference voltage signal line Vref to receive the reference voltage signal, the drain of the third reset transistor T8 is electrically connected to the source of the driving transistor T3, and the gate of the third reset transistor T8 is configured to be connected to the second reset control signal line Preset2 to receive the reset control signal.

[0071] The second electrode of the light emitting device D is electrically connected to the first voltage signal line (VSS) 62 .

[0072] Among them, the first scanning signal line Ngate is used to transmit the first scanning signal, the second scanning signal line Pgate is used to transmit the second scanning signal, the first reset control signal line Preset1 is used to transmit the first reset control signal, the second reset control signal line is used to transmit the second reset control signal, the second voltage signal line VDD is used to transmit the second voltage signal, for example, a high-voltage DC signal, the initialization signal line Vinit is used to transmit the initialization signal, the data signal line Data is used to transmit the data signal, the light-emitting control signal line EM is used to transmit the light-emitting control signal, and the first voltage signal line VSS is used to transmit the first voltage signal, for example, a low-voltage DC signal.

[0073] For example, transistors T1 to T8 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate 100, and improve the product yield. For example, transistors T1 to T8 may include P-type transistors and N-type transistors, where transistor T2 is an N-type transistor and the remaining transistors are P-type transistors.

[0074] Exemplarily, transistors T1 to T8 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor adopts oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate 100 to form a low-temperature polycrystalline oxide (LTPO) display substrate. By utilizing the advantages of both, the refresh frequency of the display substrate 100 can be switched to achieve low-frequency driving, which is conducive to reducing power consumption and improving display quality.

[0075] When the display substrate 100 switches the refresh frequency, there are usually multiple adjustment methods. One of the adjustment methods is to reduce the refresh frequency based on the basic refresh frequency (i.e., base frequency), and the refresh frequency can generally be reduced by an integer multiple. When the refresh frequency is reduced by an integer multiple, it can be called interpolation frequency modulation. In the interpolation method, the display frame of the basic refresh frequency includes a write frame. The display frame after the refresh frequency is reduced based on the basic refresh frequency includes a write frame and a hold frame, and the write frame and the hold frame have the same duration. In other words, the refresh frequency of the display substrate 100 is reduced by inserting a hold frame between adjacent write frames, and the reduction multiple of the refresh frequency is changed by changing the number of hold frames inserted between adjacent write frames. For example, if the basic refresh frequency is 120HZ, the refresh frequency is reduced to 60HZ after inserting one hold frame, and the refresh frequency is reduced to 40HZ after inserting two hold frames, and so on. The switching between two different refresh frequencies can be switching between the basic refresh frequency and the refresh frequency after the basic refresh frequency is reduced, or it can be switching between two refresh frequencies after the same basic refresh frequency is reduced.

[0076] For example, when the content to be displayed on the display substrate 100 (such as a video) requires a higher refresh frequency, such as a frequency of 120 Hz, that is, it is refreshed 120 times per second, the data writing of all rows of pixels is completed between each two refreshes (1s / 120), and the time between starting the data writing of the pixel driving circuit of the first row in the display area AA and completing the data writing of the pixel driving circuit of the last row corresponds to the time length of one display frame. Therefore, in this case 1s includes 120 display frames.

[0077] For another example, when the content to be displayed on the display substrate 100 (such as a still image) does not require a high refresh rate, a refresh rate of 1 Hz is sufficient, that is, the display data is updated only once per second. The duration of the display frame remains unchanged for different data refresh rates. Thus, in the first display frame (referred to as the write frame) of the display cycle (e.g., 1 second), data is written to the pixel driver circuits of all rows. In subsequent display frames (referred to as the hold frame), each pixel driver circuit continues to control the light-emitting element D to emit light based on the voltage on its storage capacitor C and the light-emitting control signal EM.

[0078] 2A and 2B , which is a timing signal control diagram of a pixel driving circuit according to some embodiments of the present disclosure, the second scan signal line Pgate has a first refresh frequency, and the second reset control signal line Preset2 has a second refresh frequency.

[0079] The second refresh frequency is greater than the first refresh frequency. The first refresh frequency may be 120 Hz, and the second refresh frequency may be 360 ​​Hz.

[0080] It is understood that the refresh frequency of the display substrate 100 is consistent with the frequency at which data signals are written, that is, the refresh frequency of the display substrate 100 is the first refresh frequency of the second scan signal line Pgate. Each time the second scan signal line Pgate is refreshed and a data signal is written, the second reset control signal line Preset2 is also refreshed to write an initialization signal and reset the first electrode of the light-emitting device D. This prevents the data signal written in the previous frame from affecting the data signal written in the current frame, which could result in poor light uniformity across the display substrate 100. When the first refresh frequency of the second scan signal line Pgate and the second refresh frequency of the second reset control signal line Preset2 are the same, to switch the refresh frequency of the display substrate 100 (e.g., to reduce the refresh frequency), it is necessary to simultaneously change the first refresh frequency of the second scan signal line Pgate and the second refresh frequency of the second reset control signal line Preset2. This means that it is necessary to reduce the base refresh frequency by an integer multiple by adding hold frames (i.e., the aforementioned interpolation frequency modulation). For example, when the first refresh frequency can be 120 Hz, it is possible to switch between refresh frequencies of 30 Hz, 40 Hz, or 60 Hz to ensure that each time the second scan signal line Pgate is refreshed, the second reset control signal line Preset2 is also refreshed. This results in significant changes to the signal waveforms of the signal lines. Furthermore, since the refresh frequency of the display substrate 100 is reduced, and both the first and second refresh frequencies are reduced, screen flickering may occur, affecting the display quality.

[0081] The second refresh frequency of the second reset control signal line Preset2 is set to be greater than the first refresh frequency of the second scan signal line Pgate, for example, set to three times the original frequency, 360 Hz. This can support more refresh frequency switching and improve screen flicker. As shown in FIG2B , the second refresh frequency of the second reset control signal line Preset2 is relatively high, that is, the signal transmitted by the second reset control signal line has an operating level during each frame phase, which can reset the first electrode of the light-emitting device D. To switch the refresh frequency of the display substrate 100 (for example, to reduce the refresh frequency), only the first refresh frequency of the second scan signal line Pgate needs to be changed, without changing the second refresh frequency of the second reset control signal line Preset2. This also ensures that the second reset control signal line Preset2 is refreshed every time the second scan signal line Pgate is refreshed. This simplifies the modification of the signal line timing signal. At the same time, because the first electrode of the light-emitting device D is reset during each frame phase, a visual screen refresh effect is achieved, thereby improving the screen flicker problem caused by the reduced refresh rate of the display substrate 100.

[0082] In some embodiments, the first scan signal line Ngate has a first refresh frequency, and the first reset control signal line Preset1 has a second refresh frequency. When the second scan signal line Pgate refreshes the write data signal, the first scan signal line Ngate also needs to be refreshed, turning on the threshold compensation transistor T2 for threshold compensation. When the second reset control signal line Preset2 resets the fourth node N4, the first reset control signal line Preset1 also refreshes and resets the third node N3. Therefore, the principles for setting the refresh frequencies of the first scan signal line Ngate and the first reset control signal line Preset1 are consistent with those for the second scan signal line Pgate and the second reset control signal line Preset2, and are not further described here. The operating principles of the pixel driving circuit when the display substrate 100 switches the refresh frequency will be described below in conjunction with Figures 2A and 2B. It should be noted that the timing diagram in Figure 2B is for the case where a high refresh frequency is not required (also called low-frequency display). When a high refresh frequency is required, the driving timing of each display frame (for example, 120 display frames within 1s) is the same as the timing of the write frame described in Figure 2B, and will not be repeated here.

[0083] In the scenario of low-frequency display of the display device, each three adjacent frame stages form a group. The first frame stage in a group is a writing frame stage, which is responsible for writing the display signal and emitting light. The second frame stage and the third frame stage are both holding frame stages, which are responsible for emitting light based on the display signal written in the writing frame stage. The driving process of the above-mentioned pixel driving circuit is divided into a writing frame stage and a holding frame stage:

[0084] In the write frame phase, a write frame phase includes a first reset phase t1, a data refresh and compensation phase t2, a second reset phase t3, and a first light-emitting phase t4. In the first reset phase t1, the threshold compensation transistor T2 is turned on under the control of the first scan signal, and the first reset transistor T1 is turned on under the control of the first reset control signal, so that the initialization signal is written to the first node N1, thereby resetting the first node N1.

[0085] At this time, the driving transistor T3 is turned on, the writing transistor T4, the first light emission control transistor T5 and the second light emission control transistor T6 are all in the off state, and the light emitting device OLED does not emit light.

[0086] During the data refresh and compensation phase t2, the first reset transistor T1 is turned off under the control of the first reset control signal, the threshold compensation transistor T2 remains on, the write transistor T4 is turned on under the control of the second scan signal, and the drive transistor T3 maintains the on-state of the first reset phase t1. Therefore, the data signal can be sequentially transmitted to the first node N1 through the write transistor T4, the drive transistor T3, and the threshold compensation transistor T2, causing the voltage of the first node N1 to change until the voltage of the first node N1 reaches the sum of the threshold voltage of the drive transistor T3 and the voltage of the data signal Data, turning off the drive transistor T3. During the data refresh and compensation phase t2, the threshold voltage of the drive transistor T3 can be written to the first node N1 to compensate for threshold voltage drift of the drive transistor T3, thereby preventing changes in the drive signal generated by the drive transistor and preventing an impact on the luminous intensity of the light-emitting device D. During this phase, the first and second emission control transistors T5 and T6 are turned off under the control of the emission control signal.

[0087] In the second reset stage t3, the compensation transistor T2 is disconnected under the control of the first scan signal, the write transistor T4 is disconnected under the control of the second scan signal, and the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal, so that the initialization signal is written into the second node N2 and the anode of the light-emitting device D, thereby resetting the second node N2 and the anode of the light-emitting device D (the fourth node N4).

[0088] In the first light-emitting stage t4, the second reset transistor T7 and the third reset transistor T8 are disconnected under the control of the second reset control signal, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal, so that the first voltage signal is written into the first electrode region of the driving transistor T3, and the anode voltage of the light-emitting device D can be written into the second electrode region of the driving transistor T3, so that the driving transistor T3 is turned on, thereby forming a path between the first power supply voltage line VDD and the light-emitting device D, so that the light-emitting device D emits light.

[0089] In the holding frame phase, each holding frame phase includes a third reset phase t5, a fourth reset phase t6, and a light emitting phase t7. In the third reset phase t5, the threshold compensation transistor T2 is turned on under the control of the first scanning signal, and the first reset transistor T1 is turned on under the control of the first reset control signal, so that the initialization signal is written to the first node N1, thereby resetting the first node N1.

[0090] In the fourth reset stage t6, the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal, so that the initialization signal is written into the anode of the second node N2 and D, thereby resetting the second node N2 and the anode of the light-emitting device D (the fourth node N4).

[0091] In the second light-emitting stage t7, the second reset transistor T7 and the third reset transistor T8 are disconnected under the control of the second reset control signal, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal, thereby causing the first voltage signal to be written into the first electrode region of the driving transistor T3, and the anode voltage of the light-emitting device D to be written into the second electrode region of the driving transistor T3, thereby causing the driving transistor T3 to be turned on, thereby forming a path between the first power supply voltage line VDD and the light-emitting device D, causing the light-emitting device D to emit light.

[0092] As can be seen from the driving process of the pixel driving circuit described above, during each reset phase, the initialization signal transmitted by the initialization signal line (Vinit) 40 resets the first node N1, the second node N2, the third node N3, or the fourth node N4, thereby changing the potential of these nodes, thereby raising or lowering the potential of the corresponding nodes of each pixel driving circuit to a uniform potential. This prevents interference sources in the display substrate from interfering with the potential of the nodes of each pixel driving circuit, which could cause uneven display brightness. Therefore, the routing of the initialization signal line is very important for the accuracy and uniformity of the transmitted initialization signal.

[0093] The following describes in detail the wiring method of the initialization signal line (Vinit) 40 in the display substrate 100 .

[0094] As shown in Figure 3, the display substrate 100' includes a first binding electrode group 21, a first initialization signal bus 31, a second initialization signal bus 32, and initialization signal lines 40. The first binding electrode group 21 is located in the third border region 13 and is used to connect to the driver chip 10. The first initialization signal bus 31 is provided in the first border region 11; the second initialization signal bus 32 is provided in the second border region 12. A plurality of initialization signal lines 40 are provided in at least the display area AA and are connected to the first initialization signal bus 31 and the second initialization signal bus 32.

[0095] Multiple initialization signal lines 40 introduce initialization signals from both sides of the display area AA through the first initialization signal bus 31 and the second initialization signal bus 32. Due to the existence of resistance on the initialization signal line, a voltage drop will be generated during the transmission of the initialization signal, and there is a difference between the voltage drop at the position of the initialization signal line close to the first border area 11 or the second border area 12 and the voltage drop at the position far away from the first border area 11 or the second border area 12. This will cause the initialization signals transmitted at different positions of the initialization signal line to be uneven, and the initialization signals provided to the pixel driving circuits in each sub-pixel to be inconsistent, resulting in that when the fourth node N4 is reset, the potential of the node is low, so that the corresponding sub-pixel is dark, affecting the display effect.

[0096] In particular, when the second refresh rate of the second reset control signal line Preset2 is relatively high, such as 360 Hz, the reset time of the N4 node will be reduced when the display substrate 100 displays low grayscale images. For example, when the second refresh rate is 360 Hz, the reset time of the N4 node is 1 / 360 s. This will result in insufficient reset of the N4 node when the display substrate 100 displays low grayscale images, causing defects such as horizontal stripes. For example, as shown in FIG. 4 , multiple (three) horizontal stripes appear in the display area AA of the display substrate 100.

[0097] Moreover, in a display substrate 100 of a medium or large size, since the display substrate 100 has a large area, the display area AA of the display substrate 100 is more likely to have multiple (three) stripes as shown in FIG. 4 .

[0098] Based on this, as shown in FIG5 , some embodiments of the present application provide a display substrate 100. The display substrate 100 includes at least one first binding electrode group 21, a first initialization signal bus 31, a second initialization signal bus 32, a third initialization signal bus 33, and a plurality of initialization signal lines 40. At least one first binding electrode group 21 is located in the third frame area 13, and each first binding electrode group 21 is used to connect to a driver chip 10; the first initialization signal bus 31 is provided in the first frame area 11; the second initialization signal bus 32 is provided in the second frame area 12; the third initialization signal bus 33 is provided in the third frame area 13; the third initialization signal bus 33 is connected to the first initialization signal bus 31 and the second initialization signal bus 32, and is also connected to the first binding electrode group 21; the plurality of initialization signal lines 40 are provided at least in the display area AA, and are connected to the first initialization signal bus 31, the second initialization signal bus 32, and the third initialization signal bus 33.

[0099] By providing a third initialization signal bus 33 in the third border region 13, the third initialization signal bus 33 is connected to the first initialization signal bus 31 and the second initialization signal bus 32, and to the binding electrode group 21. In addition to being connected to the first initialization signal bus 31 and the second initialization signal bus 32, the plurality of initialization signal lines 40 are also connected to the third initialization signal bus 33. Initialization signals can be simultaneously transmitted to the initialization signal lines 40 via the first initialization signal bus 31, the second initialization signal bus 32, and the third initialization signal bus 33. Furthermore, portions of the initialization signal lines 40 away from the first initialization signal bus 31 and the second initialization signal bus 32 can receive initialization signals via the third initialization signal bus 33. This can reduce the difference in IR drop across the plurality of initialization signal lines 40 at the center and edge of the display area AA, thereby ensuring that the initialization signals received by the plurality of sub-pixels are consistent, thereby preventing display defects such as horizontal streaks on the display substrate 100.

[0100] Exemplarily, the driver chip 10 can be packaged by using a Chip On Film (COF), Chip On Glass (COG), or Chip On Pi (COP), and bound to the third border area 13. For example, the driver chip 10 can be packaged by using a Chip On Film (COF), and the display substrate 100 includes a Chip On Film assembly, which includes a Flexible Printed Circuit (FPC) and the driver chip 10 bound to the FPC.

[0101] Exemplarily, the display substrate 100 may include one, two, three, four, or more first binding electrode groups 21. For example, as shown in FIG6 , which is another structural diagram of the display substrate 100 provided in some embodiments of the present disclosure, the display substrate 100 may include four first binding electrode groups 21, each of which is connected to a corresponding driver chip 10, i.e., four driver chips 10 are provided. Each of the four first binding electrode groups 21 may be provided in the third border region 13 and respectively connected to the third initialization signal bus 33 to transmit initialization signals, thereby further reducing the voltage drop (IR drop) of the initialization signal line and improving the display effect of the display substrate 100.

[0102] In some embodiments, the third border area 13 of the display substrate 100 includes a non-bending area and a bending area. The bending area is farther away from the display area AA relative to the non-bending area. The third initialization signal bus 33 is located in the non-bending area. Multiple first binding electrode groups 21 are located in the bending area. The bending area can be bent toward the non-display side of the display substrate 100, that is, bent to the back of the display substrate 100 to reduce the border of the display substrate 100. The driving chip 10 is arranged on the back of the display substrate 100, and the driving chip 10 is connected to the first binding electrode group 21 through a flexible circuit board.

[0103] In some embodiments, referring again to FIG. 6 , the display substrate 100 may further include at least one second binding electrode group 22 and a fourth initialization signal bus 34 . The second binding electrode group 22 is located in the fourth border region 14 and is used to connect to the driver chip 10 . The fourth initialization signal bus 34 is also located in the fourth border region 14 and is connected to the first initialization signal bus 31 and the second initialization signal bus 32 , respectively, and to the second binding electrode group 22 . A plurality of initialization signal lines 40 are also connected to the fourth initialization signal bus 34 . On the non-display side of the display substrate 100 , the second binding electrode group 22 is connected to the driver chip 10 in the third border region 13 and transmits initialization signals.

[0104] By providing a fourth initialization signal bus 34 in the fourth border region 14, the fourth initialization signal bus 34 is connected to the first initialization signal bus 31 and the second initialization signal bus 32. That is, the first initialization signal bus 31, the second initialization signal bus 32, the third initialization signal bus 33, and the fourth initialization signal bus 34 are interconnected to form a ring structure. The fourth initialization signal bus 34 is also connected to the second binding electrode group 22 for transmitting the initialization signal. In addition to being connected to the first initialization signal bus 31, the second initialization signal bus 32, and the third initialization signal bus 33, the plurality of initialization signal lines 40 are also connected to the fourth initialization signal bus 34. Initialization signals can be simultaneously transmitted to the initialization signal lines 40 via the first initialization signal bus 31, the second initialization signal bus 32, the third initialization signal bus 33, and the fourth initialization signal bus 34. This can further reduce the difference in IR drop between the initialization signal lines 40 at the center and the edge of the display area AA, thereby preventing display defects such as horizontal streaks on the display substrate 100 and improving the display uniformity of the display substrate 100.

[0105] Exemplarily, the display substrate 100 may include one, two, three, four, or more second binding electrode groups 22. For example, referring to FIG. 6 , the display substrate 100 may include two second binding electrode groups 22, each of which is connected to a corresponding driver chip 10. Both second binding electrode groups 22 may be disposed in the fourth border region 14 and respectively connected to the fourth initialization signal bus 34 to transmit initialization signals, thereby further reducing the voltage drop (IR drop) of the initialization signal line and improving the display effect of the display substrate 100.

[0106] In some embodiments, the fourth border region 14 of the display substrate 100 includes a non-bending region and a bending region, the bending region being farther from the display area AA than the non-bending region. The fourth initialization signal bus 34 is located in the non-bending region, and the plurality of second binding electrode groups 22 are located in the bending region. The bending region can bend toward the non-display side of the display substrate 100, that is, toward the back of the display substrate 100, to reduce the border of the display substrate 100. The driver chip 10 is disposed on the back of the display substrate 100 and is connected to the second binding electrode group 22 via a flexible circuit board disposed on the back of the display substrate 100.

[0107] Exemplarily, the first binding electrode group 21 and the second binding electrode group 22 can be connected to the same driver chip 10. For example, on the back side of the display substrate 100 (i.e., the non-display side of the display substrate 100), the second binding electrode group 22 is connected to the driver chip 10 connected to the first binding electrode group 21 via a flexible circuit board. Because the resistance of the traces in the flexible circuit board is much lower than the resistance of the traces in the display substrate 100, the second binding electrode group 22 is disposed in the fourth border area 14 of the display substrate 100 and bent to the back side of the display substrate 100. The third border area 13 and the fourth border area 14 of the display substrate 100 are connected via the flexible circuit board. This can reduce signal voltage drop, further improve the uniformity of the initialization signal in the display area AA, and thus improve display uniformity.

[0108] In some embodiments, please continue to refer to Figures 5 and 6, the display substrate 100 also includes at least one initialization signal first connection line group 51; each initialization signal first connection line group 51 includes a plurality of initialization signal first connection lines 511, and the plurality of initialization signal first connection lines 511 are located in the third border area 13 and between the first binding electrode group 21 and the third initialization signal bus 33, and are used to connect the first binding electrode group 21 and the third initialization signal bus 33 and transmit the initialization signal.

[0109] By providing a plurality of first initialization signal connection lines 511 to input the initialization signal to the third initialization signal bus 33 , the voltage drop (IR Drop) of the initialization signal on the third initialization signal bus 33 can be reduced, thereby improving the display effect of the display substrate 100 .

[0110] In some examples, as shown in FIG5 , one of the multiple first initialization signal connection lines 511 is also connected to an end of the first initialization signal bus near the third border area, and another of the multiple first initialization signal connection lines 511 is also connected to an end of the second initialization signal bus near the third border area. The initialization signal is transmitted from the first binding electrode group 21 to the first initialization signal bus and the second initialization signal bus through the first initialization signal connection line 511, and is simultaneously transmitted to the third initialization signal bus, thereby realizing signal transmission between the first binding electrode group and the initialization signal bus.

[0111] For example, the number of initialization signal first connection lines 511 in each initialization signal first connection line group 51 can be set to two, three, four, five, seven, eight or nine, as long as sufficient wiring space is ensured and the initialization signal first connection line 511 does not have the risk of short circuit with other metal lines in the display substrate 100, or the multiple initialization signal first connection lines 511 do not overlap or affect each other. No specific limitation is made here.

[0112] In some embodiments, please continue to refer to Figure 6, the display substrate 100 also includes at least one initialization signal second connection line group 52; each initialization signal second connection line group 52 includes a plurality of initialization signal second connection lines 512, and the plurality of initialization signal second connection lines 512 are located in the fourth border area 14 and between the second binding electrode group 22 and the fourth initialization signal bus 34, and are used to connect the second binding electrode group 22 and the fourth initialization signal bus 34 and transmit the initialization signal.

[0113] By providing a plurality of second initialization signal connection lines 512 to input the initialization signal to the fourth initialization signal bus 34 , the voltage drop (IR Drop) of the initialization signal on the fourth initialization signal bus 34 can be reduced, thereby improving the display effect of the display substrate 100 .

[0114] For example, the number of initialization signal second connection lines 512 in each initialization signal second connection line group 52 can be set to two, three, four, five, seven, eight or nine, as long as sufficient wiring space is ensured and the initialization signal second connection lines 512 do not have the risk of short circuit with other metal lines in the display substrate 100, or the multiple initialization signal second connection lines 512 do not overlap or affect each other. No specific limitation is made here.

[0115] 5 and 6 , in some embodiments, the initialization signal lines 40 include a plurality of first initialization signal lines 401 and a plurality of second initialization signal lines 402. Each first initialization signal line 401 extends along the second direction Y to the third border region 13 and is connected to the third initialization signal bus 33. The plurality of first initialization signal lines 401 are arranged sequentially along the first direction X. Each second initialization signal line 402 extends along the first direction X to the first border region 11 and the second border region 12 and is connected to the first initialization signal bus 31 and the second initialization signal bus 32, respectively. The plurality of second initialization signal lines 402 are arranged sequentially along the second direction Y. The plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 are connected to form a mesh structure of the initialization signal lines 40.

[0116] By setting the initialization signal line 40 to a mesh structure, the initialization signals provided by the first initialization signal bus 31, the second initialization signal bus 32 and the third initialization signal bus 33 are dispersedly transmitted through the initialization signal line 40 of the mesh structure, which can further reduce the voltage drop of the initialization signal on the transmission path and improve the uniformity of the initialization signal, thereby further improving the display uniformity and avoiding display defects such as horizontal stripes on the display substrate.

[0117] For example, the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 can be arranged in the same layer or in different layers. When the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 are arranged in the same layer, the two can be arranged as one piece. When the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 are arranged in different layers, the two can be electrically connected by punching or by switching through other conductive parts, without any specific limitation herein.

[0118] In some embodiments, as shown in Figures 7 and 8, Figure 7 is a partial structural diagram of area B in Figure 5. The display substrate 100 also includes a first voltage signal bus 61 and a plurality of first voltage signal lines 62. The first voltage signal bus 61 is arranged in the third border area 13 and is located on one side of the third initialization signal bus 33 in the second direction Y; the first voltage signal bus 61 is connected to the cathode of the light-emitting device and is used to transmit a voltage signal to the light-emitting device. The plurality of first voltage signal lines 62 extend along the second direction Y, are arranged at least in the display area AA, and extend to the third border area 13, and the plurality of first voltage signal lines 62 are connected to the first voltage signal bus 61. In the third border area 13, the plurality of first initialization signal lines 401 and the plurality of first voltage signal lines 62 are alternately arranged along the first direction X.

[0119] The above-mentioned “multiple first initialization signal lines 401 and multiple first voltage signal lines 62 are alternately arranged along the first direction X” includes that each first initialization signal line 401 and each first voltage signal line 62 are regularly alternately arranged along the first direction X. In this case, each initialization signal line 401 is electrically connected to a column of sub-pixels P, and each first voltage signal line 62 is electrically connected to a column of sub-pixels P.

[0120] The above configuration can avoid overlapping of the plurality of first initialization signal lines 401 and the plurality of first voltage signal lines 62 in the third frame area 13 to cause short circuits, and can reduce the difficulty of wiring in the third frame area 13 .

[0121] In some embodiments, referring to FIG. 7 , the display substrate 100 further includes a reference voltage signal bus 71 and a plurality of reference voltage signal lines 72 . The reference voltage signal bus 71 is disposed in the third border region 13 and is located on one side of the third initialization signal bus 33 along the second direction Y. The reference voltage signal bus 71 is configured to transmit a reference voltage signal. The plurality of reference voltage signal lines 72 extend along the second direction Y and are disposed at least in the display area AA and extend to the third border region 13 . The plurality of reference voltage signal lines 72 are connected to the reference voltage signal bus 71 . In the third border region 13 , the plurality of first initialization signal lines 401 and the plurality of reference voltage signal lines 72 are alternately disposed along the first direction X.

[0122] The above-mentioned “multiple first initialization signal lines 401 and multiple reference voltage signal lines 72 are alternately arranged along the first direction X” may mean that the multiple first initialization signal lines 401 and the multiple reference voltage signal lines 72 are regularly alternately arranged along the first direction X. In this case, each initialization signal line 401 is electrically connected to a column of sub-pixels P, and each reference voltage signal line 72 is electrically connected to a column of sub-pixels P.

[0123] The above arrangement can avoid overlapping of the plurality of first initialization signal lines 401 and the plurality of reference voltage signal lines 72 in the third frame area 13 to cause short circuits, and can reduce the difficulty of wiring in the third frame area 13 .

[0124] 7 , in the third border region 13 , a plurality of first initialization signal lines 401 , a plurality of first voltage signal lines 62 , and a plurality of reference voltage signal lines 72 are alternately arranged along the first direction X. This arrangement prevents the plurality of first initialization signal lines 401 , the plurality of first voltage signal lines 62 , and the plurality of reference voltage signal lines 72 from overlapping in the third border region 13 and causing a short circuit, and reduces the difficulty of wiring in the third border region 13 .

[0125] The above-mentioned “multiple first initialization signal lines 401, multiple first voltage signal lines 62, and multiple reference voltage signal lines 72 are alternately arranged along the first direction X” may mean that multiple first initialization signal lines 401, multiple first voltage signal lines 62, and multiple reference voltage signal lines 72 are regularly alternately arranged along the first direction X. For example, one first initialization signal line 401, one first voltage signal line 62, and one reference voltage signal line 72 form a group and are regularly alternately arranged along the first direction X, which is conducive to maintaining good wiring repeatability.

[0126] Alternatively, the plurality of first initialization signal lines 401, the plurality of first voltage signal lines 62, and the plurality of reference voltage signal lines 72 may be arranged alternately and irregularly along the first direction X. For example, the signal line wiring pattern corresponding to one pixel unit may be one first initialization signal line 401, one first voltage signal line 62, and one first initialization signal line 401, and the signal line wiring pattern corresponding to another pixel unit adjacent to the aforementioned pixel unit may be one first initialization signal line 401 and two reference voltage signal lines 72. In some embodiments, the display substrate further includes a plurality of data signal lines 81 and a plurality of second voltage signal lines 91 extending along the second direction Y. The plurality of data signal lines 81 and the plurality of second voltage signal lines 91 are arranged in the display area AA and extend to the third frame area 13. As shown in FIG7 , the plurality of data signal lines 81 and the plurality of second voltage signal lines 91 are arranged alternately in the first direction X. Each data signal line 81 is electrically connected to a column of sub-pixels P, and each second voltage signal line 91 is electrically connected to a column of sub-pixels P.

[0127] In some embodiments, as shown in Figure 7, in the third border area 13, multiple first initialization signal lines 401 and multiple data signal lines 81 are alternately arranged along the first direction X, which can avoid the multiple first initialization signal lines 401 and the multiple data signal lines 81 overlapping in the third border area 13 to cause a short circuit, and can reduce the difficulty of wiring in the third border area 13.

[0128] In some embodiments, as shown in Figure 7, in the third border area 13, multiple first initialization signal lines 401 and multiple second voltage signal lines 91 are alternately arranged along the first direction X, which can avoid the multiple first initialization signal lines 401 and the multiple second voltage signal lines 91 overlapping in the third border area 13 to cause a short circuit, and can reduce the difficulty of wiring in the third border area 13.

[0129] In some embodiments, the display substrate 100 may include multiple metal layers stacked together, and the above-mentioned third initialization signal bus 33, the initialization signal first connection line group 51, multiple first initialization signal lines 401, the first voltage signal bus 61, multiple first voltage signal lines 62, the reference voltage signal bus 71 and the multiple reference voltage signal lines 72 are arranged in the above-mentioned multiple metal layers.

[0130] For example, the multiple metal layers can be fabricated in the same layer as the metal layers of the transistors in the pixel driving circuit. It should be noted that "the multiple metal layers are fabricated in the same layer as the metal layers in the TFT" means that the multiple metal layers and the metal layers in the TFT are formed simultaneously through the same patterning process, and the "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. Deposition can be performed by any one or more selected from sputtering, evaporation, and chemical vapor deposition, coating can be performed by any one or more selected from spray coating and spin coating, and etching can be performed by any one or more selected from dry etching and wet etching.

[0131] Exemplarily, the display substrate 100 may be a low-temperature polycrystalline oxide (LTPO) substrate. As shown in FIG9 , FIG9 is a structural diagram of a display substrate 100 provided in some embodiments of the present disclosure. The display substrate 100 includes a first active layer (Poly), a first gate metal layer (Gate1), a second gate metal layer (Gate2), a second active layer (not shown), a third gate metal layer (Gate3), a first source / drain metal layer (SD1), a first planarization layer (PLN1), a second source / drain metal layer (SD2), and a second planarization layer (PLN2), which are sequentially arranged and insulated from each other on a base substrate 101.

[0132] Exemplarily, the substrate 101 may be a flexible substrate, such as a plastic substrate having excellent heat resistance and durability, such as polyvinyl ether phthalate, polyarylate, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin polymer (COP), cellulose acetate propionate (CAP), polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallyl ester, or cellulose triacetate (TAC); or it may be a rigid substrate, such as a glass substrate, without any specific limitation herein.

[0133] Exemplarily, the materials of the first flat layer (PLN1) and the second flat layer (PLN2) can be organic insulating materials such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., without any specific limitation.

[0134] For example, the metal film layers, such as the first gate metal layer (Gate1), the second gate metal layer (Gate2), the third gate metal layer (Gate3), the first source / drain metal layer (SD1), and the second source / drain metal layer (SD2), can be made of materials suitable for dry etching, such as molybdenum (Mo), aluminum (Al), and titanium (Ti). Alternatively, the metal film layers can be single-layer metals or stacked metals. For example, the first gate metal layer (Gate1), the second gate metal layer (Gate2), and the third gate metal layer (Gate3) can be single-layer molybdenum metals, and the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2) can be triple-layered, consisting of a titanium metal layer, an aluminum metal layer, and a titanium metal layer.

[0135] In some embodiments, referring to Figures 6 and 9, the third initialization signal bus 33 and the initialization signal first connection line group 51 are located in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the initialization signal first connection line group 51 are arranged in the same layer, and can be set at the same time in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2).

[0136] In other embodiments, one of the third initialization signal bus 33 and the initialization signal first connection line group 51 is located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the initialization signal first connection line group 51 are arranged in different layers. When the third initialization signal bus 33 is arranged in the first source-drain metal layer (SD1), the initialization signal first connection line group 51 is arranged in the second source-drain metal layer (SD2); when the third initialization signal bus 33 is arranged in the second source-drain metal layer (SD2), the initialization signal first connection line group 51 is arranged in the first source-drain metal layer (SD1).

[0137] In some embodiments, the third initialization signal bus 33 and one of the multiple first initialization signal lines 401 are located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the first initialization signal line 401 are arranged in different layers. When the third initialization signal bus 33 is set in the first source-drain metal layer (SD1), the first initialization signal line 401 is set in the second source-drain metal layer (SD2); when the third initialization signal bus 33 is set in the second source-drain metal layer (SD2), the first initialization signal line 401 is set in the first source-drain metal layer (SD1).

[0138] In some embodiments, one of the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 is located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2). That is, the first initialization signal line 401 and the second initialization signal line 402 can be arranged in different layers. When the first initialization signal line 401 is arranged in the first source-drain metal layer (SD1), the second initialization signal line 402 is arranged in the second source-drain metal layer (SD2); when the first initialization signal line 401 is arranged in the second source-drain metal layer (SD2), the second initialization signal line 402 is arranged in the first source-drain metal layer (SD1). When the first initialization signal line 401 or the second initialization signal line 402 is arranged in the second source-drain metal layer (SD2), the capacitance at the overlapping position with the signal line arranged in the underlying metal layer (e.g., the first gate metal layer, the second gate metal layer, or the third gate metal layer) can be reduced, which helps to further reduce the voltage drop of the first initialization signal line 401 or the second initialization signal line 402 and further improve display uniformity.

[0139] In some embodiments, please continue to refer to Figure 7, the third initialization signal bus 33 and the first voltage signal bus 61 can be located in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the first voltage signal bus 61 are set in the same layer, and can be set at the same time in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2).

[0140] In some embodiments, please continue to refer to Figure 7, the first voltage signal bus 61 and one of the multiple first voltage signal lines 62 are located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the first voltage signal bus 61 and the first voltage signal line 62 can be set in different layers. When the first voltage signal bus 61 is set in the first source-drain metal layer (SD1), the first voltage signal line 62 is set in the second source-drain metal layer (SD2); when the first voltage signal bus 61 is set in the second source-drain metal layer (SD2), the first voltage signal line 62 is set in the first source-drain metal layer (SD1).

[0141] In some embodiments, please continue to refer to Figure 7, the third initialization signal bus 33 and the reference voltage signal bus 71 can be located in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the reference voltage signal bus 71 are set in the same layer, and can be set at the same time in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2).

[0142] In some embodiments, please continue to refer to Figure 7, the reference voltage signal bus 71 and one of the multiple reference voltage signal lines 72 are located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the reference voltage signal bus 71 and the reference voltage signal line 72 can be set in different layers. When the reference voltage signal bus 71 is set in the first source-drain metal layer (SD1), the reference voltage signal line 72 is set in the second source-drain metal layer (SD2); when the reference voltage signal bus 71 is set in the second source-drain metal layer (SD2), the reference voltage signal line 72 is set in the first source-drain metal layer (SD1).

[0143] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: a display area and a peripheral area surrounding the display area; The peripheral area includes a first frame area, a second frame area, a third frame area and a fourth frame area, the first frame area and the second frame area are arranged on both sides of the display area along a first direction, the third frame area and the fourth frame area are arranged on both sides of the display area along a second direction, and the first direction intersects with the second direction; The display substrate further comprises: At least one first binding electrode group, located in the third border area, each of the first binding electrode groups is used to connect to a driving chip; A first initialization signal bus, arranged in the first border area; A second initialization signal bus, arranged in the second border area; a third initialization signal bus, arranged in the third border area; the third initialization signal bus is connected to the first initialization signal bus and the second initialization signal bus, and is connected to the first binding electrode group; A plurality of initialization signal lines are at least arranged in the display area and connected to the first initialization signal bus, the second initialization signal bus and the third initialization signal bus.

2. The display substrate according to claim 1, wherein: The display substrate further includes a data writing transistor, a second reset transistor, a second scanning signal line, and a second reset control signal line; The gate of the data writing transistor is electrically connected to the second scanning signal line; The gate of the second reset transistor is electrically connected to the second reset control signal line; The second scan signal line has a first refresh frequency, the second reset control signal line has a second refresh frequency, and the second refresh frequency is greater than the first refresh frequency.

3. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises at least one initialization signal first connection line group; Each of the initialization signal first connection line groups includes a plurality of initialization signal first connection lines, which are located in the third frame area and between the first binding electrode group and the third initialization signal bus, and are used to connect the first binding electrode group and the third initialization signal bus.

4. The display substrate according to claim 3, wherein: The display substrate further comprises a first source-drain metal layer and a second source-drain metal layer which are stacked; The third initialization signal bus and the first initialization signal connection line group are located in the first source-drain metal layer or the second source-drain metal layer; Alternatively, one of the third initialization signal bus and the initialization signal first connection line group is located in the first source-drain metal layer, and the other is located in the second source-drain metal layer.

5. The display substrate according to any one of claims 1 to 4, wherein: The plurality of initialization signal lines include: a plurality of first initialization signal lines extending along the second direction, the plurality of first initialization signal lines extending to the third frame area and connected to the third initialization signal bus, a plurality of second initialization signal lines extending along the first direction, the plurality of second initialization signal lines extending to the first frame area and the second frame area, and connected to the first initialization signal bus and the second initialization signal bus respectively; A plurality of the first initialization signal lines and a plurality of the second initialization signal lines are connected.

6. The display substrate according to claim 5, wherein: The display substrate further comprises two source-drain metal layers stacked in layers; The third initialization signal bus and the plurality of first initialization signal lines are located in different source-drain metal layers; The plurality of first initialization signal lines and the plurality of second initialization signal lines are located in different source-drain metal layers.

7. The display substrate according to any one of claims 5 to 6, wherein: The display substrate further comprises: Multiple light emitting devices: A first voltage signal bus, arranged in the third border area; located on one side of the third initialization signal bus in the second direction; the first voltage signal bus is connected to the cathode of the light emitting device; a plurality of first voltage signal lines extending along the second direction, at least arranged in the display area and extending to the third frame area, the plurality of first voltage signal lines being connected to the first voltage signal bus; In the third frame area, the plurality of first initialization signal lines and the plurality of first voltage signal lines are alternately arranged along a first direction.

8. The display substrate according to claim 7, wherein: The display substrate further comprises two source-drain metal layers stacked in layers; The first voltage signal bus and the third initialization signal bus are located in the same source-drain metal layer; The first voltage signal bus and the plurality of first voltage signal lines are located in different source-drain metal layers.

9. The display substrate according to any one of claims 5 to 6, wherein: The display substrate also includes: A plurality of pixel circuits, the pixel circuits comprising a driving transistor, a writing transistor and a first reset transistor, the driving transistor, the writing transistor and the first reset transistor being electrically connected to a first node, the first reset transistor being configured configured to transmit a reference voltage signal to the first node; A reference voltage signal bus is arranged in the third frame area and is located on one side of the third initialization signal bus along the second direction; the reference voltage signal bus is configured to transmit a reference voltage signal; A plurality of reference voltage signal lines extending along the second direction are at least arranged in the display area and extend to the third frame area, and the plurality of reference voltage signal lines are connected to the reference voltage signal bus; In the third frame area, a plurality of the first initialization signal lines and a plurality of the reference voltage signal lines are alternately arranged along the first direction.

10. The display substrate according to claim 9, wherein: The display substrate further comprises two source-drain metal layers stacked in layers; The reference voltage signal bus and the third initialization signal bus are located in the same source-drain metal layer; The reference voltage signal bus and the plurality of reference voltage signal lines are located in different source-drain metal layers.

11. The display substrate according to any one of claims 1 to 10, wherein: The display substrate further comprises: at least one second binding electrode group, located in the fourth border area, the second binding electrode group is used to connect the driving chip; a fourth initialization signal bus, located in the fourth border area, the fourth initialization signal bus being connected to the first initialization signal bus and the second initialization signal bus, and being connected to the second binding electrode group; The plurality of initialization signal lines are also connected to a fourth initialization signal bus.

12. The display substrate according to claim 11, wherein: The display substrate further comprises a second connection line group for initialization signals; The initialization signal second connection line group includes a plurality of initialization signal second connection lines, which are located in the fourth frame area and between the second binding electrode group and the fourth initialization signal bus, and are used to connect the second binding electrode group and the fourth initialization signal bus.

13. A display device, comprising: The display substrate according to any one of claims 1 to 12; At least one driving chip is connected to the at least one first binding electrode group respectively.

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