Manufacturing method for solar cell, and solar cell

Abstract

The present application relates to a manufacturing method for a solar cell, and a solar cell. The manufacturing method for the solar cell comprises: preparing a first silicon material layer on a surface of a substrate; laser-etching the first silicon material layer to form an etched area on the first silicon material layer, so as to form a laser-etched product; performing annealing processing on the etched area of the laser-etched product, to prepare an annealed product; and wet-etching the etched area of the annealed product. The annealing processing can improve the crystallization rate of the first silicon material layer in the etched area, so that the etching difficulty of the etched area in subsequent wet etching can be reduced, thereby facilitating the reduction of the risk of incomplete etching during the wet etching.

Description

Method for preparing solar cell and solar cell

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 29, 2023, with application number 2023116195297 and invention name “Method for preparing solar cells and solar cells”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0003] During the production of solar cells, laser etching is often used to pattern the silicon material layer, followed by wet etching to remove the remaining silicon material layer in the laser-etched area. However, during this production process, laser etching may induce amorphization of the silicon material layer, reducing the crystallization rate of the silicon material layer remaining in the laser-etched area, thereby increasing the difficulty of wet etching and the risk of incomplete etching during the wet etching process.

[0004] Summary of the Invention

[0005] Based on this, it is necessary to provide a method for preparing a solar cell and a solar cell, wherein the method for preparing a solar cell can reduce the risk of incomplete etching during a wet etching process.

[0006] A method for preparing a solar cell comprises the following steps:

[0007] preparing a first silicon material layer on the surface of the substrate;

[0008] performing laser etching on the first silicon material layer to form an etched area on the first silicon material layer to prepare a laser-etched product;

[0009] performing an annealing treatment on the etched region of the laser-etched product to prepare an annealed product; wherein the crystallization rate of the first silicon material layer in the etched region of the annealed product is greater than the crystallization rate of the first silicon material layer in the etched region of the laser-etched product;

[0010] The etched region of the annealed product is wet-etched.

[0011] In some embodiments, a crystallization rate of the first silicon material layer in the etched region of the annealed product is greater than a crystallization rate of the first silicon material layer in the etched region of the laser-etched product.

[0012] In some embodiments, the crystallization rate of the first silicon material layer in the etched region of the annealed product is 60% to 90%.

[0013] In some embodiments, the crystallization rate of the first silicon material layer in the etched region of the laser etched product is 10% to 30%.

[0014] In some embodiments, the annealing treatment is performed at a temperature of 400°C to 950°C.

[0015] In some embodiments, the annealing treatment lasts for 5 minutes to 30 minutes.

[0016] In some embodiments, the atmosphere gas used in the annealing process includes at least one of a protective gas and oxygen.

[0017] In some embodiments, before wet etching the etched region of the annealed product, the method further includes: acid etching the etched region of the annealed product.

[0018] In some embodiments, the acid etching is performed using a first etching solution; the first etching solution includes hydrofluoric acid.

[0019] In some embodiments, the mass percentage of the hydrofluoric acid in the first etching solution is 0.01% to 2%.

[0020] In some embodiments, the temperature of the first etching solution is 10°C to 50°C.

[0021] In some embodiments, the acid etching time is 5s to 120s.

[0022] In some embodiments, the wet etching is performed using a second etching solution; the second etching solution includes an alkaline solute.

[0023] In some embodiments, the alkaline solute includes at least one of potassium hydroxide and sodium hydroxide.

[0024] In some embodiments, the mass percentage of the alkaline solute in the second etching solution is 2% to 50%.

[0025] In some embodiments, the temperature of the second etching solution is 60°C to 90°C.

[0026] In some embodiments, the wet etching time is 100s to 700s.

[0027] In some embodiments, the first silicon material layer includes a first silicon base material and a first doping element doped in the first silicon base material.

[0028] In some embodiments, the doping concentration of the first doping element in the first silicon material layer is 4×10 19 / cm3 ~1×10 20 / cm 3 .

[0029] In some embodiments, the first doping element includes boron; the laser etching increases the doping concentration of the boron element on the surface of the first silicon material layer; and the annealing treatment reduces the doping concentration of the boron element on the surface of the first silicon material layer.

[0030] In some embodiments, preparing the first silicon material layer includes: preparing a first intrinsic polysilicon layer on the surface of the substrate; and performing a first doping treatment on the first intrinsic polysilicon layer to dope the first doping element into the first intrinsic polysilicon layer.

[0031] In some embodiments, after wet etching the etched area of ​​the annealed product, the method further includes: preparing a second silicon material layer in the etched area, the second silicon material layer including a second silicon substrate and a second doping element doped in the second silicon substrate; the second doping element and the first doping element are of opposite types, and there is a gap between the second silicon material layer and the first silicon material layer.

[0032] In some embodiments, the concentration of the second doping element in the second silicon material layer is 1×10 20 / cm 3 ~6×10 20 / cm 3 .

[0033] In some embodiments, preparing the second silicon material layer includes: preparing a second intrinsic polysilicon layer in the etched area; and performing a second doping treatment on the second intrinsic polysilicon layer to dope the second doping element into the second intrinsic polysilicon layer.

[0034] A solar cell is prepared by the preparation method.

[0035] In the above-mentioned solar cell fabrication method, after laser etching, the etched area of ​​the laser-etched product is annealed. This annealing treatment can improve the crystallization rate of the first silicon material layer in the etched area, thereby reducing the difficulty of subsequent wet etching in the etched area and helping to reduce the risk of incomplete etching during the wet etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] 1 to 11 are schematic structural diagrams of products corresponding to corresponding steps in a method for preparing a solar cell according to an embodiment of the present application.

[0037] FIG12 is a surface morphology diagram of the solar cells in Example 1 and Comparative Example 1.

[0038] FIG13 is an ECV curve of the solar cell in Example 1.

[0039] FIG14 is a Raman spectrum of the solar cell in Example 1.

[0040] Description of the marks in the figure:

[0041] 10. Substrate; 20. Silicon oxide layer; 30. First silicon material layer; 301. Etching area; 302. Silicon oxide layer; 40. First doped layer; 50. Second doped layer; 60. Passivation layer; 70. Gate line. DETAILED DESCRIPTION

[0042] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar modifications without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0043] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] One embodiment of the present application provides a method for fabricating a solar cell. The method includes the following steps: forming a first silicon material layer 30 on a surface of a substrate 10; performing laser etching on the first silicon material layer 30 to form an etched region 301 on the first silicon material layer 30, thereby producing a laser-etched product; annealing the etched region of the laser-etched product to produce an annealed product; and wet etching the etched region of the annealed product.

[0047] In the solar cell fabrication method of this embodiment, after laser etching, the etched area of ​​the laser-etched product is annealed. This annealing process can improve the crystallization rate of the first silicon material layer in the etched area, thereby reducing the difficulty of subsequent wet etching in the etched area and helping to reduce the risk of incomplete etching during the wet etching process.

[0048] It is understandable that the first silicon material layer may be a polysilicon layer, a doped polysilicon layer, an amorphous silicon layer, or a doped amorphous silicon layer.

[0049] In some embodiments, the crystallization rate of the first silicon material layer in the etched region of the annealed product is greater than the crystallization rate of the first silicon material layer in the etched region of the laser-etched product.

[0050] In some embodiments, the crystallization rate of the first silicon material layer in the etched area can be increased from 10% to 30% to 60% to 90% through annealing.

[0051] In some embodiments, the crystallization rate of the first silicon material layer in the etched area of ​​the annealed product is 60% to 90%. The crystallization rate of the first silicon material layer in the etched area of ​​the laser-etched product is 10% to 30%. Alternatively, the crystallization rate of the first silicon material layer in the etched area of ​​the annealed product can be 60%, 70%, 80%, 90%, etc. The crystallization rate of the first silicon material layer in the etched area of ​​the laser-etched product can be 10%, 20%, 30%, etc.

[0052] In some embodiments, the crystallization rate of the first silicon material layer is 50% to 85%. For example, the crystallization rate of the first silicon material layer can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, etc.

[0053] Optionally, the substrate 10 may be an N-type silicon substrate. Further, optionally, the resistivity of the N-type silicon substrate is 1 Ω·m to 7 Ω·m. For example, the resistivity of the N-type silicon substrate is 1 Ω·m, 2 Ω·m, 3 Ω·m, 4 Ω·m, 5 Ω·m, 6 Ω·m, 7 Ω·m, etc. Further, optionally, the thickness of the N-type silicon substrate is 120 μm to 200 μm. For example, the thickness of the N-type silicon substrate may be 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, etc.

[0054] It is understandable that before forming the first silicon material layer 30 on the surface of the substrate 10 , the substrate 10 may be cleaned to remove mechanical damage and dirt on the surface of the substrate 10 .

[0055] It is understood that, referring to Figures 1 and 2, during the solar cell manufacturing process, when forming the first silicon material layer 30 on the surface of the substrate 10, low-pressure chemical vapor deposition (LPCVD) can be used to form the first silicon material layer 30 on the surface of the substrate 10. Optionally, the thickness of the first silicon material layer 30 is 100 nm to 400 nm. Further optionally, the thickness of the first silicon material layer 30 can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, etc.

[0056] It is also understood that when preparing a solar cell, a silicon oxide layer 20 can be grown on the surface of the substrate 10, and the silicon oxide layer 20 serves as a tunneling layer. Then, a first intrinsic polysilicon layer 30 is formed on the surface of the silicon oxide layer 20. Optionally, the thickness of the silicon oxide layer 20 is 1 nm to 2 nm.

[0057] It is also understood that the first silicon material layer 30 can be patterned by laser etching. The etched region 301 represents the region of the first silicon material layer 30 after laser etching. Laser etching may reduce the crystallization rate of the first silicon material layer remaining in the etched region 301, resulting in increased difficulty in subsequent wet etching, which may lead to the problem of incomplete wet etching. Annealing treatment can increase the crystallization rate of the first silicon material layer 30 in the etched region 301, thereby reducing the difficulty of subsequent wet etching in the etched region 301, which helps reduce the risk of incomplete etching during the wet etching process.

[0058] It is also understandable that when the etched area 301 of the laser-etched product is annealed, the entire laser-etched product may be annealed. Optionally, the annealing process may be tubular annealing or chain annealing.

[0059] In some embodiments, the annealing temperature is 400° C. to 950° C. Alternatively, the annealing temperature may be 400° C., 450° C., 500° C., 550° C., 600° C., 650° C., 700° C., 750° C., 800° C., 850° C., 900° C., 950° C., etc. Alternatively, the annealing temperature is 850° C. to 950° C.

[0060] In some embodiments, the annealing treatment time is 5 min to 30 min. Alternatively, the annealing treatment time can be 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, etc. Alternatively, the annealing treatment time is 20 min to 25 min.

[0061] It is understood that the annealing temperature refers to the temperature at which the laser-etched product is kept warm, and the annealing time refers to the time during which the laser-etched product is kept warm.

[0062] In some embodiments, after the annealing treatment, the laser etched product is cooled to room temperature at a cooling rate of 2°C / min to 50°C / min. Alternatively, the cooling rate can be 2°C / min, 5°C / min, 8°C / min, 10°C / min, 15°C / min, 20°C / min, 25°C / min, 30°C / min, 35°C / min, 40°C / min, 45°C / min, 50°C / min, etc.

[0063] In some embodiments, the atmosphere gas used in the annealing process includes at least one of a protective gas and oxygen. Alternatively, the protective gas may include at least one of nitrogen and argon. Further optionally, the atmosphere gas used in the annealing process includes at least one of nitrogen, argon, and oxygen.

[0064] In some embodiments, before wet etching the etched area of ​​the annealed product, the process further includes: acid etching the etched area of ​​the annealed product. When laser etching the first silicon material layer 30, silicon oxide may be generated under the action of the thermal radiation of the laser, that is, a silicon oxide layer 302 may be formed in the etched area 301, as shown in Figure 3. The silicon oxide layer 302 formed in the etched area 301 will have a certain impact on the subsequent wet etching, making the wet etching more difficult, thereby increasing the risk of incomplete etching. By acid etching the etched area of ​​the annealed product, the silicon oxide layer 302 generated in the etched area 301 can be removed, thereby reducing the impact of the silicon oxide layer 302 on subsequent wet etching and reducing the risk of incomplete etching. Optionally, the acid etching method includes chain acid etching or trough acid etching.

[0065] In some embodiments, the acid etching is performed using a first etching solution. The first etching solution includes hydrofluoric acid. Optionally, the mass percentage of hydrofluoric acid in the first etching solution is 0.01% to 2%. For example, the mass percentage of hydrofluoric acid in the first etching solution can be 0.01%, 0.05%, 0.08%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, 0.8%, 0.9%, 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, etc.

[0066] In some embodiments, the temperature of the first etching solution is 10° C. to 50° C. For example, the temperature of the first etching solution can be 10° C., 15° C., 20° C., 25° C., 30° C., 35° C., 40° C., 45° C., 50° C., etc.

[0067] In some embodiments, the acid etching time is 5 seconds to 120 seconds. Alternatively, the acid etching time can be 10 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, 60 seconds, 70 seconds, 80 seconds, 90 seconds, 100 seconds, 110 seconds, 120 seconds, etc.

[0068] In some embodiments, wet etching is performed using a second etching solution. The second etching solution includes an alkaline solute. Optionally, the wet etching is alkaline etching. Optionally, the alkaline solute includes at least one of potassium hydroxide and sodium hydroxide. Further optionally, the mass percentage of the alkaline solute in the second etching solution is 2% to 50%. For example, the mass percentage of the alkaline solute in the second etching solution can be 2%, 5%, 8%, 10%, 15%, 20%, 30%, 40%, 50%, etc. As an example, the product obtained after wet etching is shown in Figure 4.

[0069] In some embodiments, the temperature of the second etching solution is 60°C to 90°C. For example, the temperature of the second etching solution can be 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, etc. Optionally, the wet etching time is 100s to 700s. For example, the wet etching time can be 100s, 200s, 300s, 400s, 500s, 600s, etc. Further, after the wet etching, the depth of the etched area is 1μm to 10μm.

[0070] In some embodiments, the first silicon material layer includes a first silicon substrate and a first doping element doped in the first silicon substrate. Optionally, the doping concentration of the first doping element in the first silicon material layer is 4×10 19 / cm 3 ~1×10 20 / cm 3Optionally, the doping concentration of the first doping element in the first silicon material layer may be 4×10 19 / cm 3 , 5×10 19 / cm 3 , 6×10 19 / cm 3 , 7×10 19 / cm 3 , 8×10 19 / cm 3 , 9×10 19 / cm 3 Optionally, the doping concentration of the first doping element in the first silicon material layer represents the doping concentration of the first doping element at a doping depth less than or equal to 0.3 μm. It is understood that the doping depth represents the depth extending from the laser-etched surface of the first silicon material layer into the interior of the first silicon material layer.

[0071] In some embodiments, the first doping element includes boron. Laser etching increases the doping concentration of boron on the surface of the first silicon material layer. Annealing reduces the doping concentration of the boron on the surface of the first silicon material layer. Laser etching causes the boron to migrate toward the laser-etched surface of the first silicon material layer, thereby increasing the doping concentration of the boron on the surface of the first silicon material layer. Annealing redistributes the boron in the first silicon material layer, thereby reducing the doping concentration of the boron on the surface of the first silicon material layer. That is, annealing can redistribute the boron in the first silicon material layer, which can lay the foundation for improving the difficulty of wet etching and help reduce the difficulty of alkaline etching. Optionally, when the doping depth is less than or equal to 0.2 μm, laser etching increases the doping concentration of the boron within the doping depth of the first silicon material layer. Annealing reduces the doping concentration of the boron within the doping depth of the first silicon material layer.

[0072] Optionally, preparing the first silicon material layer includes: preparing a first intrinsic polycrystalline silicon layer on the surface of the substrate. Performing a first doping treatment on the first intrinsic polycrystalline silicon layer to dope a first doping element into the first intrinsic polycrystalline silicon layer. As an exemplary structure, as shown in FIG5 , after the first intrinsic polycrystalline silicon layer undergoes the first doping treatment, the first silicon material layer can be represented by a first doped layer 40. It will be understood that the silicon oxide layer 20 in the etched region 301 in FIG5 is a tunneling layer grown on the surface of the substrate 10.

[0073] It is understandable that the first doping treatment of the first intrinsic polysilicon layer can be performed using a conventional doping treatment method. For example, by performing P-type doping on the first intrinsic polysilicon layer, borosilicate glass can be formed on the surface of the first intrinsic polysilicon layer, causing boron atoms to diffuse into the first intrinsic polysilicon layer, thereby obtaining a first doped layer. The borosilicate glass in the etched area is removed during subsequent laser etching and acid etching (such as hydrofluoric acid etching). The borosilicate glass outside the etched area can be etched during acid etching (such as hydrofluoric acid etching), and the residual thickness of the borosilicate glass after acid etching can be 5nm to 30nm.

[0074] In some embodiments, after wet etching the etched area of ​​the annealed product, the method further includes: preparing a second silicon material layer in the etched area, the second silicon material layer including a second silicon substrate and a second doping element doped in the second silicon substrate. The second doping element is of an opposite type to the first doping element, and a gap exists between the second silicon material layer and the first silicon material layer. By preparing the second silicon material layer, a first silicon material layer and a second silicon material layer spaced apart can be formed on the same surface of the substrate, and the first silicon material layer and the second silicon material layer have opposite doping types. Optionally, the second doping element is an N-type doping element.

[0075] It is understandable that the second silicon material layer may be a polysilicon layer, a doped polysilicon layer, an amorphous silicon layer, or a doped amorphous silicon layer.

[0076] In some embodiments, the concentration of the second doping element in the second silicon material layer is 1×10 20 / cm 3 ~6×10 20 / cm 3 Alternatively, the concentration of the second doping element in the second silicon material layer may be 1×10 20 / cm 3 , 2×10 20 / cm 3 , 3×10 20 / cm 3 , 4×10 20 / cm 3 , 5×10 20 / cm 3 , 6×10 20 / cm 3 wait.

[0077] In some embodiments, the preparation of the second silicon material layer includes: preparing a second intrinsic polysilicon layer in the etched area, and performing a second doping process on the second intrinsic polysilicon layer to dope a second doping element into the second intrinsic polysilicon layer.

[0078] It is understood that the second doping treatment of the second intrinsic polysilicon layer can be performed using conventional doping methods. For example, N-type doping of the second intrinsic polysilicon layer can form phosphosilicate glass on the surface of the second intrinsic polysilicon layer, causing phosphorus atoms to diffuse into the second intrinsic polysilicon layer, thereby forming a second doped layer. The phosphosilicate glass can then be removed by laser etching, wet etching, or other methods.

[0079] Optionally, the second intrinsic polysilicon layer has a thickness of 100 nm to 400 nm, and the thickness of the second intrinsic polysilicon layer can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, etc.

[0080] It will be appreciated that after the second intrinsic polysilicon layer undergoes the second doping treatment, the second silicon material layer can be represented by a second doped layer 50. Referring to Figures 6 and 8 , the positional relationship between the second doped layer 50 and the first doped layer 40 during the preparation of the second doped layer 50 in one embodiment is illustrated. The second doped layer 50 can be formed on the etched region 301 and the first doped layer 40. The second doped layer 50 is then patterned using methods such as laser etching and wet etching to obtain the structure shown in Figure 8 , wherein a gap is provided between the first doped layer 40 and the second doped layer 50.

[0081] Please refer to Figure 7, which shows the upper layer treatment of two opposite surfaces of the substrate during the preparation of a solar cell in one embodiment. During the preparation of the solar cell, the first intrinsic polysilicon, the first doping treatment, the second intrinsic polysilicon and the second doping treatment are respectively performed simultaneously on the two opposite surfaces of the substrate. Among them, a silicon oxide layer 20, a first doping layer 40, a silicon oxide layer 20 and a second doping layer 50 are sequentially formed on one surface of the substrate. It can be understood that the oxide layer 20 can be used as a tunneling layer with a thickness of 1nm to 2nm. These layers on the surface are then removed by single-sided etching, thereby obtaining the structure shown in Figure 6. Optionally, acid etching is used for single-sided etching, and further optionally, chain acid etching is used for single-sided etching.

[0082] In some embodiments, after preparing the second doping layer 50 , the process further includes: performing a texturing process on the product to form a pyramid-shaped texturing structure on the surface of the substrate. The corresponding product structure after texturing is shown in FIG9 .

[0083] Furthermore, the texturing process further includes forming a passivation layer on the surface of the product. As shown in Figure 10, a passivation layer 60 is formed on the surface of the product after texturing. Optionally, the passivation layer can include at least one of aluminum oxide and silicon nitride. Further, aluminum oxide can be formed by atomic layer deposition. Silicon nitride can be formed by plasma-enhanced chemical vapor deposition.

[0084] Furthermore, after forming the passivation layer, the process further includes forming a gate line 70 on the first doping layer 40 and the second doping layer 50. As shown in FIG11 , the gate line 70 is formed on the first doping layer 40 and the second doping layer 50. Optionally, the gate line can be formed by screen printing.

[0085] Another embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0086] S01: Pre-clean the N-type silicon wafer to remove mechanical damage and dirt from the surface. The resistivity of the silicon wafer is 1Ω·m to 7Ω·m. The thickness of the silicon wafer is 120μm to 200μm.

[0087] S02: growing a silicon oxide layer (ie, a tunneling layer) on two opposite surfaces of the silicon wafer, wherein the thickness of the silicon oxide layer is 1 nm to 2 nm.

[0088] S03: Depositing a first intrinsic polysilicon layer on the surface of the silicon oxide layer by low pressure chemical vapor deposition (LPCVD), wherein the thickness of the first intrinsic polysilicon layer is 100 nm to 400 nm.

[0089] S04: Perform boron doping on the first intrinsic polysilicon layer to prepare a first doped layer. The concentration of boron in the first doped layer is 4×10 19 / cm 3 ~1×10 20 / cm 3 .

[0090] S05: performing laser etching on the first doping layer on one of the surfaces to form an etching area on the first doping layer, thereby preparing a laser etching product.

[0091] S06: Annealing the laser-etched product to prepare an annealed product. The annealing temperature is 400° C. to 950° C. The annealing time is 5 minutes to 30 minutes. The atmosphere gas used in the annealing includes at least one of an inert gas and oxygen.

[0092] S07: The etched area of ​​the annealed product is etched with hydrofluoric acid. The etching solution includes hydrofluoric acid, and the mass percentage of hydrofluoric acid in the etching solution is 0.01% to 2%. The hydrofluoric acid etching time is 5 seconds to 120 seconds.

[0093] S08: Performing alkaline etching on the product after hydrofluoric acid etching. The alkaline solute in the etching solution used in the alkaline etching includes at least one of potassium hydroxide and sodium hydroxide. The alkaline solute accounts for 2% to 50% by mass of the etching solution.

[0094] S09: Depositing a second intrinsic polysilicon layer on the surface of the product after alkaline etching by low pressure chemical vapor deposition (LPCVD), wherein the thickness of the second intrinsic polysilicon layer is 100 nm to 400 nm.

[0095] S10: The second intrinsic polysilicon layer is subjected to phosphorus doping treatment to prepare a second doped layer. The concentration of phosphorus in the second doped layer is 1×10 20 / cm 3 ~6×10 20 / cm 3 The structure shown in Figure 7 is obtained.

[0096] S11: Single-side etching is performed on the surface opposite to the surface etched by laser in S05 to remove the second doping layer, phosphosilicate glass, etc. on this surface, thereby obtaining the structure shown in FIG6 .

[0097] S12: Laser-etching the surface that was laser-etched in S05 to separate the first doped layer from the second doped layer, thereby obtaining the structure shown in FIG8 .

[0098] S13: Texturing the product obtained in S12 to obtain the structure shown in FIG9 .

[0099] S14: forming a passivation layer on the surface of the product obtained in S13, obtaining a structure as shown in FIG10. The passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence in a direction away from the substrate.

[0100] S15: Screen-printing grid lines on the surface of the product obtained in S14 to obtain the structure shown in FIG11 .

[0101] Another embodiment of the present application provides a solar cell, which is prepared by the above-mentioned preparation method.

[0102] Example

[0103] Example 1

[0104] S101: Pre-clean the N-type silicon wafer to remove mechanical damage and dirt from the surface. The resistivity of the silicon wafer is 5 Ω·cm. The thickness of the silicon wafer is 150μm.

[0105] S102: growing a silicon oxide layer (ie, a tunneling layer) on two opposite surfaces of the silicon wafer, wherein the thickness of the silicon oxide layer is 1.4 nm.

[0106] S103: Depositing a first intrinsic polysilicon layer on the surface of the silicon oxide layer by low pressure chemical vapor deposition (LPCVD). The thickness of the first intrinsic polysilicon layer is 300 nm.

[0107] S104: Perform boron doping on the first intrinsic polysilicon layer to prepare a first doped layer. The concentration of boron in the first doped layer is 7×10 19 / cm 3 .

[0108] S105: performing laser etching on the first doping layer on one of the surfaces to form an etching area on the first doping layer, thereby preparing a laser etching product.

[0109] S106: Annealing the laser-etched product to prepare an annealed product. The annealing temperature is 800° C. and the annealing time is 20 minutes. The annealing atmosphere includes at least one of an inert gas and oxygen.

[0110] S107: Perform hydrofluoric acid etching on the etched area of ​​the annealed product. The etching solution includes hydrofluoric acid, and the mass percentage of hydrofluoric acid in the etching solution is 1%. The hydrofluoric acid etching time is 10 seconds. The temperature of the etching solution is 20°C.

[0111] S108: The product after hydrofluoric acid etching is subjected to alkaline etching. The alkaline solute in the etching solution used for alkaline etching includes at least one of potassium hydroxide and sodium hydroxide. The alkaline solute accounts for 10% by mass of the etching solution. The temperature of the etching solution is 65° C. and the etching time is 300 seconds.

[0112] S109: Depositing a second intrinsic polysilicon layer on the surface of the product after alkaline etching by low pressure chemical vapor deposition (LPCVD). The thickness of the second intrinsic polysilicon layer is 300 nm.

[0113] S110: Perform phosphorus doping on the second intrinsic polysilicon layer to prepare a second doped layer. The concentration of phosphorus in the second doped layer is 3×10 20 / cm 3 .

[0114] S111: Single-side etching is performed on the surface opposite to the surface etched by laser in S105 to remove the second doping layer, phosphorus silicon glass, etc. on this surface.

[0115] S112: performing laser etching on the surface that was laser-etched in S105 to separate the first doped layer from the second doped layer.

[0116] S113: performing texturing treatment on the product obtained in S112.

[0117] S114: forming a passivation layer on the surface of the product obtained in S113. The passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence in a direction away from the product.

[0118] S115: Screen-printing grid lines on the surface of the product obtained in S114.

[0119] Example 2 to Example 6

[0120] Compared with Example 1, the difference between Examples 2 to 6 is that the temperature and / or time of the annealing treatment in S106 are different, as shown in Table 1.

[0121] Comparative Example 1

[0122] Compared with Example 1, the difference of Comparative Example 1 is that steps S106 and S107 are not performed. In S108, the product obtained in S105 is subjected to alkaline etching.

[0123] Table 1

[0124] Test Case

[0125] (1) The surfaces of the solar cells obtained in Examples 1 to 6 and Comparative Example 1 were analyzed. The surface morphology of the cell obtained in Comparative Example 1 after alkaline etching is shown in Figure 12a, and the surface morphology of the cell obtained in Example 1 after alkaline etching is shown in Figure 12b. As can be seen from Figure 12, the cell surface after alkaline etching in Example 1 is cleaner, and the problem of incomplete etching has been greatly improved. The surface conditions of alkaline etching in Examples 2 to 6 are shown in Table 1. In Table 1, whether the alkaline etching is clean indicates whether the cell surface is clean after alkaline etching. As can be seen from Table 1, alkaline etching in Examples 2 to 6 can achieve good etching effects.

[0126] (2) The battery performance obtained in Example 1 and Comparative Example 1 was tested. The results are shown in Table 2. It is understood that in Table 2, Eta represents conversion efficiency. Voc represents open-circuit voltage. Jsc represents short-circuit current. FF represents fill factor. Rsh represents parallel resistance. Rs represents series resistance. As can be seen from Table 2, Example 1 has higher conversion efficiency and yield than Comparative Example 1.

[0127] Table 2

[0128] (3) The electrochemical capacitance-voltage method (ECV) was used to test the doping concentration of boron in the etched areas of the batteries of Examples 1 to 6 after S104, S105 and S106. The ECV curve obtained for the battery of Example 1 is shown in FIG13. As can be seen from FIG13, laser etching will increase the concentration of boron on the surface of the product, which may affect the effect of alkaline etching. After annealing, the concentration of boron on the surface of the product is redistributed and the concentration decreases, which can reduce the difficulty of alkaline etching and improve the effect of alkaline etching. The changes in doping concentration of Examples 2 to 6 are shown in Table 1. Among them, the doping concentration before annealing in Table 1 represents the doping concentration of boron before annealing after laser etching, and the doping concentration after annealing represents the doping concentration of boron after annealing. As can be seen from Table 1, after annealing in Examples 2 to 6, the concentration of boron on the surface of the product is redistributed and the concentration decreases, which can reduce the difficulty of alkaline etching and improve the effect of alkaline etching.

[0129] (4) Raman spectroscopy (Raman) was used to test the crystallization rate of the etched areas in the batteries of Examples 1 to 6 after S104, S105 and S106. The Raman spectrum obtained from the battery of Example 1 is shown in Figure 14. As can be seen from Figure 14, after laser etching, the crystallization rate of the intrinsic polysilicon layer decreases, which may increase the difficulty of alkaline etching. After annealing, the crystallization rate of the intrinsic polysilicon layer increases, which is conducive to reducing the difficulty of alkaline etching and improving the effect of alkaline etching. The changes in the crystallization rate of Examples 2 to 6 are shown in Table 1. Among them, the crystallization rate before annealing in Table 1 represents the crystallization rate before annealing after laser etching, and the crystallization rate doping concentration after annealing represents the crystallization rate after annealing. As can be seen from Table 1, after annealing in Examples 2 to 6, the crystallization rate of the intrinsic polysilicon layer increases, which is conducive to reducing the difficulty of alkaline etching and improving the effect of alkaline etching.

[0130] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The above-described embodiments merely represent several implementation methods of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make a number of variations and improvements without departing from the concept of the present application, and these variations and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the patent application shall be based on the appended claims, and the description and drawings may be used to interpret the content of the claims.

Claims

1. A method for preparing a solar cell, comprising the following steps: Prepare a first silicon material layer on the surface of the substrate; Performing laser etching on the first silicon material layer to form an etching area on the first silicon material layer to prepare a laser etching product; Annealing the etched area of ​​the laser etched product to prepare an annealed product; the crystallization rate of the first silicon material layer in the etched area of ​​the annealed product is greater than the crystallization rate of the first silicon material layer in the etched area of ​​the laser etched product; The etched region of the annealed product is wet-etched.

2. The method for preparing a solar cell according to claim 1, wherein: The crystallization rate of the first silicon material layer in the etched area of ​​the annealed product is 60% to 90%.

3. The method for preparing a solar cell according to any one of claims 1 to 2, wherein: The crystallization rate of the first silicon material layer in the etched area of ​​the laser etched product is 10% to 30%.

4. The method for preparing a solar cell according to any one of claims 1 to 3, wherein: The annealing treatment is performed at a temperature of 400°C to 950°C.

5. The method for preparing a solar cell according to any one of claims 1 to 4, wherein: The annealing treatment time is 5 min to 30 min.

6. The method for preparing a solar cell according to any one of claims 1 to 5, wherein: The atmosphere gas used in the annealing process includes at least one of a protective gas and oxygen.

7. The method for preparing a solar cell according to any one of claims 1 to 6, wherein: Before wet etching the etched area of ​​the annealed product, the method further includes: Acid etching is performed on the etched region of the annealed product.

8. The method for preparing a solar cell according to claim 7, wherein: The acid etching is performed using a first etching solution; the first etching solution includes hydrofluoric acid.

9. The method for preparing a solar cell according to claim 8, wherein: The mass percentage of the hydrofluoric acid in the first etching solution is 0.01% to 2%.

10. The method for preparing a solar cell according to any one of claims 8 to 9, wherein: The temperature of the first etching solution is 10°C to 50°C.

11. The method for preparing a solar cell according to any one of claims 8 to 10, wherein: The acid etching time is 5s to 120s.

12. The method for preparing a solar cell according to any one of claims 1 to 11, wherein: The wet etching is performed using a second etching solution; the second etching solution includes an alkaline solute.

13. The method for preparing a solar cell according to claim 12, wherein: The alkaline solute includes at least one of potassium hydroxide and sodium hydroxide.

14. The method for preparing a solar cell according to any one of claims 12 to 13, wherein: The mass percentage of the alkaline solute in the second etching solution is 2% to 50%.

15. The method for preparing a solar cell according to any one of claims 12 to 14, wherein: The temperature of the second etching solution is 60°C to 90°C.

16. The method for preparing a solar cell according to any one of claims 12 to 15, wherein: The wet etching time is 100s to 700s.

17. The method for preparing a solar cell according to any one of claims 1 to 16, wherein: The first silicon material layer includes a first silicon substrate and a first doping element doped in the first silicon substrate.

18. The method for preparing a solar cell according to claim 17, wherein: The doping concentration of the first doping element in the first silicon material layer is 4×10 19 / cm 3 ~1×10 20 / cm 3 .

19. The method for preparing a solar cell according to claim 18, wherein: The first doping element includes boron; the laser etching increases the doping concentration of the boron element on the surface of the first silicon material layer; and the annealing treatment reduces the doping concentration of the boron element on the surface of the first silicon material layer.

20. The method for preparing a solar cell according to any one of claims 17 to 19, wherein: The preparation of the first silicon material layer comprises: A first intrinsic polysilicon layer is prepared on the surface of the substrate; and a first doping treatment is performed on the first intrinsic polysilicon layer to dope the first doping element into the first intrinsic polysilicon layer.

21. The method for preparing a solar cell according to any one of claims 17 to 20, wherein: After wet etching the etched area of ​​the annealed product, the method further comprises: A second silicon material layer is prepared in the etching area, wherein the second silicon material layer includes a second silicon substrate and a second doping element doped in the second silicon substrate; the second doping element and the first doping element are of opposite types, and there is a gap between the second silicon material layer and the first silicon material layer.

22. The method for preparing a solar cell according to claim 21, wherein: The concentration of the second doping element in the second silicon material layer is 1×10 20 / cm 3 ~6×10 20 / cm 3 .

23. The method for preparing a solar cell according to any one of claims 21 to 22, wherein: The preparation of the second silicon material layer comprises: A second intrinsic polysilicon layer is prepared in the etched area; and a second doping treatment is performed on the second intrinsic polysilicon layer to dope the second doping element into the second intrinsic polysilicon layer.

24. A solar cell prepared by the preparation method according to any one of claims 1 to 23.

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