Design assistance system and integration device

Abstract

This design assistance system comprises: a design unit for designing a wafer process and a packaging process; a wafer process unit for managing the wafer process; a package unit for managing the packaging process for a wafer manufactured by the wafer process unit; and an integration device for acquiring wafer process information measured in the wafer process from the wafer process unit, acquiring packaging process information measured in the packaging process from the package unit, and providing, to the design unit, design assistance information obtained on the basis of the wafer process information and the packaging process information.

Description

Design support system and control device

[0001] The present invention relates to a design support system and a control device.

[0002] Conventionally, general-purpose semiconductors that can be installed in various products have been mass-produced. Examples of general-purpose semiconductors include central processing units (CPUs) installed in personal computers. Conventional general-purpose semiconductors based on the von Neumann architecture have been designed to have high performance in sequential processing.

[0003] According to Moore's Law, it is believed that production costs can be reduced by increasing the integration density of semiconductors, and traditionally the main goal has been to increase the production volume of general-purpose semiconductors and reduce production costs. However, increasing the production volume of semiconductors requires a large amount of capital investment. For this reason, the fabless production method, in which companies that mainly design semiconductors outsource semiconductor production to external companies, has become mainstream.

[0004] Patent Document 1 discloses a technique relating to lithography-based pattern optimization.

[0005] U.S. Pat. No. 1,144,9659

[0006] With the recent advancement of AI (Artificial Intelligence) technology, semiconductors are now being used for AI processing. Because AI processing involves parallel processing, it is not appropriate to use general-purpose semiconductors. For this reason, there has been a demand for the manufacture of specialized semiconductors optimized for each AI used. However, specialized semiconductors can only be used in specific products, and will not function if installed in products other than the specific product. For this reason, mass-producing specialized semiconductors is not realistic, and even if it were possible to mass-produce specialized semiconductors, there is the problem of enormous costs.

[0007] As semiconductors continue to become more miniaturized, not only has the turn-around time (TAT) for semiconductor manufacturing become longer, but the rules and constraints for semiconductor design have also become more complex, lengthening the time required for design. As a result, if a problem is discovered in the semiconductor development process, it can take a huge amount of time and money to redo the design and manufacturing (prototype). Therefore, a method to reduce the number of redesigns required for semiconductors was needed.

[0008] In the current semiconductor manufacturing system, businesses that design semiconductors and businesses that manufacture semiconductors exist separately. Therefore, optimal manufacturing conditions or causes of failures, which can only be determined by the semiconductor manufacturing businesses manufacturing semiconductors based on design information from the semiconductor design businesses, are not shared with the semiconductor design businesses. Even if optimal manufacturing conditions and causes of failures are shared between businesses, the semiconductor design businesses simply repeat trial and error without knowing how to optimally design semiconductors, resulting in time-consuming design. Furthermore, even with the technology disclosed in Patent Document 1, the time-consuming design process remains unchanged.

[0009] The present invention has been made in view of the above circumstances, and has as its object to significantly reduce the time required from the design to production of semiconductors.

[0010] The design support system according to the present invention comprises a design unit that designs a wafer process for manufacturing wafers and a packaging process for manufacturing packages from the wafers, a wafer process unit that manages the wafer process, a packaging unit that manages the packaging process for wafers manufactured by the wafer process unit, and a control device that acquires wafer process information measured in the wafer process from the wafer process unit, acquires packaging process information measured in the packaging process from the packaging unit, and provides design support information calculated based on the wafer process information and packaging process information to the design unit.

[0011] According to the present invention, by providing design support information based on information obtained during semiconductor manufacturing, it is possible to significantly reduce the time required from semiconductor design to production. Problems, configurations, and effects other than those described above will become clear from the description of the following embodiments.

[0012] 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to one embodiment of the present invention. FIG. 2 is a diagram showing an example of a back-end process in a packaging process according to one embodiment of the present invention. FIG. 3 is a block diagram showing an example of the overall configuration of a design support system according to one embodiment of the present invention. FIG. 4 is a block diagram showing an example of the internal configuration of a supervision device according to one embodiment of the present invention. FIG. 5 is a flowchart showing an example of an AI-assisted design solution provided by a design department according to one embodiment of the present invention. FIG. 6 is a diagram showing an experiment showing the difference in data obtained by a batch process and a single wafer process according to one embodiment of the present invention. FIG. 7 is a diagram showing the contents of data obtained by a batch process and a single wafer process according to one embodiment of the present invention. FIG. 8 is a diagram showing the difference in turnaround time between a conventional manufacturing method and a manufacturing method according to this embodiment. FIG. 9 is a diagram explaining a manufacturing method using an all-single wafer device according to one embodiment of the present invention. FIG. 10 is a diagram showing an example of the operation of a guide and management unit according to one embodiment of the present invention. FIG. 11 is a diagram showing an example of heterogeneous integration (hetero) design using chiplets according to one embodiment of the present invention. FIG. 12 is a diagram showing three examples of processes that can shorten the packaging turnaround time according to one embodiment of the present invention. FIG. 13 is a diagram showing an example of change in turnaround time in a packaging process according to one embodiment of the present invention.

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functions or configurations are designated by the same reference numerals, and redundant description will be omitted.

[0014] [One Embodiment] <An Example of a Semiconductor Manufacturing Process> FIG. 1 is an overall configuration diagram showing an example of a semiconductor manufacturing process according to one embodiment.

[0015] The semiconductor manufacturing process is broadly divided into a design process, a wafer process for manufacturing wafers, and a packaging process for manufacturing packages from wafers. In this embodiment, the manufacturing technology for design is called MFD (Manufacturing for Design) to distinguish it from DFM (Design for Manufacturing), a conventional design technology for manufacturing. MFD is a methodology for supporting design based on data obtained in the wafer and packaging processes. In a design support system 10 according to this embodiment (see FIG. 3 , described later), repeated MFD and DFM enable design-manufacturing co-optimization (DMCO), which represents the coordination and optimization of semiconductor design and manufacturing. As a result, the design support system 10 according to this embodiment aims to halve the total cycle time from semiconductor design to packaging.

[0016] In the design process, semiconductors and circuit layouts are designed. In this embodiment, a new design methodology supported by an AI (Artificial Intelligence) model is provided to the applicant's customers. For example, the AI ​​model learns silicon big data measured by various measurement devices in the wafer process and packaging process, thereby training each AI model shown in FIG. 4 (described later) and improving the performance of the PDK (Process Design Kit). In this embodiment, the trained AI model is used in the design process to assist the customer's designer in their design, thereby automating semiconductor design.

[0017] The PDK contains technology information necessary for semiconductor design, such as what device models are available, what design rules should be used, and what regulatory components should be extracted. Designers import this information into the PDK tool to design semiconductors. The MFD, in which the AI ​​model learns from silicon big data as shown in Figure 1, and the MFD, in which the AI ​​model assists the designer in design by navigating them, are structured in a hierarchical structure.

[0018] (General wafer and packaging processes) The wafer and packaging processes are divided into front-end and back-end processes. The front-end process includes the front-end line (FEOL) where device formation is performed, the back-end line (BEOL) where wiring formation is performed, and wafer characteristic inspection.

[0019] The FEOL includes, for example, a cleaning process, a film formation process, a photolithography process, an etching process, an ion implantation process, and a wafer inspection process, and these processes are performed repeatedly. The BEOL includes, for example, a cleaning process, a film formation process, a photolithography process, an etching process, a planarization process, and a wafer inspection process, and these processes are performed repeatedly on wafers manufactured through the FEOL. In the wafer characteristic inspection in the wafer inspection process, an electrical characteristic inspection of the wafer is performed on the wafer manufactured through the BEOL. When the wafer characteristic inspection is completed, the wafer is completed.

[0020] The back-end process includes an assembly process and an inspection process. The assembly process includes a dicing process, a die bonding process, a wire bonding process, and a molding process for wafers that are determined to be non-defective as a result of the wafer characteristic inspection. The inspection process includes a final inspection process for semiconductors produced in the molding process. This back-end process consisting of assembly and inspection processes is carried out in a simple packaging process using wire bonding of a single chip, as well as a complex packaging process in which multiple chips are stacked. Once the final inspection process is completed, a packaged semiconductor (also called a chip) is completed.

[0021] (Wafer Process and Packaging Process According to the Present Embodiment) In general, wafer processes are divided into batch processes, in which all wafers in a lot undergo the same process, and single-wafer processes, in which wafers in a lot are processed one by one and the process for each wafer can be changed. Typically, both processes are mixed. In the wafer process according to the present embodiment, all processes are performed using the single-wafer process. This reduces the time required to complete a lot to less than the normal time required for completion. Furthermore, by prototyping each wafer under different conditions, a larger amount of data can be accumulated in the same time period compared to processes including batch processes, resulting in the creation of silicon big data. Silicon big data contributes to improving wafer yield in the wafer process. Silicon big data is also used to train AI models (design AI model 72 in Figure 4, described below) in the design process (MFD). Furthermore, in the wafer process, the single-wafer process reduces the processing time (x) per wafer to less than half of the conventional process.

[0022] With the advancement of chiplet technology, the packaging process has evolved to include highly sophisticated bonding of wafers to wafers, wafers to chips, and chips to chips to form multi-chips, which are then mounted on a substrate, resulting in a wide variety of complex combinations. The post-processing described below conceptually involves chipping the wafers completed in the pre-processing, mounting them on a substrate (such as a silicon substrate) with additional redistribution, and then mounting the resulting substrate on the final packaging substrate. Because a substrate with additional redistribution is mounted on the packaging substrate, multiple chips with various functions are integrated and connected. Therefore, even if not all functions are integrated on a single chip, the same functionality can be achieved by using a packaging substrate product that integrates multiple chips with each function.

[0023] 2 is a diagram showing an example of a post-process in a packaging process that supports multi-chip integration. For example, a bump formation process and a dicing process are performed on the wafer manufactured in the above-mentioned pre-process. Furthermore, a TSV (Through-Silicon Via) process, a rewiring layer formation process, and a bump formation process are performed on the rewiring substrate. Thereafter, a chip mounting process is performed in which the chips separated by the dicing process are combined with the rewiring substrate. After the sealing process and the bump formation process, a substrate mounting process is performed on the packaging substrate. After the sealing process, a final inspection process is performed.

[0024] During the design process, heterogeneous (heterogeneous integration) design using chiplet technology is possible based on design support information received from a chiplet technology platform containing multiple IPs. In the semiconductor field, functional blocks that make up LSIs (Large Scale Integration), such as CPUs, image processing circuits, and memories, are considered design assets and are referred to as IP (Intellectual Property) cores or simply IPs. In this specification, IPs are described as circuit elements in semiconductor design. Circuit elements can include a variety of elements, such as simple standard cells, interface functional blocks, or CPU cores. Details of chiplets are described later, starting with Figure 11.

[0025] 3 is a block diagram showing an example of the overall configuration of a design support system 10 according to this embodiment. The design support system 10 includes a control device 1, a design section 2, a wafer process section 3, and a packaging section 4.

[0026] The supervising device 1 provides a platform that can be arbitrarily accessed by the design section 2, wafer process section 3, and packaging section 4. To this end, the supervising device 1 acquires wafer process information measured in the wafer process for manufacturing wafers from the wafer process section 3, acquires packaging process information measured in the packaging process from the packaging section 4, and provides design support information calculated based on the wafer process information and packaging process information to the design section 2.

[0027] The supervision device 1 uses the wafer process information as silicon big data and the packaging process information as packaging big data to perform analysis using a design AI model 72 shown in FIG. 4 (described later) to create design support information. The analysis using the design AI model 72 determines correlations between various types of parameters based on the silicon big data and the packaging big data. The design AI model 72 provides design support information including optimal parameter combinations, values, etc. to the design unit 2.

[0028] The design unit 2 designs the wafer process and the wafer packaging process. The design support information provided by the supervision device 1 and the design support function of the AI ​​model enable optimal semiconductor design, so the design unit 2 can increase the design convergence speed. Note that the design unit 2 may import information on semiconductor design created by a designer using the design support function of the AI ​​model, or the AI ​​model may import information on semiconductor design created by itself.

[0029] The wafer process section 3 has a function of managing the wafer process, and manufactures wafers based on the design information designed by the design section 2. The wafer process section 3 transmits data measured by various measuring devices in the wafer process to the supervising device 1 as wafer process information.

[0030] The packaging unit 4 has a function of managing the packaging process for wafers manufactured by the wafer process unit 3. The packaging unit 4 performs a packaging process for wafers manufactured by the wafer process unit 3, in which various chips are placed on a substrate and wiring is performed between the multiple chips based on the placement information designed by the design unit 2. The packaging unit 4 also transmits data measured by various measuring devices in the packaging process to the supervising device 1 as packaging process information.

[0031] 4 is a block diagram showing an example of the internal configuration of the supervising device 1 according to this embodiment. The supervising device 1 operates as a platform that provides the functions of each section of the design section 2. The supervising device 1 includes a wafer process information collection section 50, a packaging process information collection section 60, a design process learning section 70, and an isolation section 75. Conventionally, correlation data was obtained from data acquired during the wafer process using the knowledge of engineers. In contrast, this system enables the design AI model 72 to extract new correlation data with high accuracy from large amounts of data that engineers cannot handle.

[0032] The wafer process information collection unit 50 accumulates wafer process information acquired for each wafer manufactured in the wafer process, and outputs the wafer process information to the design process learning unit 70. This wafer process information collection unit 50 includes a data acquisition unit 51, a feedback unit 52, and a wafer process DB (Data Base) 55.

[0033] The data acquisition unit 51 acquires a large amount of data for each wafer in the wafer process as wafer process information. The data acquired by the data acquisition unit 51 is stored in the wafer process DB 55.

[0034] The feedback unit 52 outputs the data (wafer process information) read from the wafer process DB 55 to the design process learning unit 70 .

[0035] The packaging process information collection unit 60 accumulates packaging process information acquired each time a chip cut out from a wafer manufactured in the packaging process is packaged, and outputs the packaging process information to the design process learning unit 70. This packaging process information collection unit 60 includes a data acquisition unit 61, a feedback unit 62, and a packaging process DB 65.

[0036] The data acquisition unit 61 acquires a large amount of data measured for each packaged product in the packaging process as packaging process information. The data acquired by the data acquisition unit 61 is stored in the packaging process DB 65.

[0037] The feedback unit 62 outputs the data (packaging process information) read from the packaging process DB 65 to the design process learning unit 70 .

[0038] The design process learning unit 70 has a design AI model 72 that obtains first design support information for supporting the design of the wafer process based on wafer process information, and obtains second design support information for supporting the design of the packaging process based on packaging process information. This design process learning unit 70 includes a design DB 71 and a design learning unit 73.

[0039] The design DB 71 stores wafer process information provided by the wafer process information collection unit 50 and stores packaging process information provided by the packaging process information collection unit 60. The design DB 71 also stores a design AI model 72 used in the design process. The design AI model 72 has functions to support various designs in the design process. Therefore, the design AI model 72 provides the functions of the generation unit 21, optimization unit 22, and guidance and management unit 23 to the design unit 2.

[0040] The machine learning in the design AI model 72 uses either unsupervised, supervised, or reinforcement learning depending on the application of the DMCO. For example, the optimization unit 22 and the guidance and management unit 23, which will be described later, use reward-based machine learning to determine which wiring and design policy is most preferable, so reinforcement learning is likely to be used. For example, when the optimization unit 22 obtains a correlation between manufacturing data and electrical characteristics, supervised learning is used, in which the electrical characteristics are used as the correct output result. Unsupervised learning is used in processes such as the optimization unit 22 automatically classifying defect data. The machine learning in the design AI model 72 is not limited to these machine learning methods.

[0041] The design learning unit 73 performs machine learning and the like based on the wafer process information and packaging process information stored in the design DB 25 to update the design AI model 72. The updated design AI model 72 is stored in the design DB 71.

[0042] The isolation unit 75 sets the isolation range of the process between the customer designer and the person who manufactures the wafer based on the design (for example, the manufacturer who is the applicant). The isolation unit 75 can arbitrarily set the isolation range of the process between the designer and the applicant and isolate them. In this embodiment, multiple processes included in the design process are isolated, and the design unit 2 assists the customer designer in designing according to the isolation range. The isolation range is shown in FIG. 5, which will be described later.

[0043] The design unit 2 has a generation unit 21 (Generator), an optimization unit 22 (Optimizer), and a guidance and management unit 23 (Navigator / Manager) as functions provided by the design AI model 72.

[0044] The generation unit 21 has a function of generating code required for design based on specifications written in natural language. The optimization unit 22 performs processing to search for an optimal solution for a combination of design parameters under various predetermined constraints. For example, the optimization unit 22 searches for an optimal combination by reducing leakage current while maintaining the clock frequency, and when an optimal solution is obtained, it outputs the information to the guidance and management unit 23.

[0045] The guidance and management unit 23 provides at least one of the first design support information and the second design support information to the designer based on the combination optimum solution, thereby guiding the designer through the design and managing the designer's design. For example, the guidance and management unit 23 has a function of navigating the designer to speed up the convergence of the performance power area (PPA) of the current design based on past design experience. PPA will be described later with reference to FIG. 7.

[0046] The guidance function of the guidance and management unit 23 is related to the overall design flow. In order to proceed with the various steps included in the design process, the designer is guided based on past experience to avoid repetitive steps. The management function of the guidance and management unit 23 is to plan and manage the design itself. For example, when designing a chip with certain specifications, the guidance and management unit 23 plans how to divide the system on chip (SoC) into blocks so that the design can proceed without bottlenecks.

[0047] 5 is a flowchart showing an example of an AI-aided design solution. The AI-aided design solution is provided to a customer by a design AI model 72 running on the design unit 2.

[0048] In semiconductor design, the semiconductor requirements specifications are first formulated (Requirement specification formulation). Then, development planning is formulated and system-level design is carried out (System-level design). After system-level design, front-end design (F / E Design) and back-end design (B / E Design) are carried out.

[0049] Front-end design includes everything from algorithm design to logic verification. In front-end design, after a designer designs an algorithm, the algorithm is rewritten as a program in, for example, C language. Then, high-level synthesis is performed, which automatically generates a hardware description language using an operational description in C language as input. After the designer designs the system level, RTL (Register Transfer Level) design is performed, which realizes logic circuits and the like using a hardware description language. After RTL design or high-level synthesis, function verification is performed, logic synthesis is performed, and then logic verification is executed. After logic verification, the process returns to system-level design or moves on to the next step, back-end design.

[0050] In the back-end design, floorplanning is performed based on the results of logic verification and test circuit insertion in the front-end design. After floorplanning, floor layout is designed. After placement and routing, physical verification and lithography verification are performed.

[0051] After placement and routing, static timing analysis and power rail analysis are performed. Power rail analysis also includes signal integrity. After placement and routing, power consumption analysis is performed. After the above-mentioned test circuit insertion, test pattern generation is performed, and after placement and routing, gate simulation is performed. These are the contents of each design included in the back-end design.

[0052] Back-end design includes physical verification including placement and routing, timing, and power analysis. After back-end design, the wafer and packaging processes shown in Figure 1 are carried out. That is, after power supply analysis, samples produced by the wafer and packaging processes are shipped (sample shipment), and the operation of the samples is verified. If the sample operation is satisfactory, mass-production products produced by the wafer and packaging processes are shipped (mass-production shipment).

[0053] The AI-aided design solution shown in FIG. 5 is composed of three elements (a generation unit 21, an optimization unit 22, and a guidance and management unit 23) that the design AI model 72 shown in FIG. 4 provides to the design unit 2.

[0054] The generation unit 21 includes, for example, a system level design, an algorithm design, a program description, and an RTL design in the front-end design, as shown in the area enclosed by the dashed line in the upper part of Fig. 5. The generation unit 21 automatically generates program code and the like.

[0055] 5, the optimization unit 22 includes, for example, floor planning, placement and routing, physical verification, lithography verification, static timing analysis, power supply analysis, power consumption analysis, test circuit insertion, test pattern generation, and gate simulation in back-end design. The optimization unit 22 determines optimal conditions for various processes and encourages the designer to design under optimal conditions.

[0056] The guidance and management unit 23 can optimize the hierarchical design to achieve a short TAT (Turn Around Time) design according to this embodiment. TAT refers to the time required from the start to the completion of a process. The TAT may refer to a long period from the start of semiconductor design to the completion of manufacturing, or, as in this embodiment, the TAT may refer to the period from the start of design to the completion of design in the design process.

[0057] As shown on the right side of Figure 5 as (1) to (3), and as already explained, the applicant and the customer can arbitrarily divide the scope of responsibility. The division of the scope of responsibility is determined based on the customer's design capabilities and business model, and the division unit 75 shown in Figure 4 manages the divided scope of responsibility. For example, in the division shown in Figure 5 (1), the customer, who wants to fully utilize the applicant's manufacturing technology, is responsible for the entire design, including development planning, front-end design, and back-end design, while the applicant manufactures and ships sample products or ships mass-produced products.

[0058] In the division shown in Figure 5 (2), the customer is responsible for everything from development planning to front-end design, while the applicant performs back-end design and manufactures and ships sample products or mass-produced products. In this case, the customer wants to entrust the applicant with design that corresponds to manufacturing technology, i.e., back-end design, which involves a large burden. In the division shown in Figure 5 (3), a customer with little design experience who wants to create products using semiconductors is responsible for up to system-level design, while the applicant handles all subsequent processes.

[0059] Traditionally, various vendors have provided various design tools for each block shown in Figure 5. In recent years, the complexity of design rules and constraints associated with miniaturization has led to increasingly sophisticated designs, making it increasingly difficult for designers to master the design tools required for implementing them. Furthermore, in front-end design, designers have tended to cram as many circuits capable of implementing various functions onto a single semiconductor in order to obtain as many functions as possible. Meanwhile, in back-end design, physical design is performed. Therefore, back-end designers cram as many cells as possible into a small area of ​​the wafer and design how to wire them. As a result, back-end designers often spend an increasing amount of time on designing to realize the functions designed in the front-end.

[0060] 5, the system-level design, algorithm design, and rewriting in C language may be performed as an automatic generation process in which the design AI model 72 analyzes specifications written in natural language and automatically generates machine language. Also, the design AI model 72 can encompass each process in the back-end design, consider various constraints, and automatically perform optimization processing to find the optimal combination of parameters.

[0061] Furthermore, the design AI model 72 can judge the quality of a design by learning from various designs or patterns that have been performed in the past. For this reason, the design AI model 72 has a support function that suggests to the designer, for example, the optimal combination of design tools, so that the designer can create an optimal design.

[0062] The AI-aided design solution shown in FIG. 5 can halve the cycle time compared to conventional design methods. Furthermore, the AI-aided design solution according to this embodiment can replicate the capabilities of an experienced designer using a navigator. This allows even an unskilled designer to design semiconductors in the same way as an experienced designer. Conventional design methods often require rework (ECO: Engineering Change Order) at the final design stage, lengthening the design process. By using the AI-aided design solution according to this embodiment, the number of reworks can be significantly reduced, further shortening the TAT.

[0063] <Differences in Data Obtained Between Batch Process and Single-Wafer Process> Next, the differences in data obtained in a conventional manufacturing process and in the manufacturing process according to the present embodiment, as well as the results derived from the data, will be described with reference to FIGS. 6 and 7.

[0064] Figure 6 is a diagram showing the difference in data obtained by the batch process and the single-wafer process through experiments. The horizontal axis of Figure 6 represents the number of parameters that can be obtained during semiconductor production, and the vertical axis represents the experimental time. The parameters shown on the horizontal axis are values ​​obtained by varying certain process conditions (e.g., temperature, pressure, flow rate, plasma power, etc.) (e.g., 850°C, 900°C, 950°C, etc. for temperature). The experimental time on the vertical axis represents the time it takes to obtain a semiconductor manufactured under certain process conditions.

[0065] In the batch process, the same process is performed on a large number of wafers at once. The black dots in Figure 6 represent data acquired for each process. As shown in Figure 6 as "Batch," connecting four black dots creates a linear graph.

[0066] On the other hand, in the case of the single-wafer method (denoted as "single" in FIG. 6), the data obtained in the manufacturing process for each wafer is represented by numerous white dots. Note that FIG. 6 shows the difference between the data obtained by the single-wafer method and the data obtained by the batch method. That is, in the case of the batch method in FIG. 6, because the processing time is long, only four pieces of data (black dots) can be obtained in the same experimental time as the single-wafer method, and the data are arranged in a roughly linear fashion, resulting in a linear change in the graph. On the other hand, in the case of the single-wafer method (single), a large amount of data can be obtained in the same experimental time, resulting in a nonlinear change in the graph.

[0067] Figure 7 shows the data obtained by the batch and single-wafer processes. The explanatory diagram (1) at the top of Figure 7 shows a PPA graph. The PPA graph represents the density distribution function of a certain characteristic parameter. The horizontal axis of the graph represents characteristic variation. For example, the threshold voltage of a transistor has characteristic variation due to manufacturing variations. If the characteristic variation is high, the response will be slow, and if the characteristic variation is low, the response will be fast.

[0068] The PPA is designed using various parameters of the PDK. The PPA is expressed as a function with multiple types of σ as variables, as shown in the following equation (1): PPA = f(..., σ,...) ... (1)

[0069] Here, σ represents the variation of the most important design parameter. Design parameters are parameters that are set by the designer when designing a semiconductor. For example, σ is formed by values ​​that are directly linked to physical manufacturing, such as the alignment accuracy of the equipment, the gas flow rate, and the temperature of the furnace body. Ultimately, the PPA of the chip is a function of the manufacturing parameters. The manufacturing parameters are parameters that are set in the manufacturing equipment when manufacturing semiconductors. This σ is expressed as a function with multiple manufacturing parameters m as variables, as shown in the following equation (2): σ = g(m1, m2, ...) ... (2)

[0070] Typically, designers do not need to worry about physical information because they create various designs based on data called σ, which incorporates manufacturing parameters m1, m2, .... Also, because the complex processes in semiconductor manufacturing are expressed by σ, designers do not need to know how semiconductors are manufactured.

[0071] The graph shown in Figure 6 is reproduced at the bottom of Figure 7. Graph (2) in Figure 7 shows data obtained using the batch method, and graph (3) in Figure 7 shows data obtained using the single, i.e., sheet-based, method.

[0072] As mentioned above, σ is a value determined by the correlation of manufacturing parameters. Designers want to minimize the variation of design parameters, and the sooner the variation is reduced, the better. The smaller the value of σ, the better. However, in the data obtained by the batch method, only a few m shown by black dots in Figure 7 ｉ A linear graph is drawn due to the correlation of the parameters. Therefore, even if a designer fits with the smallest σ, it is unclear whether this σ is the minimum value. Furthermore, if the minimum value of σ fluctuates left and right, the amount of change in σ becomes large, which makes semiconductor manufacturing unstable.

[0073] On the other hand, in the single-fed system, many m ｉA nonlinear graph is drawn based on the correlation of the parameters. In this graph, the minimum value of σ becomes clear, making it easy to find the optimal solution. Therefore, the optimization unit 22 shown in FIG. 4 determines the minimum value of a function with multiple manufacturing parameters as variables for each of the wafer process information and packaging process information as the optimal solution, and the guidance and management unit 23 can guide the designer to the optimal solution.

[0074] The error shown in graph (3) is the value that was judged to be the minimum value of σ in graph (2) showing the data obtained by the batch method. In reality, it is not the minimum value of σ, but the slope of the graph is large. Therefore, a slight m ｉ On the other hand, the point shown as the optimal solution in graph (3) has a small slope, so if this point is the minimum value of σ, then m ｉ Even if changes, σ is less likely to change.

[0075] As mentioned above, if a designer fits at an incorrect position without realizing the optimal value of σ, the quality of the manufactured semiconductors will vary, and many semiconductors will be produced that do not pass inspection in later processes. In semiconductor design, it is important to the design how early the minimum value of σ can be found in advance, so it can be said that there are far greater benefits to using the single-wafer method to find the minimum value of σ than using the batch method.

[0076] Furthermore, designers can accelerate PDK verification by combining silicon big data with a TCAD (Technology CAD) model. For example, designers first use TCAD to predict the correlation between manufacturing parameters and design parameters. Next, designers can verify the correlation between manufacturing parameters and design parameters using silicon big data through MFD, in which silicon big data obtained in a full single-wafer process is analyzed by a design AI model 72.

[0077] 8 is a diagram showing the difference between the TAT in a conventional manufacturing method and the TAT in a manufacturing method according to the present embodiment. In the conventional manufacturing method shown in the upper part of FIG. 8, the front-end line (FEOL) is executed, followed by the back-end line (BEOL), and the manufacturing of semiconductors is completed. In this way, the time from the start to the completion of semiconductor manufacturing is called the conventional TAT.

[0078] 8, the front-end line and the back-end line are started simultaneously and semiconductors are manufactured in parallel. That is, after both the front-end line and the back-end line are completed, the wafers produced in the front-end line and the wafers produced in the back-end line are bonded together to complete the semiconductor manufacturing process.

[0079] This manufacturing method of bonding wafers together is called wafer bonding. In this way, the manufacturing method according to this embodiment can significantly shorten the TAT compared to conventional manufacturing methods. Reducing the TAT in the manufacturing method according to this embodiment is called "shortening the TAT."

[0080] 9 is a diagram illustrating a manufacturing method using an all-single-wafer apparatus (not shown) according to this embodiment. The all-single-wafer apparatus is an apparatus used in the wafer process and the packaging process.

[0081] The lower left of Figure 9 shows a graph illustrating the difference in data obtained using the batch and single-wafer processing methods shown in Figure 6. In the single-wafer processing system according to this embodiment, integrated production is performed for each wafer. In this integrated production, the amount of silicon data obtained from the single-wafer processing system is, for example, approximately 100 times the amount of conventional data. For this reason, the silicon data obtained from the single-wafer processing system is called silicon big data.

[0082] Silicon big data is data acquired by advanced measuring devices and sensors installed in each piece of equipment. After useful data is extracted from the silicon big data, it is analyzed by the design AI model 72. Furthermore, packaging big data is data acquired by advanced measuring devices and sensors installed in each piece of equipment installed in the packaging process.

[0083] The design AI model 72 evaluates highly accurate correlations and characteristics by combining various types of data included in silicon big data, enabling highly accurate correlations and characterization. In this embodiment, a series of processes in which data is passed from the manufacturing domain to the design domain and trends, optimal values, etc. obtained from the data acquired in the manufacturing domain are used in the design domain is called MFD.

[0084] Silicon big data includes, for example, TEG (Test Element Group) data, sample data, and MP (Mass Production) data. The TEG data, sample data, and MP data each include design data, electrical property test data, and manufacturing data (measurement data, film thickness, defect information, etc.) during manufacturing.

[0085] TEG data is data obtained using a foundry's process verification mask that includes a TEG. TEG data is data obtained from device and process technology, such as SPICE models and design rules. TEG data is used for device and process technology in the design domain.

[0086] Sample data is data obtained using a mask for operation verification based on a customer's design. Sample data is data obtained in a design environment, such as data on PDKs and standard cells. MP data is data obtained using a mask for mass-produced products. MP data is used in the design process to achieve rapid design convergence.

[0087] SPICE models and design rules in device and process technologies, PDKs and standard cells in the design environment, and high design convergence in the design process are all related to and influence each other.

[0088] The right side of Figure 9 shows a comparison example between a PDK without an MFD and a PDK with an MFD. The PDK without an MFD is designed using conventional silicon data, and the processing window for the PDK without an MFD is shown. With conventional silicon data, the processing window size is small and data analysis is not possible with high accuracy, whereas with a PDK with an MFD, abundant silicon data (silicon big data) is obtained, resulting in a larger processing window size. As a result, the PDK according to this embodiment improves data analysis accuracy.

[0089] Furthermore, with regard to the variability (margin) considered in the design, in a PDK without an MFD, the variability is small and the design is limited, resulting in multiple redesigns and slower convergence of the design. On the other hand, in a PDK with an MFD according to this embodiment, the variability is large and the degree of freedom in the design is improved. Therefore, with a PDK with an MFD, redesigns are not required, resulting in extremely fast convergence of the design.

[0090] 10 is a diagram showing an example of the operation of the guide and management unit 23 described in FIG. 5. Here, an example of the operation of the guide and management unit 23 in the chip design process will be described. The guide and management unit 23 detects a bottleneck design block from multiple design blocks into which the overall design is divided. The guide and management unit 23 then changes the bottleneck design block to equalize the time required to complete multiple design blocks designed in parallel, and guides the designer to the changed multiple design blocks. An example of the operation of the guide and management unit 23 will be described with reference to operations (1) to (4) shown in FIG. 10.

[0091] In operation (1), the guide and manager 23 performs optimal design partitioning for rapid design convergence. For example, the guide and manager 23 partitions the whole design into multiple individual design blocks HLB1 to HLBn.

[0092] In operation (2), the guide and management unit 23 detects bottlenecks in each divided design block early and finds a solution to eliminate the bottleneck. For example, as shown by the dashed-dotted circle in Figure 10, the guide and management unit 23 detects design block HLB3 as a bottleneck. In this case, the guide and management unit 23 redesigns the design block so that the bottleneck can be eliminated. At this time, the shape of each design block is changed, the netlist is updated, and so on.

[0093] In operation (3), the guide and management unit 23 applies the design change. At this time, the guide and management unit 23 creates a best-case plan for the design change. For example, the guide and management unit 23 changes the size and shape of the design block. The guide and management unit 23 also performs ECO (Economic Change Over) on the design block HLB2, which does not significantly affect the manufacturing schedule. The guide and management unit 23 also performs re-PnR (Place and Route) on the design block HLB4. As a result, the manufacturing time of the block HLB3 detected as a bottleneck is shortened, and the manufacturing times of the design blocks HLB1 to HLBn are no longer affected by the bottleneck, thereby shortening the overall design time for the design blocks HLB1 to HLBn.

[0094] In operation (4), the guide and management unit 23 verifies the full chip. A full chip is a combination of design blocks HLB1 to HLBn whose bottlenecks have been resolved in operation (3). If the verification results in operation (4) are satisfactory, the design information is taped out and shared with the upstream and downstream processes.

[0095] FIG. 11 is a diagram showing an example of heterogeneous integration (hetero) design using chiplets. FIG. 11 shows a chiplet library 80 and an example of the configuration of a chiplet. The chiplet library 80 is constructed, for example, in the design DB 71 shown in FIG. 4. For this reason, the design process learning unit 70 has the chiplet library 80 that stores chiplet information. In the packaging process according to this embodiment, a chiplet platform consisting of multiple circuit elements (IPs) is used.

[0096] The left side of Fig. 11 shows IP groups including specialized IPs and AI accelerators that provide features for the customer's product. The IPs that the customer selects for their own design are called domain-specific IP groups 81. Individual IPs included in the domain-specific IP group 81 are indicated in Fig. 11 as "IP Core1," "IP Core2," etc.

[0097] The IPs included in the domain-specific IP group 81 do not function as products by themselves, so they require a CPU for a controller, a memory interface, etc. The CPU for a controller, the memory interface, etc. are general-purpose IPs that can be shared and are therefore referred to as a platform IP group called a platform IP group (Platform IPs) 82. The platform IP group 82 is used as the platform for chiplets.

[0098] The chiplet library 80 is a library that stores existing chiplets that can be combined according to customer applications. The chiplet library 80 stores various IPs included in a domain-specific IP group 81, a foundation IP group 82, etc. Customers can select any chiplet from the chiplet library 80.

[0099] Customers can design their own chiplets, even if they are not stored in the chiplet library 80, to differentiate them from other companies' chiplets. By using chiplets selected from the chiplet library 80, customers can quickly determine the configuration of a system-on-chip (SOC) that meets their own specifications. This allows customers to mount custom chiplets they have designed on a semiconductor substrate.

[0100] For example, the board 85 shown on the right side of Fig. 11 is an example in which domain-specific IPs 81a and 81b obtained from the chiplet library 80 and a board IP 82a are mounted. Also, the board 86 is an example in which a domain-specific IP 81b obtained from the chiplet library 80, a domain-specific IP 81c newly created by a customer, and a board IP 82a are mounted. Thus, the boards 85 and 86 are mounted with the common board IP 82a, while the board 85 is mounted with a combination of existing chiplets. Also, the board 86 is mounted with a combination of existing chiplets and new chiplets.

[0101] Information about the chiplets mounted on the substrates 85 and 86 is stored in the chiplet library 80 and is also fed back to the packaging design process (MFD), as indicated by the arrow at the bottom of FIG. 11 . Therefore, the design unit 2 can inform the designer of the optimal combination of chiplets and support the chiplet design. For example, the guidance and management unit 23 guides the designer to a combination of board-type circuit elements (board IP group 82) and specialized circuit elements (domain-specific IP group 81) based on the chiplet combination information stored in the chiplet library 80. Therefore, whereas it took a long time to determine circuit elements through trial and error in the past, in this embodiment, the combination of circuit elements guided by the guidance and management unit 23 can be quickly determined.

[0102] Figure 12 shows three examples of processes that can shorten the TAT of the packaging process. In Figure 12, the interposer is an inorganic material such as silicon that has been subjected to wiring processing using semiconductor front-end process technology. Multiple chips are connected by mounting them on the interposer.

[0103] The packaging process according to this embodiment uses techniques such as LDI (Laser Direct Imager) exposure (maskless exposure technology), chip size standardization, and parallel integration, as shown in FIG. 12. The maskless exposure technology includes, for example, a maskless direct writing technology that directly writes circuits by irradiating a laser. Furthermore, for example, a unique two-dimensional or three-dimensional packaging technology is used for chip size standardization and parallel integration.

[0104] Two-dimensional packaging technology arranges multiple chips on a plane, while three-dimensional packaging technology arranges multiple chips not only horizontally but also vertically. Furthermore, useful information obtained from the packaging process is extracted and sent to the design process for learning (MFD). The optimization unit 22 optimizes the maskless direct writing of interposers in the packaging process, the standardization of chip sizes on the interposers, and the mounting of at least one chip on the interposers and the manufacturing of package substrates. The guidance and management unit 23 provides design support by guiding designers to the optimized information. This makes it easier for designers to design semiconductors based on the optimized information.

[0105] The explanatory diagram (1) in Figure 12 shows an example of a maskless exposure technique for forming a circuit pattern on a substrate. The left side of the explanatory diagram (1) shows an example of conventional stepper exposure. In stepper exposure, a wiring pattern 92 is formed on the top surface of an interposer 91 using a photomask 93. The wiring pattern 92 formed by the photomask 93 is the same everywhere.

[0106] An example of LDI exposure according to this embodiment is shown on the right side of explanatory diagram (1). LDI exposure is a maskless exposure technique in which a laser beam 95 is irradiated onto the upper surface of an interposer 91, and a wiring pattern is directly written. The laser beam 95 is irradiated onto the interposer 91 based on three-dimensional CAD data designed by the design department 2 (see FIG. 3). The laser beam 95 can change the wiring pattern 94 for each section of the interposer 91.

[0107] 12 (2) shows an example of standardizing the chip size of the interposer 91. The chip size of the interposer 91 is standardized to, for example, a mm × b mm. In this embodiment, standardizing the chip size eliminates the need to create interposers 91 of various sizes, and therefore allows for centralized settings of the transport mechanism for the interposer 91, etc.

[0108] The explanatory diagram (3) in Figure 12 shows an example of parallel integration of packaging devices. In wafer manufacturing in the explanatory diagram (3), for example, three wafers are shown being manufactured. In interposer manufacturing in the explanatory diagram (3), a defective portion 96, where a defect has occurred in part of the wiring pattern formed on the interposer 91, is indicated by an x. In conventional interposer manufacturing shown on the left side of the interposer manufacturing, the defective portion 96 is left as is. On the other hand, in interposer manufacturing according to this embodiment, multiple chips determined to be non-defective in wafer manufacturing are mounted in a non-defective portion 97 that avoids the defective portion 96.

[0109] In package substrate manufacturing in explanatory diagram (3), a package substrate 98 is manufactured. The package substrate 98 is typically fabricated by wiring a substrate made of an organic material using semiconductor post-processing technology. At least one chip integrated on an interposer 91 is mounted on the package substrate 98 to form a package. In conventional package substrate manufacturing shown on the left side of explanatory diagram (3) in Figure 12, no correlation is observed between the interposer manufactured in the interposer manufacturing process and the defective portion. On the other hand, in package substrate manufacturing according to this embodiment, a good portion 97 of the interposer 91 manufactured in the interposer manufacturing process is mounted directly on the package substrate 98.

[0110] FIG. 13 shows an example of changes in TAT during the packaging process. The upper part of FIG. 13 shows an example of homogeneous integration. In homogeneous integration, all functions are integrated onto a single silicon chip, resulting in a longer TAT. The lower part of FIG. 13 shows an example of heterogeneous integration. In heterogeneous integration, chiplets with separate functions are manufactured in parallel, and these chiplets are integrated in the assembly step.

[0111] As shown in FIG. 13 , for example, a CPU (x nm), memory (y nm), and I / O (z nm) are manufactured in parallel. The process tailored to the CPU (x nm), which has the longest manufacturing time, is called the wafer MFG step. Furthermore, the manufacturing of the interposer also begins at the same time as the manufacturing of the heterogeneous integrated components. The manufacturing process of the interposer is called the interposer MFG step. (1) Exposure processing and (2) Standardization of chip size, which are performed in the interposer MFG step and are described in FIG. 12 , contribute to shortening the processing time of the interposer MFG step. The processing time of the interposer MFG step is shorter than that of the wafer MFG step.

[0112] After the wafer MFG step, an integration step is performed. In the integration step, each chip is integrated in parallel on an interposer. As a result, in the packaging process, the parallel integration (3) described in FIG. 12 contributes to shortening the processing time of the integration step. Therefore, the TAT for heterogeneous integration is shorter than that for homogeneous integration.

[0113] In the design support system 10 according to the embodiment described above, the supervisory device 1 acquires wafer process information from the wafer process section 3 and acquires packaging process information from the packaging section 4. The design AI model 72 of the supervisory device 1 analyzes the wafer process information and packaging process information, and provides the information obtained by determining the optimal conditions for parameters in each process to the design section 2 as design support information. The design section 2 provides the designer with design support information suitable for semiconductor design, and supports the design of each process in semiconductor manufacturing. The designer can reduce the time spent on trial and error in the design process, thereby shortening the time required for design.

[0114] 4 has the function of generating the code required for design from specifications written in natural language, allowing the designer to concentrate on writing the specifications in natural language. Therefore, compared to the conventional method in which the designer analyzes the specifications and generates the code himself, it is possible to automatically obtain code that appropriately reflects the specifications.

[0115] The optimization unit 22 of the design unit 2 optimizes each process included in the wafer process and packaging process based on the design support information received from the supervision device 1. The design AI model 72 according to this embodiment calculates the correlation and trend of various manufacturing parameters based on the massive amount of silicon big data obtained in the single-wafer process to find an optimal solution. By optimizing the wafer process and packaging process designed by the design unit 2, unnecessary processes, redundant processes, etc., are eliminated during actual semiconductor manufacturing. This eliminates the need for the designer to redesign the semiconductor and process, shortening the TAT until design completion.

[0116] Furthermore, the guidance and management unit 23 of the design unit 2 navigates the designer to speed up the PPA convergence of the current design based on past design experience, allowing the designer to seek an optimal solution that minimizes the variability of design parameters and speed up the design of a good semiconductor.

[0117] 10, divided design blocks that could become bottlenecks are detected at an early stage. Then, the bottlenecks are eliminated by modifying the shape of the design blocks, etc. As a result, the manufacturing times of the divided design blocks are standardized, and the time until they are manufactured as a full chip is significantly shorter than conventional manufacturing times.

[0118] 11 stores a domain-specific IP group 81 and a platform IP group 82. A designer can select any chip from the chiplet library 80 and combine at least one chip on a substrate to create a design. This increases the degree of freedom in chiplet design.

[0119] 12 and 13, in the packaging process, direct drawing of wiring patterns is performed by irradiating the interposer with laser light, standardization of the chip size of the interposer, and parallel integration are performed. Therefore, in the packaging process, the TAT for heterogeneous integration according to this embodiment can be shortened compared to the TAT for conventional homogeneous integration.

[0120] It is also possible to arrange various manufacturing equipment in the wafer process unit 3 and the packaging unit 4 in a virtual space, and to perform a simulation of the manufacturing equipment in the virtual space based on the silicon big data described above. In this simulation, the supervisory device 1 may again acquire information obtained from the manufacturing equipment in the virtual space that operates based on various information designed by the design AI model 72 of the supervisory device 1, as well as information on virtual wafers, etc. By repeating the simulation, it becomes possible to identify areas where defects are predicted and extract bottleneck processes before actual wafer manufacturing, thereby further improving the design accuracy by the design unit 2.

[0121] The present invention is not limited to the above-described embodiments, and various other applications and modifications are possible without departing from the spirit of the present invention as defined in the claims. For example, the above-described embodiments provide detailed and specific descriptions of the system configuration in order to clearly explain the present invention, and are not necessarily limited to systems that include all of the described configurations. Furthermore, it is also possible to add, delete, or replace part of the configuration of the present embodiments with other configurations. Furthermore, the control lines and information lines shown are those considered necessary for explanation, and do not necessarily represent all control lines and information lines in the product. In reality, it can be assumed that almost all configurations are interconnected.

[0122] 1...Supervising device, 2...Design department, 3...Wafer process department, 4...Packaging department, 10...Design support system, 21...Generation department, 22...Optimization department, 23...Guidance and management department, 50...Wafer process information collection department, 60...Packaging process information collection department, 71...Slicing department, 80...Chiplet library, 81...Domain-specific IP group, 82...Infrastructure IP group, 91...Interposer

Claims

1. A design support system comprising: a design department which designs a wafer process for manufacturing wafers and a packaging process for manufacturing packages from the wafers; a wafer process department which manages the wafer process; a packaging department which manages the packaging process for the wafers manufactured by the wafer process department; and a control device which acquires wafer process information measured in the wafer process from the wafer process department, acquires packaging process information measured in the packaging process from the packaging department, and provides design support information calculated based on the wafer process information and the packaging process information to the design department.

2. The design support system of claim 1, wherein the control device comprises: a wafer process information collection unit that accumulates the wafer process information obtained for each of the wafers manufactured in the wafer process; a packaging process information collection unit that accumulates the packaging process information obtained each time a chip cut out from the wafer manufactured in the packaging process is packaged; and a design process learning unit having a design AI model that determines first design support information for supporting the design of the wafer process based on the wafer process information output from the wafer process information collection unit, and determines second design support information for supporting the design of the packaging process based on the packaging process information output from the packaging process information collection unit.

3. The design support system according to claim 2, wherein the design AI model comprises: a generation unit that generates code required for design based on specifications written in natural language; an optimization unit that searches for an optimal combination of design parameters under predetermined constraints; and a guidance and management unit that provides at least one of the first design support information and the second design support information based on the optimal combination solution to guide the design and manage the design, and the design unit is provided with the functions of the design AI model.

4. The design support system according to claim 3, wherein the optimization unit determines, for each of the wafer process information and the packaging process information, a minimum value of a function having a plurality of manufacturing parameters as variables as the optimal solution, and the guidance and management unit provides guidance on the optimal solution.

5. The design support system according to claim 4, wherein the guidance and management unit detects a design block that is a bottleneck from among multiple design blocks into which an overall design is divided, modifies the design block that is the bottleneck, equalizes the time required to complete multiple design blocks that are designed in parallel, and provides guidance for the modified multiple design blocks.

6. The design support system according to claim 4, wherein the design process learning unit has a chiplet library that accumulates information on chiplets, and the guidance and management unit provides guidance on combinations of platform-type circuit elements and specialized-type circuit elements based on information on combinations of the chiplets accumulated in the chiplet library.

7. The design support system according to claim 6, wherein the optimization unit optimizes maskless direct writing of an interposer in the packaging process, standardization of a chip size of the interposer, and mounting of a chip on the interposer and manufacturing of a package substrate, and the guidance and management unit provides guidance on optimized information.

8. A control device which acquires wafer process information measured in a wafer process from a wafer process section which manages the wafer process for manufacturing wafers, acquires packaging process information measured in the packaging process from a packaging section which manages the packaging process for the wafers manufactured by the wafer process section, and provides design support information calculated based on the wafer process information and the packaging process information to a design section which designs the wafer process and the packaging process.

Images