Solid-state imaging device and electronic apparatus

Abstract

[Problem] To avoid feed-through effects when a plurality of conversion efficiency switching transistors and a plurality of floating diffusion regions are provided. [Solution] This solid-state imaging device comprises: a photoelectric conversion element that generates electric charge in accordance with the intensity of incident light; a plurality of conversion efficiency switching transistors that switch to respectively different photoelectric conversion efficiencies; a plurality of floating diffusion regions that each retain at least a portion of the electric charge generated by the photoelectric conversion element according to switching control for turning the plurality of conversion efficiency switching transistors on or off; and a reset transistor that flushes the retained electric charge in the plurality of floating diffusion regions to a reference voltage node. The reset transistor flushes the retained electric charge in two or more of the plurality of floating diffusion regions to the reference voltage node so that the electric charge does not go through the plurality of conversion efficiency switching transistors.

Description

Solid-state imaging device and electronic device

[0001] The present disclosure relates to a solid-state imaging device and an electronic device.

[0002] A technique is known in which a conversion efficiency switching transistor is provided to change the sensitivity and read out pixel signals multiple times, thereby expanding the dynamic range (see Patent Document 1).

[0003] By providing a plurality of conversion efficiency switching transistors and a plurality of floating diffusion regions in each pixel, the dynamic range can be further expanded.

[0004] JP 2023-11858 A

[0005] When multiple conversion efficiency switching transistors and multiple floating diffusion regions are provided in each pixel, it is necessary to enable the charge generated in the photoelectric conversion element to be sequentially stored in each floating diffusion region via a transfer transistor, and to enable the charge stored in the multiple floating diffusion regions to be discharged to a power supply voltage node via a reset transistor. For this reason, it is conceivable to adopt a configuration in which the conversion efficiency switching transistors and the floating diffusion regions are alternately connected in series between the reset transistor and the transfer transistor.

[0006] However, there is a problem in that the potential change range (hereinafter referred to as "FD range") of the floating diffusion (hereinafter referred to as "floating diffusion region") decreases as the floating diffusion region is farther away from the power supply voltage node connected to the drain of the reset transistor due to the influence of feedthrough of the conversion efficiency switching transistor when the conversion efficiency switching transistor or the reset transistor is turned off. Feedthrough refers to a phenomenon in which, when the conversion efficiency switching transistor transitions from on to off, a drop in the gate voltage of the conversion efficiency switching transistor causes a drop in the voltage level of the floating diffusion region, reducing the amount of charge that can be held in the floating diffusion region.

[0007] Therefore, the present disclosure provides a solid-state imaging device and electronic equipment that can avoid the influence of feedthrough when multiple conversion efficiency switching transistors and multiple floating diffusion regions are provided.

[0008] In order to solve the above problems, according to the present disclosure, there is provided a solid-state imaging device comprising: a photoelectric conversion element that generates charges according to the amount of incident light; a plurality of conversion efficiency switching transistors that switch to different photoelectric conversion efficiencies; a plurality of floating diffusion regions that respectively hold at least a portion of the charges generated in the photoelectric conversion element in accordance with on / off switching control of the plurality of conversion efficiency switching transistors; and a reset transistor that discharges the charges held in the plurality of floating diffusion regions to a reference voltage node, wherein the reset transistor discharges the charges held in two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0009] The semiconductor device may further include two or more charge transfer regions connecting the reset transistor to the two or more floating diffusion regions, respectively.

[0010] The reset transistor may have two or more sources, and the two or more charge transfer regions may have two or more diffusion regions connecting the two or more sources and the two or more floating diffusion regions.

[0011] The reset transistor may have two or more sources, and at least one of the two or more charge transfer regions may have two or more metal members connecting the two or more sources to the two or more floating diffusion regions.

[0012] The metal member may include a first contact member connected to the source of the reset transistor, a second contact member connected to the floating diffusion region, and a metal wiring layer connecting the first contact member and the second contact member at a height different from that of the source of the reset transistor and the floating diffusion region.

[0013] The reset transistor may have a single gate corresponding to the two or more sources.

[0014] The reset transistor may have two or more gates that correspond to the two or more sources and are spaced apart from each other, and a metal member that electrically connects the two or more gates to each other.

[0015] The reset transistor may have two or more drains connected to a reference voltage node.

[0016] The reset transistor may have a single drain connected to a reference voltage node.

[0017] The photoelectric conversion element may include a transfer transistor that sequentially transfers charges photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and the reset transistor may discharge charges held in the two or more floating diffusion regions other than the floating diffusion region to which charges are first transferred from the transfer transistor to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0018] The photoelectric conversion element may include a transfer transistor that transfers charges photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and the reset transistor may discharge charges held in two or more floating diffusion regions, including a floating diffusion region to which charges are first transferred from the transfer transistor, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0019] The pixel may include two or more of the photoelectric conversion elements, wherein the plurality of floating diffusion regions include two or more floating diffusion regions that hold charges generated in the two or more photoelectric conversion elements, and the reset transistor may discharge the charges held in the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions.

[0020] The two or more photoelectric conversion elements may have different light receiving areas.

[0021] The pixel may include: a pixel that outputs a pixel signal multiple times by controlling the on / off switching of the multiple conversion efficiency switching transistors in one exposure operation, with each transistor having a different sensitivity; and a signal processing unit that converts the pixel signal into a digital signal and performs double data sampling (DDS) to detect a difference between a signal level and a reset level of the pixel signal, wherein the pixel may have the photoelectric conversion element, the multiple conversion efficiency switching transistors, the multiple floating diffusion regions, and the reset transistor.

[0022] a pixel that outputs a pixel signal multiple times by controlling the on / off switching of the multiple conversion efficiency switching transistors in a single exposure operation, with each transistor having a different sensitivity; and a signal processing unit that converts the pixel signal into a digital signal and performs correlated double sampling (CDS) to detect a difference between a reset level and a signal level of the pixel signal, wherein the pixel may have the photoelectric conversion element, the multiple conversion efficiency switching transistors, the multiple floating diffusion regions, and the reset transistor.

[0023] According to the present disclosure, there is provided an electronic device comprising: a solid-state imaging device that generates an image according to the amount of incident light; and a processing unit that processes the image, wherein the solid-state imaging device has: a photoelectric conversion element that generates charge according to the amount of incident light; a plurality of conversion efficiency switching transistors that each switch to a different photoelectric conversion efficiency; a plurality of floating diffusion regions that each hold at least a portion of the charge generated in the photoelectric conversion element according to on / off switching control of the plurality of conversion efficiency switching transistors; and a reset transistor that discharges the charge held in the plurality of floating diffusion regions to a reference voltage node, and the reset transistor discharges the charge held in two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0024] 1 is a block diagram of an electronic device according to a first embodiment of the present disclosure. FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to an embodiment of the present disclosure. FIG. 2 is a block diagram showing a configuration around a vertical signal line of a solid-state imaging device according to the present disclosure. FIG. 3 is a circuit diagram of each pixel of a solid-state imaging device according to an embodiment. FIG. 4 is a planar layout diagram of a pixel according to an embodiment. FIG. 5 is a potential diagram of a pixel according to an embodiment. FIG. 6 is a potential diagram when the FDG transistor is further turned off. FIG. 7 is a potential diagram when the RST transistor is further turned off. FIG. 8 is a circuit diagram of a pixel according to a comparative example. FIG. 9 is a planar layout diagram of a pixel according to a comparative example. FIG. 10 is a potential diagram of a pixel according to a comparative example. FIG. 11 is a potential diagram when the FDG transistor is turned off. FIG. 12 is a potential diagram when the FCG transistor is further turned off. FIG. 13 is a potential diagram when the RST transistor is further turned off. FIG. 14 is a planar layout diagram of a pixel according to a first modified example of an embodiment. FIG. 15 is a circuit diagram of a pixel according to a second modified example of an embodiment. FIG. 16 is a planar layout diagram of a pixel according to a second modified example of an embodiment. FIG. 17 is a circuit diagram of a pixel according to a third modified example of an embodiment. FIG. 18 is a planar layout diagram of a pixel according to a third modified example of an embodiment. FIG. 19 is a planar layout diagram when three RST transistors are provided. FIG. 19 is a planar layout diagram of a pixel according to a fourth modified example of an embodiment. FIG. 19 is a circuit diagram of a pixel according to a fifth modified example of an embodiment. FIG. 10 is a planar layout diagram of pixels according to a fifth modified example of an embodiment. FIG. 11 is a planar layout diagram of pixels according to a sixth modified example of an embodiment. FIG. 12 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 13 is an explanatory diagram showing an example of installation positions of an outside-of-vehicle information detection unit and an imaging unit. FIG. 14 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 15 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0025] Hereinafter, embodiments of a solid-state imaging device and an electronic device will be described with reference to the drawings. The following description will focus on the main components of the solid-state imaging device and the electronic device, but the solid-state imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0026] Fig. 1 is a block diagram of an electronic device 10 according to a first embodiment of the present disclosure. The electronic device 10 has a function of generating an image according to the luminance of incident light. The electronic device 10 in Fig. 1 includes a solid-state imaging device 1, an imaging lens 2, an image processing unit 3, a recording unit 4, and a control unit 5. The electronic device 10 can be applied to, for example, a surveillance camera or a camera mounted on an industrial robot, or a camera for general use, but the specific use and configuration of the electronic device 10 are arbitrary.

[0027] The imaging lens 2 collects incident light and guides it to the solid-state imaging device 1. The solid-state imaging device 1 captures an image of the incident light. The solid-state imaging device 1 has a function of generating a captured image by photoelectrically converting light in a predetermined wavelength range, such as visible light or infrared light. The captured image generated by the solid-state imaging device 1 is sent to an image processing unit 3 and a recording unit 4.

[0028] The image processing unit 3 performs predetermined image processing on the captured image, such as color or brightness adjustment, image compression, image recognition, tracking, or analysis. The image processed by the image processing unit 3 is output to the recording unit 4, for example.

[0029] The recording unit 4 records the image output from the solid-state imaging device 1 or the image processing unit 3. The recording unit 4 may be disposed in a server connected via a network. In the electronic device 10 according to this embodiment, at least one of the image processing unit 3 and the recording unit 4 in FIG. 1 can be omitted.

[0030] The control unit 5 controls the operation of the solid-state imaging device 1. Furthermore, although not explicitly shown in FIG.

[0031] FIG. 2 is a block diagram showing a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present disclosure. As shown in FIG. 2 , the solid-state imaging device 1 according to the embodiment includes a pixel array unit 11. In addition, the solid-state imaging device 1 includes, for example, a vertical driver 12, a column processor 13, a horizontal driver 14, and a system controller 15. The solid-state imaging device 1 further includes a signal processor 16 and a data storage unit 17. The signal processor 16 and the data storage unit 17 may be mounted on the same substrate as the pixel array unit 11, the vertical driver 12, etc., or may be disposed on a separate substrate. Furthermore, the processing of the signal processor 16 and the data storage unit 17 may be performed by an external signal processor, such as a DSP (Digital Signal Processor) circuit, provided on a semiconductor chip separate from the solid-state imaging device 1.

[0032] The pixel array section 11 has a configuration in which pixels 21, each having a photoelectric conversion element that generates and accumulates an electric charge according to the amount of received light, are two-dimensionally arranged in a matrix in row and column directions. Here, the row direction refers to the pixel rows of the pixel array section 11, i.e., the horizontal arrangement direction, and the column direction refers to the pixel columns of the pixel array section 11, i.e., the vertical arrangement direction. A specific circuit configuration of the pixel 21 will be described later. The pixel 21 is sometimes called a unit pixel, but will be referred to as a pixel 21 in this specification.

[0033] In the pixel array unit 11, pixel drive wiring 22 as row signal lines is wired along the row direction for each pixel row, and vertical signal lines VSL as column signal lines are wired along the column direction for each pixel column. The pixel drive wiring 22 transmits drive signals for driving the pixels 21 when reading out signals. Although FIG. 2 illustrates each pixel drive wiring 22 as a single wire, the number of pixel drive wirings 22 is not limited to one. One end of the pixel drive wiring 22 is connected to an output terminal of the vertical drive unit 12 corresponding to each row.

[0034] The vertical drive unit 12 is configured with a shift register, an address decoder, etc., and drives each pixel 21 of the pixel array unit 11 simultaneously for all pixels or in row units, etc. The vertical drive unit 12, together with the system control unit 15, configures a drive unit that controls the operation of each pixel 21 of the pixel array unit 11. Although the specific configuration of the vertical drive unit 12 is not shown in the figure, it generally has two scan systems: a read scan system and a sweep scan system.

[0035] The readout scanning system sequentially selects and scans the pixels 21 of the pixel array unit 11 row by row to read out signals from the pixels 21. The signals read out from the pixels 21 are analog signals. The sweep scanning system performs sweep scanning on the readout rows to be read out by the readout scanning system, prior to the readout scanning by an exposure time.

[0036] The sweep scanning by this sweep scanning system sweeps out unnecessary charges from the photoelectric conversion elements of the pixels 21 in the readout row, thereby resetting the photoelectric conversion elements of each pixel 21. Then, by sweeping out (resetting) the unnecessary charges by this sweep scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the charges in the photoelectric conversion elements and starting a new exposure (starting the accumulation of charge).

[0037] The signal read by the readout scanning system corresponds to the amount of light received after the immediately preceding readout operation or electronic shutter operation. The exposure period of the pixel 21 is the period from the readout timing of the immediately preceding readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation.

[0038] The signals output from each pixel 21 in a pixel row selected and scanned by the vertical drive unit 12 are input to the column processing unit 13 through each vertical signal line VSL for each pixel column. The column processing unit 13 performs predetermined signal processing on the signals output from each pixel 21 in the selected row through the vertical signal line VSL for each pixel column in the pixel array unit 11, and temporarily holds the pixel signals after signal processing.

[0039] Specifically, the column processing unit 13 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing, as signal processing. For example, CDS processing removes reset noise and pixel-specific fixed pattern noise such as threshold variations of AMP transistors in pixels. In addition to noise removal processing, the column processing unit 13 also has, for example, an AD (analog-digital) conversion function, and converts analog pixel signals into digital signals and outputs them.

[0040] The horizontal driving unit 14 is configured with a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 13. By selective scanning by this horizontal driving unit 14, pixel signals that have been signal-processed for each unit circuit in the column processing unit 13 are sequentially output.

[0041] The system control unit 15 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 12, column processing unit 13, and horizontal driving unit 14 based on the various timings generated by the timing generator.

[0042] The signal processing unit 16 has at least an arithmetic processing function and performs various signal processing such as arithmetic processing on the pixel signals output from the column processing unit 13. The data storage unit 17 temporarily stores data necessary for the signal processing in the signal processing unit 16. The pixel signals that have been signal processed in the signal processing unit 16 are converted into a predetermined format and output from the output unit 18 to the outside of the solid-state imaging device 1.

[0043] 3 is a block diagram showing the configuration around the vertical signal line VSL of the solid-state imaging device 1 according to the present disclosure. As shown in FIG. 3, a vertical signal line VSL is provided for each pixel column of the pixel array unit 11. As will be described later, each pixel 21 included in the pixel column has a photoelectric conversion element and a pixel circuit. The photoelectric conversion element generates charges according to the amount of incident light. The pixel circuit reads out the charges generated by the photoelectric conversion element in one exposure operation multiple times and outputs pixel signals whose signal levels change to multiple levels according to the read-out charges to the signal line.

[0044] Each vertical signal line VSL is connected to a current source 24 and a column processing section 13. The current source 24 is provided for each vertical signal line VSL, while the column processing section 13 is connected to all vertical signal lines VSL.

[0045] The current source 24 generates a current that flows through the corresponding vertical signal line VSL. The current that flows through each vertical signal line VSL is drawn into the ground node through the corresponding current source 24. By causing the current source 24 to flow through the vertical signal line VSL, it is possible to shorten the settling time of the voltage level of the pixel signal on the vertical signal line VSL.

[0046] A DAC (Digital to Analog Converter) 27 is connected to the column processing section 13. The column processing section 13 has a comparator 28 and a counter 29 for each vertical signal line VSL.

[0047] Each comparator 28 compares the pixel signal on the corresponding vertical signal line VSL with the reference signal output from the DAC 27. When the signal levels of the pixel signal and the reference signal match, the signal level of the output signal of the comparator 28 transitions. The counters 29 start counting operation in response to a start signal from the system control unit 15 shown in FIG. 2, and when the signal level of the output signal of each comparator 28 transitions, the corresponding counter 29 ends its counting operation. The count value of the counter 29 is a value obtained by AD converting the signal level of the pixel signal.

[0048] 4 is a circuit diagram of each pixel 21 of a solid-state imaging device 1 according to an embodiment. As shown in FIG. 4 , the pixel 21 according to the present disclosure includes a photoelectric conversion element PD, a transfer transistor 31, a reset transistor 32, an AMP transistor 33, a SEL transistor 34, a first conversion efficiency switching transistor 35, a second conversion efficiency switching transistor 36, a first floating diffusion region FD1, a second floating diffusion region FD2, and a third floating diffusion region FD3. Hereinafter, the transfer transistor 31 will be referred to as the TG transistor 31, the reset transistor 32 as the RST transistor 32, the AMP transistor 33 as the AMP transistor 33, the SEL transistor 34 as the SEL transistor 34, the first conversion efficiency switching transistor 35 as the FDG transistor 35, and the second conversion efficiency switching transistor 36 as the FCG transistor 36.

[0049] 4 shows two symbols 32a and 32b representing the RST transistor 32, but in reality, the RST transistor 32 is composed of one RST transistor 32 having at least two sources. Hereinafter, one of the two sources of the RST transistor 32 will be referred to as a first source, and the other will be referred to as a second source.

[0050] The first source is connected to the drain of the FDG transistor 35, i.e., the second floating diffusion region FD2, and the second source is connected to the drain of the FCG transistor 36, i.e., the third floating diffusion region FD3.

[0051] 4 shows an example in which the RST transistor 32 (32a, 32b) has two drains, but as will be described later, a modified example in which the RST transistor 32 has a single drain is also possible. Both of the two drains are connected to the power supply voltage VDD node.

[0052] The RST transistor 32 discharges the charges held in two or more floating diffusion regions (e.g., the second floating diffusion region FD2 and the third floating diffusion region FD3) among the plurality of floating diffusion regions in the pixel 21 to a reference voltage (e.g., power supply voltage VDD) node without passing through a plurality of conversion efficiency switching transistors (e.g., the FDG transistor 35 and the FCG transistor 36). In the example of Fig. 4, the RST transistor 32 discharges the charges held in the second and third floating diffusion regions FD2 and FD3 directly to the power supply voltage VDD node.

[0053] The photoelectric conversion element PD is, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to the ground node, and the cathode is connected to the source of the transfer transistor 31.

[0054] The drain of the FDG transistor 35 is connected to the second floating diffusion region FD2, the source of the FCG transistor 36, and the first source of the RST transistor 32. A first charge holding unit C1 may be connected to the second floating diffusion region FD2. The first charge holding unit C1 is, for example, a MOS (Metal Oxide Semiconductor) capacitance, a MIM (Metal Insulator Metal) capacitance, or a wiring capacitance.

[0055] The drain of the FCG transistor 36 is connected to the third floating diffusion region FD3 and the second source of the RST transistor 32. A second charge holding unit C2 may be connected to the third floating diffusion region FD3. The second charge holding unit C2 is, for example, a MOS capacitance, an MIM capacitance, or a wiring capacitance.

[0056] The AMP transistor 33 and the SEL transistor 34 form a source follower circuit. The drain of the AMP transistor 33 is connected to the power supply voltage VDD node, and the source is connected to the drain of the SEL transistor 34. The source of the SEL transistor 34 is connected to the vertical signal line VSL.

[0057] The gate of the TG transistor 31 receives a TG signal, the gate of the FDG transistor 35 receives an FDG signal, the gate of the FCG transistor 36 receives an FCG signal, the gate of the RST transistor 32 receives an RST signal, and the gate of the SEL transistor 34 receives a SEL signal.

[0058] 5 is a planar layout diagram of a pixel 21 according to an embodiment. Between a power supply voltage VDD node and a photoelectric conversion element PD, an RST transistor 32, an FCG transistor 36, an FDG transistor 35, and a TG transistor 31 are arranged in this order in the column direction. More specifically, from the power supply voltage VDD node toward the photoelectric conversion element PD, the drain, gate, and source of the RST transistor 32, the drain, gate, and source of the FCG transistor 36, the drain, gate, and source of the FDG transistor 35, and the drain, gate, and source of the TG transistor 31 are arranged in this order.

[0059] The gate of each transistor is made of a metal material such as copper (Cu) or polysilicon. The drain and source of each transistor are diffusion regions formed by implanting impurity ions into the silicon layer, which is the substrate material. These diffusion regions are sometimes referred to as active areas (AA) in this specification.

[0060] 4, the RST transistor 32 according to one embodiment has two drains (a first drain 32d1 and a second drain 32d2) and two sources (a first source 32s1 and a second source 32s2). As will be described later, a configuration in which the drain is not divided into two drains 32d1 and 32d2 is also possible.

[0061] The first source 32s1 and the second floating diffusion region FD2 are connected by an active area AA1 made of a diffusion region. The second source 32s2 and the third floating diffusion region FD3 are connected by an active area AA2 made of a diffusion region. The active area AA1 connected to the first source 32s1 is arranged apart from the active area AA2 connected to the second source 32s2 so as not to come into contact with each other. A SiO ２These active areas AA1 and AA2 are charge transfer regions for discharging the charges held in the second floating diffusion region FD2 and the third floating diffusion region FD3 to the power supply voltage VDD node via the RST transistor 32.

[0062] In the pixel 21 according to the embodiment, when the charges held in the first to third floating diffusion regions FD1 to FD3 are discharged to the power supply voltage VDD node, it is not necessary to turn on the FCG transistor 36. This eliminates the influence of feedthrough that occurs when the FCG transistor 36 transitions from on to off, and makes it possible to suppress a decrease in the amount of charges held in the first and second floating diffusion regions FD2.

[0063] 6A, 6B, and 6C are potential diagrams of the pixel 21 according to an embodiment. Fig. 6A is a potential diagram when the TG transistor 31, the FDG transistor 35, and the RST transistor 32 are all on, and the FCG transistor 36 is off. As described above, because the first source 32s1 of the RST transistor 32 is connected to the second floating diffusion region FD2, the charges held in the first floating diffusion region FD1 and the second floating diffusion region FD2 can be discharged to the power supply voltage VDD node even when the FCG transistor 36 is off.

[0064] 6B is a potential diagram when the FDG transistor 35 is further turned off. When the FDG transistor 35 is turned off, the first floating diffusion region FD1 enters a floating state, and the voltage level of the first floating diffusion region FD1 drops due to the drop in the gate voltage of the FDG transistor 35. In other words, the potential of the first floating diffusion region FD1 rises.

[0065] 6C is a potential diagram when the RST transistor 32 is further turned off. When the RST transistor 32 is turned off, the first floating diffusion region FD1, the second floating diffusion region FD2, and the third floating diffusion region FD3 enter a floating state, and the potential of the first to third floating diffusion regions FD1 to FD3 increases due to the decrease in the gate voltage of the RST transistor 32.

[0066] 6B and 6C , for simplicity of explanation, the potentials of the first to third floating diffusion regions FD1 to FD3 are shown to increase by one step due to the effect of feedthrough each time the FDG transistor 35 or the RST transistor 32 is turned off. The potential of the first floating diffusion region FD1 increases by two steps due to the effect of feedthrough caused by both the FDG transistor 35 and the RST transistor 32 being turned off. The potentials of the second floating diffusion region FD2 and the third floating diffusion region FD3 increase by one step because they are only affected by the effect of feedthrough caused by the RST transistor 32 being turned off.

[0067] As described above, in one embodiment, when discharging the charges held in the first to third floating diffusion regions FD1 to FD3 to the power supply voltage VDD node, it is not necessary to turn on the FCG transistor 36, but rather it is sufficient to first turn off the FDG transistor 35, and then turn off the RST transistor 32. This eliminates the influence of feedthrough when the FCG transistor 36 transitions from on to off, and makes it possible to suppress a decrease in the amount of charges held in the first to third floating diffusion regions FD1 to FD3.

[0068] 7 is a circuit diagram of a pixel 21 according to a comparative example. In the pixel 21 according to the comparative example, the source of the RST transistor 32 is connected only to the drain of the FCG transistor 36 and the third floating diffusion region FD3, and is not connected to the second floating diffusion region FD2. Other connections are the same as those in FIG. 4. Therefore, in the pixel 21 according to the comparative example, the charges held in the first floating diffusion region FD1 and the second floating diffusion region FD2 cannot be transferred directly to the RST transistor 32. Therefore, the FCG transistor 36 must be turned on to drain the charges held in the first floating diffusion region FD1 and the second floating diffusion region FD2. When the FCG transistor 36 is subsequently turned off, the amount of charge held in the first floating diffusion region FD1 and the second floating diffusion region FD2 decreases due to the effect of feedthrough.

[0069] 8 is a planar layout diagram of a pixel 21 according to a comparative example. In the pixel 21 according to the comparative example, as shown in FIG. 8, the drain, gate, and source of the RST transistor 32, the drain, gate, and source of the FCG transistor 36, the drain, gate, and source of the FDG transistor 35, and the drain, gate, and source of the TG transistor 31 are arranged in this order in the column direction between the power supply voltage VDD node and the photoelectric conversion element PD.

[0070] 9A, 9B, 9C, and 9D are potential diagrams of the pixel 21 according to a comparative example. In the pixel 21 according to the comparative example, the FCG transistor 36 needs to be turned on in order to discharge the charges held in the first floating diffusion region FD1 and the second floating diffusion region FD2.

[0071] FIG. 9A is a potential diagram when the TG transistor 31, the FDG transistor 35, the FCG transistor 36, and the RST transistor 32 are all on.

[0072] 9B is a potential diagram when the FDG transistor 35 is turned off. In this case, the first floating diffusion region FD1 is in a floating state, and therefore the potential of the first floating diffusion region FD1 increases due to the decrease in the gate voltage of the FDG transistor 35.

[0073] 9C is a potential diagram when the FCG transistor 36 is further turned off. In this case, the first floating diffusion region FD1 and the second floating diffusion region FD2 are in a floating state, and therefore, the potential of the first floating diffusion region FD1 and the second floating diffusion region FD2 increases due to the decrease in the gate voltage of the FCG transistor 36.

[0074] 9D is a potential diagram when the RST transistor 32 is further turned off. In this case, the first to third floating diffusion regions FD1 to FD3 are in a floating state, and therefore, the potential of the first to third floating diffusion regions FD1 to FD3 increases due to the decrease in the gate voltage of the RST transistor 32.

[0075] 9A to 9D with FIG. 6A to 6C, in the comparative example, the potential of the first to third floating diffusion regions FD1 to FD3 increases by one step each compared to the embodiment due to the effect of feedthrough caused by turning off the FCG transistor 36. As a result, the pixel 21 according to the comparative example has a smaller amount of charge that can be held in the first to third floating diffusion regions FD1 to FD3 than the pixel 21 according to the embodiment, resulting in a narrower dynamic range.

[0076] 10 is a planar layout diagram of a pixel 21 according to a first modified example of an embodiment. The pixel 21 according to the first modified example differs from that shown in FIG. 5 in the structure of the RST transistor 32. The RST transistor 32 according to the first modified example has two reset transistors 32a and 32b. The reset transistor 32a has a first gate 32g1, a first drain 32d1, and a first source 32s1. The reset transistor 32b has a second gate 32g2, a second drain 32d2, and a second source 32s2. The first drain 32d1 and the second drain 32d2 are connected to a power supply voltage VDD node.

[0077] Similar to FIG. 5, the first source 32s1 is connected to the drain of the FDG transistor 35 and the second floating diffusion region FD2, and the second source 32s2 is connected to the drain of the FCG transistor 36 and the third floating diffusion region FD3.

[0078] The metal member 41 connecting the first gate 32g1 and the second gate 32g2 of the RST transistor 32 may be made of the same metal material as the first gate 32g1 and the second gate 32g2, or may be made of a different metal material.

[0079] In the pixel 21 according to the first modification, the RST transistor 32 is configured with two small RST transistors 32a and 32b, and the gates 32g1 and 32g2 are connected to each other by a metal member 41, so that the two RST transistors 32a and 32b can be turned on and off simultaneously. Furthermore, the two sources (the first source 32s1 and the second source 32s2) of the two RST transistors 32a and 32b can be connected to different floating diffusion regions FD2 and FD3, as in the case of FIG. 5 . This allows the charges held in the second floating diffusion region FD2 and the third floating diffusion region FD3 to be directly discharged via the RST transistor 32.

[0080] Fig. 11 is a circuit diagram of a pixel 21 according to a second modified example of an embodiment. Fig. 12 is a planar layout diagram of the pixel 21 according to the second modified example of an embodiment. The pixel 21 according to the second modified example differs from that shown in Fig. 4 in that the first source 32s1 of the RST transistor 32 is connected to the first floating diffusion region FD1 instead of the second floating diffusion region FD2. The other circuit configurations are the same as those shown in Fig. 4.

[0081] The first floating diffusion region FD1 is connected to the gate of the AMP transistor 33, and it is desirable to minimize the amount of noise contained in the retained charge. For this reason, it is desirable that the second source 32s2 of the RST transistor 32 is not connected to the first floating diffusion region FD1. However, if high pixel signal accuracy is not required, the second source 32s2 of the RST transistor 32 may be connected to the first floating diffusion region FD1. In this case, the retained charge in the second floating diffusion region FD2 can be discharged by turning on the FDG transistor 35.

[0082] 12, the first source 32s1 and the first floating diffusion region FD1 of the RST transistor 32 according to the second modification are connected by an active area AA1 made of a diffusion region. The second source 32s2 and the third floating diffusion region FD3 of the RST transistor 32 are connected by an active area AA2 made of a diffusion region, similar to FIG.

[0083] In the second modified example, the charges held in the first floating diffusion region FD1 and the second floating diffusion region FD2 can be discharged to the power supply voltage VDD node without turning on the FCG transistor 36. Therefore, when the RST transistor 32 is turned off, the potential increase in the first to third floating diffusion regions FD1 to FD3 due to feedthrough can be suppressed, and the charges held in the first to third floating diffusion regions FD1 to FD3 can be increased compared to the comparative example.

[0084] FIG. 13 is a circuit diagram of a pixel 21 according to a third modification of an embodiment. In addition to the configuration of the pixel 21 shown in FIG. 4 , the pixel 21 according to the third modification includes a third conversion efficiency switching transistor 37 and a fourth floating diffusion region FD4, and the RST transistor 32 has three sources (hereinafter referred to as first to third sources). A third charge holding unit C3 may be connected to the fourth floating diffusion region FD4. The third charge holding unit C3 may be configured, for example, by a MOS capacitor, an MIM capacitor, or a wiring capacitor. Hereinafter, the first conversion efficiency switching transistor 35 will be referred to as the FDG transistor 35, the second conversion efficiency switching transistor 36 as the FCG1 transistor 36, and the third conversion efficiency switching transistor as the FCG2 transistor 37.

[0085] The first source 32s1 of the RST transistor 32 is connected to the second floating diffusion region FD2, the second source 32s2 is connected to the third floating diffusion region FD3, and the third source 32s3 is connected to the fourth floating diffusion region FD4.

[0086] 14A and 14B are planar layout diagrams of a pixel 21 according to a third modification of an embodiment. As shown in Fig. 13 and 14A, the second floating diffusion region FD2 and the third floating diffusion region FD3 are directly connected to the RST transistor 32, so that the charges held in the first to fourth floating diffusion regions can be discharged to the power supply voltage VDD node without turning on the FCG2 transistor 37.

[0087] When the RST transistor 32 is turned off, the potential of the first to fourth floating diffusion regions FD1 to FD4 increases by two stages only in the first floating diffusion region FD1, and increases by only one stage in the second to fourth floating diffusion regions FD2 to FD4. Therefore, it is possible to suppress the increase in potential and the decrease in the amount of stored charge in the first to fourth floating diffusion regions FD1 to FD4 due to feedthrough when the FCG transistor 36 and the RST transistor 32 are turned off.

[0088] 14A shows an example in which a single gate is provided corresponding to the first to third sources of the RST transistor 32, while Fig. 14B shows an example in which first to third gates are provided corresponding to the first to third sources. Fig. 14B shows an example in which three small RST transistors 32a, 32b, and 32c are provided and the gates of the RST transistors 32a, 32b, and 32c are connected to each other by, for example, a metal member 41.

[0089] 14A simplifies the structure of the RST transistor 32, making the manufacturing process easier. On the other hand, if the area of ​​a single gate is large, it becomes difficult to apply a uniform voltage to the entire gate. In the case of FIG. 14B , the structure of the RST transistor 32 is more complex than in FIG. 14A , but since the RST transistor 32 is composed of three small RST transistors 32, it is easier to make the electrical characteristics uniform.

[0090] 15 is a planar layout diagram of a pixel 21 according to a fourth modified example of an embodiment. The pixel 21 according to the fourth modified example has a circuit configuration similar to that of FIG. 4. The pixel 21 according to the fourth modified example differs from the planar layout of FIG. 5 in that the first source 32s1 of the RST transistor 32 and the second floating diffusion region FD2 are connected by a metal member 42, rather than by an active area made of a diffusion region.

[0091] The metal member 42 is configured using, for example, a contact and a metal wiring layer. More specifically, the metal member 42 is configured with a first contact connected to the first source 32s1 and extending upward (or downward), a second contact connected to the second floating diffusion region FD2 and extending upward (or downward), and a metal wiring layer connected to the upper end (or lower end) of the first contact and the upper end (or lower end) of the second contact. The first contact, the second contact, and the metal wiring layer are formed using, for example, copper (Cu) or aluminum (Al).

[0092] 12, 14A, and 14B, the first source 32s1 or the second source 32s2 of the RST transistor 32 may be connected to the second floating diffusion region FD2 or the third floating diffusion region FD3 by a metal member 42 similar to that in FIG. 15, instead of being connected by an active area.

[0093] 16 is a circuit diagram of a pixel 21 according to a fifth modification of an embodiment. The pixel 21 according to the fifth modification includes a plurality of photoelectric conversion elements PD. The following describes an example in which the pixel 21 includes two photoelectric conversion elements (a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2), two transfer transistors (a TG1 transistor 31a and a TG2 transistor 31b), and two conversion efficiency switching transistors (an FDG1 transistor 35a and an FDG2 transistor 35b). However, the pixel 21 may include three or more photoelectric conversion elements PD. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may have different light receiving areas.

[0094] 16, the pixel 21 according to the fifth modification includes an RST transistor 32 (32b), an FDG1 transistor 35a, and a TG1 transistor 31a connected in series between the power supply voltage VDD node and the cathode of the first photoelectric conversion element PD1, and an RST transistor 32 (32b), an FDG2 transistor 35b, and a TG2 transistor 31b connected in series between the power supply voltage VDD node and the cathode of the first photoelectric conversion element PD1. A first source of the RST transistor 32 (32a) is connected to the first floating diffusion region FD1.

[0095] 17 is a planar layout diagram of a pixel 21 according to a fifth modification of an embodiment. The RST transistor 32 has a first source 32s1 and a second source 32s2. The first source 32s1 and the first floating diffusion region FD1 are connected by an active area AA1 made of a diffusion region. The second source 32s2 and the third floating diffusion region FD3 are connected by an active area AA2 made of a diffusion region.

[0096] In the pixel 21 according to the fifth modification, the first floating diffusion region FD1 and the third floating diffusion region FD3 are directly connected to the RST transistor 32, so that the charges held in the first floating diffusion region FD1 and the third floating diffusion region FD3 can be discharged to the power supply voltage VDD node without turning on the FDG1 transistor 35 a and the FDG2 transistor 35 b. In addition, it is possible to suppress a potential increase and a decrease in the held charges in the first to third floating diffusion regions FD1 to FD3 due to feedthrough when the FDG1 transistor 35 a, the FDG2 transistor 35 b, or the RST transistor 32 is turned off.

[0097] 18 is a planar layout diagram of a pixel 21 according to a sixth modified example of the embodiment. The pixel 21 according to the sixth modified example has the same circuit configuration as that shown in FIG.

[0098] The pixel 21 according to the sixth modification is characterized in that the channel under the gate of the RST transistor 32 has a bilaterally symmetrical structure. This allows the first source 32s1 and the second source 32s2 of the RST transistor 32 to be arranged bilaterally symmetrically, and a single drain is provided on the axis of symmetry and connected to the power supply voltage VDD node. This symmetrical structure facilitates layout design. In the pixel 21 according to the sixth modification, similar to FIG. 5 , the first source 32s1 is connected to the second floating diffusion region FD2 via the active area AA1, and the second source 32s2 is connected to the third floating diffusion region FD3 via the active area AA2.

[0099] The pixel 21 according to the embodiment and the pixels 21 according to the first to sixth modifications described above are specific examples of the pixel 21 according to the present disclosure, and various modifications are possible. For example, the number of conversion efficiency switching transistors included in the pixel 21 may be any number equal to or greater than two. Furthermore, multiple pixels 21 may share multiple conversion efficiency switching transistors 35, multiple floating diffusion regions FD, and RST transistors 32. The circuit configuration of the pixel 21 is also not limited to that shown in FIG. 4, etc.

[0100] As described above, in the solid-state imaging device 1 according to one embodiment, the charges held in two or more of the floating diffusion regions FD provided in the pixel 21 can be discharged directly via the RST transistor 32, without passing through the conversion efficiency switching transistors 35. Therefore, even if the gate voltage drops when the conversion efficiency switching transistor 35 is turned off, the device is less susceptible to the influence of feedthrough, and it is possible to suppress an increase in the potential of the floating diffusion regions FD and a decrease in the amount of held charge.

[0101] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0102] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0103] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0104] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0105] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0106] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0107] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0108] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0109] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0110] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0111] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0112] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0113] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0114] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0115] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0116] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0117] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0118] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0119] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0120] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0121] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the above-described configurations. Specifically, the solid-state imaging device 1 according to the present embodiment can be applied to the imaging unit 12031. (By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.)

[0122] <Application Example to Endoscopic Surgery System> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0123] FIG. 21 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0124] 21 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0125] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0126] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0127] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0128] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0129] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0130] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0131] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0132] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0133] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0134] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0135] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0136] FIG. 22 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0137] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0138] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0139] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0140] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0141] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0142] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0143] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0144] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0145] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0146] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0147] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0148] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0149] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0150] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0151] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0152] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0153] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the endoscope 11100, the camera head 11102 (the imaging unit 11402), and the CCU 11201 (the image processing unit 11412) among the above-described components. Specifically, the solid-state imaging device 1 according to this embodiment can be applied to the imaging unit 10402. By applying the technology according to the present disclosure to the imaging unit 10402, a clearer image of the surgical site can be obtained, allowing the surgeon to reliably confirm the surgical site.

[0154] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0155] The present technology may have the following configurations: (1) A solid-state imaging device comprising: a photoelectric conversion element that generates charges according to the amount of incident light; a plurality of conversion efficiency switching transistors that switch to different photoelectric conversion efficiencies; a plurality of floating diffusion regions that respectively hold at least a portion of the charges generated in the photoelectric conversion element in accordance with on / off switching control of the plurality of conversion efficiency switching transistors; and a reset transistor that discharges the charges held in the plurality of floating diffusion regions to a reference voltage node, wherein the reset transistor discharges the charges held in two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors. (2) The solid-state imaging device according to (1), comprising two or more charge transfer regions that connect the reset transistor to each of the two or more floating diffusion regions. (3) The solid-state imaging device according to (2), wherein the reset transistor has two or more sources, and the two or more charge transfer regions have two or more diffusion regions that connect the two or more sources to the two or more floating diffusion regions. (4) The solid-state imaging device according to (2), wherein the reset transistor has two or more sources, and at least one of the two or more charge transfer regions has two or more metal members connecting the two or more sources and the two or more floating diffusion regions. (5) The solid-state imaging device according to (4), wherein the metal members include: a first contact member connected to the source of the reset transistor; a second contact member connected to the floating diffusion region; and a metal wiring layer connecting the first contact member and the second contact member at a height different from that of the source of the reset transistor and the floating diffusion region. (6) The solid-state imaging device according to any one of (3) to (5), wherein the reset transistor has a single gate corresponding to the two or more sources. (7) The solid-state imaging device according to any one of (3) to (5), wherein the reset transistor has two or more gates corresponding to the two or more sources and arranged spaced apart from each other, and a metal member connecting the two or more gates to each other.(8) The solid-state imaging device according to any one of (1) to (7), wherein the reset transistor has two or more drains connected to a reference voltage node. (9) The solid-state imaging device according to any one of (1) to (7), wherein the reset transistor has a single drain connected to a reference voltage node. (10) The solid-state imaging device according to any one of (1) to (9), further comprising a transfer transistor that sequentially transfers charges photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, wherein the reset transistor discharges charges held in the two or more floating diffusion regions other than a floating diffusion region to which charges are first transferred from the transfer transistor, of the plurality of floating diffusion regions, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors. (11) The solid-state imaging device according to any one of (1) to (9), further comprising: a transfer transistor that transfers charges photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and the reset transistor discharges charges held in two or more floating diffusion regions among the plurality of floating diffusion regions, including a floating diffusion region to which charges are first transferred from the transfer transistor, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors. (12) The solid-state imaging device according to any one of (1) to (11), further comprising: a pixel having two or more of the photoelectric conversion elements, wherein the plurality of floating diffusion regions include two or more floating diffusion regions that hold charges generated in the two or more photoelectric conversion elements, and the reset transistor discharges the charges held in the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions. (13) The solid-state imaging device according to (12), further comprising: a pixel having two or more of the photoelectric conversion elements, wherein the plurality of floating diffusion regions include two or more floating diffusion regions that hold charges generated in the two or more photoelectric conversion elements, and the reset transistor discharges the charges held in the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions.(14) A solid-state imaging device according to any one of (1) to (13), comprising: a pixel that outputs a pixel signal multiple times by controlling the on / off switching of the multiple conversion efficiency switching transistors in a single exposure operation, with each transistor having a different sensitivity; and a signal processing unit that converts the pixel signal into a digital signal and performs double data sampling (DDS) to detect a difference between the signal level and a reset level of the pixel signal, wherein the pixel has the photoelectric conversion element, the multiple conversion efficiency switching transistors, the multiple floating diffusion regions, and the reset transistor. (15) A solid-state imaging device according to any one of (1) to (13), comprising: a pixel that outputs a pixel signal multiple times by controlling the on / off switching of the multiple conversion efficiency switching transistors in a single exposure operation, with each transistor having a different sensitivity; and a signal processing unit that converts the pixel signal into a digital signal and performs correlated double sampling (CDS) to detect a difference between a reset level and a signal level of the pixel signal, wherein the pixel has the photoelectric conversion element, the multiple conversion efficiency switching transistors, the multiple floating diffusion regions, and the reset transistor. (16) An electronic device comprising: a solid-state imaging device that generates an image according to the amount of incident light; and a processing unit that processes the image, wherein the solid-state imaging device has: a photoelectric conversion element that generates charges according to the amount of incident light; a plurality of conversion efficiency switching transistors that each switch to a different photoelectric conversion efficiency; a plurality of floating diffusion regions that each hold at least a portion of the charges generated in the photoelectric conversion element according to on / off switching control of the plurality of conversion efficiency switching transistors; and a reset transistor that discharges the charges held in the plurality of floating diffusion regions to a reference voltage node, wherein the reset transistor discharges the charges held in two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

[0156] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0157] 1 Solid-state imaging device, 2 Imaging lens, 3 Image processing unit, 4 Recording unit, 5 Control unit, 10 Electronic device, 11 Pixel array unit, 12 Vertical driving unit, 13 Column processing unit, 14 Horizontal driving unit, 15 System control unit, 16 Signal processing unit, 17 Data storage unit, 18 Output unit, 21 Pixel, 22 Pixel driving wiring, 24 Current source, 28 Comparator, 29 Counter, 31 TG transistor, 32 RST transistor, 32a RST transistor, 32b RST transistor, 32c RST transistor, 32d1 First drain, 32d2 Second drain, 32g1 First gate, 32g2 Second gate, 32s1 First source, 32s2 Second source, 32s3 Third source, 33 AMP transistor, 34 SEL transistor, 35 FDG transistor, 36 FCG transistor, 37 FCG1 transistor, 41 Metal member, 42 metal member, AA active area, AA1 active area, AA2 active area, C1 first charge retention portion, C2 second charge retention portion, C3 third charge retention portion, FD floating diffusion region, FD1 first floating diffusion region, FD2 second floating diffusion region, FD3 third floating diffusion region, FD4 fourth floating diffusion region, FDG1 RST transistor, FDG2 RST transistor, PD photoelectric conversion element, PD1 first photoelectric conversion element, PD2 second photoelectric conversion element, VSL vertical signal line

Claims

1. A solid-state imaging device comprising: a photoelectric conversion element that generates charges according to the amount of incident light; a plurality of conversion efficiency switching transistors that each switch to a different photoelectric conversion efficiency; a plurality of floating diffusion regions that each hold at least a portion of the charges generated in the photoelectric conversion element in response to on / off switching control of the plurality of conversion efficiency switching transistors; and a reset transistor that discharges the charges held in the plurality of floating diffusion regions to a reference voltage node, wherein the reset transistor discharges the charges held in two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

2. The solid-state imaging device according to claim 1, further comprising two or more charge transfer regions connecting said reset transistor and said two or more floating diffusion regions, respectively.

3. The solid-state imaging device according to claim 2, wherein the reset transistor has two or more sources, and the two or more charge transfer regions have two or more diffusion regions connecting the two or more sources and the two or more floating diffusion regions.

4. The solid-state imaging device according to claim 2, wherein the reset transistor has two or more sources, and at least one of the two or more charge transfer regions has two or more metal members connecting the two or more sources and the two or more floating diffusion regions.

5. The solid-state imaging device of claim 4, wherein the metal member comprises: a first contact member connected to the source of the reset transistor; a second contact member connected to the floating diffusion region; and a metal wiring layer connecting the first contact member and the second contact member at a height different from that of the source of the reset transistor and the floating diffusion region.

6. The solid-state imaging device according to claim 3, wherein the reset transistor has a single gate corresponding to the two or more sources.

7. The solid-state imaging device according to claim 3, wherein the reset transistor has: two or more gates corresponding to the two or more sources and spaced apart from each other; and a metal member that connects the two or more gates together.

8. The solid-state imaging device according to claim 1, wherein the reset transistor has two or more drains connected to a reference voltage node.

9. The solid-state imaging device according to claim 1, wherein the reset transistor has a single drain connected to a reference voltage node.

10. A solid-state imaging device as described in claim 1, further comprising a transfer transistor which sequentially transfers charges photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and the reset transistor discharges the charges held in the two or more floating diffusion regions other than the floating diffusion region to which charges are first transferred from the transfer transistor, among the plurality of floating diffusion regions, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

11. A solid-state imaging device as described in claim 1, further comprising a transfer transistor which transfers charges photoelectrically converted by the photoelectric conversion element to the plurality of floating diffusion regions, and the reset transistor discharges the charges held in the two or more floating diffusion regions, including the floating diffusion region to which charges are first transferred from the transfer transistor, to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

12. The solid-state imaging device of claim 1, comprising a pixel having two or more of the photoelectric conversion elements, the plurality of floating diffusion regions having two or more floating diffusion regions that hold charges generated in the two or more photoelectric conversion elements, and the reset transistor discharging the charges held in the two or more floating diffusion regions to the reference voltage node without passing through other floating diffusion regions.

13. The solid-state imaging device according to claim 12, wherein the two or more photoelectric conversion elements have different light receiving areas.

14. A solid-state imaging device as described in claim 1, comprising: a pixel that outputs a pixel signal multiple times with different sensitivities by controlling the on / off switching of the multiple conversion efficiency switching transistors in a single exposure operation; and a signal processing unit that converts the pixel signal into a digital signal and performs double data sampling (DDS) to detect a difference between a signal level and a reset level of the pixel signal, wherein the pixel has the photoelectric conversion element, the multiple conversion efficiency switching transistors, the multiple floating diffusion regions, and the reset transistor.

15. A solid-state imaging device as described in claim 1, comprising: a pixel that outputs a pixel signal multiple times with different sensitivities by controlling the on / off switching of the multiple conversion efficiency switching transistors in a single exposure operation; and a signal processing unit that converts the pixel signal into a digital signal and performs correlated double sampling (CDS) to detect the difference between a reset level and a signal level of the pixel signal, wherein the pixel has the photoelectric conversion element, the multiple conversion efficiency switching transistors, the multiple floating diffusion regions, and the reset transistor.

16. An electronic device comprising: a solid-state imaging device that generates an image according to the amount of incident light; and a processing unit that processes the image, wherein the solid-state imaging device has: a photoelectric conversion element that generates charge according to the amount of incident light; a plurality of conversion efficiency switching transistors that each switch to a different photoelectric conversion efficiency; a plurality of floating diffusion regions that each hold at least a portion of the charge generated in the photoelectric conversion element in response to on / off switching control of the plurality of conversion efficiency switching transistors; and a reset transistor that discharges the charge held in the plurality of floating diffusion regions to a reference voltage node, wherein the reset transistor discharges the charge held in two or more of the plurality of floating diffusion regions to the reference voltage node without passing through the plurality of conversion efficiency switching transistors.

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