High-electron-mobility transistor and method for manufacturing same

Abstract

The present invention relates to a high-electron-mobility transistor and a method for manufacturing same. The method for manufacturing a high-electron-mobility transistor comprises the steps of: forming a HEMT structure by successively forming a buffer layer including InAlAs, a channel layer including InGaAs and having a 2DEG state, a spacer layer and a barrier layer including InAlAs, and a cap layer including InP on a substrate including InP; forming a dummy gate made of an oxide layer on the cap layer; removing regions corresponding to source / drain regions of the cap layer so as to expose diffusion regions corresponding to source / drain regions of the barrier layer; diffusing and doping Si atoms in the diffusion regions; forming sources and drains on the surface of the barrier layer in which the Si atoms are diffused and doped; and forming Ohmic electrodes on the sources and the drains. According to the present invention, the barrier layer reduces resistance components, thereby improving element operation characteristics in devices having small gate line widths, possible operating voltages can be increased by preventing device characteristics from being degraded due to hot electrons, and the low level of process reproducibility and instability of conventional recess processes can be overcome.

Description

High electron mobility transistor and its manufacturing method

[0001] The present invention relates to a high electron mobility transistor and a method for manufacturing the same. More specifically, the present invention relates to a high electron mobility transistor and a method for manufacturing the same, which can reduce the resistance component caused by a barrier layer between a conventional source / drain and a channel, reduce the possibility of hot electron generation caused by a sharp doping interface between a conventional cap layer and a channel, and overcome the low process reproducibility and instability of a conventional recess process.

[0002] As communications technology advances, research is being conducted on electronic devices used in the high-frequency range. In particular, field-effect semiconductor devices such as high electron mobility transistors (HEMTs) are attracting attention as power electronic devices used in the high-frequency range.

[0003] High-electron-mobility transistors (HEMs) comprise a heterojunction structure formed by adjacent semiconductor material layers with different band gaps, with the larger-bandgap semiconductor layer acting as a donor. By forming a heterojunction structure with materials with different band gaps, a two-dimensional electron gas (2DEG) layer is induced in the smaller-bandgap semiconductor layer, which can enhance electron mobility and other properties.

[0004] High-electron-mobility transistors (HEMs) can be used not only to increase electron carrier mobility, but also as high-voltage transistors, a type of power electronic device. HEMs include semiconductors with wide band gaps, such as compound semiconductors, and can exhibit relatively high breakdown voltages, making them suitable for applications requiring high voltages.

[0005] In the case of silicon, a material commonly used in semiconductor devices, high source resistance can occur due to low electron mobility, so research is currently being conducted to apply group III-V semiconductor compounds to high electron mobility transistors.

[0006] Meanwhile, due to the nature of the high electron mobility transistor structure, a barrier layer of a material with a large band gap is formed between the channel where the 2DEG is formed and the source / drain, which causes the current path to act as a high resistance component during device operation. In particular, as the gate line width is reduced to secure high RF operation characteristics, the proportion of this resistance component increases significantly, which is a problem.

[0007] [Prior Art Literature]

[0008] [Patent Document]

[0009] (Patent Document 1) Patent Publication No. 10-2014-0110617 (Published on September 17, 2014, Title: High Electron Mobility Transistor)

[0010] (Patent Document 2) Patent Publication No. 10-2011-0098439 (Published on September 1, 2011, Title: Manufacturing Method of High Electron Mobility Transistor)

[0011] (Patent Document 3) Patent Publication No. 10-2013-0007051 (Published on January 18, 2013, Title: High Electron Mobility Transistor and Manufacturing Method Thereof)

[0012] The technical problem of the present invention is to provide a high electron mobility transistor and a manufacturing method thereof capable of reducing the resistance component caused by a barrier layer between a conventional source / drain and a channel.

[0013] In addition, the technical task of the present invention is to provide a high electron mobility transistor and a manufacturing method thereof that can reduce the possibility of hot electron generation due to a sharp doping interface between a conventional cap layer and a channel.

[0014] In addition, the technical task of the present invention is to provide a high electron mobility transistor and a manufacturing method thereof that can overcome the low process reproducibility and instability of the conventional recess process.

[0015] In order to solve these technical problems, the method for manufacturing a high electron mobility transistor according to the present invention includes a HEMT structure forming step of sequentially forming a buffer layer including InAlAs on a substrate including InP, a channel layer including InGaAs and having a 2DEG (2-dimensional electron gas) state, a spacer layer and a barrier layer including InAlAs, and a cap layer including InP to form a HEMT structure, a dummy gate forming step of forming a dummy gate made of an oxide layer on the cap layer, a diffusion region exposing step of removing a region corresponding to a source / drain region of the cap layer to expose a diffusion region corresponding to the source / drain region of the barrier layer, a diffusion doping step of diffusion-doping Si atoms into the diffusion region, a source / drain forming step of forming a source and a drain on a surface of the barrier layer into which the Si atoms are diffusion-doped, and an ohmic electrode forming step of forming an ohmic electrode on the source and the drain.

[0016] In the method for manufacturing a high electron mobility transistor according to the present invention, in the HEMT structure forming step, the barrier layer and spacer layer including InAlAs are characterized in that they are Si delta-doped.

[0017] In the method for manufacturing a high electron mobility transistor according to the present invention, in the diffusion doping step, Si atoms are diffusion-doped into the diffusion region to change the region corresponding to the source / drain region of the barrier layer and the spacer layer into an n-type InAlAs layer, and the region corresponding to the source / drain region of the channel layer into an n-type InGaAs layer.

[0018] In the method for manufacturing a high electron mobility transistor according to the present invention, in the diffusion doping step, the region of the barrier layer and the spacer layer located below the dummy gate and covered by the dummy gate maintains the state of Si delta doping, thereby allowing the channel layer to maintain the 2DEG state.

[0019] In the method for manufacturing a high electron mobility transistor according to the present invention, in the diffusion doping step, the Si atoms are laterally diffused into a portion of a barrier layer, a spacer layer, and a channel layer located below the dummy gate, thereby forming an LD (Lightly Doping) region between the channel layer, the source, and the drain.

[0020] In the method for manufacturing a high electron mobility transistor according to the present invention, in the source / drain forming step, the source and the drain are formed by sequentially re-growing an n+ InAlAs layer and an n+ InGaAs layer on the surface of the barrier layer changed into the n-type InAlAs layer.

[0021] In the method for manufacturing a high electron mobility transistor according to the present invention, the current between the source and the drain is characterized in that it flows from the n+ InGaAs layer and the n+ InAlAs layer, which are re-grown layers, through the n-type InAlAs layer and the n-type InGaAs layer, which are diffusion layers, to the channel layer having the 2DEG (2-dimensional electron gas) state.

[0022] The method for manufacturing a high electron mobility transistor according to the present invention is characterized in that it further includes a gate electrode forming step of forming a gate electrode on a cap layer exposed after removing a portion of the dummy gate after the ohmic electrode forming step.

[0023] In the method for manufacturing a high electron mobility transistor according to the present invention, the cap layer including InP is characterized in that it prevents natural oxidation of the barrier layer including InAlAs located therebelow.

[0024] A high electron mobility transistor according to the present invention is manufactured using a high electron mobility transistor manufacturing method according to the present invention.

[0025] According to the present invention, there is an effect of improving the device operating characteristics in a device with a low gate line width by reducing the resistance component due to the barrier layer.

[0026] Additionally, it has the effect of preventing deterioration of device characteristics due to hot electrons, thereby increasing the possible operating voltage.

[0027] Additionally, it has the effect of overcoming the low process reproducibility and instability of the conventional recess process.

[0028] Figure 1 is a process flow diagram of a method for manufacturing a high electron mobility transistor according to one embodiment of the present invention.

[0029] FIG. 2 is an exemplary process cross-sectional view for explaining a HEMT structure forming step in one embodiment of the present invention.

[0030] FIG. 3 is an exemplary process cross-sectional view for explaining a dummy gate formation step in one embodiment of the present invention.

[0031] FIG. 4 is an exemplary process cross-sectional view for explaining a diffusion region exposure step in one embodiment of the present invention.

[0032] FIG. 5 and FIG. 6 are exemplary process cross-sectional views for explaining the diffusion doping step in one embodiment of the present invention.

[0033] FIG. 7 and FIG. 8 are exemplary process cross-sectional views for explaining a source / drain formation step in one embodiment of the present invention.

[0034] FIG. 9 is an exemplary process cross-sectional view for explaining an ohmic electrode forming step in one embodiment of the present invention.

[0035] FIG. 10 is an exemplary process cross-sectional view for explaining a gate electrode forming step in one embodiment of the present invention.

[0036] FIG. 11 is a drawing for explaining the current flow of a high electron mobility transistor manufactured according to one embodiment of the present invention.

[0037] FIG. 12 is a diagram schematically showing a process sequence in which one embodiment of the present invention is equally applied to a GaN-HEMT structure.

[0038] Any specific structural or functional descriptions of embodiments according to the concept of the present invention disclosed in this specification are merely illustrative for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and are not limited to the embodiments described in this specification.

[0039] Embodiments according to the concept of the present invention may have various modifications and take various forms, and thus, embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit embodiments according to the concept of the present invention to specific disclosed forms, but rather includes all modifications, equivalents, or alternatives falling within the spirit and technical scope of the present invention.

[0040] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0042] FIG. 1 is a process flow diagram of a high electron mobility transistor manufacturing method according to an embodiment of the present invention, FIG. 2 is an exemplary process cross-sectional diagram for explaining a HEMT structure forming step (S10), FIG. 3 is an exemplary process cross-sectional diagram for explaining a dummy gate forming step (S20), FIG. 4 is an exemplary process cross-sectional diagram for explaining a diffusion region exposure step (S30), FIGS. 5 and 6 are exemplary process cross-sectional diagrams for explaining a diffusion doping step (S40), FIGS. 7 and 8 are exemplary process cross-sectional diagrams for explaining a source / drain forming step (S50), FIG. 9 is an exemplary process cross-sectional diagram for explaining an ohmic electrode forming step (S60), and FIG. 10 is an exemplary process cross-sectional diagram for explaining a gate electrode forming step (S70).

[0043] Referring to FIGS. 1 to 10, a method for manufacturing a high electron mobility transistor according to an embodiment of the present invention may be configured to include a HEMT structure forming step (S10), a dummy gate forming step (S20), a diffusion region exposure step (S30), a diffusion doping step (S40), a source / drain forming step (S50), an ohmic electrode forming step (S60), and a gate electrode forming step (S70).

[0044] First, referring to FIGS. 1 and 2, in the HEMT structure forming step (S10), a process of forming a HEMT structure (10) is performed by sequentially forming a buffer layer (200) including InAlAs on a substrate (100) including InP, a channel layer (300) including InGaAs and having a 2DEG (2-dimensional electron gas) state, a spacer layer (400) and a barrier layer (500) including InAlAs, and a cap layer (600) including InP.

[0045] For example, in the HEMT structure formation step (S10), the barrier layer (500) and the spacer layer (400) including InAlAs may be Si delta-doped, and the cap layer (600) including InP may be configured to prevent natural oxidation of the barrier layer (500) including InAlAs located therebelow.

[0046] Next, referring to FIGS. 1 and 3, in the dummy gate forming step (S20), a process of forming a dummy gate (20) made of an oxide layer on a cap layer (600) is performed. For example, in the dummy gate forming step (S20), a diffusion process may be performed in an area where a source (S) and a drain (D) are to be formed, and a patterning process may be performed on the dummy gate (20) that serves as a masking layer with an oxide layer to prevent diffusion doping of an actual channel area.

[0047] Next, referring to FIGS. 1 and 4, in the diffusion region exposure step (S30), a process is performed in which a region corresponding to the source / drain region where the source (S) and drain (D) are to be formed is removed from the entire region of the cap layer (600), thereby exposing the diffusion region (30) corresponding to the source / drain region from the entire region of the barrier layer (500).

[0048] Next, referring to FIG. 1, FIG. 5 and FIG. 6, in the diffusion doping step (S40), a process of diffusion doping Si atoms into the diffusion region (30) is performed.

[0049] For example, in the diffusion doping step (S40), Si atoms are diffused into the diffusion region (30) to change the region corresponding to the source / drain region of the barrier layer (500) and spacer layer (400) including InAlAs into an n-type InAlAs layer (31), and the region corresponding to the source / drain region of the channel layer (300) including InGaAs and having a 2DEG (2-dimensional electron gas) state into an n-type InGaAs layer (32).

[0050] In addition, for example, in the diffusion doping step (S40), the region of the barrier layer (500) and the spacer layer (400) located below the dummy gate (20) and covered by the dummy gate (20) can be configured to maintain a state of Si delta doping, thereby allowing the channel layer (300) to maintain a 2DEG state.

[0051] In addition, for example, in the diffusion doping step (S40), Si atoms may be configured to diffuse laterally into a portion of the barrier layer (500) and spacer layer (400) located below the dummy gate (20) and the channel layer (300), thereby forming an LD (Lightly Doping) region between the channel layer (300) and the source (S) and drain (D).

[0052] The composition of this diffusion doping step (S40) is described more specifically and illustratively as follows.

[0053] For example, in the diffusion doping step (S40), a sample whose diffusion region (30) was exposed in the previous step may be introduced into a MOCVD (metal-organic chemical vapor deposition) process chamber for performing an epitaxial process, and a diffusion process may be performed by flowing SiH4 gas at a high temperature. When the Si atoms decomposed from SiH4 are doped into the lower layer through diffusion, an n-type InAlAs layer (31) is formed in the region where the spacer layer (400) and barrier layer (500) including the existing InAlAs were, and an n-type InGaAs layer (32) is formed in the region where the channel layer (300) including InGaAs was. On the other hand, the region covered by the dummy gate (20) maintains Si delta doping, so that a 2DEG can be maintained inside the channel layer (300). In addition, as diffusion occurs naturally in the lateral direction, a lightly doped (LD) region is formed due to diffusion between the n+ layer and the channel layer (300) that will be re-grown later, thereby preventing a rapid change in doping distribution.

[0054] Next, referring to FIG. 1, FIG. 7 and FIG. 8, in the source / drain formation step (S50), a process of forming a source (S) and a drain (D) on the surface of a barrier layer (500) into which Si atoms are diffusion-doped is performed.

[0055] For example, in the source / drain formation step (S50), the source (S) and drain (D) can be formed by sequentially re-growing an n+ InAlAs layer (41) and an n+ InGaAs layer (42) on the surface of the barrier layer (500) that has been changed to an n-type InAlAs layer (31).

[0056] The configuration of this source / drain formation step (S50) is described more specifically and illustratively as follows.

[0057] For example, in the source / drain formation step (S50), the re-growth process may be configured to proceed directly on the surface of the n-type InAlAs layer (31) formed by diffusion doping in the MOCVD chamber. The n+ InAlAs layer (41) and the n+ InGaAs layer (42) may be sequentially re-grown to form a source (S) / drain (D) that will later come into contact with the ohmic electrodes (71, 72). The initial re-growth layer of the n+ InAlAs layer (41) forms a homojunction of the same material as the existing diffusion-doped n-type InAlAs layer (31), thereby lowering the contact resistance between the re-growth layer and the diffusion layer and improving the interface characteristics. In addition, the re-growth of the n+ InGaAs layer (42) may subsequently reduce the contact resistance between metals, thereby improving the device performance.

[0058] Next, referring to FIG. 1 and FIG. 9, in the ohmic electrode formation step (S60), a process of forming ohmic electrodes (71, 72) on the source (S) and drain (D) is performed.

[0059] Next, referring to FIG. 1 and FIG. 10, in the gate electrode formation step (S70), a process of forming a gate electrode (G) on the cap layer (600) exposed after removing a portion of the dummy gate (20) is performed.

[0060] Referring to FIG. 11 for explaining the current flow of a high electron mobility transistor manufactured according to one embodiment of the present invention, the current between the source (S) and the drain (D) can be configured to flow from the n+ InGaAs layer (42) and the n+ InAlAs layer (41), which are re-grown layers, through the n-type InAlAs layer (31) and the n-type InGaAs layer (32), which are diffusion layers, to the channel layer (300) having the 2DEG (2-dimensional electron gas) state. According to this configuration, the resistance component generated by the current between the source (S) and the drain (D) in the past passing through the barrier layer (500) can be effectively reduced.

[0061] FIG. 12 is a diagram schematically showing a process sequence in which one embodiment of the present invention is equally applied to a GaN-HEMT structure.

[0062] Referring additionally to FIG. 12, a series of processes of a high electron mobility transistor manufacturing method according to an embodiment of the present invention, which has been described in detail with reference to FIGS. 1 to 11 above, can be equally applied to a GaN-HEMT structure, such that the high resistance component of a barrier layer including AlGaN can be lowered by utilizing diffusion doping, and the ohmic characteristics of the source / drain region can be improved by utilizing a regrown n+ layer.

[0063] As described in detail above, according to the present invention, there is an effect of improving the device operating characteristics in a device with a low gate line width by reducing the resistance component due to the barrier layer.

[0064] Additionally, it has the effect of preventing deterioration of device characteristics due to hot electrons, thereby increasing the possible operating voltage.

[0065] Additionally, it has the effect of overcoming the low process reproducibility and instability of the conventional recess process.

[0066] [Explanation of symbols]

[0067] 10: HEMT structure

[0068] 100: Substrate

[0069] 200: Buffer layer

[0070] 300: Channel layer

[0071] 400: Spacer layer

[0072] 500: Barrier layer

[0073] 600: Cap layer

[0074] 20: Dummy Gate

[0075] 30: Diffusion area

[0076] 31: n-type InAlAs layer

[0077] 32: n-type InGaAs layer

[0078] 41: n+ InAlAs layer

[0079] 42: n+ InGaAs layer

[0080] 71, 72: Ohmic electrode

[0081] S: Source

[0082] D: Drain

[0083] G: Gate electrode

[0084] S10: HEMT structure formation step

[0085] S20: Dummy gate formation step

[0086] S30: Diffusion area exposure stage

[0087] S40: Diffusion doping step

[0088] S50: Source / Drain Formation Stage

[0089] S60: Ohmic electrode formation step

[0090] S70: Gate electrode formation step

Claims

1. A method for manufacturing a high electron mobility transistor, A HEMT structure forming step of forming a HEMT structure by sequentially forming a buffer layer including InAlAs on a substrate including InP, a channel layer including InGaAs and having a 2DEG (2-dimensional electron gas) state, a spacer layer and a barrier layer including InAlAs, and a cap layer including InP; A dummy gate formation step of forming a dummy gate made of an oxide layer on the cap layer; A diffusion region exposure step for removing a region corresponding to the source / drain region of the cap layer to expose a diffusion region corresponding to the source / drain region of the barrier layer; A diffusion doping step of diffusion doping Si atoms into the above diffusion region; A source / drain formation step of forming a source and drain on the surface of a barrier layer into which the Si atoms are diffusely doped; and A method for manufacturing a high electron mobility transistor, comprising an ohmic electrode forming step of forming an ohmic electrode on the source and the drain.

2. In paragraph 1, In the above HEMT structure formation step, A method for manufacturing a high electron mobility transistor, characterized in that the barrier layer and spacer layer including the above InAlAs are Si delta-doped.

3. In paragraph 2, In the above diffusion doping step, A method for manufacturing a high electron mobility transistor, characterized in that the above diffusion region is diffusion-doped with Si atoms to change the region corresponding to the source / drain region of the barrier layer and the spacer layer into an n-type InAlAs layer, and the region corresponding to the source / drain region of the channel layer into an n-type InGaAs layer.

4. In paragraph 3, In the above diffusion doping step, A method for manufacturing a high electron mobility transistor, characterized in that the region of the barrier layer and the spacer layer located below the dummy gate and covered by the dummy gate maintains the state of Si delta doping, thereby allowing the channel layer to maintain the 2DEG state.

5. In paragraph 3, In the above diffusion doping step, A method for manufacturing a high electron mobility transistor, characterized in that the Si atoms diffuse laterally into a portion of a barrier layer, a spacer layer, and a channel layer located below the dummy gate, thereby forming an LD (Lightly Doping) region between the channel layer, the source, and the drain.

6. In paragraph 3 In the above source / drain formation step, A method for manufacturing a high electron mobility transistor, characterized in that the source and the drain are formed by sequentially re-growing an n+ InAlAs layer and an n+ InGaAs layer on the surface of a barrier layer changed into the n-type InAlAs layer.

7. In paragraph 6, A method for manufacturing a high electron mobility transistor, characterized in that the current between the source and the drain flows from the n+ InGaAs layer and the n+ InAlAs layer, which are re-grown layers, through the n-type InAlAs layer and the n-type InGaAs layer, which are diffusion layers, to the channel layer having the 2DEG (2-dimensional electron gas) state.

8. In paragraph 1, A method for manufacturing a high electron mobility transistor, characterized in that it further includes a gate electrode forming step of forming a gate electrode on a cap layer exposed after removing a part of the dummy gate after the above ohmic electrode forming step.

9. In paragraph 1, A method for manufacturing a high electron mobility transistor, characterized in that the cap layer including the InP prevents natural oxidation of the barrier layer including the InAlAs located thereunder.

10. A high electron mobility transistor manufactured by any one of the manufacturing methods of claims 1 to 9.

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