True random number generator, integrated circuit, control method, chip and electronic device

Abstract

The present application provides a true random number generator, an integrated circuit, a control method, a chip and an electronic device. The true random number generator comprises: a first oscillator; a second oscillator having adjustable phase and oscillation frequency; a sampling module having a data input end connected to a signal output end of the first oscillator, and a clock end connected to a signal output end of the second oscillator; and an entropy value analysis module having an input end separately connected to a signal output end of the sampling module, the signal output end of the first oscillator and the signal output end of the second oscillator, and an output end connected to the second oscillator, the entropy value analysis module being used for adjusting the phase and / or oscillation frequency of the second oscillator on the basis of an output signal of the first oscillator, an output signal of the second oscillator and an output signal of the sampling module. According to the present application, the phase and oscillation frequency of the second oscillator can be adjusted by means of the entropy value analysis module, so that an entropy value of an output sequence can reach a target entropy value, thereby reducing the area of a chip and reducing the power consumption.

Description

True random number generator, integrated circuit and control method, chip and electronic device

[0001] This application claims priority to Chinese patent application No. 202311680949.6 filed on December 7, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as part of this application. Technical Field

[0002] The embodiments of the present application relate to a true random number generator, an integrated circuit and a control method, a chip and an electronic device. Background Art

[0003] Common true random number generators are usually implemented using two free-running ring oscillators, ring1 and ring2, and a D flip-flop for sampling, as shown in Figure 1. Ring1 outputs a high-frequency clock signal f h , connected to the data input D terminal of the D flip-flop; ring2 outputs the low-frequency clock signal f s As the sampling clock, it is connected to the clk (clock) terminal of the D flip-flop. Ring 1 and ring 2 are independent of each other and generate different oscillation frequencies. Due to the presence of thermal noise and interference in the circuit, the clock signal f h and f s There is jitter, and f h Much larger than f s , high frequency clock f h The jitter of the sampling clock is much larger than the s The jitter of the sampling clock f s The high frequency clock f is sampled by a D flip-flop h The jitter makes the output sequence Q OUT It has uncertainty, that is, a sequence with a certain degree of randomness is obtained.

[0004] For this type of true random number generator, the sampling clock f s The closer the sampling point is to the center of the high-frequency clock jitter distribution, the greater the entropy of the output sequence, and vice versa. Since system safety requirements are related to the entropy of the output sequence, in many scenarios the entropy of the output sequence must reach a set target entropy value to meet safety requirements.

[0005] Currently, to ensure that the entropy of the output sequence reaches the target entropy value, the number of high-frequency ring oscillators is typically increased, filling the entire high-frequency clock cycle with jitter to ensure that the entropy of the output sequence reaches the target entropy value. However, this approach requires a large number of ring oscillators, resulting in larger chip area and higher power consumption.

[0006] Summary of the Invention

[0007] The purpose of the embodiments of the present application is to provide a true random number generator, an integrated circuit and a control method, a chip and an electronic device to solve the problem existing in the related art that, in order to ensure that the entropy value of the output sequence can reach the target entropy value, multiple high-frequency oscillators need to be set up, resulting in a large chip area and high power consumption.

[0008] An embodiment of the present application provides a true random number generator, comprising: a first oscillator; a second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable; a sampling module, wherein a data input end of the sampling module is connected to a signal output end of the first oscillator, a clock end of the sampling module is connected to a signal output end of the second oscillator, and the sampling module is used to sample and output the output signal of the first oscillator according to the output signal of the second oscillator; an entropy analysis module, wherein an input end of the entropy analysis module is respectively connected to the signal output end of the sampling module, the signal output end of the first oscillator, and the signal output end of the second oscillator, an output end of the entropy analysis module is connected to the second oscillator, and the entropy analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator, and the output signal of the sampling module.

[0009] In the above implementation, the entropy analysis module can adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module. This allows the true random number generator to adjust the phase and oscillation frequency of the second oscillator to a suitable position through the action of the entropy analysis module when it is working, so that even if the true random number generator does not set up multiple high-frequency oscillators, the entropy value of the output sequence can reach the target entropy value, thereby reducing the chip area and power consumption.

[0010] Furthermore, the second oscillator includes: a first delay unit, the input end of the first delay unit is connected to the first output end of the entropy analysis module, and the first delay unit generates different delays in response to different output signals of the first output end.

[0011] In the above implementation, a first delay unit is set in the second oscillator. By adjusting the delay of the first delay unit, the delay time value from the signal input to the signal output in the second oscillator can be adjusted, that is, the signal period of the second oscillator can be adjusted (since the signal period and the oscillation frequency are reciprocals of each other, the oscillation frequency of the second oscillator can also be adjusted).

[0012] Furthermore, the true random number generator also includes a second delay unit and an enable signal receiving end; the input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; the input end of the second delay unit is connected to the second output end of the entropy analysis module, and the second delay unit generates different delays in response to different output signals of the second output end.

[0013] In the above implementation, since the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit, and the input end of the first oscillator is directly connected to the enable signal receiving end, once the delay time of the second delay unit changes, the time difference between the enable signal reaching the first oscillator and the second oscillator will change, thereby causing the phase of the output signal of the second oscillator relative to the output signal of the first oscillator to change, thereby achieving phase adjustment of the second oscillator.

[0014] Furthermore, the entropy analysis module includes: a first counter, a second counter and a first judgment circuit; the first counter is respectively connected to a preset reference clock source and a signal output end of the first oscillator to count the output signal of the first oscillator according to the reference clock source; the second counter is respectively connected to the reference clock source and the signal output end of the second oscillator to count the output signal of the second oscillator according to the reference clock source; the input end of the first judgment circuit is respectively connected to the output end of the first counter and the second counter, and the output end of the first judgment circuit is connected to the second oscillator; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0015] In the above implementation, the first counter can effectively record the number of rising edges or falling edges generated by the output signal of the first oscillator within a reference clock (this number reflects the frequency of the output signal of the first oscillator, that is, the oscillation frequency of the first oscillator), and the second counter can effectively record the number of rising edges or falling edges generated by the output signal of the second oscillator within a reference clock (this number reflects the frequency of the output signal of the second oscillator, that is, the oscillation frequency of the second oscillator). Based on the count values ​​of the first counter and the second counter, the first judgment circuit can determine whether the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator, and then determine whether the signal currently output by the second oscillator is suitable for sampling by the sampling module. Therefore, when it is not suitable, the oscillation frequency of the second oscillator can be adjusted.

[0016] Furthermore, the entropy analysis module includes: a third counter and a second judgment circuit; the third counter is respectively connected to the signal output end of the second oscillator and the signal output end of the sampling module, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; the input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the second delay unit, and the second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

[0017] In the above implementation, the third counter can be used to count the number of cycles experienced when a signal transition occurs in the output signal of the sampling module. The entropy value of the output sequence output by the true random number generator (i.e., the sequence composed of the output signals of the sampling module) is related to the number of cycles experienced when a signal transition occurs in the output signal of the sampling module. The greater the number of cycles experienced when a signal transition occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence is in theory. In the above implementation, by presetting the signal transition cycle threshold, the delay of the second delay unit can be adjusted when the count value of the third counter is greater than the preset signal transition cycle threshold, that is, the phase of the second oscillator is adjusted. This makes it possible to adjust the sampling point of the output signal of the second oscillator slowly toward the center position of the jitter distribution of the output signal of the first oscillator by adjusting the phase of the second oscillator, so that the entropy value of the output sequence can reach the target entropy value.

[0018] The present application also provides an integrated circuit, comprising: an entropy analysis module and a plurality of true random number generators; each of the true random number generators comprises: a first oscillator; a second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable; a sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is configured to sample and output an output signal of the first oscillator based on an output signal of the second oscillator;

[0019] The input end of the entropy analysis module is respectively connected to the signal output end of the sampling module of each true random number generator through a first multiplexer; the input end of the entropy analysis module is also respectively connected to the signal output end of the first oscillator of each true random number generator through a second multiplexer; the input end of the entropy analysis module is also respectively connected to the signal output end of the second oscillator of each true random number generator through a third multiplexer; the output end of the entropy analysis module is respectively connected to the second oscillator of each true random number generator through a fourth multiplexer; the entropy analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator of any one of the true random number generators according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module.

[0020] Based on the above integrated circuit, since the entropy analysis module can adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module, this allows the true random number generator to adjust the phase and oscillation frequency of the second oscillator to appropriate positions through the action of the entropy analysis module when it is working. As a result, even if the true random number generator does not set up multiple high-frequency oscillators, the entropy value of the output sequence can reach the target entropy value, thereby reducing chip area and power consumption.

[0021] At the same time, based on the above-mentioned integrated circuit, it is only necessary to control each multiplexer so that the entropy analysis module is connected to one true random number generator each time, and then one entropy analysis module can be used to adjust the phase and oscillation frequency of the second oscillator of different true random number generators in turn, thereby realizing the reuse of multiple true random number generators for the entropy analysis module, further reducing chip area overhead and power consumption.

[0022] Furthermore, for any one of the true random number generators, the second oscillator includes: a first delay unit; the first output end of the entropy analysis module is connected to the input end of the first delay unit of each of the true random number generators through the fourth multiplexer; the first delay unit generates different delays in response to different output signals of the first output end.

[0023] Furthermore, for any one of the true random number generators, the true random number generator also includes a second delay unit and an enable signal receiving end; the input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; the second output end of the entropy analysis module is connected to the input end of the second delay unit of each of the true random number generators through a fifth multiplexer; the second delay unit generates different delays in response to different output signals of the second output end.

[0024] Furthermore, the entropy analysis module includes: a first counter, a second counter and a first judgment circuit; the first counter is connected to a preset reference clock source, and is connected to the signal output end of the first oscillator of each of the true random number generators through a second multiplexer, so as to count the output signal of the first oscillator according to the reference clock source; the second counter is connected to the reference clock source, and is connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer, so as to count the output signal of the second oscillator according to the reference clock source; the input end of the first judgment circuit is respectively connected to the output end of the first counter and the second counter, and the output end of the first judgment circuit is respectively connected to the second oscillator of each of the true random number generators through the fourth multiplexer; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0025] Furthermore, the entropy analysis module includes: a third counter and a second judgment circuit; the third counter is respectively connected to the signal output end of the second oscillator of each true random number generator through the third multiplexer, and is respectively connected to the signal output end of the sampling module of each true random number generator through the first multiplexer, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; the input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is respectively connected to the input end of the second delay unit of each true random number generator through the fifth multiplexer, and the second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

[0026] An embodiment of the present application also provides a control method, which is applied to any of the aforementioned true random number generators, and the method includes: the entropy analysis module adjusts the oscillation frequency of the second oscillator in response to the rising edge of the output signal of the second oscillator and the rising edge or falling edge of the output signal of the first oscillator being misaligned; the entropy analysis module determines whether the number of cycles experienced when a signal transition occurs in the output signal of the sampling module is less than or equal to a preset signal transition period threshold in response to the rising edge of the output signal of the second oscillator and the rising edge or falling edge of the output signal of the first oscillator being aligned; if the number of cycles experienced when a signal transition occurs in the output signal of the sampling module is greater than the signal transition period threshold, adjusting the phase of the second oscillator.

[0027] In the above implementation, when the rising edge of the output signal of the second oscillator is not aligned with the rising edge or falling edge of the output signal of the first oscillator, it means that when the sampling module samples the output signal of the first oscillator under the triggering of the output signal of the second oscillator, it samples a fixed value, thus not meeting the random number generation requirements. Therefore, it is necessary to adjust the signal frequency of the output signal of the second oscillator (i.e., the oscillation frequency of the second oscillator) so that the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator, so that when the sampling module samples the output signal of the first oscillator under the triggering of the output signal of the second oscillator, it samples a random value in a metastable state. When the conditions for random number generation are met, since the entropy value of the output sequence output by the true random number generator (i.e., the sequence composed of the output signals of the sampling module) is related to the number of cycles experienced when the output signal of the sampling module undergoes a signal transition, the greater the number of cycles experienced when the output signal of the sampling module undergoes a signal transition, the smaller the entropy value of the output sequence. Therefore, when the number of cycles experienced during a signal jump is greater than the signal jump period threshold, the phase of the second oscillator is adjusted. This allows the sampling center of the output signal of the second oscillator to be slowly adjusted toward the center position of the jitter distribution of the output signal of the first oscillator by continuously adjusting the phase of the second oscillator (that is, the number of cycles experienced when a signal jump occurs in the output signal of the sampling module gradually decreases), so that the entropy value of the output sequence can reach the target entropy value.

[0028] An embodiment of the present application further provides a control method, which is applied to any of the aforementioned integrated circuits, the method comprising: in response to a conduction control signal, the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer connect the entropy analysis module to the true random number generator corresponding to the conduction control signal among the multiple true random number generators; the entropy analysis module adjusts the true random number generator in response to the rising edge of the output signal of the second oscillator of the true random number generator and the rising edge or falling edge of the output signal of the first oscillator of the true random number generator not being aligned the entropy analysis module determines, in response to the alignment of the rising edge of the output signal of the second oscillator of the true random number generator and the rising edge or the falling edge of the output signal of the first oscillator of the true random number generator, whether the number of cycles experienced when a signal transition occurs in the output signal of the sampling module of the true random number generator is less than or equal to a preset signal transition period threshold; if the number of cycles experienced when a signal transition occurs in the output signal of the sampling module of the true random number generator is greater than the signal transition period threshold, adjusting the phase of the second oscillator of the true random number generator.

[0029] In the above implementation, the entropy analysis module can be controlled by a conduction control signal to adjust the oscillation frequency and phase of the second oscillator of a particular true random number generator. As described above, the oscillation frequency and phase of the second oscillator in the true random number generator can be adjusted to a range that allows the entropy of the output sequence of the true random number generator to reach a target entropy value, eliminating the need for multiple high-frequency oscillators. Furthermore, the conduction control signal allows multiple true random number generators to reuse a single entropy analysis module, further reducing chip area and power consumption.

[0030] An embodiment of the present application further provides a chip comprising any one of the aforementioned true random number generators, or comprising any one of the aforementioned integrated circuits.

[0031] An embodiment of the present application also provides an electronic device, including the aforementioned chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a schematic diagram of a true random number generator based on FIG;

[0034] FIG2 is a schematic diagram showing the corresponding relationship between sampling points, high-frequency clock signal jitter distribution, and entropy value in a true random number generator;

[0035] FIG3 is a schematic diagram of the basic structure of a true random number generator provided in an embodiment of the present application;

[0036] FIG4 is a schematic structural diagram of a specific true random number generator provided in an embodiment of the present application;

[0037] FIG5 is a schematic structural diagram of a specific first delay unit provided in an embodiment of the present application;

[0038] FIG6 is a schematic structural diagram of a true random number generator provided with a second delay unit according to an embodiment of the present application;

[0039] FIG7 is a schematic structural diagram of a specific second delay unit provided in an embodiment of the present application;

[0040] FIG8 is a schematic diagram of the structure of an entropy analysis module provided in an embodiment of the present application;

[0041] FIG9 is a flow chart of a control method provided in an embodiment of the present application and applied to a true random number generator provided in the present application;

[0042] FIG10 is a schematic diagram of the basic structure of an integrated circuit of an entropy analysis module for multiplexing true random numbers provided in an embodiment of the present application;

[0043] FIG11 is a schematic structural diagram of a method of setting a first delay unit in each true random number according to an embodiment of the present application;

[0044] FIG12 is a schematic diagram of a structure in which a second delay unit is provided in each true random number according to an embodiment of the present application;

[0045] FIG13 is a schematic diagram of the structure of a multiplexed entropy analysis module provided in an embodiment of the present application;

[0046] FIG14 is a flow chart of a control method provided in an embodiment of the present application and applied to an integrated circuit provided in the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0048] For the true random number generator shown in Figure 1, the information entropy of the output sequence QOUT is calculated by formula (1): H(p) = -p*log2p–(1-p)*log2(1-p) Formula (1)

[0049] Where p is the probability of output being 1, and 1-p is the probability of output being 0. High-frequency clock signal f h The jitter distribution of is a normal distribution (μ,σ), where μ is the mean value and σ is the variance value. The sampling clock signal f s The sampling point of the D flip-flop is at different positions in the high-frequency clock jitter distribution, and the output will obtain different entropy values. As shown in Figure 2, if the sampling point is within (μ-3σ, μ+3σ), the maximum probability of sampling 1 is 0.998, and the entropy value of the output sequence QOUT is ≥0.01; if the sampling point is within the range of (μ-2σ, μ+2σ), the maximum probability of the D flip-flop sampling 1 is 0.977, and the entropy value of the output sequence QOUT is ≥0.16; if the sampling point is within the range of (μ-σ, μ+σ), the maximum probability of the D flip-flop sampling 1 is 0.841, and the entropy value of the output sequence QOUT is ≥0.63. It can be seen that the sampling clock signal f s The closer the sampling point is to the high-frequency clock signal f h The closer the center position of the jitter distribution is, the larger the entropy value of the output sequence QOUT is, and vice versa.

[0050] Since the system safety requirements are related to the entropy of the output sequence, in many scenarios, the entropy of the output sequence must reach the set target entropy to meet the safety requirements. In order to make the entropy of the output sequence reach the set target entropy, the current method is usually to increase the number of high-frequency ring oscillators and fill the entire high-frequency clock cycle with jitter, thereby ensuring that the entropy of the output sequence can reach the target entropy. Assuming the target entropy is 0.5, the low-frequency clock sampling points must all be within the jitter distribution of the high-frequency clock signal (μ-1.23σ, μ+1.23σ). Assuming that there is no overlap between the high-frequency clock jitter distributions of each high-frequency ring oscillator, the number of high-frequency ring oscillators n required to satisfy formula (2) can fill the entire high-frequency clock cycle with jitter, thereby ensuring that the entropy of the output sequence can reach the target entropy. n>T / 2.46σ Formula (2)

[0051] Where T is the period of the high-frequency ring oscillator. If σ = 0.01T, 41 high-frequency ring oscillators are required; if σ = 0.001T, 410 high-frequency ring oscillators are required. This approach requires a large number of ring oscillators, resulting in larger chip area and higher power consumption. In practice, the high-frequency clock jitter distributions of each high-frequency ring oscillator overlap, requiring more high-frequency ring oscillators than ideal to ensure the output sequence reaches the target entropy.

[0052] Then, in order to solve the problem that multiple high-frequency oscillators need to be set up to ensure that the entropy value of the output sequence can reach the target entropy value, resulting in a large chip area and high power consumption, a new true random number generator is provided in the embodiment of the present application, as shown in Figure 3, including: a first oscillator, a second oscillator, a sampling module and an entropy value analysis module.

[0053] The second oscillator is an oscillator with adjustable phase and oscillation frequency.

[0054] The data input end of the sampling module is connected to the signal output end of the first oscillator, and the clock end of the sampling module is connected to the signal output end of the second oscillator, so that the sampling module samples and outputs the output signal of the first oscillator according to the output signal of the second oscillator.

[0055] Optionally, the sampling module can be implemented using, but not limited to, a D flip-flop.

[0056] Optionally, the first oscillator and the second oscillator may be, but are not limited to, a ring oscillator, a relaxation oscillator, a voltage-controlled oscillator, or the like. The first oscillator and the second oscillator may be of the same or different types. The oscillation frequency of the first oscillator may be higher than the oscillation frequency of the second oscillator to facilitate sampling by the sampling module to obtain random numbers. For example, an oscillator having an oscillation frequency much higher than the oscillation frequency of the second oscillator may be selected as the first oscillator.

[0057] In an embodiment of the present application, the input end of the entropy analysis module is respectively connected to the signal output end of the sampling module, the signal output end of the first oscillator, and the signal output end of the second oscillator, and the output end of the entropy analysis module is connected to the second oscillator.

[0058] The entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module.

[0059] Specifically, since the sampling module samples the output signal of the first oscillator based on the output signal of the second oscillator, that is, the sampling module samples the output signal of the first oscillator when the rising edge of the output signal of the second oscillator arrives, then, in order to ensure the randomness of the output value of the sampling module, it is necessary to sample on the rising edge or falling edge of the output signal of the first oscillator. At this time, the output signal of the first oscillator is in a metastable state, thereby ensuring the randomness of the output result of the sampling module. In other words, in order to ensure the randomness of the output result of the sampling module, the rising edge of the output signal of the second oscillator must be aligned with the rising edge or falling edge of the output signal of the first oscillator.

[0060] To this end, the entropy analysis module can adjust the oscillation frequency of the second oscillator when the rising edge of the second oscillator's output signal is misaligned with the rising edge or falling edge of the first oscillator's output signal. For example, the oscillation frequency of the second oscillator can be reduced or increased by a set value. The above process is then repeated until the rising edge of the second oscillator's output signal is aligned with the rising edge or falling edge of the first oscillator's output signal.

[0061] In a true random number generator, assuming that every M cycles, the output of the sampling module has a 0 / 1 transition (i.e., the output value jumps from 0 to 1), or a 1 / 0 transition (i.e., the output value jumps from 1 to 0), then the probability that the output of the sampling module is 0 or 1 is at least 1 / M, and the entropy of the output sequence is: H(p) = (1 / M)*log2M+(M-1) / M*log2M / (M-1) Formula (3)

[0062] Assuming M=10, the entropy value of the output sequence is H(P)=0.46, and assuming M=4, the entropy value of the output sequence is H(P)=0.80. It can be seen that the entropy value of the output sequence output by the true random number generator (i.e., the sequence composed of the output signal of the sampling module) is related to the number of cycles experienced when a signal transition occurs in the output signal of the sampling module. The greater the number of cycles experienced when a signal transition occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence. Based on this principle, in the embodiment of the present application, the M value can be determined according to the target entropy value required by the business, that is, the signal transition cycle threshold value is determined. When the number of cycles experienced when the signal transitions (i.e., the number of sampling cycles experienced by the sampling module when the output signal output by the sampling module transitions 0 / 1 or 1 / 0) is greater than the signal transition cycle threshold, the phase of the second oscillator is adjusted, for example, the phase of the second oscillator can be reduced or increased according to the set value.

[0063] By continuously repeating the above process, the sampling point of the sampling module (i.e., the rising edge of the output signal of the second oscillator) can be continuously moved closer to the center position of the jitter distribution of the first oscillator, so that the entropy value of the sequence composed of the output signals of the sampling module (i.e., the output sequence) can reach the target entropy value.

[0064] It can be seen that based on the true random number generator adopted in the embodiment of the present application, the phase and oscillation frequency of the second oscillator can be adjusted to a suitable position through the action of the entropy analysis module, so that even if the true random number generator does not set up multiple high-frequency oscillators (i.e., the first oscillator), the entropy value of the output sequence can reach the target entropy value, thereby reducing the chip area and reducing power consumption.

[0065] In an embodiment of the present application, as shown in FIG4 , the first oscillator and the second oscillator may be composed of a plurality of delay units connected end to end in a ring. These delay units may be implemented using, but are not limited to, one or more logic devices such as inverters and NAND gates.

[0066] The delay unit constituting the second oscillator may include at least one first delay unit, the input end of the first delay unit being connected to the first output end of the entropy analysis module, and the first delay unit generating different delays in response to different output signals of the first output end of the entropy analysis module.

[0067] Exemplarily, the first delay unit can be an inverter. In this case, the first delay unit has at least two inputs, namely, a delay unit located before the first delay unit in the second oscillator, and a first output terminal of the entropy analysis module. Then the change in the output value of the first output terminal of the entropy analysis module will change the magnitude of the current input to the first delay unit. It can be understood that the greater the current input to the inverter, the smaller the delay of the inverter, and the smaller the current input to the inverter, the greater the delay of the inverter. Therefore, the entropy analysis module can control the first delay unit to produce different delays by controlling the output value of the first output terminal. By adjusting the delay of the first delay unit, the delay time from the signal input to the signal output in the second oscillator can be adjusted, that is, the signal period of the second oscillator can be adjusted (since the signal period and the oscillation frequency are reciprocal to each other, the oscillation frequency of the second oscillator can also be adjusted).

[0068] Exemplarily, as shown in FIG5 , the first delay unit may also be a delay link with different delays connected through a multiplexer, and each delay link may have a different number of delay units connected in series, and the first output end of the entropy analysis module is connected to the control end of the multiplexer, so that the selected delay link can be controlled, thereby realizing the control of the delay of the first delay unit.

[0069] It can be understood that the above are only two optional implementation methods of the first delay unit exemplified in the embodiments of the present application. In addition, the first delay unit can also be implemented using any other circuit structure that can controllably adjust the delay time, and this is not limited in the embodiments of the present application.

[0070] In the embodiment of the present application, in order to adjust the phase of the second oscillator, as shown in FIG6 , the true random number generator may further include a second delay unit and an enable signal receiving terminal EN.

[0071] The input end of the first oscillator is connected to the enable signal receiving end EN, and the input end of the second oscillator is connected to the enable signal receiving end EN through the second delay unit.

[0072] The input end of the second delay unit is connected to the second output end of the entropy value analysis module, and the second delay unit generates different delays in response to different output signals of the second output end.

[0073] In this way, since the input end of the second oscillator is connected to the enable signal receiving end EN through the second delay unit, and the input end of the first oscillator is directly connected to the enable signal receiving end EN, once the delay time of the second delay unit changes, the time difference between the enable signal reaching the first oscillator and the second oscillator will change, thereby causing the phase of the output signal of the second oscillator relative to the output signal of the first oscillator to change, thereby achieving phase adjustment of the second oscillator.

[0074] Exemplarily, the second delay unit can be an inverter. In this case, the second delay unit has at least two inputs, namely an enable signal and the first output terminal of the entropy analysis module. Then, a change in the output value of the second output terminal of the entropy analysis module will change the magnitude of the current input to the second delay unit. It can be understood that the greater the current input to the inverter, the smaller the delay of the inverter, and the smaller the current input to the inverter, the greater the delay of the inverter. Therefore, the entropy analysis module can control the second delay unit to produce different delays by controlling the output value of the second output terminal. By adjusting the delay of the second delay unit, the phase of the output signal of the second oscillator relative to the output signal of the first oscillator can be adjusted.

[0075] Exemplarily, as shown in FIG7 , the second delay unit may also be a delay link with different delays connected through a multiplexer, and each delay link may have a different number of delay units connected in series, and the first output end of the entropy analysis module is connected to the control end of the multiplexer, so that the selected delay link can be controlled, thereby realizing the control of the delay of the second delay unit.

[0076] It can be understood that the above are only two optional implementation methods of the second delay unit exemplified in the embodiments of the present application. In addition, the second delay unit can also be implemented using any other circuit structure that can controllably adjust the delay time, and this is not limited in the embodiments of the present application.

[0077] In the embodiment of the present application, as shown in FIG6 , the first delay unit of the first oscillator and the second oscillator can be implemented by using a NAND gate, so that when forming a ring, an enable signal is input, so that the first oscillator and the second oscillator will work only after receiving the enable signal. h is the output signal of the first oscillator, f s_adj is the output signal of the second oscillator.

[0078] In an embodiment of the present application, as shown in FIG8 , the entropy analysis module may include a first counter, a second counter, and a first judgment circuit.

[0079] The first counter is connected to a preset reference clock source and a signal output terminal of the first oscillator respectively, so as to count the output signal of the first oscillator according to the reference clock source.

[0080] The second counter is connected to the reference clock source and the signal output terminal of the second oscillator respectively, so as to count the output signal of the second oscillator according to the reference clock source.

[0081] The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0082] In the embodiment of the present application, the reference clock source is used to provide a reference clock f ref The clock source may be a clock source outside the true random number generator in the chip.

[0083] It can be understood that the first counter can effectively record the number of rising edges or falling edges generated by the output signal of the first oscillator within a reference clock (this number reflects the frequency of the output signal of the first oscillator, that is, the oscillation frequency of the first oscillator). Similarly, the second counter can effectively record the number of rising edges or falling edges generated by the output signal of the second oscillator within a reference clock (this number reflects the frequency of the output signal of the second oscillator, that is, the oscillation frequency of the second oscillator).

[0084] It can be understood that when two consecutive rising edges of the output signal of the second oscillator are aligned with the rising edge of the output signal of the first oscillator, the oscillation frequency of the first oscillator can be divided by the oscillation frequency of the second oscillator, that is, the quotient of the oscillation frequency of the first oscillator and the oscillation frequency of the second oscillator should be an even multiple of 0.5; when the first rising edge of the output signal of the second oscillator is aligned with the rising edge of the output signal of the first oscillator and the second rising edge is aligned with the falling edge of the output signal of the first oscillator, the quotient of the oscillation frequency of the first oscillator and the oscillation frequency of the second oscillator should be an odd multiple of 0.5. Therefore, by determining the count value of the first counter and determining whether the quotient of the count value of the first counter and the count value of the second counter is an integer multiple of 0.5, it can be determined whether the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator, and then determine whether the signal currently output by the second oscillator is suitable for sampling by the sampling module. Therefore, if it is not suitable, the oscillation frequency of the second oscillator can be adjusted.

[0085] In the embodiment of the present application, still referring to Figure 8 , the entropy value analysis module may include a third counter and a second judgment circuit. In Figure 8 , Q represents the output signal of the sampling module.

[0086] The third counter is connected to the signal output terminal of the second oscillator and the signal output terminal of the sampling module respectively, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator;

[0087] The input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the second delay unit. The second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and the preset signal jump period threshold.

[0088] In this way, the third counter can be used to count the number of cycles experienced when a signal transition occurs in the output signal of the sampling module. As mentioned above, the entropy value of the output sequence output by the true random number generator is related to the number of cycles experienced when a signal transition occurs in the output signal of the sampling module. The greater the number of cycles experienced when a signal transition occurs in the output signal of the sampling module, the smaller the entropy value of the output sequence is theoretically. Therefore, by presetting a reasonable signal transition cycle threshold M, the phase of the second oscillator can be adjusted by continuously adjusting the delay of the second delay unit so that the sampling center of the output signal of the second oscillator moves toward the center of the jitter distribution of the output signal of the first oscillator, ultimately allowing the entropy value of the output sequence to reach the target entropy value.

[0089] Optionally, in an embodiment of the present application, some post-processing modules may be connected to the output end of the sampling module. The post-processing modules may be configured to obtain the sampling signals output by the sampling module and integrate them into a sequence for output.

[0090] Among them, the post-processing module can be implemented by a processor with signal processing capabilities, such as a CPU core, or a device with data integration capabilities such as a register, which is not limited in this embodiment of the present application.

[0091] Based on the same inventive concept, the embodiment of the present application further provides a control method based on the above-mentioned true random number generator, as shown in FIG9 , including:

[0092] S901: In response to a misalignment between a rising edge of an output signal of the second oscillator and a rising edge or a falling edge of an output signal of the first oscillator, the entropy analysis module adjusts the oscillation frequency of the second oscillator.

[0093] For example, as described above, the first counter of the entropy analysis module can count the output signal of the first oscillator based on the reference clock to obtain a count value C1. At the same time, the first counter can count the output signal of the second oscillator based on the reference clock to obtain a count value C2. Then, the first judgment circuit determines whether C1 / C2 is equal to an integer multiple of 0.5. If not, it indicates that the rising edge of the output signal of the second oscillator is not aligned with the rising edge or falling edge of the output signal of the first oscillator. A new first signal is output to the second oscillator according to a preset increase or decrease value, for example, to the first delay unit, thereby adjusting the oscillation frequency of the second oscillator. If C1 / C2 is equal to an integer multiple of 0.5, it indicates that the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator. At this time, the output first signal remains unchanged.

[0094] S902: In response to the alignment of the rising edge of the output signal of the second oscillator with the rising edge or the falling edge of the output signal of the first oscillator, the entropy analysis module determines whether the number of cycles during which a signal transition occurs in the output signal of the sampling module is less than or equal to a preset signal transition period threshold. If the number of cycles during which a signal transition occurs in the output signal of the sampling module is greater than the signal transition period threshold, the phase of the second oscillator is adjusted.

[0095] For example, as described above, the third counter of the entropy analysis module can count the number of cycles during which a signal transition occurs in the output signal of the sampling module according to the output signal of the second oscillator to obtain a count value C3.

[0096] That is, the third counter can add 1 to the count value each time the rising edge of the output signal of the second oscillator arrives, and when the output signal of the sampling module is inconsistent with the output signal of the sampling module received by the third counter the previous time (that is, when a 0 / 1 jump occurs, or a 1 / 0 jump occurs), it outputs the count value C3 and resets the count value.

[0097] The second judgment circuit compares C3 with a preset signal transition period threshold M. If C3 is greater than M, a new second signal can be output to the second delay unit according to a preset increase or decrease value, thereby adjusting the phase of the second oscillator. If C3 is less than or equal to M, it indicates that the sampling point of the sampling clock signal (i.e., the output signal of the second oscillator) has fallen within the jitter distribution of the high-frequency clock signal (i.e., the output signal of the first oscillator) and can meet the target entropy value range, so there is no need to adjust the phase of the second oscillator.

[0098] To facilitate understanding of the above solution, the following uses the structure obtained by combining FIG3 with FIG6 and FIG8 as an example to illustrate an embodiment of the present application:

[0099] First, the first oscillator and the second oscillator work and output signals f respectively. h and f s_adj .

[0100] Afterward, the first counter outputs count value C1, and the second counter outputs count value C2. The first determination circuit then determines whether C1 / C2 is an integer multiple of 0.5. If not, a new first signal is output to the first delay unit according to a preset increment or decrement value, thereby adjusting the oscillation frequency of the second oscillator. This process is repeated until C1 / C2 is an integer multiple of 0.5.

[0101] The third counter outputs a count value C3, and the second judgment circuit determines whether C3 is greater than a preset signal transition period threshold M. M is set based on the target entropy value. If C3 is greater than M, a new second signal is output to the second delay unit according to a preset increment or decrement value, thereby adjusting the phase of the second oscillator. The above process of determining whether to adjust the oscillation frequency of the second oscillator and adjusting the phase is then repeated. If C3 is less than or equal to M, the adjustment is terminated.

[0102] It will be understood that the above is only an example of a single true random number generator. In a chip or system, multiple true random number generators may be required. In this case, one implementation method is to deploy multiple true random number generators provided in the above embodiments. Another implementation method is to reuse the same entropy analysis module with multiple true random number generators that do not include an entropy analysis module, and implement the gating of the entropy analysis module to the true random number generator through multiple multiplexers.

[0103] For example, referring to FIG10, an embodiment of the present application provides an integrated circuit in which multiple true random number generators reuse the same entropy analysis module, including an entropy analysis module and multiple true random number generators. It is understood that FIG10 only shows the case of including two true random number generators. In actual applications, more true random number generators can be included. Among them, f h1 is the output signal of the first oscillator in the true random number generator 1, f h2 is the output signal of the first oscillator in the true random number generator 2, f s_adj1 is the output signal of the second oscillator in the true random number generator 1, f s_adj2 is the output signal output by the second oscillator in the true random number generator 2, Q1 is the output signal output by the sampling module in the true random number generator 1, and Q2 is the output signal output by the sampling module in the true random number generator 2.

[0104] Each true random number generator includes:

[0105] First oscillator;

[0106] a second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable;

[0107] a sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is used to sample and output the output signal of the first oscillator according to the output signal of the second oscillator;

[0108] The input end of the entropy value analysis module is connected to the signal output end of the sampling module of each true random number generator through the first multiplexer;

[0109] The input end of the entropy value analysis module is also connected to the signal output end of the first oscillator of each true random number generator through the second multiplexer;

[0110] The input end of the entropy value analysis module is also connected to the signal output end of the second oscillator of each true random number generator through the third multiplexer;

[0111] The output end of the entropy value analysis module is connected to the second oscillator of each true random number generator through a fourth multiplexer;

[0112] The entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator of any true random number generator according to the output signal of the first oscillator of the true random number generator, the output signal of the second oscillator and the output signal of the sampling module.

[0113] It can be understood that the control ends of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer can be connected to the control module of the integrated circuit (for example, it can be but not limited to a processor core, a coprocessor, etc.), so that the control module can control the gating of the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer, so that the entropy analysis module is only connected to one true random number generator at the same time (that is, the input end of the entropy analysis module is connected to the signal output end of the sampling module of the same true random number generator, the signal output end of the first oscillator, and the signal output end of the second oscillator, and the output end of the entropy analysis module is also connected to the second oscillator of the true random number generator).

[0114] Optionally, in an embodiment of the present application, for example, as shown in FIG11 , for any true random number generator, similar to the above, the second oscillator in the true random number generator may include a first delay unit.

[0115] The first output end of the entropy value analysis module is connected to the input end of the first delay unit of each true random number generator through a fourth multiplexer, and the first delay unit generates different delays in response to different output signals of the first output end.

[0116] The specific implementation of the first delay unit is as described above and will not be repeated here.

[0117] Optionally, in an embodiment of the present application, as shown in FIG12 , for any true random number generator, similar to the above, the true random number generator may further include a second delay unit and an enable signal receiving terminal EN.

[0118] The input terminal of the first oscillator is connected to the enable signal receiving terminal EN, and the input terminal of the second oscillator is connected to the enable signal receiving terminal EN through a second delay unit. The second output terminal of the entropy value analysis module is connected to the input terminal of the second delay unit of each true random number generator through a fifth multiplexer; the second delay unit generates different delays in response to different output signals of the second output terminal.

[0119] The specific implementation of the second delay unit is as described above and will not be repeated here.

[0120] In addition, similarly, as shown in FIG13 , for example, the entropy value analysis module may include a first counter, a second counter, and a first judgment circuit.

[0121] The first counter is connected to a preset reference clock source and is connected to the signal output end of the first oscillator of each true random number generator through a second multiplexer to count the output signal of the first oscillator according to the reference clock source.

[0122] The second counter is connected to the reference clock source and is respectively connected to the signal output end of the second oscillator of each true random number generator through a third multiplexer to count the output signal of the second oscillator according to the reference clock source.

[0123] The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator of each true random number generator respectively through a fourth multiplexer; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

[0124] Optionally, similar to the above, as shown in FIG13 , the entropy analysis module may further include a third counter and a second judgment circuit.

[0125] The third counter is connected to the signal output end of the second oscillator of each true random number generator through the third multiplexer, and is connected to the signal output end of the sampling module of each true random number generator through the first multiplexer, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator.

[0126] The input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the input end of the second delay unit of each true random number generator through a fifth multiplexer. The second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

[0127] It can be understood that the fifth multiplexer can also be controlled by the control module to achieve conduction between the entropy analysis module and the same true random number generator.

[0128] Correspondingly, based on the same inventive concept, an embodiment of the present application further provides a control method based on the above integrated circuit, as shown in FIG14 , including:

[0129] S1401: In response to a conduction control signal, the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer conduct the entropy analysis module to the true random number generator corresponding to the conduction control signal among the multiple true random number generators.

[0130] It can be understood that the conduction control signal can be issued by the control module in the integrated circuit, so that the first multiplexer connects the input end of the entropy analysis module to the signal output end of the sampling module of a true random number generator, and the second multiplexer connects the input end of the entropy analysis module to the signal output end of the first oscillator of the same true random number generator, and the third multiplexer connects the input end of the entropy analysis module to the signal output end of the second oscillator of the same true random number generator, and the fourth multiplexer connects the output end of the entropy analysis module to the control end of the second oscillator of the same true random number generator.

[0131] S1402: The entropy analysis module adjusts the oscillation frequency of the second oscillator of the true random number generator in response to the rising edge of the output signal of the second oscillator of the true random number generator being misaligned with the rising edge or falling edge of the output signal of the first oscillator of the true random number generator.

[0132] Exemplarily, as described above, the first counter of the entropy analysis module can count the output signal of the first oscillator based on the reference clock to obtain a count value C1. At the same time, the first counter can count the output signal of the second oscillator based on the reference clock to obtain a count value C2. Then, the first judgment circuit determines whether C1 / C2 is equal to an integer multiple of 0.5. If not, it indicates that the rising edge of the output signal of the second oscillator is not aligned with the rising edge or falling edge of the output signal of the first oscillator. A new first signal is output to the second oscillator according to a preset increase or decrease value, for example, to the first delay unit, thereby adjusting the oscillation frequency of the second oscillator. If C1 / C2 is equal to an integer multiple of 0.5, it indicates that the rising edge of the output signal of the second oscillator is aligned with the rising edge or falling edge of the output signal of the first oscillator. At this time, the output first signal remains unchanged.

[0133] S1403: In response to the alignment of the rising edge of the output signal of the second oscillator of the true random number generator and the rising edge or falling edge of the output signal of the first oscillator of the true random number generator, the entropy analysis module determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is less than or equal to a preset signal jump period threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is greater than the signal jump period threshold, the phase of the second oscillator of the true random number generator is adjusted.

[0134] For example, as described above, the third counter of the entropy analysis module can count the number of cycles during which a signal transition occurs in the output signal of the sampling module according to the output signal of the second oscillator to obtain a count value C3.

[0135] That is, the third counter can add 1 to the count value when the rising edge of the output signal of the second oscillator arrives, and when the output signal of the sampling module is inconsistent with the output signal of the sampling module received by the third counter the previous time (that is, when a 0 / 1 jump occurs, or a 1 / 0 jump occurs), it outputs the count value C3 and resets the count value.

[0136] The second judgment circuit compares C3 with a preset signal transition period threshold M. If C3 is greater than M, a new second signal can be output to the second delay unit according to a preset increase or decrease value, thereby adjusting the phase of the second oscillator. If C3 is less than or equal to M, it indicates that the sampling point of the sampling clock signal (i.e., the output signal of the second oscillator) has fallen within the jitter distribution of the high-frequency clock signal (i.e., the output signal of the first oscillator) and can meet the target entropy value range, so there is no need to adjust the phase of the second oscillator.

[0137] It can be understood that after the entropy analysis module has adjusted the phase and oscillation frequency of the second oscillator in a true random number generator, the control module can output a new conduction control signal to connect the entropy analysis module to the new true random number generator, thereby adjusting the phase and oscillation frequency of the new true random number generator.

[0138] To facilitate understanding of the above solution, the following uses the structure obtained by combining FIG10 with FIG11 to FIG13 as an example to illustrate an embodiment of the present application:

[0139] First, the control module sends a conduction control signal to the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, and the fifth multiplexer, respectively, so that the first multiplexer connects the input end of the entropy analysis module with the signal output end of the sampling module of the true random number generator 1, the second multiplexer connects the input end of the entropy analysis module with the signal output end of the first oscillator of the true random number generator 1, the third multiplexer connects the input end of the entropy analysis module with the signal output end of the second oscillator of the true random number generator 1, the fourth multiplexer connects the output end of the entropy analysis module with the first delay unit of the true random number generator 1, and the fifth multiplexer connects the output end of the entropy analysis module with the second delay unit of the true random number generator 1.

[0140] Afterward, the first counter outputs count value C1, and the second counter outputs count value C2. The first determination circuit then determines whether C1 / C2 is an integer multiple of 0.5. If not, a new first signal is output to the first delay unit of true random number generator 1 according to a preset increment or decrement value, thereby adjusting the oscillation frequency of the second oscillator of true random number generator 1. This process is repeated until C1 / C2 is an integer multiple of 0.5.

[0141] The third counter outputs a count value C3, and the second judgment circuit determines whether C3 is greater than a preset signal transition period threshold M. M is set according to the target entropy value. If C3 is greater than M, a new second signal can be output to the second delay unit of the true random number generator 1 according to a preset increment or decrement value, thereby adjusting the phase of the second oscillator of the true random number generator 1. The above process of determining whether to adjust the oscillation frequency of the second oscillator of the true random number generator 1 and adjusting the phase is then repeated. If C3 is less than or equal to M, the adjustment is terminated.

[0142] Afterwards, the control module sends conduction control signals to the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, and the fifth multiplexer respectively, so that the first multiplexer connects the input end of the entropy analysis module with the signal output end of the sampling module of the true random number generator 2, the second multiplexer connects the input end of the entropy analysis module with the signal output end of the first oscillator of the true random number generator 2, the third multiplexer connects the input end of the entropy analysis module with the signal output end of the second oscillator of the true random number generator 2, the fourth multiplexer connects the output end of the entropy analysis module with the first delay unit of the true random number generator 2, and the fifth multiplexer connects the output end of the entropy analysis module with the second delay unit of the true random number generator 2.

[0143] Afterward, the first counter outputs count value C1, and the second counter outputs count value C2. The first determination circuit then determines whether C1 / C2 is an integer multiple of 0.5. If not, a new first signal is output to the first delay unit of true random number generator 2 according to a preset increment or decrement value, thereby adjusting the oscillation frequency of the second oscillator of true random number generator 2. This process is repeated until C1 / C2 is an integer multiple of 0.5.

[0144] The third counter outputs a count value C3, and the second judgment circuit determines whether C3 is greater than a preset signal transition period threshold M. M is set according to the target entropy value. If C3 is greater than M, a new second signal can be output to the second delay unit of the true random number generator 2 according to a preset increment or decrement value, thereby adjusting the phase of the second oscillator of the true random number generator 2. The above process of determining whether to adjust the oscillation frequency of the second oscillator of the true random number generator 2 and adjusting the phase is then repeated. If C3 is less than or equal to M, the adjustment is terminated.

[0145] Based on the same inventive concept, an embodiment of the present application further provides a chip, including the aforementioned true random number generator, or including the aforementioned integrated circuit.

[0146] The chip provided in the embodiments of the present application may be a random number generation chip that only encapsulates a random number sequence generator, or it may be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, an NPU (Neural-network Processing Unit) chip, etc., but is not limited to this.

[0147] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned chip.

[0148] The electronic device may be a small electronic device such as a CPU board, graphics card, dedicated integrated circuit, controller, etc. that can be integrated into a large electronic device. In addition, the electronic device may also be an electronic device such as a mobile phone, computer, server, etc. that can directly provide services.

[0149] It is understood that when the electronic device is an electronic device such as a mobile phone, a computer, or a server that can directly provide services, in addition to the aforementioned chip, the electronic device may also have devices such as memory and a communication bus to cooperate with the chip to complete complex tasks or provide complex services. Among them, the memory can be RAM (Random Access Memory), ROM (Read-Only Memory), flash memory, hard disk, etc., but it is not limited to this. The communication bus can be a USB (Universal Serial Bus), a CAN (Controller Area Network) bus, etc., but it is not limited to this.

[0150] In the embodiments provided herein, it should be understood that the various modules and methods of the disclosed products can be implemented in other ways. The embodiments described above are merely illustrative. Furthermore, the connections shown or discussed may be direct or indirect electrical connections via interfaces or units.

[0151] Furthermore, the features in the various embodiments of the present application can be combined without conflict to obtain new embodiments.

[0152] In this document, relational terms such as first, second, third, fourth, fifth, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0153] As used herein, a plurality refers to two or more than two.

[0154] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A true random number generator, comprising: First oscillator; A second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable; A sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator; An entropy analysis module, wherein the input end of the entropy analysis module is respectively connected to the signal output end of the sampling module, the signal output end of the first oscillator, and the signal output end of the second oscillator, the output end of the entropy analysis module is connected to the second oscillator, and the entropy analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator according to the output signal of the first oscillator, the output signal of the second oscillator and the output signal of the sampling module.

2. The true random number generator of claim 1, wherein: The second oscillator comprises: A first delay unit, wherein an input end of the first delay unit is connected to a first output end of the entropy value analysis module, and the first delay unit generates different delays in response to different output signals of the first output end.

3. A true random number generator as claimed in claim 1 or 2, wherein: The true random number generator also includes a second delay unit and an enable signal receiving terminal; The input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; The input end of the second delay unit is connected to the second output end of the entropy value analysis module, and the second delay unit generates different delays in response to different output signals of the second output end. Late.

4. A true random number generator as claimed in any one of claims 1 to 3, wherein: The entropy value analysis module includes: a first counter, a second counter and a first judgment circuit; The first counter is connected to a preset reference clock source and a signal output terminal of the first oscillator respectively, so as to count the output signal of the first oscillator according to the reference clock source; The second counter is connected to the reference clock source and the signal output terminal of the second oscillator respectively, so as to count the output signal of the second oscillator according to the reference clock source; The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

5. A true random number generator as claimed in claim 3 or 4, wherein: The entropy value analysis module includes: a third counter and a second judgment circuit; The third counter is connected to the signal output terminal of the second oscillator and the signal output terminal of the sampling module respectively, so as to count the number of cycles experienced when a signal jump occurs in the output signal of the sampling module according to the output signal of the second oscillator; The input end of the second judgment circuit is connected to the output end of the third counter, the output end of the second judgment circuit is connected to the second delay unit, and the second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

6. An integrated circuit comprising: Entropy analysis module and multiple true random number generators; Each of the true random number generators comprises: First oscillator; A second oscillator, wherein the phase and oscillation frequency of the second oscillator are adjustable; A sampling module, wherein a data input terminal of the sampling module is connected to a signal output terminal of the first oscillator, a clock terminal of the sampling module is connected to a signal output terminal of the second oscillator, and the sampling module is used to sample and output an output signal of the first oscillator according to an output signal of the second oscillator; The input end of the entropy value analysis module is respectively connected to the signal output end of the sampling module of each true random number generator through a first multiplexer; The input end of the entropy value analysis module is also connected to the signal output end of the first oscillator of each of the true random number generators through a second multiplexer; The input end of the entropy value analysis module is also connected to the signal output end of the second oscillator of each of the true random number generators through a third multiplexer; The output end of the entropy value analysis module is respectively connected to the second oscillator of each of the true random number generators through a fourth multiplexer; The entropy value analysis module is used to adjust the phase and / or oscillation frequency of the second oscillator of the true random number generator according to the output signal of the first oscillator of any one of the true random number generators, the output signal of the second oscillator and the output signal of the sampling module.

7. The integrated circuit of claim 6, wherein: For any one of the true random number generators, the second oscillator includes: a first delay unit; The first output end of the entropy value analysis module is respectively connected to the input end of the first delay unit of each of the true random number generators through the fourth multiplexer; The first delay unit generates different delays in response to different output signals of the first output terminal.

8. An integrated circuit as claimed in claim 6 or 7, wherein: For any one of the true random number generators, the true random number generator further includes a second delay unit and an enable signal receiving end; The input end of the first oscillator is connected to the enable signal receiving end, and the input end of the second oscillator is connected to the enable signal receiving end through the second delay unit; The second output end of the entropy value analysis module is connected to the input end of each of the second delay units of the true random number generator through a fifth multiplexer; The second delay unit generates different delays in response to different output signals of the second output terminal.

9. An integrated circuit as claimed in any one of claims 6 to 8, wherein: The entropy value analysis module includes: a first counter, a second counter and a first judgment circuit; The first counter is connected to a preset reference clock source, and is respectively connected to the signal output end of the first oscillator of each of the true random number generators through a second multiplexer, so as to count the output signal of the first oscillator according to the reference clock source; The second counter is connected to the reference clock source and is respectively connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer to count the output signal of the second oscillator according to the reference clock source; The input end of the first judgment circuit is connected to the output end of the first counter and the second counter respectively, and the output end of the first judgment circuit is connected to the second oscillator of each true random number generator respectively through the fourth multiplexer; the first judgment circuit is used to adjust the oscillation frequency of the second oscillator according to the count values ​​of the first counter and the second counter.

10. An integrated circuit as claimed in claim 8 or 9, wherein: The entropy value analysis module includes: a third counter and a second judgment circuit; The third counter is respectively connected to the signal output end of the second oscillator of each of the true random number generators through the third multiplexer, and is respectively connected to the signal output end of the sampling module of each of the true random number generators through the first multiplexer, so as to The output signal of the second oscillator counts the number of cycles experienced when a signal jump occurs in the output signal of the sampling module; The input end of the second judgment circuit is connected to the output end of the third counter, and the output end of the second judgment circuit is connected to the input end of each of the second delay units of the true random number generator through the fifth multiplexer. The second judgment circuit is used to adjust the delay of the second delay unit according to the count value of the third counter and a preset signal jump period threshold.

11. A control method, applied to the true random number generator according to any one of claims 1 to 5, the method comprising: The entropy value analysis module adjusts the oscillation frequency of the second oscillator in response to the rising edge of the output signal of the second oscillator and the rising edge or the falling edge of the output signal of the first oscillator not being aligned; The entropy analysis module responds to the alignment of the rising edge of the output signal of the second oscillator with the rising edge or falling edge of the output signal of the first oscillator, and determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is less than or equal to a preset signal jump cycle threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module is greater than the signal jump cycle threshold, the phase of the second oscillator is adjusted.

12. A control method, applied to the integrated circuit according to any one of claims 6 to 10, the method comprising: In response to a conduction control signal, the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer conduct the entropy value analysis module with a true random number generator among the plurality of true random number generators corresponding to the conduction control signal; The entropy value analysis module responds to the rising edge of the output signal of the second oscillator of the true random number generator and the rising edge of the output signal of the first oscillator of the true random number generator. If the rising edge or the falling edge is not aligned, adjusting the oscillation frequency of the second oscillator of the true random number generator; The entropy analysis module responds to the alignment of the rising edge of the output signal of the second oscillator of the true random number generator with the rising edge or falling edge of the output signal of the first oscillator of the true random number generator, and determines whether the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is less than or equal to a preset signal jump cycle threshold; if the number of cycles experienced when a signal jump occurs in the output signal of the sampling module of the true random number generator is greater than the signal jump cycle threshold, the phase of the second oscillator of the true random number generator is adjusted.

13. A chip, comprising the true random number generator as claimed in any one of claims 1 to 5, or comprising the integrated circuit as claimed in any one of claims 6 to 10.

14. An electronic device comprising the chip according to claim 13.

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