Display panel and display terminal

Abstract

A display panel and a display terminal. The display panel comprises an active portion (20), a gate insulating layer (60), a gate electrode (50), and a source / drain electrode layer, wherein the active portion (20) comprises a first contact portion (21), a channel portion (22) and a second contact portion (23) which are stacked, a portion of the first contact portion (21) that is staggered with the second contact portion (23) being a first sub-portion (210), and a portion of the second contact portion (23) that is staggered with the first contact portion (21) being a second sub-portion (230); the active portion (20) is provided with a first side wall (22A); the gate electrode (50) at least covers the channel portion (22) on the first side wall (22A); and a source electrode (71) is electrically connected to the first sub-portion (210) by means of a via hole, and a drain electrode (72) is electrically connected to the second sub-portion (230) by means of a via hole.

Description

Display panel and display terminal

[0001] This application claims priority to Chinese patent application No. 202311693235.9 filed on December 8, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0003] SOG technology (system on glass) integrates gate driver circuits, source driver circuits, timing controllers, and other chip circuits onto a glass substrate. This improves the integration density of display panels, reduces chip reliance, and lowers costs. Implementing SOG technology requires increasing the maximum operating frequency and current density of thin-film transistors. These requirements require thin-film transistors with shorter channel lengths, higher mobility, and smaller size.

[0004] Based on the above reasons, the prior art provides a vertical TFT structure. To achieve better device performance, the channel layer of the vertical TFT structure is relatively thin. When drilling holes in the active layer to connect the source and drain electrodes, the stacked connection layer is easily punched through, causing device failure.

[0005] Therefore, there is an urgent need to provide a new array substrate structure to solve the above problems. Summary of the Invention

[0006] The present application provides a display panel and a display terminal to solve the technical problem of functional failure of thin film transistor devices of the display panel and improve the process yield.

[0007] To solve the above technical problems, the technical solutions provided by this application are as follows:

[0008] The present application provides a display panel, comprising:

[0009] substrate;

[0010] an active portion disposed on the substrate, the active portion comprising a stacked first contact portion, a channel portion, and a second contact portion, wherein the channel portion is partially disposed on a side of the first contact portion facing away from the substrate, and the second contact portion is disposed on a side of the channel portion facing away from the substrate; wherein, on the substrate, an orthographic projection of the second contact portion overlaps with an orthographic projection of the channel portion, and an orthographic projection of the second contact portion partially overlaps with an orthographic projection of the first contact portion; in a direction perpendicular to the substrate, a portion where the first contact portion intersects with the first contact portion is a first sub-portion, and a portion where the second contact portion intersects with the first contact portion is a second sub-portion;

[0011] a gate insulating layer, disposed on a side of the active portion facing away from the substrate;

[0012] a gate disposed on a side of the gate insulating layer facing away from the substrate, the active portion having a first sidewall, the first sidewall being an inclined side surface of an overlapping portion of the first contact portion, the channel portion, and the second contact portion; the gate covering at least the channel portion on the first sidewall on the gate insulating layer;

[0013] A source-drain layer is provided on a side of the active portion facing away from the substrate, and the source-drain layer includes a source and a drain; the source is electrically connected to the first sub-portion, and the drain is electrically connected to the second sub-portion.

[0014] The present application provides a display terminal, which includes a display panel. The display panel includes:

[0015] substrate;

[0016] an active portion disposed on the substrate, the active portion comprising a stacked first contact portion, a channel portion, and a second contact portion, wherein the channel portion is partially disposed on a side of the first contact portion facing away from the substrate, and the second contact portion is disposed on a side of the channel portion facing away from the substrate; wherein, on the substrate, an orthographic projection of the second contact portion overlaps with an orthographic projection of the channel portion, and an orthographic projection of the second contact portion partially overlaps with an orthographic projection of the first contact portion; in a direction perpendicular to the substrate, a portion where the first contact portion intersects with the first contact portion is a first sub-portion, and a portion where the second contact portion intersects with the first contact portion is a second sub-portion;

[0017] a gate insulating layer, disposed on a side of the active portion facing away from the substrate;

[0018] a gate disposed on a side of the gate insulating layer facing away from the substrate, the active portion having a first sidewall, the first sidewall being an inclined side surface of an overlapping portion of the first contact portion, the channel portion, and the second contact portion; the gate covering at least the channel portion on the first sidewall on the gate insulating layer;

[0019] A source-drain layer is provided on a side of the active portion facing away from the substrate, and the source-drain layer includes a source and a drain; the source is electrically connected to the first sub-portion, and the drain is electrically connected to the second sub-portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1a is a schematic diagram of a partial top view of a display panel in the related art;

[0021] FIG1b is a schematic cross-sectional structure diagram of the AA section in FIG1a;

[0022] FIG1c is a schematic cross-sectional structure diagram of the BB section in FIG1a;

[0023] FIG2 a is a schematic diagram of a partial top view of the structure of a first display panel provided in an embodiment of the present application;

[0024] FIG2 b is a schematic cross-sectional structural diagram of the CC section of the first display panel in FIG2 a ;

[0025] FIG2c is a schematic cross-sectional structural diagram of the DD section of the first display panel in FIG2a;

[0026] FIG3 is a schematic diagram of a partial top view of the structure of a second display panel provided in an embodiment of the present application;

[0027] FIG4 a is a schematic cross-sectional structural diagram of the CC section of the third display panel in FIG2 a ;

[0028] FIG4 b is a schematic cross-sectional structural diagram of the DD section of the third display panel in FIG2 a ;

[0029] FIG5 a is a schematic cross-sectional structural diagram of the CC section of the fourth display panel in FIG2 a ;

[0030] FIG5 b is a schematic cross-sectional structural diagram of the DD section of the fourth display panel in FIG2 a ;

[0031] 6a to 6c are flowcharts of a manufacturing process of a first display panel provided by an embodiment of the present application. Modes for Carrying Out the Invention

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0033] As shown in Figures 1a to 1c, in the related art, the active layer 100 of a thin-film transistor includes a stacked first conductor layer 101, a channel layer 102, and a second conductor layer 103. Since the channel layer 102 is located between the first and second conductor layers 101, 103 in a direction perpendicular to the substrate 11, the thickness of the channel layer 102 is the channel length. Because the dimensional control precision of the film thickness in the display panel manufacturing process is greater than the control precision of the film layer's dimensions in a plane parallel to the substrate 11, the thickness of the channel layer 102 can be reduced. This arrangement enables the realization of a short-channel thin-film transistor. The source and drain layers 105 are electrically connected to the first and second conductor layers 101, 103, respectively, through perforations. However, as shown at E in Figure 1b, since the channel layer 102 is thinner between the first and second conductor layers 101, if the vias are too deep, it is easy for the first and second conductor layers 101, 103, to penetrate through, causing device failure.

[0034] Based on the above technical problems, this application proposes the following solutions.

[0035] The present application provides a display panel, as shown in Figures 2a to 2c, the display panel includes a substrate 11, an active portion 20, a gate insulating layer 60, a gate 50, and a source and drain layer. The active portion 20 is arranged on the substrate 11, and the active portion 20 includes a stacked first contact portion 21, a channel portion 22, and a second contact portion 23. The channel portion 22 is arranged on the side of the first contact portion 21 away from the substrate 11, and the second contact portion 23 is arranged on the side of the channel portion 22 away from the substrate 11. On the substrate 11, the orthographic projection of the second contact portion 23 overlaps with the orthographic projection of the channel portion 22, and the orthographic projection of the second contact portion 23 partially overlaps with the orthographic projection of the first contact portion 21; in the direction perpendicular to the substrate 11, the part where the first contact portion 21 and the first contact portion 21 intersect is a first sub-portion. 210, the part where the second contact portion 23 and the first contact portion 21 intersect is the second sub-portion 230; the gate insulating layer 60 is arranged on the side of the active portion 20 away from the substrate 11; the gate 50 is arranged on the side of the gate insulating layer 60 away from the substrate 11, and the active portion 20 has a first side wall 22A, and the first side wall 22A is the inclined side surface of the overlapping part of the first contact portion 21, the channel portion 22 and the second contact portion 23; the gate 50 covers at least the channel portion 22 on the first side wall 22A on the gate insulating layer 60; the source and drain layer is arranged on the side of the active portion 20 away from the substrate 11, and the source and drain layer includes a source 71 and a drain 72; the source 71 is electrically connected to the first sub-portion 210 through a via, and the drain 72 is electrically connected to the second sub-portion 230 through a via.

[0036] In this embodiment, the substrate 11 may be a flexible substrate or a rigid substrate. The flexible substrate may be made of a material selected from the group consisting of colorless polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET). The rigid substrate may be made of a material selected from the group consisting of glass and the like.

[0037] In this embodiment, the display panel may be an OLED panel, a Mini-LED panel, a Micro-LED panel, or the like. The display panel includes thin film transistors, which may be used for, but are not limited to, gate drive circuits, source 71 drive circuits, timing controllers, pixels, and the like. By integrating various circuit functions originally implemented by chips onto the display panel, the display panel's dependence on chips can be reduced, the cost of the display panel can be reduced, and SOG technology can be implemented.

[0038] In this embodiment, the active portion 20 includes a first contact portion 21, a channel portion 22, and a second contact portion 23 stacked in sequence. Through the above arrangement, the thickness direction of the channel portion 22 can be used as the channel length. The thickness direction of the channel portion 22 refers to the direction perpendicular to the substrate 11. The supporting surface of the substrate 11 is the plane of the substrate 11 on the side close to the active portion 20. The supporting surface of the substrate 11 is parallel to the display surface of the display panel. Since the process accuracy of the thickness of the channel portion 22 is greater than the process accuracy of the dimension of the channel portion 22 parallel to the display surface when the channel portion 22 is manufactured in the existing process, a thin film transistor with a smaller channel length can be manufactured.

[0039] The channel portion 22 may be made of polycrystalline silicon. The first contact portion 21 and the second contact portion 23 may be formed by ion doping the polycrystalline silicon. Doping improves the conductivity of the first contact portion 21 and the second contact portion 23, enabling ohmic contact with the source 71 and drain 72 of the thin-film transistor. The doped ions may be, but are not limited to, phosphorus ions, boron ions, and the like. The doping method may be light or heavy, and this application is not limited thereto.

[0040] It should be noted that the polycrystalline silicon in the channel portion 22 can be formed from amorphous silicon through an excimer laser annealing (ELA) process. After the excimer laser annealing process, the amorphous silicon melts and recrystallizes, achieving a grain-free channel 22 perpendicular to the substrate 11. This results in a single crystal grain along the channel length, with a grain size of approximately 0.3 microns. This creates a short channel and improves the electrical properties of the thin-film transistor.

[0041] In this embodiment, the gate insulating layer 60 can be made of a stack of one or more layers of materials such as silicon nitride, silicon oxide, or silicon oxynitride, but is not limited thereto. The gate insulating layer 60 can separate the gate 50 and the active portion 20 to achieve insulation between the gate 50 and the active portion 20.

[0042] In this embodiment, the source electrode 71 and the drain electrode 72 can be made of a conductive material. The source electrode 71 and the drain electrode 72 can be formed of any one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

[0043] In this embodiment, the orthographic projection of the first contact portion 21 on the substrate 11 partially overlaps with the orthographic projection of the second contact portion 23 on the substrate 11. The orthographic projection of the first sub-portion 210 of the first contact portion 21 on the substrate 11 and the orthographic projection of the second sub-portion 230 of the second contact portion 23 on the substrate 11 do not overlap. By setting the orthographic projections of the first sub-portion 210 and the second sub-portion 230 on the substrate 11 to not overlap, the first sub-portion 210 can be electrically connected to the source 71 through a via, and the second sub-portion 230 can be electrically connected to the drain 72 through a via. In this way, when making a via, even if the via is too deep, the via will not penetrate the second contact portion 23. This can prevent the first contact portion 21 and the second contact portion 23 from being conductive when the via is pierced, causing functional failure.

[0044] In this embodiment, the first contact portion 21, the channel portion 22, and the second contact portion 23 overlap in a portion of the active portion 20, and the gate 50 is correspondingly disposed on the first sidewall 22A at the overlapping portion. The first sidewall 22A is the inclined side surface of the overlapping portion of the first contact portion 21, the channel portion 22, and the second contact portion 23; that is, the sidewalls of the first contact portion 21, the channel portion 22, and the second contact portion 23 at the first sidewall 22A are aligned. The gate 50 is disposed on the side of the gate insulating layer 60 facing away from the substrate 11, and the gate 50 at least covers the channel portion 22 on the first sidewall 22A.

[0045] In this embodiment, the gate 50 is a conductive material, and the gate 50 can be formed of any one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

[0046] In the display panel of the present application, the orthographic projection of the gate 50 on the substrate 11 covers part of the orthographic projection of the first side wall 22A on the substrate 11, one end of the gate 50 extends along the first side wall 22A to cover the side surface of the active portion 20 facing away from the substrate 11, and the other end of the gate 50 extends along the first side wall 22A to cover the substrate 11.

[0047] In this embodiment, the gate 50 is disposed corresponding to the first sidewall 22A, and the orthographic projection of the gate 50 on the substrate 11 at least partially overlaps with the first sidewall 22A. In other words, the gate 50 at least covers a portion of the first sidewall 22A.

[0048] In this embodiment, as shown in Figures 2a to 2c, the gate 50 covers the first sidewall 22A and then extends along both ends of the first sidewall 22A in the first direction D1, with one end extending to the upper surface of the active portion 20 and the other end extending to the surface of the substrate 11. This arrangement makes it easier for the gate 50 to cover the first sidewall 22A during the manufacturing process, thereby enhancing the gate 50's ability to control the channel portion 22.

[0049] In the display panel of the present application, as shown in Figures 2a to 2c, the first contact portion 21 extends along the first direction D1, and the second contact portion 23 extends along the second direction D2, and the first direction D1 and the second direction D2 have a preset angle; in the second direction D2, the length dimension of the gate 50 is less than or equal to the length dimension of the channel portion 22, and the channel portion 22 includes a second side wall 22B opposite to the first side wall 22A. The second direction D2 is the direction from the first side wall 22A to the second side wall 22B, and the orthographic projection of the channel portion 22 on the substrate 11 overlaps with the orthographic projection of the second contact portion 23 on the substrate 11.

[0050] In this embodiment, the preset angle may be an acute angle, a right angle, or an obtuse angle, and may be adaptively set according to the shape of the space.

[0051] In this embodiment, the length of the gate 50 in the second direction D2 is less than or equal to the length of the channel portion 22 in the second direction D2. This arrangement reduces the length of the gate 50 in the second direction D2, thereby reducing the size of the thin film transistor. In this case, the length W of the gate 50 in the second direction D2 corresponds to the channel width of the thin film transistor.

[0052] In this embodiment, the orthographic projection of the second contact portion 23 on the channel portion 22 overlaps with the channel portion 22 , that is, the second contact portion 23 and the channel portion 22 have the same projection shape and area.

[0053] In this embodiment, the orthographic projection of the gate 50 on the substrate 11 does not overlap with the first sub-portion 210 or the second sub-portion, thereby avoiding the formation of parasitic capacitance.

[0054] In the display panel of the present application, as shown in FIG3 , FIG3 is a partial top view of the structure of the second display panel provided in an embodiment of the present application. The only difference between the second display panel and the first display panel is the size of the gate 50 and the active portion 20. The cross-sectional view of the second display panel is similar to the cross-sectional view of the first display panel. The second contact portion 23 includes a long portion along the second direction D2 and a short portion along the first direction D1. The first sidewall 22A is located on the inclined side of the short portion and extends along the second direction D2. In the second direction D2, the length dimension of the gate 50 is greater than the length dimension of the channel portion 22. The channel portion 22 includes a second sidewall 22B opposite to the first sidewall 22A. The second direction D2 is the direction from the first sidewall 22A to the second sidewall 22B. The orthographic projection of the channel portion 22 on the substrate 11 overlaps with the orthographic projection of the second contact portion 23 on the substrate 11.

[0055] In this embodiment, to prevent the gate 50 from overlapping with the second contact portion 23 and forming a parasitic capacitance, the second contact portion 23 is configured to be L-shaped. With this configuration, when the length of the gate 50 in the second direction D2 is greater than the length of the channel portion 22, the corners of the L-shape can form a space to avoid the gate 50.

[0056] In this embodiment, the length of the gate 50 in the second direction D2 is greater than the length of the channel portion 22 in the second direction D2. The orthographic projection of the second contact portion 23 on the channel portion 22 overlaps with the channel portion 22, that is, the projection shape and area of ​​the second contact portion 23 and the channel portion 22 are the same. Through the above arrangement, the width of the channel can be increased. The width of the channel is W1+2a, where W1 is the length of the second contact portion 23 in the second direction D2, and a is the length of the portion of the gate 50 that overlaps with the second contact portion 23 in the first direction D1. The first direction D1 and the second direction D2 are arranged at an angle, for example, the angle can be a right angle or an acute angle.

[0057] This embodiment increases the width of the channel to increase the channel's width-to-length ratio, thereby increasing the on-state current of the thin-film transistor and improving the electrical properties of the thin-film transistor. The channel's width-to-length ratio refers to the ratio of the channel's width to its length. In this application, the channel's length is the thickness of the channel portion 22 in a direction perpendicular to the substrate 11.

[0058] In the display panel of the present application, as shown in Figures 2a and 2b, the display panel includes a first barrier layer 30, which is arranged between the first contact portion 21 and the channel portion 22; the first barrier layer 30 covers the first sub-portion 210, and the orthographic projection of the first side wall 22A on the substrate 11 is spaced apart from the orthographic projection of the first barrier layer 30 on the substrate 11.

[0059] In this embodiment, the orthographic projection of the first sub-portion 210 on the first barrier layer 30 is located inside the first barrier layer 30 , and the orthographic projection of the first sidewall 22A on the first barrier layer 30 is located outside the first barrier layer 30 .

[0060] In this embodiment, the first barrier layer 30 is disposed between the first contact portion 21 and the channel portion 22. The first end 31 of the first barrier layer 30 is located near the gate 50. The other end of the first barrier layer 30 extends away from the gate 50 and separates the channel portion 22 from the first contact portion 21. The first barrier layer 30 serves to shorten the path length of leakage current between the first contact portion 21 and the channel portion 22, thereby improving the electrical properties of the thin film transistor. It also serves as a protective layer, preventing over-etching of the upper surface of the first contact portion 21 when the channel portion 22 and the second contact portion 23 are etched together, thereby improving the yield of the patterning process.

[0061] In some embodiments, to minimize the length of the leakage current path between the first contact portion 21 and the channel portion 22, the distance between the first end 31 of the first barrier layer 30 and the first sidewall 22A can be set to a first distance d. The first distance d is 0.01 microns to 0.1 microns, thereby maintaining only very short contact between the first contact portion 21, the channel portion 22, and the second contact portion 23, further shortening the leakage current path length.

[0062] In this embodiment, the first barrier layer 30 is made of an insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., but is not limited thereto.

[0063] In the display panel of the present application, the via electrically connecting the source 71 with the first sub-section 210 is the first via 710, and the via electrically connecting the drain 72 with the second sub-section 230 is the second via 720. The first via 710 is configured to pass through the gate insulating layer 60 and the first barrier layer 30, and the second via 720 is configured to pass through the gate insulating layer 60.

[0064] It should be understood that when other insulating layers are provided between the gate insulating layer 60 and the source and drain electrode layers, the first via holes 710 and the second via holes 720 also pass through the other insulating layers.

[0065] In the display panel of the present application, as shown in Figures 2a to 2c, the display panel includes a light-shielding layer 90, which is arranged on the side of the active portion 20 close to the substrate 11, and the orthographic projection of the first side wall 22A on the light-shielding layer 90 is located within the light-shielding layer 90.

[0066] In this embodiment, the light shielding layer 90 can be made of a material with light shielding capabilities. For example, the light shielding layer 90 can be an opaque metal. Since the first sidewall 22A of the channel portion 22 serves as the channel length in this application, the light shielding layer 90 needs to be able to shield the first sidewall 22A from light. That is, the orthographic projection of the first sidewall 22A on the light shielding layer 90 is located within the light shielding layer 90. Through this arrangement, the light shielding layer 90 can block light incident on the channel portion 22 from the substrate 11 side, thereby preventing the channel portion 22 from being exposed to light and causing electrical degradation.

[0067] Furthermore, in addition to shielding the first side wall 22A, the shading layer 90 can also simultaneously block the surface of the gate 50 close to the substrate 11, preventing light from being incident on the first side wall 22A from the side after reflection or refraction, thereby improving the shading effect of the shading layer 90.

[0068] In the display panel of the present application, as shown in Figures 4a and 4b, a boss 13 is provided on the substrate 11, and the active part 20 is provided on the boss 13, and the positive projection of the active part 20 on the substrate 11 overlaps with the boss 13; wherein, in the direction perpendicular to the substrate 11, the sum of the thickness of the boss 13 and the thickness of the first contact part 21 is greater than or equal to the thickness of the gate insulation layer 60.

[0069] In this embodiment, as shown in Figures 4a and 4b, a boss 13 is provided on the substrate 11. The boss 13 can be formed by a patterning process. For example, a buffer layer 12 can be provided on the substrate 11, and the buffer layer 12 is patterned to form the boss 13. In the direction perpendicular to the substrate 11, the sum of the thickness of the boss 13 and the thickness of the first contact portion 21 is greater than or equal to the thickness of the gate insulating layer 60. Since the gate 50 is provided on the gate insulating layer 60, when the sum of the thickness of the boss 13 and the thickness of the first contact portion 21 is greater than or equal to the thickness of the gate insulating layer 60, the boss 13 can raise the channel portion 22, so that the surface of the gate 50 close to the first side wall 22A can cover the channel portion 22 in the thickness direction of the channel portion 22, thereby improving the control ability of the gate 50 over the channel portion 22 and improving the electrical properties of the thin film transistor.

[0070] In the display panel of the present application, as shown in Figures 5a and 5b, the display panel includes a second barrier layer 40, which is arranged on the side of the second contact portion 23 facing away from the substrate 11, and the orthographic projection of the second barrier layer 40 on the second contact portion 23 overlaps with the second contact portion 23.

[0071] In this embodiment, as shown in Figures 5a and 5b, a second barrier layer 40 is formed over the second contact portion 23 to block ion penetration into the second contact portion 23. Specifically, ion doping can be performed on the second contact portion 23 after the second barrier layer 40 is formed. The material of the second barrier layer 40 can be an inorganic material, such as silicon nitride, silicon oxide, or silicon oxynitride. The thickness of the second barrier layer 40 can be matched to the ion implantation parameters. Optionally, the thickness of the second barrier layer 40 is 100 to 2000 angstroms. This configuration prevents the channel portion 22 from being heavily doped, thereby forming a channel.

[0072] Furthermore, because the active portion 20 comprises a three-layer stack of a first contact portion 21, a channel portion 22, and a second contact portion 23, the active portion 20 of the present application requires more hydrogen replenishment compared to a conventional single-layer channel structure. Therefore, the second barrier layer 40 can be made of a silicon nitride material with a high hydrogen content. This allows hydrogen to diffuse into the polysilicon layer during the hydrogenation process after ion doping, repairing silicon dangling bonds and improving the electrical properties of the thin film transistor.

[0073] As shown in FIG. 6 a to FIG. 6 c , the manufacturing process of the display panel of the present application will be described below by taking the first display panel as an example.

[0074] In step S10 , a substrate 11 is provided, and a light shielding layer 90 is formed on the substrate 11 by a patterning process.

[0075] In step S20 , a buffer layer 12 is formed on the light shielding layer 90 , and a first contact portion 21 is formed on the buffer layer 12 by a patterning process.

[0076] In step S30 , a first barrier layer 30 is formed on the first contact portion 21 by a patterning process.

[0077] In step S40 , a channel portion 22 and a second contact portion 23 are formed on the first barrier layer 30 by a patterning process.

[0078] The orthographic projections of the channel portion 22 and the second contact portion 23 on the substrate 11 overlap, so that the active portion 20 can be patterned using one mask, thereby simplifying the manufacturing process of the display panel.

[0079] In step S50 , a gate insulating layer 60 is formed on the active portion 20 , and a gate 50 is formed on the gate insulating layer 60 by a patterning process. The gate 50 at least covers the first sidewall 22A of the channel portion 22 .

[0080] Step S60 , forming an interlayer insulating layer 80 on the gate insulating layer 60 , and forming via holes in the interlayer insulating layer 80 by a patterning process, wherein the via holes expose the first contact portion 21 and the second contact portion 23 .

[0081] In step S70 , a source electrode 71 and a drain electrode 72 are formed on the interlayer insulating layer 80 . The source electrode 71 and the drain electrode 72 fill the via holes. The source electrode 71 is electrically connected to the first contact portion 21 , and the drain electrode 72 is electrically connected to the second contact portion 23 .

[0082] In the present application, the patterning process includes steps such as coating photoresist, exposure, development, etching, and stripping photoresist. The desired pattern can be formed on the film layer through the patterning process.

[0083] The manufacturing processes of the second display panel, the third display panel, and the fourth display panel are similar to this and will not be repeated here.

[0084] The present application provides a display terminal, which includes the above-mentioned display panel.

[0085] In this embodiment, the display terminal may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0086] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] The above is a detailed introduction to a display panel and a display terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising: substrate; An active portion is arranged on the substrate, the active portion comprises a stacked first contact portion, a channel portion, and a second contact portion, the channel portion is partially arranged on a side of the first contact portion away from the substrate, and the second contact portion is arranged on a side of the channel portion away from the substrate; wherein, on the substrate, an orthographic projection of the second contact portion overlaps with an orthographic projection of the channel portion, and an orthographic projection of the second contact portion partially overlaps with an orthographic projection of the first contact portion; in a direction perpendicular to the substrate, a portion where the first contact portion intersects with the first contact portion is a first sub-portion, and a portion where the second contact portion intersects with the first contact portion is a second sub-portion; A gate insulating layer, disposed on a side of the active portion facing away from the substrate; A gate is arranged on a side of the gate insulating layer away from the substrate, the active portion has a first side wall, and the first side wall is an inclined side surface of an overlapping portion of the first contact portion, the channel portion and the second contact portion; the gate at least covers the channel portion on the first side wall on the gate insulating layer; A source-drain electrode layer is arranged on a side of the active portion away from the substrate, and the source-drain electrode layer includes a source electrode and a drain electrode; the source electrode is electrically connected to the first sub-portion through a via hole, and the drain electrode is electrically connected to the second sub-portion through a via hole.

2. The display panel according to claim 1, wherein: The orthographic projection of the gate on the substrate covers part of the orthographic projection of the first side wall on the substrate, and one end of the gate extends along the first side wall to a surface of the active portion facing away from the substrate, and the other end of the gate extends along the first side wall to the substrate.

3. The display panel according to claim 2, wherein: The first contact portion extends along a first direction, the second contact portion extends along a second direction, and the first direction and the second direction have a preset angle; the orthographic projection of the first side wall on the substrate extends along the second direction, and in the second direction, the length dimension of the gate is less than or equal to the length dimension of the first side wall.

4. The display panel according to claim 3, wherein: The second contact portion includes a long portion along the second direction and a short portion along the first direction, the first sidewall is located on an inclined side of the short portion and extends along the second direction, and in the second direction, a length dimension of the gate is greater than a length dimension of the channel portion.

5. The display panel according to claim 3 or 4, wherein: The display panel comprises a first barrier layer, wherein the first barrier layer is disposed between the first contact portion and the channel portion; The first barrier layer covers the first sub-portion, and an orthographic projection of the first side wall on the substrate is spaced apart from an orthographic projection of the first barrier layer on the substrate.

6. The display panel according to claim 5, wherein: A first distance is formed between an end of the first barrier layer close to the gate and the first sidewall, and the first distance is in a range of 0.01 micrometers to 0.1 micrometers.

7. The display panel according to claim 5, wherein: The via electrically connecting the source and the first sub-section is a first via, the via electrically connecting the drain and the second sub-section is a second via, the first via is configured to penetrate the gate insulating layer and the first barrier layer, and the second via is configured to penetrate the gate insulating layer.

8. The display panel according to claim 1, wherein: The display panel comprises a light shielding layer, which is arranged on a side of the active portion close to the substrate, and an orthographic projection of a first side wall of the channel portion on the light shielding layer is located within the light shielding layer.

9. The display panel according to claim 1, wherein: A boss is provided on the substrate, the active part is provided on the boss, and the orthographic projection of the active part on the substrate overlaps with the boss; Wherein, in a direction perpendicular to the substrate, a sum of a thickness of the boss and a thickness of the first contact portion is greater than or equal to a thickness of the gate insulating layer.

10. The display panel according to claim 1, wherein: The display panel includes a second barrier layer, which is disposed on a side of the second contact portion facing away from the substrate, and an orthographic projection of the second barrier layer on the second contact portion overlaps with the second contact portion.

11. The display panel according to claim 10, wherein: The second barrier layer has a thickness of 100 angstroms to 2000 angstroms.

12. A display terminal, comprising a display panel, wherein the display panel comprises: substrate; An active portion is arranged on the substrate, the active portion comprises a stacked first contact portion, a channel portion, and a second contact portion, the channel portion is partially arranged on a side of the first contact portion away from the substrate, and the second contact portion is arranged on a side of the channel portion away from the substrate; wherein, on the substrate, an orthographic projection of the second contact portion overlaps with an orthographic projection of the channel portion, and an orthographic projection of the second contact portion partially overlaps with an orthographic projection of the first contact portion; in a direction perpendicular to the substrate, a portion where the first contact portion intersects with the first contact portion is a first sub-portion, and a portion where the second contact portion intersects with the first contact portion is a second sub-portion; A gate insulating layer, disposed on a side of the active portion facing away from the substrate; A gate is arranged on a side of the gate insulating layer away from the substrate, the active portion has a first side wall, and the first side wall is an inclined side surface of an overlapping portion of the first contact portion, the channel portion and the second contact portion; the gate at least covers the channel portion on the first side wall on the gate insulating layer; A source-drain electrode layer is arranged on a side of the active portion away from the substrate, and the source-drain electrode layer includes a source electrode and a drain electrode; the source electrode is electrically connected to the first sub-portion through a via hole, and the drain electrode is electrically connected to the second sub-portion through a via hole.

13. The display terminal according to claim 12, wherein: The orthographic projection of the gate on the substrate covers part of the orthographic projection of the first side wall on the substrate, and one end of the gate extends along the first side wall to a surface of the active portion facing away from the substrate, and the other end of the gate extends along the first side wall to the substrate.

14. The display terminal according to claim 13, wherein: The first contact portion extends along a first direction, the second contact portion extends along a second direction, and the first direction and the second direction have a preset angle; the orthographic projection of the first side wall on the substrate extends along the second direction, and in the second direction, the length dimension of the gate is less than or equal to the length dimension of the first side wall.

15. The display terminal according to claim 14, wherein: The second contact portion includes a long portion along the second direction and a short portion along the first direction, the first sidewall is located on an inclined side of the short portion and extends along the second direction, and in the second direction, a length dimension of the gate is greater than a length dimension of the channel portion.

16. The display terminal according to claim 14 or 15, wherein: The display panel comprises a first barrier layer, wherein the first barrier layer is disposed between the first contact portion and the channel portion; The first barrier layer covers the first sub-portion, and an orthographic projection of the first side wall on the substrate is spaced apart from an orthographic projection of the first barrier layer on the substrate.

17. The display terminal according to claim 16, wherein: The via electrically connecting the source and the first sub-section is a first via, the via electrically connecting the drain and the second sub-section is a second via, the first via is configured to penetrate the gate insulating layer and the first barrier layer, and the second via is configured to penetrate the gate insulating layer.

18. The display terminal according to claim 12, wherein: The display panel comprises a light shielding layer, which is arranged on a side of the active portion close to the substrate, and an orthographic projection of a first side wall of the channel portion on the light shielding layer is located within the light shielding layer.

19. The display terminal according to claim 12, wherein: A boss is provided on the substrate, the active part is provided on the boss, and the orthographic projection of the active part on the substrate overlaps with the boss; Wherein, in a direction perpendicular to the substrate, a sum of a thickness of the boss and a thickness of the first contact portion is greater than or equal to a thickness of the gate insulating layer.

20. The display terminal according to claim 12, wherein: The display panel includes a second barrier layer, which is disposed on a side of the second contact portion facing away from the substrate, and an orthographic projection of the second barrier layer on the second contact portion overlaps with the second contact portion.

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