Data writing method and apparatus

Abstract

A data writing method and apparatus, relating to the field of data storage. The method comprises: on the basis of written data, a control circuit performs a set operation or a reset operation on a storage unit corresponding to each bit, the set operation being used for converting the storage unit from an amorphous state to a crystalline state, and the reset operation being used for converting the storage unit from an amorphous state to a crystalline state; and when performing the reset operation, the control circuit applies a first pulse to the storage unit and then applies a second pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the relationship between the total pulse width tRtotal of a third pulse applied to execute the reset operation and the total pulse width tStotal of a pulse applied to execute the set operation is: |tRtotal-tStotal| / tStotal<0.5. The method can reduce a time delay of a phase change memory.

Description

Data writing method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 6, 2023, with application number 202311675676.6 and application name “Data Writing Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data storage, and more particularly, to a data writing method and device. Background Art

[0003] With the widespread adoption of technologies such as mobile internet, cloud computing, big data, deep learning, and the Internet of Things, market demand for low-latency, high-density, and large-capacity data storage is rapidly increasing. Phase change memory (PCM), a promising non-volatile storage technology, has been commercialized in various storage architectures.

[0004] How to reduce the delay of PCM is an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The present application provides a data writing method and device, which can reduce the latency of a phase change memory.

[0007] In a first aspect, a data writing method is provided, the method being used to write data in a phase change memory, the phase change memory comprising a control circuit and a memory array, the memory array comprising a plurality of memory cells; the method comprising: the control circuit acquiring data to be written into the memory array, the data comprising a plurality of bits, each bit corresponding to a memory cell; the control circuit performing a set operation or a reset operation on the memory cell corresponding to each bit according to the written data, the set operation being used to convert the memory cell from an amorphous state to a crystalline state, and the reset operation being used to convert the memory cell from an amorphous state to a crystalline state; when performing the reset operation, the control circuit applying a first pulse and then a second pulse to the memory cell, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the third pulse applied when performing the reset operation is less than t. Rtotal The total pulse width t of the pulse applied to perform the set operation Stotal The relationship is:|t Rtotal -t Stotal | / t Stotal <0.5.

[0008] For example, the resistance value of the PCM may be two, wherein a higher resistance value (also called a high resistance state or a reset state) is used to indicate a value of 0, and a lower resistance value (also called a low resistance state or a set state) is used to indicate a value of 1.

[0009] The operation that changes a PCM from a high-resistance state to a low-resistance state is called a set operation. Similarly, the set operation causes the phase-change material to transition from a predominantly amorphous state to a predominantly crystalline state, a phase transition process also known as a set process. Therefore, a set operation can also be understood as a "setting 1" operation, changing the value of 0 to 1.

[0010] The operation that changes the PCM from a low-resistance state to a high-resistance state can be called a reset operation. Similarly, the reset operation causes the phase-change material to transition from a primarily crystalline state to a primarily amorphous state, a phase change process that can also be called a reset process. Therefore, the reset operation can also be understood as a "zero" operation, changing the value of 1 to 0.

[0011] In the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material. These crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state, thereby reducing the delay of the PCM in performing a set operation. It is understandable that write instructions are often executed on multiple storage cells at the same time, some of which perform set operations and some perform reset operations. The write operation with the highest delay affects the total delay of these write instructions. The above scheme makes the delay of the set operation and the reset operation close, avoiding the situation where the set delay is large and the reset delay is small, thereby improving the execution speed of the write operation. In addition, the second pulse can accelerate the relaxation of the threshold voltage of the storage cell where the PCM is located, so that the threshold voltage of the reset state can return to a stable state faster, avoiding the read voltage mistakenly identifying the set state as the reset state, and reducing the read error rate. Moreover, the application of the second pulse can expand the read voltage window. When the threshold voltage does not return to a stable state, the original read voltage can still be used to successfully distinguish between the set state memory cell and the reset state memory cell, thereby reducing the read error rate.

[0012] In combination with the first aspect, in some implementations of the first aspect, there is a time interval between the second pulse and the first pulse.

[0013] Immediately after the first pulse's falling edge, the phase-change material may be at a high temperature, and its reset state may be unstable. Applying the second pulse directly at this point may cause the reset operation to fail. Therefore, setting a time interval between the second and first pulses can increase the success rate of the reset operation, thereby improving the accuracy of data written to the storage system.

[0014] In combination with the first aspect, in some implementations of the first aspect, the time interval is 100-1000 nanoseconds (ns).

[0015] In combination with the first aspect, in certain implementations of the first aspect, the maximum amplitude of the waveform of the second pulse is 10-50 microamperes (μA) and / or 0.5-4.5 volts (V).

[0016] Because the phase-change material produces a greater number of crystal nuclei under the stimulation of a higher current / voltage, increasing the maximum amplitude of the second pulse waveform further shortens the time required to generate a sufficient number of crystal nuclei, thereby accelerating the process of transforming the phase-change material from an amorphous state to a crystalline state, thereby reducing the delay in writing the first value to the PCM. Furthermore, under the stimulation of a higher current / voltage, the relaxation of the threshold voltage of the memory cell containing the PCM is further accelerated, further reducing the read error rate. Furthermore, the read voltage window is further expanded, further reducing the read error rate.

[0017] In combination with the first aspect, in some implementations of the first aspect, the pulse width of the second pulse is 10-500 ns.

[0018] Because the phase-change material produces a greater number of crystal nuclei under long-term current / voltage stimulation, applying the second pulse for a longer period of time can further shorten the time required to generate a sufficient number of crystal nuclei, thereby accelerating the process of transforming the phase-change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay in writing the first value into the PCM.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the waveform of the second pulse includes at least one of a square wave, a triangle wave, or a step wave.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the maximum amplitude of the waveform of the third pulse is 5.5-7.5V.

[0021] Because the second pulse is applied after the first pulse, the reset state threshold voltage of the memory cell containing the PCM increases. Therefore, for the set operation, the required peak maximum amplitude is higher, so that the third pulse reaches the reset state threshold voltage first. In this way, the set operation can only be achieved by applying the latter part of the third pulse. However, the dynamic resistance of the memory cell containing the PCM does not increase with the application of the second pulse. Therefore, when the latter part of the third pulse is applied to the PCM, a higher current can be provided, thereby accelerating the set operation of the PCM.

[0022] In combination with the first aspect, in certain implementations of the first aspect, a pulse width of the third pulse is 10-500 ns.

[0023] In the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material. These crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of the PCM writing the first value, i.e., performing the set operation.

[0024] In combination with the first aspect, in certain implementations of the first aspect, the waveform of the third pulse has at least two amplitude platforms greater than zero.

[0025] Different memory cells in the memory array have different physical distances from the driving circuit. Therefore, the interconnect resistances and interconnect capacitances that the current signal of the third pulse passes through when it reaches these memory cells from the driving circuit are also different in size. This results in different amplitude platforms of the pulses for the set operation that the driving circuit needs to send to different memory cells. In addition, different memory cells have certain differences in material composition, structural dimensions, morphological damage, etc. during the process preparation process, which will also result in different amplitude platforms of the waveform of the pulses for the set operation that the driving circuit needs to send to different memory cells. Therefore, using a third pulse with a waveform having at least two amplitude platforms helps to cover the amplitude platforms required for different memory cells in the memory array to perform better crystallization operations, thereby improving the success rate of the set operation.

[0026] In a second aspect, a phase change memory is provided, the phase change memory including a control circuit and a memory array, the control circuit being configured to: obtain data to be written into the memory array, the data including a plurality of bits, each bit corresponding to a memory cell; perform a set operation or a reset operation on the memory cell corresponding to each bit according to the written data, the set operation being configured to convert the memory cell from an amorphous state to a crystalline state, and the reset operation being configured to convert the memory cell from an amorphous state to a crystalline state; when performing the reset operation, the control circuit applies a first pulse to the memory cell and then applies a second pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulses applied when performing the reset operation is less than t. Rtotal The total pulse width t of the third pulse applied to perform the set operation is Stotal The relationship is:|t Rtotal -t Stotal | / t Stotal <0.5.

[0027] In a third aspect, a computing device is provided, comprising a processor and a phase change memory, wherein the processor is used to input data to be written into the phase change memory, and the phase change memory is used to execute the first aspect and any possible method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic block diagram of a storage unit.

[0029] FIG2 is a schematic block diagram of a storage system.

[0030] FIG. 3 is a schematic diagram showing waveforms of pulses applied in a write operation and a read voltage.

[0031] FIG4 is a schematic diagram of a three-dimensional memory array.

[0032] FIG5 is a schematic flowchart of a data writing method provided in an embodiment of the present application.

[0033] FIG6 is a schematic block diagram of a computing device provided in an embodiment of the present application.

[0034] FIG7 is a schematic diagram of a first pulse and a second pulse provided in an embodiment of the present application.

[0035] FIG8 is a schematic diagram of a third pulse provided in an embodiment of the present application.

[0036] FIG9 is a schematic block diagram of a phase change memory provided in an embodiment of the present application.

[0037] FIG10 is a schematic block diagram of another computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solution in this application will be described below with reference to the accompanying drawings.

[0039] FIG1 is a schematic block diagram of a memory cell 100 .

[0040] 1 , a memory cell 100 may include a PCM 110 and an ovonic threshold switch (OTS) 120 .

[0041] The PCM 110 is a non-volatile memory (NVM) that can maintain its resistance value unchanged when power is off.

[0042] The PCM 110 can have two resistance values, where a higher resistance value (also called a high-resistance state or a reset state) indicates a value of 0, and a lower resistance value (also called a low-resistance state or a set state) indicates a value of 1. The PCM 110 can maintain its resistance for a period ranging from 1 second to 10 years, or even longer than 10 years.

[0043] PCM 110 can be based on a phase change material, such as a chalcogenide phase change material. PCM 110 can switch between different resistance values ​​under thermal conditions, with the difference between the reset state and the set state being 10 to 10,000 times greater, enabling accurate storage of values ​​0 and 1.

[0044] The operation of changing PCM 110 from a high-resistance state to a low-resistance state can be called a set operation. Correspondingly, the set operation causes the phase-change material to transition from a predominantly amorphous state to a predominantly crystalline state, a phase change process also known as a set process. Therefore, a set operation can also be understood as a "setting 1" operation, changing a value of 0 to a value of 1.

[0045] The operation of changing PCM 110 from a low-resistance state to a high-resistance state can be called a reset operation. Correspondingly, the reset operation causes the phase-change material to transition from a primarily crystalline state to a primarily amorphous state, a phase change process also known as a reset process. Therefore, the reset operation can also be understood as a "zero" operation, changing a value of 1 to a value of 0.

[0046] OTS120 is a volatile device. For example, OTS120 can be made of a chalcogenide material. OTS120 can function as a gate transistor connected in series with PCM 110. Thus, the combination of OTS120 and PCM 110 can function as a unit of a memory array, namely, memory cell 100. At low voltages, OTS120 exhibits a high-resistance state, suppressing leakage current and preventing changes in the resistance state of PCM 110 that could lead to data storage errors. At higher programming voltages, OTS120 exhibits a low-resistance state, providing sufficient current for read and write operations. Thus, when a memory cell 100 is selected, OTS120 opens a current path, enabling the PCM 110 within that memory cell 100 to perform read or write operations. When a memory cell 100 is unselected, OTS120 remains closed, preventing a current path within that memory cell 100 and preventing interference with read or write operations on other selected memory cells 100.

[0047] The memory cell 100 can be a 1-selector-1-resistor (1S1R) configuration. 1S1R can also be understood as a 1-selector plus a 1-resistor variable resistor memory. 1S1R can also be understood as a 1-memory cell. Alternatively, 1S1R can mean a memory cell consisting of a 1-selector plus a 1-resistor variable resistor memory. However, this application is not limited to this, and the memory cell 100 can also include multiple selectors and multiple memories.

[0048] A plurality of memory cells 100 are connected via word lines (WL) and bit lines (BL) to form an array of memory cells 100 .

[0049] FIG2 is a schematic block diagram of a storage system 200 .

[0050] The memory system 200 includes a plurality of memory cells 100 (eg, a plurality of 1S1R), a row decoder 210 , and a column decoder 220 .

[0051] Referring to Figure 2 , from the perspective of memory cells 100, each of the n WLs connects to a row of memory cells 100, with the row decoder connected to the n WLs. Each of the m BLs connects to a column of memory cells 100, with the column decoder connected to the m BLs. From the perspective of the overall memory system 200, this solution can also be understood as a memory cell 100 located at the intersection of each WL and each BL. The n WLs and m BLs connect multiple memory cells 100, forming an n*m memory array.

[0052] The storage system 200 may also include components such as a sense amplifier, a driver circuitry, a digital controller, a data buffer, or an input / output interface (not shown). The storage system 200 can read and write data using the sense amplifier and the driver circuitry, which may include a read driver circuit and a write driver circuit. Data to be written may be stored in the data buffer before being written, and data to be read may also be stored in the data buffer. In addition, the digital controller may control the above operations and exchange data and commands with other external systems through the input / output interface.

[0053] The storage system 200 can select a specific WL from among multiple WLs. This allows a different voltage level to be applied to the selected WL than to the other WLs, thereby performing a read or write operation on the memory cells on the selected WL (e.g., the 1S1R cells in a row). For example, a write operation can transmit an electrical signal to the selected WL to write data; a read operation can transmit an electrical signal to the selected WL, and then transmit an electrical signal indicating feedback from the read operation along the selected WL to a row decoder. The storage system can select a specific BL from among multiple BLs. This allows a different voltage level to be applied to the selected BL than to the other BLs, thereby performing a read or write operation on the memory cells on the selected BL (e.g., the 1S1R cells in a column). For example, a write operation can transmit an electrical signal to the selected BL to write data; a read operation can transmit an electrical signal to the selected BL, and then transmit an electrical signal indicating feedback from the read operation along the selected BL to a column decoder.

[0054] In this way, the storage system 200 can choose to turn on or off the OTS 120 in any one storage cell 100 by selecting a WL and a BL, thereby realizing a read operation or a write operation on any storage cell 100 in the entire storage array, and avoiding the situation where, when one storage cell 100 is selected, there is a current conduction path in other storage cells 100, thereby causing a current sneak path and ultimately leading to a high read and write error rate.

[0055] It should be noted that the present application does not limit the storage system 200 to only being able to select one WL and one BL at the same time. The storage system 200 may also simultaneously select multiple WLs and multiple BLs, thereby enabling the OTS 120 of multiple storage units 100 to be turned on or off at the same time.

[0056] Referring to FIG2 , taking writing to a specific memory cell 100 (hereinafter referred to as the target memory cell) as an example, a write driver circuit (not shown in FIG2 ) can modulate the voltage of WLx (where x is a value between 1 and n) connected to the target memory cell to a voltage pulse with an amplitude of V1, hence, this pulse can also be referred to as a V1 pulse. Furthermore, the write driver circuit can apply a pulse with an amplitude of V2 to BLy (where y is a value between 1 and m) connected to the target memory cell, hence, this pulse can also be referred to as a V2 pulse. The above process can also be understood as the process of selecting WLx and BLy.

[0057] The V1 and V2 pulses can have opposite polarities. For example, V1 can be 4V and V2 can be -4V. Since these two pulses are applied to both ends of the target memory cell (i.e., WL and BL, respectively), the total effective pulse applied to the target memory cell is the difference between the two pulses. For example, the maximum peak voltage of the total pulse of 4V and -4V is 8V.

[0058] The write driver circuit may modulate the voltage of the WLs not connected to the target memory cell (i.e., WLs other than WLx) to V3 (e.g., 0 V), and modulate the voltage of the BLs not connected to the target memory cell (i.e., BLs other than BLy) to V4 (e.g., 0 V). The above process may also be understood as a process in which WLs other than WLx and BLs other than BLy are not selected.

[0059] In this way, only the target memory cells corresponding to the selected WLx and BLy have a sufficiently large voltage difference, for example, the maximum peak voltage of the total pulse of |V1-V2| is 8V. This voltage difference is greater than the threshold voltage for turning on the target memory cell, enabling and completing the corresponding write operation. Specifically, for the reset operation, the target memory cell is in the set state, so the voltage difference needs to be greater than the threshold voltage of the set state; for the set operation, the target memory cell is in the reset state, so the voltage difference needs to be greater than the threshold voltage of the reset state.

[0060] The voltage differences of the memory cells corresponding to the unselected WL and BL, that is, the memory cells other than the target memory cell, are all lower than the threshold voltage required to turn on these memory cells, causing them to be in the off state and preventing a write operation from being performed on PCM 110. For example, the maximum peak voltage of the total pulse of |V1-V4| is 4V, the maximum peak voltage of the total pulse of |V3-V2| is 4V, and the maximum peak voltage of the total pulse of |V3-V4| is 0V. Both 4V and 0V are lower than the threshold voltage required to turn on these memory cells.

[0061] Referring to Figure 2 , taking the reading of a memory cell 100 (hereinafter referred to as the target memory cell) as an example, the read driver circuit may modulate the voltage of a WL connected to the target memory cell to a voltage pulse with an amplitude of V5, hence, this pulse may also be referred to as a V5 pulse. Furthermore, the read driver circuit may apply a pulse with an amplitude of V6 to a BL connected to the target memory cell, hence, this pulse may also be referred to as a V6 pulse. The above process can also be understood as the process of selecting a WL and a BL. The V5 pulse and the V6 pulse have opposite polarities.

[0062] Similar to the write operation, the read driver circuit may modulate the voltage of WL not connected to the target memory cell to V7 (eg, 0V), and modulate the voltage of BL not connected to the target memory cell to V8 (eg, 0V).

[0063] In this way, only the target memory cells corresponding to the selected WL and the selected BL have a sufficiently large voltage difference (e.g., the maximum peak voltage of the total pulse of |V5-V6|), which is greater than the threshold voltage of the target memory cell in the set state and less than the threshold voltage in the reset state. Therefore, when the target memory cell is in the set state, the voltage of the read operation (hereinafter referred to as the read voltage) can turn on the target memory cell, so that a large current can be read; when the target memory cell is in the reset state, the read voltage cannot turn on the target memory cell, so that only a small current can be read. By distinguishing between large current and small current, the storage system 200 can determine whether the target memory cell is in the reset state or the set state, that is, determine whether the target memory cell stores a value of 0 or a value of 1.

[0064] The voltage differences of the memory cells corresponding to the unselected WL and BL (e.g., the maximum peak voltages of the total pulses of |V5-V8|, |V7-V6|, and |V7-V8|, respectively) are all lower than the threshold voltages for turning on these memory cells, causing these memory cells to be in a turned-off state, and the PCM 110 will not be read.

[0065] FIG3 is a schematic diagram of the waveform of the pulse applied in the write operation and the read voltage. The read operation and the write operation are described below with reference to FIG3 .

[0066] Figures 3(a) and 3(b) show the waveforms of the pulses applied during the write operation, wherein Figure 3(a) shows the waveform of the pulses applied during the reset operation, and Figure 3(b) shows the waveform of the pulses applied during the set operation.

[0067] Referring to FIG. 3 (a), the pulse applied during the reset operation has a short pulse width and high amplitude, such as a pulse width of 10-50 nanoseconds (ns), an amplitude of 50-200 μA (microamperes), and / or 7.5-10 volts (V). After the threshold voltage of the set state is reached, PCM 110 quickly reaches the melting temperature of the phase change material. Then, the pulse is quickly removed with a short falling edge, causing the phase change material in PCM 110 to be rapidly quenched from the molten state to the amorphous state.

[0068] If the pulse width of the reset pulse is too long, the total power consumption of the reset operation will be too high. If the falling edge of the reset pulse waveform is too long, the phase change material will enter the set temperature range, causing nucleation and grain growth, and the phase change material will become crystalline, resulting in an unsuccessful reset operation, that is, a false set operation.

[0069] Referring to (b) in FIG3 , the pulse applied by the set operation has a longer pulse width and a lower amplitude, such as a pulse width of 500-1000 ns, an amplitude of 10-100 μA, and / or 4.5-5.5 V. After the threshold voltage of the reset state is turned on, the temperature of the PCM 110 is controlled to be higher than the glass transition temperature of the phase change material and lower than the melting temperature, so as to facilitate the nucleation and grain growth of the phase change material in the PCM 110. Ultimately, after a longer time than that of the reset operation, the phase change material in the PCM 110 transforms from an amorphous state to a crystalline state. In particular, the pulse applied by the set operation has a spike pulse at the very beginning that turns on the OTS 120, and the amplitude of the spike pulse can be 100-150 μA. After turning on the OTS 120, the amplitude of the waveform of the pulse applied by the set operation may further decrease, and gradually decrease to 0 after stable operation.

[0070] See (c) in Figure 3, the read voltage V R0 It can be between the threshold voltage of the set state and the threshold voltage of the reset state. During the read operation, the sensitive amplifier circuit can distinguish the target memory cells in the set state and the reset state when the read voltage is applied. For the target memory cell in the set state, the applied read voltage V R0 is greater than the threshold voltage of the target memory cell, the target memory cell can be turned on, thereby reading a high current; for the target memory cell in the reset state, the applied read voltage V R0 If the voltage is lower than the threshold voltage of the target memory cell, the target memory cannot be turned on, thereby reading a low current.

[0071] Due to the introduction of OTS120, the threshold voltage of the memory cell 100 will drift. As shown in Figure 3 (c), before the threshold voltage drifts, the read voltage can correctly distinguish the memory cell 100 in the set state and the reset state. As shown in Figure 3 (d), after the threshold voltage drifts, the threshold voltages of the set state and the reset state increase with the drift. If the original read voltage V R0 , it will cause a portion of the set state memory cells 100 to be recognized as the reset state, thereby increasing the read error rate at the chip level.

[0072] As shown in (e) of FIG3 , the physical mechanism of threshold voltage drift caused by OTS120 can be understood through defect states. In the initial state, OTS120 is in a low leakage state, and there are few defect states in the center of the band gap of the OTS material. When performing the initial opening (first fire) operation, OTS120 is stimulated by voltage (V FF ) will generate a metastable defect state. The energy of the metastable defect state is located in the center of the band gap of the OTS material, which can support a large turn-on current to flow. After the initial opening, when the OTS120 is opened again, since the defect state has been generated, a part of the defect state will remain in the center of the band gap. The OTS120 and the PCM 110 are connected in series to form the memory cell 100. The turn-on voltage of the OTS120 will affect the threshold voltage of the entire memory cell 100. Therefore, when it is not initially turned on, it may not be necessary to provide the same voltage V as that at the initial opening. FF , so that the threshold voltage (V th@t0 ) is higher than V FF In other words, the OTS120 does not need to reach the voltage V FF , it is possible to generate enough defect states to support the flow of the turn-on current. It is worth noting that after OTS120 is turned off at time t0, the metastable defect states will relax over time, and the number of defect states will gradually decrease. For example, as time passes from time t0 to time t1 and time t2, the threshold voltage of the memory cell 100 gradually returns to the threshold voltage V when the OTS material is initially turned on. FF .

[0073] To solve this problem, a read retry mechanism can be introduced at the controller level. Specifically, error correction code (ECC) can be performed on the read data. If a correctable error data bit is identified, the data bit is reread using a different read voltage than the first read operation. For example, see (f) in Figure 3. A read voltage V R0 Higher read voltage V R1, thus successfully distinguishing whether the storage unit 100 is in the set state or the reset state, thereby successfully reading data. However, this solution introduces additional ECC error correction and repeated read latency overhead, reducing the read performance of the storage system 200.

[0074] The following introduces some solutions for three-dimensional storage arrays.

[0075] All storage arrays of a two-dimensional non-volatile memory are located on the same plane. All storage arrays of a three-dimensional non-volatile memory (3D NVM) are located in a three-dimensional space and can be located on multiple parallel or intersecting planes. Storage system 200 can be two-dimensional or three-dimensional. In the case of a three-dimensional storage system 200, FIG2 can be understood as a cross-section of storage system 200, or as a deck of storage system 200, or as a plane of storage system 200.

[0076] Figure 4 is a schematic diagram of a three-dimensional memory array, wherein NVM1 and NVM2 may be PCMs.

[0077] Referring to the left portion of Figure 4 , the upper memory cell includes NVM1, gate transistor 1, and electrode 2. Metal extending within a horizontal plane (the plane defined by the x and y directions in Figure 4 ) connects each memory cell to the others. Electrode 1 connects Metal 1 to NVM1, and Electrode 3 connects Metal 2 to gate transistor 1.

[0078] The extension directions of the metals above and below the memory cell are not in the same direction, and these metals can serve as WL and BL respectively. For example, metal 1 extends along the y direction and metal 2 extends along the x direction. If metal 1 serves as WL (or BL), metal 2 can serve as BL (or WL). The memory cells connected by metal 1 and metal 2 form a two-dimensional memory array, which is arranged on a layer. Further stacking the memory array of a layer in the vertical direction (z direction in Figure 4) forms a cross-stacked three-dimensional memory array. The outside of the three-dimensional memory array can be encapsulated with an insulating layer, as shown in the right part of Figure 4. Through the patterning of vertical columnar structures, the three-dimensional memory array can reach the extreme scale of lithography, so the unit density of a single layer is high.

[0079] During the manufacturing process, two etching steps are performed to form a memory cell in a three-dimensional memory array. Taking the memory cell in the lower layer of Figure 4 as an example, the memory cell in the upper layer includes metal 3, electrode 4, NVM 2, electrode 5, gate 2, electrode 6, and metal 4.

[0080] The first etch determines the orientation and shape of metal 4 below gate tube 2. For example, electrode 4, NVM2, electrode 5, gate tube 2, electrode 6, and metal 4 can be etched in the y direction. The second etch determines the orientation and shape of metal 3 above NVM2. For example, metal 3, electrode 4, NVM2, electrode 5, gate tube 2, and electrode 6 can be etched in the x direction. NVM2, gate tube 2, and electrodes 4, 5, and 6 are etched in both etching steps, leaving the remaining portions in a columnar shape. Metal 4 only undergoes the first etching, extending in the y direction; metal 3 only undergoes the second etching, extending in the x direction.

[0081] After etching the lower memory cells, the upper memory cells may be etched in the same manner, that is, etching metal 1, electrode 1, NVM 1, electrode 2, gate tube 1, electrode 3, and metal 2.

[0082] For high-density stacked three-dimensional memory arrays, due to their small size and high heating efficiency, the amorphization operation during the reset process is more complete, resulting in a reduction in nucleation centers in the NVM material, making the crystallization operation during the set process more difficult, increasing the delay of the set operation and affecting the delay performance of the PCM.

[0083] Figure 5 is a schematic flow chart of a data writing method 500 provided in an embodiment of the present application. Method 500 can reduce PCM latency. Method 500 is used to write data into a phase-change memory, which includes a control circuit and a memory array, wherein the memory array includes multiple memory cells. Method 500 is described below in conjunction with Figure 5 and other accompanying figures.

[0084] S510 , the control circuit obtains data to be written into the storage array, where the data includes a plurality of bits, and each bit corresponds to a storage unit.

[0085] The control circuit can be a controller chip, or any device with a control function.

[0086] For example, the data to be written into the memory array may be "1100." Thus, the data includes four bits, each corresponding to a memory cell. Specifically, the first bit "1" may correspond to memory cell #1, the second bit "1" may correspond to memory cell #2, the third bit "0" may correspond to memory cell #3, and the fourth bit "0" may correspond to memory cell #4. The memory array includes the aforementioned memory cells #1 to #4.

[0087] FIG6 is a schematic block diagram of a computing device 600 provided in an embodiment of the present application. Referring to FIG6 , the computing device 600 includes a processor 610, a controller chip 620, and a memory chip 630. Specifically, a phase change memory may include the controller chip 620 and the memory chip 630.

[0088] The processor 610 can also be understood as the central processing unit (CPU) of the host. The controller chip 620 is located between the processor 610 and the memory chip 630. The memory chip 630 can also be understood as the aforementioned storage system 200. The memory chip 630 includes the aforementioned storage array. The controller chip 620 can convert the write data request of the processor 610 and the data to be written into a write data command and write data format that can be recognized by the memory chip 630. The controller chip 620 can also convert the read data request of the processor 610 into a read data command that can be recognized by the memory chip 630, and convert the read data read from the memory chip 630 into a read data format that can be recognized by the processor 610. In addition, the controller chip 620 can also include functions for managing various types of memory failures, such as bad block management, wear leveling, repeated reading, ECC error correction calculation, and other functions.

[0089] The data in S510 above may come from the processor 610. It should be noted that the scenario shown in FIG6 is merely for ease of understanding and does not constitute a limitation of the present application. It does not mean that the embodiments of the present application are only applicable to this scenario. The data in S510 above may also come from other devices, such as the controller chip 620.

[0090] S520, the control circuit performs a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, the set operation is used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation is used to convert the storage cell from an amorphous state to a crystalline state.

[0091] The memory cell may include a phase-change material having a crystalline state or an amorphous state, wherein the crystalline state may correspond to a first value and the amorphous state may correspond to a second value, and the first value and the second value may be different. For example, the first value may be 1 and the second value may be 0, that is, the crystalline state corresponds to 1 and the amorphous state corresponds to 0.

[0092] The set operation can write 1 to the memory cell that stores 0, and the reset operation can write 0 to the memory cell that stores 1.

[0093] S530, when performing the reset operation, the control circuit applies a second pulse to the memory cell after applying the first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the third pulse applied during the reset operation is Rtotal The total pulse width t of the pulse applied to perform the set operation Stotal The relationship is:|t Rtotal -t Stotal | / t Stotal <0.5.

[0094] The first pulse may be referred to as a pulse applied by a reset operation. For example, the first pulse may be as shown in FIG3( a ), but the present application is not limited thereto, and may be other waveforms, for example.

[0095] The third pulse may be referred to as a pulse applied by a set operation. For example, the third pulse may be as shown in FIG. 3( b ), but this application is not limited thereto. For example, the third pulse may have a shorter pulse width than the pulse shown in FIG. 3( b ). If the third pulse is applied to PCM 110, the value in PCM 110 is rewritten from the second value to the first value. For example, the value 0 in PCM 110 is rewritten to the value 1.

[0096] In some optional embodiments, the maximum amplitude of the waveform of the second pulse is less than the maximum amplitude of the waveform of the third pulse. Therefore, applying the second pulse to PCM 110 does not transform the phase-change material from an amorphous state to a crystalline state. In other words, after applying the second pulse (i.e., executing S530), the phase-change material in PCM 110 remains in an amorphous state, i.e., the value in PCM 110 remains at the second value, such as 0. The second pulse can be considered a post-processing pulse for the reset operation.

[0097] On the one hand, the third pulse transforms the phase-change material from an amorphous state to a crystalline state (a process also referred to as crystallization), thereby storing the first value in PCM 110. As previously mentioned, the crystallization process consists of two steps: nucleation and grain growth. Under the stimulation of the second pulse, a certain number of nuclei are hatched within the phase-change material. These nuclei serve as nucleation centers for the subsequent grain growth process. It is understood that if these nuclei are not already present, the phase-change material must first generate sufficient nuclei under the influence of the third pulse before grain growth can proceed. However, if these nuclei are present, the phase-change material itself has sufficient nuclei and can directly undergo grain growth; alternatively, the phase-change material can generate sufficient nuclei in a shorter time. Therefore, the second pulse can shorten the time required to generate a sufficient number of nuclei, thereby accelerating the process of transforming the phase-change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the latency required to write the first value to PCM 110. In other words, this approach can reduce the latency of set operations. It's understandable that write instructions often execute simultaneously on multiple memory cells. Some of these cells perform set operations, while others perform reset operations. The write operation with the highest latency affects the overall latency of these write instructions. The above solution makes the latency of set and reset operations similar, avoiding the situation where set latency is higher and reset latency is lower, thereby improving the execution speed of write operations.

[0098] Furthermore, the maximum amplitude of the second pulse is smaller than the maximum amplitude of the first pulse, that is, smaller than the maximum amplitude of the pulse waveform applied during the reset operation. This causes the temperature of the phase-change material after the second pulse is applied to be lower than the temperature range where melting occurs, thus preventing an erroneous reset operation. Therefore, the maximum amplitude of the second pulse being smaller than the maximum amplitude of the first pulse can prevent erroneous reset operations, thereby ensuring the accuracy of written data.

[0099] On the other hand, when PCM 110 and OTS 120 are connected in series, a second pulse is applied to both ends of OTS 120. At this time, the defect states in the metastable state in OTS 120 will gain energy under the stimulation of the voltage of the second pulse and relax faster, thereby reducing the defect states until they return to the threshold voltage corresponding to V FF Therefore, the second pulse can accelerate the relaxation of the threshold voltage of the memory cell, allowing the threshold voltage of the reset state to return to a stable state more quickly, avoiding the read voltage from mistakenly identifying the set state as the reset state, and reducing the read error rate. Moreover, compared to the solution that introduces ECC error correction and repeated reads, the embodiment of the present application reduces the probability of read errors and reduces the delay overhead of introducing additional ECC error correction and repeated reads.

[0100] On the other hand, when PCM 110 and OTS 120 are connected in series, a second pulse is applied to both ends of OTS 120. At this time, the threshold voltage of the reset state is increased, while the threshold voltage of the set state does not change. As mentioned above, the read voltage needs to be between the threshold voltage of the reset state and the threshold voltage of the set state. Therefore, the application of the second pulse can expand the range in which the read voltage can be applied, that is, expand the read voltage window. Therefore, even if the threshold voltage drifts, due to the expansion of the read voltage window, the original read voltage may still be within the read window. In this way, when the threshold voltage has not returned to a stable state, it is still possible to successfully distinguish between the memory cell in the set state and the memory cell in the reset state using the original read voltage, thereby reducing the read error rate.

[0101] In summary, in the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material. These crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state, thereby reducing the delay of the PCM in performing a set operation. It is understandable that write instructions are often executed on multiple storage cells at the same time, where some storage cells perform set operations and some storage cells perform reset operations. The write operation with the highest delay affects the total delay of these write instructions. The above scheme makes the delay of the set operation and the reset operation close, avoiding the situation where the set delay is large and the reset delay is small, thereby improving the execution speed of the write operation. In addition, the second pulse can accelerate the relaxation of the threshold voltage of the storage cell where the PCM is located, so that the threshold voltage of the reset state can return to a stable state faster, avoiding the read voltage mistakenly identifying the set state as the reset state, and reducing the read error rate. Moreover, the application of the second pulse can expand the read voltage window. When the threshold voltage has not returned to a stable state, the original read voltage can still be used to successfully distinguish between set state memory cells and reset state memory cells, thereby reducing the read error rate.

[0102] In some embodiments, there is a time interval between the second pulse and the first pulse.

[0103] Figure 7 is a schematic diagram of a first pulse and a second pulse provided in an embodiment of the present application. The images in Figure 7 are for illustration only and do not constitute a limitation of the present application.

[0104] Referring to FIG. 7 (a), the waveform of the first pulse has a current / voltage of I R1 / V R1 The second pulse waveform has a current / voltage of I R2 / V R2A certain time interval is set between the first pulse and the second pulse, and the voltage during this time interval is 0. However, this application is not limited to this, and the voltage during the time interval may also be a value close to 0, or other values.

[0105] For example, the current / voltage is I R1 / V R1 The width of the amplitude platform can be 10-50ns.

[0106] Immediately after the first pulse's falling edge, the phase-change material may be at a high temperature, and its reset state may be unstable. Applying the second pulse directly at this point may cause the reset operation to fail. Therefore, setting a time interval between the second and first pulses can increase the success rate of the reset operation, thereby improving the accuracy of data written to the storage system.

[0107] In some embodiments, the time interval is 100-1000 ns.

[0108] For example, the time interval shown in (a) of FIG. 7 may be taken from 100 to 1000 ns.

[0109] It should be noted that the present application does not limit the time interval between the second pulse and the first pulse. For example, referring to FIG7(b), there may be no time interval between the second pulse and the first pulse, and the second pulse may be applied before the falling edge of the first pulse reaches 0.

[0110] In some embodiments, the maximum amplitude of the waveform of the second pulse is 10-50 μA and / or 0.5-4.5V.

[0111] The maximum amplitude mentioned in this application may refer to the absolute value of the maximum amplitude. For example, the I shown in (a), (b), (d), (e) and (f) in FIG7 R2 Taken from 10-50μA. For another example, the I R2 The absolute value of is taken from 10-50 μ A. In addition, the maximum amplitude mentioned in the present application is not limited to the maximum amplitude of the current, for example, it can also be the maximum amplitude of the voltage.

[0112] Because the phase change material is stimulated by a larger current / voltage, the amount of crystal nuclei generated in the phase change material will be greater. Therefore, increasing the maximum amplitude of the waveform of the second pulse can further shorten the time required to generate a sufficient number of crystal nuclei, thereby accelerating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of PCM 110 writing the first value. In addition, under the stimulation of a larger current / voltage, OTS 120 further accelerates the relaxation of the threshold voltage of the storage cell where PCM 110 is located, further reducing the read error rate. In addition, the read voltage window is further expanded, thereby further reducing the read error rate.

[0113] In some embodiments, the second pulse has a pulse width of 10-500 ns.

[0114] For example, the applied current / voltage in (a), (b) and (c) of FIG7 is I R2 / V R2 The pulse width of the pulse with the amplitude of 1 is 10-500ns. For another example, in FIG7 (d), the applied current / voltage is I R2 / V R2 The pulse width of the pulse is the same as the applied current / voltage I R3 / V R3 The sum of the pulse widths of the pulses with the same amplitude is 10-500ns. For another example, in FIG7 (e), the current / voltage is applied from I R2 / V R2 The pulse width of the pulse that decays to 0 is 10-500ns. For another example, in FIG7 (f), the applied current / voltage changes from 0 and the current / voltage is I R2 / V R2 , and then drops to 0, the pulse width is 10-500ns.

[0115] Because the phase-change material produces a greater number of crystal nuclei under prolonged current / voltage stimulation, applying the second pulse for a longer period of time can further shorten the time required to generate a sufficient number of crystal nuclei, thereby accelerating the process of transforming the phase-change material from an amorphous state to a crystalline state, thereby reducing the delay in writing the first value into the PCM.

[0116] In some embodiments, the waveform of the second pulse includes at least one of a square wave, a triangle wave, or a step wave.

[0117] For example, (a), (b), and (c) in FIG7 illustrate some embodiments of square waves. For another example, (d) in FIG7 illustrates an embodiment of a step wave. For another example, (e) in FIG7 illustrates an embodiment of a triangle wave.

[0118] It should be noted that the waveform of the second pulse may also be other shapes. For example, FIG7( f ) shows an embodiment of a sine wave.

[0119] FIG8 is a schematic diagram of a third pulse provided in an embodiment of the present application.

[0120] In some embodiments, the waveform of the third pulse has a peak, and the maximum amplitude of the peak is 5.5-7.5V.

[0121] For example, see (a) in FIG8 , I S1 It can be taken from 5.5-7.5V. It should be noted that in the relevant technical solutions, the maximum amplitude of the peak of the pulse waveform applied by the set operation is often less than 5.5V. The maximum amplitude of the peak can also be 50-150μA. The maximum amplitude of the peak can also be called the maximum amplitude of the third pulse.

[0122] Because the second pulse is applied after the first pulse, the reset state threshold voltage of the memory cell 100 where PCM 110 resides increases. Therefore, for a set operation, the required peak maximum amplitude is higher, so that the third pulse reaches the reset state threshold voltage first. In this way, the set operation can only be achieved by applying the latter portion of the third pulse. However, the dynamic resistance of the memory cell 100 where PCM 110 resides does not increase with the application of the second pulse. Therefore, when the latter portion of the third pulse is applied to PCM 110, a higher current can be provided, thereby accelerating the set operation on PCM 110.

[0123] In some embodiments, the third pulse has a pulse width of 10-500 ns.

[0124] For example, referring to (a) and (b) in FIG8 , the pulse width can be taken from 10 to 500 ns. It should be noted that in related technical solutions, the pulse width of the pulse applied by the set operation is often greater than 500 ns.

[0125] As mentioned above, the pulse width of the first pulse may be 10-50 ns, and the pulse width of the second pulse may be 10-500 ns. Therefore, the total pulse width of the first pulse and the second pulse may be 20-550 ns.

[0126] It can be seen that after adding the second pulse, the total duration of the first and second pulses is close to the duration of the third pulse. In other words, the total pulse width of the pulses applied by the reset operation is close to the pulse width of the pulse applied by the set operation. The total pulse width of the pulses applied by the reset operation and the pulse width of the pulse applied by the set operation can be expressed by the following formula.

[0127] Among them, t Rtotal Represents the total pulse width of the pulse applied by the reset operation (or the total duration of the first pulse and the second pulse), t Stotal Indicates the pulse width of the pulse applied by the set operation (or the duration of the third pulse).

[0128] In the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material. These crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of the PCM writing the first value, i.e., performing the set operation.

[0129] In some embodiments, the waveform of the third pulse has at least two amplitude plates greater than zero.

[0130] When the current / voltage is kept at a certain value for a period of time, the current / voltage during this period will be reflected in the graph with current / voltage and time as the coordinate axes, which will be in the shape of an amplitude platform. For example, see (a) in Figure 8, the current / voltage is I S2 / V S2 The part of the amplitude can be called the amplitude platform. For example, see (b) in Figure 8, the current / voltage is I S2 / V S2 The part can be called the amplitude platform, and the current / voltage is I S3 / V S3 The part can also be called the amplitude platform.

[0131] 8( b ) shows an embodiment in which the waveform of the third pulse has two amplitude platforms greater than 0. The waveform of the third pulse having at least two amplitude platforms greater than zero can also be called a stepped set waveform.

[0132] Different memory cells 100 in the memory array have different physical distances from the driving circuit. Therefore, the interconnect resistance and capacitance that the current signal of the third pulse passes through from the driving circuit to these memory cells 100 are also different. This results in different amplitude platforms of the pulse waveforms applied by the driving circuit to the set operation required for different memory cells 100. Some memory cells 100 have different current / voltage values ​​when the current / voltage is I S2 / V S2 The amplitude platform can achieve a better crystallization effect, while some memory cells 100 need to be crystallized at a current / voltage of I S3 / V S3Achieving a good crystallization effect requires an amplitude platform. Furthermore, different memory cells 100 have certain differences in material composition, structural dimensions, morphological damage, and other aspects during the manufacturing process, which can also result in different amplitude platforms in the waveform of the pulses applied by the driver circuit for the set operation to different memory cells 100. Therefore, using a third pulse with at least two amplitude platforms helps cover the amplitude platforms required for a good crystallization operation for different memory cells 100 in the memory array, thereby improving the success rate of the set operation.

[0133] The method embodiments of the present application are described in detail above. The following describes the device embodiments of the present application. The device embodiments correspond to the method embodiments, so for parts not described in detail, please refer to the previous method embodiments. The device can implement any possible implementation method of the above method.

[0134] FIG9 is a schematic block diagram of a phase change memory 900 provided in an embodiment of the present application.

[0135] As shown in FIG9 , the phase change memory device 900 includes a control circuit 910 and a memory array 920. The control circuit 910 is used to: obtain data to be written into the memory array 920, where the data includes multiple bits, each bit corresponding to a memory cell; perform a set operation or a reset operation on the memory cell corresponding to each bit according to the written data, where the set operation is used to convert the memory cell from an amorphous state to a crystalline state, and the reset operation is used to convert the memory cell from an amorphous state to a crystalline state; when performing the reset operation, the control circuit 910 applies a first pulse to the memory cell and then applies a second pulse, where the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulse applied when performing the reset operation is t. Rtotal The total pulse width t of the third pulse applied to perform the set operation is Stotal The relationship is:|t Rtotal -t Stotal | / t Stotal <0.5.

[0136] This application also provides another computing device 1000. As shown in Figure 10, computing device 1000 includes a bus 1002, a processor 1004, a phase-change memory 900, and a communication interface 1008. Processor 1004, phase-change memory 900, and communication interface 1008 communicate with each other via bus 1002. Computing device 1000 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in computing device 1000.

[0137] Bus 1002 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, among others. Buses may be classified as address buses, data buses, control buses, and the like. For ease of illustration, FIG10 illustrates a single bus line, but this does not imply a single bus or type of bus. Bus 1002 may include a path for transmitting information between various components of computing device 1000 (e.g., memory 1006, processor 1004, and communication interface 1008).

[0138] The processor 1004 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0139] Phase change memory 900 may include volatile memory, such as random access memory (RAM). Memory 1006 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0140] The processor 1004 is used to input data to be written into the phase change memory 900 into the phase change memory 900 , and the phase change memory 900 is used to execute the aforementioned data writing method.

[0141] The communication interface 1008 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 1000 and other devices or a communication network.

[0142] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0143] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0144] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data writing method, characterized in that: The method is used to write data in a phase change memory, the phase change memory includes a control circuit and a storage array, the storage array includes a plurality of storage cells; The method comprises: The control circuit acquires data to be written into the storage array, the data comprising a plurality of bits, each bit corresponding to a storage unit; The control circuit performs a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, wherein the set operation is used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation is used to convert the storage cell from an amorphous state to a crystalline state; When performing the reset operation, the control circuit applies a second pulse to the storage unit after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulses applied during the reset operation is Rtotal The total pulse width t of the third pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.

5.

2. The method according to claim 1, characterized in that There is a time interval between the first pulse and the second pulse.

3. The method according to claim 2, characterized in that The time interval is 100-1000 nanoseconds ns.

4. The method according to any one of claims 1 to 3, characterized in that The maximum amplitude of the waveform of the second pulse is 10-50 microamperes μA and / or 0.5-4.5 volts V.

5. The method according to any one of claims 1 to 4, characterized in that: The pulse width of the second pulse is 10-500ns.

6. The method according to any one of claims 1 to 5, characterized in that The waveform of the second pulse includes at least one of a square wave, a triangle wave or a step wave.

7. The method according to any one of claims 1 to 6, characterized in that: The maximum amplitude of the waveform of the third pulse is 5.5-7.5V.

8. The method according to any one of claims 1 to 7, characterized in that The pulse width of the third pulse is 10-500ns.

9. The method according to any one of claims 1 to 8, characterized in that The waveform of the third pulse has at least two amplitude platforms greater than zero.

10. A phase change memory, comprising a control circuit and a storage array, characterized in that: The control circuit is used for: Acquire data to be written into the storage array, the data comprising a plurality of bits, each bit corresponding to a storage unit; Performing a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, wherein the set operation is used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation is used to convert the storage cell from an amorphous state to a crystalline state; When performing the reset operation, the control circuit applies a second pulse to the storage unit after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulses applied during the reset operation is Rtotal The total pulse width t of the third pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.

5.

11. A computing device, characterized in that: The method comprises a processor and a phase change memory, wherein the processor is used to input data to be written into the phase change memory, and the phase change memory is used to execute the method according to any one of claims 1 to 9.

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