A baseband signal processor and a method for processing wireless communications signals

Abstract

A baseband signal processor (400) for wireless communications signals. The baseband signal processor (400) comprises an analog channel select filter (401) for filtering the wireless communications signals. The analog channel select filter (401) comprises an analog crossbar array of memristors. Each memristor of the analog crossbar array is configured to represent a respective filter coefficient of a filter function implemented as a filter matrix.

Description

[0001]A BASEBAND SIGNAL PROCESSOR AND A METHOD FOR PROCESSING WIRELESSCOMMUNICATIONS SIGNALS TECHNICAL FIELD The embodiments herein relate to a baseband signal processor and a method forprocessing wireless communications signals. A corresponding computer program and acomputer program carrier are also disclosed. BACKGROUND In a typical wireless communication system 10 schematically illustrated in Figure1, the communication is performed between multiple user equipments (UE) 12, 14, 16such as cell phones, Internet of Things (IoT) devices, etc. and a base station (BS) 11 viaa respective wireless channel 22, 24, 26. The wireless channel between the BS and theUEs may be represented using a channel state information (CSI) matrix, which describes channel effects like signal attenuation, phase change, etc. on the propagated signals. Since the available frequency spectrum is limited, the transmission resources must be utilized as efficiently as possible. In order to improve spectral efficiency, throughput, and link reliability, advanced communication techniques are needed for wireless data transmission between the BS 11 and the UEs 12, 14, 16. Massive multiple-input multiple- output (MIMO) is such a technique, which may offer very high spectral and energy efficiency and it is considered as a key technology in Fifth Generation (5G) networks complying with third generation partnership program (3GPP). In massive MIMO systems, the BS is equipped with a large number of antennas, serving several UEs simultaneously using the same time and frequency resources. In such systems, the data transmission is done through uplink and downlink paths as described below. Figure 2 is a schematic illustration of data transmission over the wireless channeland processing of wireless signals in a transmitter chain 210 and in a receiver chain220. At a transmitter (TX) side, i.e., in the transmitter chain 210, information bits areencoded with a channel encoder 211, and the encoded bits are mapped to constellationsymbols by a symbol mapper 213. Before mapping the bits to constellation symbols thebits may be interleaved in an interleaver 212. The symbols may be precoded in a precoder 214. The symbols are then modulated by a modulator 215, such as by anOrthogonal Frequency Division Multiplexing (OFDM) modulator, and then converted toanalog signals to be transmitted over the wireless channel in the uplink or downlink pathusing one or more antennas. The OFDM modulator may use an Inverse Discrete FourierTransform (IDFT) for the modulation. The modulated symbols are then passed through a digital front end 216. Thedigital front end 216 may include digital signal conditioning to convert the baseband signal to a conditioned signal that compensates for inaccuracies in the analog transmit chain.Functions of the digital front end 216 may include Digital Upconversion (DUC), alsoknown as channelization. The symbols are then passed through an analog front end 218. The TX / RX analogand digital front-end chains may include several modules such as low noise amplifiers (LNAs), mixers, analog to digital converters, and filters. These blocks perform several operations such as amplifying, filtering, predistortion, and down / up conversion of the transmitted / received signals. The calibration and compensation for hardwareimperfections may be done either in the analog chains and / or in the digital front-end.Moreover, one of the tasks in the digital front-end block is to perform symbolsynchronization to determine the exact timing of the incoming OFDM symbols. The analog signals are propagated from one or more antennas 219 through theatmosphere in the form of electromagnetic waves, and they are received by one or moreantennas at the receiver (RX) side.The receiver chain 220 performs inverse transformations (demodulation) on thereceived signals in a demodulator 223 and corrects errors introduced by the propagationchannel and TX / RX chains to extract the transmitted information, e.g., from a certain UE.To this end, the received signal goes through the analog front-end and is eventuallyfiltered and demodulated. Then, the received symbols are detected in a detector 224,demapped by a symbol demapper 226, and decoded by a channel decoder 228 toobtain an estimate of the transmitted bits. In the detection process, the receiver chain 220 may need to know the channelstate. This may be done by, for example, sending known pilots used to estimate theeffects of the propagation channel on the transmitted signal. The receiver chain 220 maycomprise a channel estimator 225. Furthermore, the receiver chain may also comprise a de-interleaver 227.It can be seen that the digital baseband processor of wireless communicationsystems should perform several operations such as digital front end, orthogonal frequency-division multiplexing (OFDM) modulation / demodulation, channel estimation, MIMO processing, interleaving / deinterleaving, channel encoding and decoding, etc. Eventually, these complex baseband signal processing algorithms have to be realized using very large-scale integration (VLSI) architectures and implemented in hardware, which is a very challenging task. Some of the problems and challenges regarding hardware implementation of baseband processor are described below. The benefits of massive MIMO technology entail a significant increase in signal processing complexity at the baseband, where sophisticated signal processing techniquesare required. The large number of BS antennas and number of UEs result in challenges tomeet the requirements on latency, data rate, and hardware cost. Some of thesechallenges are listed below.• Computational Complexity and Memory RequirementsDue to the large number of antennas in massive MIMO systems, the size of the CSI matrix becomes very large. This results in two main challenges: First, the computational complexity of the baseband processor is increased significantly since all the computations should be done using very large matrices and vectors. Second, the amount of memory which is needed to store the CSI data becomes very large. Higher complexity and size of required memory make the hardware implementation of the baseband processor very challenging and costly. •High ThroughputThe demand for higher data rate has been increased remarkably over the pastdecades, especially in some use cases like video streaming, eXtended Reality (XR) andAugmented Reality (AR). In order to achieve ever-increasing data rates, higher parallelismof the baseband processor is required, which is very challenging using the traditional hardware implementation methods. •High Performance and Low Bit Error Rate (BER)There are many applications like remote surgery and autonomous vehicles, which require a very low probability of error. In order to enhance link reliability, channel codingschemes may be used. However, designing high-performance and hardware-friendlydecoding algorithms is very challenging using traditional hardware implementation methods. •Ultra-low LatencyNew services and applications require very low-latency communication links and aim for data delivery within a specified delay (i.e., time-critical communications). Moreover, in time division duplexing (TDD) mode, which is a typical operation mode of massive MIMO systems, the latency requirement becomes far more challenging. This is due to the sharing of available time budget between uplink and downlink processing. Thus, efficient hardware implementation is needed to reduce the processing latency of the baseband processor. •FlexibilitySince the propagation environment as well as the required throughput, latency, andreliability change over the time in different applications, flexible signal processing at thebaseband processor is needed. Thus, to keep up with the rapid growth in wireless data traffic and number of subscriptions, and to support emerging applications, the baseband processor should deliver higher data rates, lower latency, and higher link-reliability. As a result, hardware implementation of baseband processor using the traditional approaches has become a critical challenge. SUMMARY Due to the large number of BS antennas and number of UEs, most of thecomputations in a baseband signal processor are performed using large matrices andvectors. This results in challenges to meet the requirements on latency, data rate, and hardware cost. There is thus a need for a more efficient approach for implementing basebandprocessing. An object of embodiments herein may be to obviate some of the problemsrelated to baseband processing mentioned above.Embodiments herein disclose a baseband signal processor and a method forprocessing of wireless communication signals. Specifically, embodiments herein disclosea baseband signal processor for massive MIMO applications. The disclosed basebandsignal processor uses Processing In Memory (PIM) techniques. All the functional blockswithin the baseband processing chain may be realized using analog crossbar arrays.However, in some embodiments a mixture of analog crossbar arrays and digital circuitsmay be used to implement different functions of the baseband signal processor. Inparticular, the baseband signal processor comprises an analog filter for filtering thewireless communications signals. The analog filter comprises an analog crossbar array.An analog crossbar is a 2-dimensional array that consists of M×N memristivedevices, each of which can be programmed to represent an m-bit binary value. According to a first aspect, the object is achieved by a baseband signal processorfor wireless communications signals. The baseband signal processor comprises ananalog channel select filter for filtering the wireless communications signals. The analogchannel select filter comprises an analog crossbar array of memristors. Each memristor ofthe analog crossbar array is configured to represent a respective filter coefficient of a filter function implemented as a filter matrix. According to a second aspect, the object is achieved by a method for filteringwireless communications signals with a baseband signal processor.The method comprises filtering the wireless communications signals with an analogchannel select filter of the baseband signal processor by using matrix vectormultiplication. The analog channel select filter comprises an analog crossbar array ofmemristors. Each memristor of the analog crossbar array represents a respective filtercoefficient of a filter function implemented as filter matrix. According to a further aspect, the object is achieved by a computer programcomprising instructions, which when executed by a processor, causes the processor toperform actions according to any of the aspects above. According to a further aspect, the object is achieved by a carrier comprising the computer program of the aspect above, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium. Since the baseband signal processor comprises the analog channel select filterwhich comprises the analog crossbar array of memristors the baseband signal processor is able to fully process the baseband signals in parallel. The crossbar arrays according to embodiments herein enable performing massive multiply-accumulate (MAC) operations in parallel. More specifically, the crossbar arrays may compute matrix-vector multiplication (MVM) by calculating a dot-product of the input vector applied to crossbar rows (i.e., wordlines) and every column of the crossbar (i.e., bit lines). This reduces the latency andincreases throughput. Further, the baseband signal processor according to embodiments herein is veryflexible. For example, the size of the filter matrix can be changed as well as the filtercoefficients. This allows the baseband signal processor to be adapted to different systemparameters such as bandwidth, frequency spacing, size of OFDM, modulation order,different coding, detection, precoding schemes etc. The baseband signal processor mayfurther be adapted to a propagation environment and application requirements.Further, there is no need for Analog to Digital Converters (ADCs) nor Digital toAnalog Converters (DACs) for the inputs and outputs of the baseband processing chainas well as in between different functional blocks within the processing chain. By realization of the complicated algorithms of the baseband signal processor usingprocessing in memory approach, the computational complexity will be reduced to ^(1). This results in a significant reduction in hardware complexity of the baseband signal processor especially in case of massive MIMO with a large number of base station antennas and UEs. This is due to the fact that, in embodiments herein, the computationsare done through the inherent features of memristive devices.Embodiments herein may reduce the power consumption, which in turn leads toincreased battery life at the device side (i.e., UE) since embodiments herein reduce thehardware complexity and also use low-energy memristive devices to implement thebaseband signal processor. This may be of particular interest for IoT devices.The baseband signal processor according to embodiments herein is scalable interms of number of antennas and UEs, bandwidth, number of subcarriers carrying data, and modulation order, etc. The baseband signal processor according to embodiments herein supports serial,partial parallel, and fully parallel implementation of different baseband processingfunctions, specifically the filtering function.Latency of the baseband signal processor according to embodiments herein is onlylimited by a read cycle of the crossbar array, and it is not limited by the complexity of the algorithms or hardware architectures. Due to the reduction in the complexity and energy consumption, the basebandsignal processor according to embodiments herein enables employing lager number ofbase station antennas and UEs, compared to traditional wireless communication systems.BRIEF DESCRIPTION OF THE DRAWINGS In the figures, features that appear in some embodiments are indicated by dashed lines. The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating a wireless communication system, Figure 2 is a block diagram schematically illustrating a transmitter chain and areceiver chain according to prior art,Figure 3 is a block diagram schematically illustrating an electronic device comprisinga memristive crossbar array, Figure 4a is a further block diagram schematically illustrating a baseband signalprocessor according to some embodiments herein, Figure 4b is a further block diagram schematically illustrating a baseband signal processor according to some further embodiments herein, Figure 4c is a further block diagram schematically illustrating a transmitter according to some embodiments herein, Figure 4d is a further block diagram schematically illustrating a receiver according tosome further embodiments herein, Figure 5 is a further block diagram schematically illustrating a network node according to some embodiments herein, Figure 6 is a further block diagram schematically illustrating details of the networknode according to some embodiments herein,Figure 7 is a block diagram schematically illustrating a memristive crossbar arrayimplementing a matched filter function,Figure 8 is a block diagram schematically illustrating a memristive crossbar array implementing a function, Figure 9 is a further block diagram schematically illustrating details of the network node according to some embodiments herein, Figure 10a is a further block diagram schematically illustrating a wireless communications device according to some embodiments herein, Figure 10b is a further block diagram schematically illustrating details of a wirelesscommunications device according to some embodiments herein, Figure 11 is a flowchart illustrating embodiments of a method for filtering wirelesscommunications signals with a baseband signal processor, Figure 12 is a flowchart illustrating embodiments of a method for programming acrossbar array of memristors, Figure 13a is a schematic block diagram illustrating embodiments of a method forprogramming a crossbar array of memristors, Figure 13b is a schematic block diagram illustrating further embodiments of amethod for programming a crossbar array of memristors, Figure 14 is a schematic block diagram illustrating further embodiments of anelectronic device according to some embodiments herein, Figure 15 is a block diagram schematically illustrating a network node. Figure 16 is a block diagram schematically illustrating a wireless communications device. Figure 17 is a block diagram schematically illustrating a wireless communicationsystem. DETAILED DESCRIPTION Embodiments herein relate to a baseband signal processor for wireless communications signals. Aprocessing chain of a baseband signal processor includes several complexalgorithms, which usually are performed in analog and digital domains. On the other hand, transmitted signals in a downlink and received signals in an uplink path are analogsignals. As a result, these signals should be converted to digital and / or analog versionsthroughout the baseband processing chain. The domain transformation between analogand digital domains increases the hardware cost (e.g., power consumption) as well asdegrading the accuracy and the performance of the system. In embodiments disclosedherein, an efficient baseband signal processor is proposed, which performs computationsin the analog domain and eliminates need for ADCs and DACs.As mentioned above, the baseband signal processor according to embodimentsherein comprises one or more analog crossbar arrays of memristors to implementdifferent functions of the baseband signal processor. A memristor may also be referred to as a memristive device. Analog memristive devices have emerged as a new technology for storing and processing information in analog domain. These devices make it possible to perform computations in a place wheredata is stored. This concept is called in-memory computing (or processing in memory),which eliminates the need for moving data from a memory to a processing unit. There are different types of memristive devices, which are differentiated with respect to the used materials, switching principles, device endurance, retention, etc. The main types of memristive devices include phase change memory (PCM), resistive random-access memory (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), ferroelectric memristive devices (FeRAM). Memristive devices may support a limited bit precision, attributed to the limited number of conductance levels that may be reliably programmed inthe device. For example, a PCM device may support around 50 conductance levels,meaning that it may represent around 6 bits. A number of memristor devices may be organized to form an analog crossbar array.Figure 3 illustrates an electronic device 301, such as a baseband signal processor,comprising a memristor crossbar array 310 which computes MVM by calculating a dot-product of the input vector applied to crossbar rows (i.e., word lines) and every column ofthe crossbar (i.e., bit lines). The memristor crossbar array 310 is a two-dimensional arraythat comprises an M×N array of memristors 311, 312, 321, 322, each of which may beprogrammed to represent an m-bit binary value. A memristor is a tunable andprogrammable. The memristor may comprise a dielectric layer sandwiched by twoelectrodes. A unique feature of memristors is that the conductance depends on historicalelectrical signals, making them capable of working as nonvolatile memory. In addition, memristors may store multibit information with continuously tunable conductance, in contrast to binary states “0” and “1” in traditional digital storage systems, equipping them with higher bit density. Thus, the m-bit binary value of the memristor may be set or programmed by applying a current to the memristor. The binary value may depend on theamplitude of the current. Thus, an ^ × ^ matrix of binary words, G, may be representedby the memristor crossbar array 310 comprising ^ × ^ memristors. The input to thememristor crossbar array 310 is an electronic input signal of multiple samples, such as avector of ^ analog voltages, e.g., V, which correspond to M binary values.Analog crossbar arrays comprise parallel conductors, such as metal lines, termedword lines and bit lines, respectively, as electrodes of the memristors. The word lines andbit lines may be perpendicular to each other. The memristors are formed at theintersections of word and bit lines. In embodiments herein input conductors 331 of theanalog crossbar array 310 corresponds to the word lines and output conductors 332 ofthe analog crossbar array 310 corresponds to the bit lines.The analog crossbar array 310 computes MVM by calculating the dot-product ofthe input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines), all performed in analog domain using Ohm’s law for multiplication and Kirchhoff’s law for accumulation. In Figure 3 the entries of a matrix G (an M×M matrix) are programmed to thememristive devices 311, 312, 321, 322 of the M×M crossbar array 310 while the inputvector V (an M×1 vector) is applied to the crossbar rows. Note that, the vector Vcorresponds to the actual input vector (Input 1, …, Input M), which may be converted toanalog voltages using one or more DAC modules 304 illustrated in Figure 3. As a result,the following MVM may be realized using the illustrated crossbar array 310,^ = 1, … , ^ (1) where an output vector I is the output current of crossbar columns, which is equal tothe result of matrix-vector multiplication, i.e., I = G‧V. The output vector I may beconverted to the corresponding binary words using one or more ADC modules 305 asshown in Figure 3. This conversion may be done either separately for each crossbarcolumn (i.e., one ADC for each binary word) or in a time-multiplexed fashion and hencereduce ADC overhead (i.e., multiple bit lines may share one ADC 305).In this disclosure vectors and matrices are represented using capital boldface letters while their entries are shown using normal letters. Thus, when the electronic input signal is digital then the electronic device 301further comprises the one or more DACs 304 adapted to convert the input signal ofmultiple samples to corresponding analog voltages V1, V2, … VN. In other words, when the input signal of the multiple samples is digital, the electronicdevice 301 may further comprise the DACs 304 configured to convert the digital inputsignal of the multiple samples to the analog voltages. There may be one DAC 304 per input sample. In some other embodiments theremay be less than one DAC 304 per input sample as one DAC 304 may be shared amongseveral input samples by multiplexing. For example, two input samples may share the same DAC 304. Output signals will be extracted from the bit lines (columns in Figure 3) of thecrossbar array 310. If digital output values of the crossbar array 310 are needed then theoutputs of the crossbar array 310 may be converted to digital values. Thus, the electronicdevice 301 may further comprise the one or more ADCs 305 adapted to convert theoutput samples, comprising analog output current, to corresponding digital output values.In other words, the electronic device 301 may further comprise ADCs 305 configured toconvert the output from the respective output conductor to a digital signal. If analog signals are needed in a next block in the processing chain then the ADCs305 in the electronic device 301 may not be needed.Further, if the analog outputs are sent to another crossbar array then they may beconverted to voltage signals, which may be done by a resistor.Figure 4a schematically illustrates a baseband signal processor 400 for wirelesscommunications signals according to embodiments disclosed herein. The basebandsignal processor 400 may perform parallel processing of a signal and processing ofmultiple signals in parallel.The baseband signal processor 400 comprises an analog channel select filter 401for filtering the wireless communications signals. The analog channel select filter 401comprises the analog crossbar array 310 of memristors 311, 312. Each memristor 311,312 of the analog crossbar array is configured to represent a respective filter coefficient ofa filter function implemented as a filter matrix or filter vector.Filters are used in different places within the signal processing chain of wireless communication systems for different purposes. Some of these applications and needs are explained below. Filters are used in uplink to discard unwanted signals, which are usually receivedfrom the wireless channel. So, these filters select a desired frequency band of thereceived signal, and they are called channel select filters (CSF).Moreover, in some cases like for frequency division duplexing (FDD), a filter may beused to remove interference between a transmitter and a receiver located in the samedevice, which both work at the same time. Similarly, filters may be needed in downlink to remove out-of-band emissions fromthe transmitted signal and to discard noise and other non-idealities, which are introduced by power amplifiers and other blocks in the processing chain. In this way, the transmitter only sends the signal in the target frequency range. Due to the fact that the output signal of the above-mentioned filters will beprocessed in the baseband, these filters are usually low pass filters which may be realizedusing memristors. To this end, the functionality (i.e., the filter impulse response) may be converted to a matrix vector multiplication like X = F*x, in which x is the input signal to the filter, X is the filtered version of the signal, and F represents the filter coefficients. Depending on the required characteristics of the filter, the coefficients may beadjusted such that a target filter impulse response is realized.As an example, a 32th-order FIR lowpass filter may be realized using the followingset of coefficients. In this example, the sampling rate of 30.72 MS / s and the normalized cut-off frequency of 0.48, which corresponds to the frequency of 7.3728 MHz are considered. In the context of memristive-based filters, the following vector contains thevalues, which are programmed to the memristors.F=[-0.0013 -0.0011 0.0020 0.0026 -0.0039 -0.0064 0.0068 0.0135 -0.0104 -0.0260 0.0140 0.0483 -0.0172 -0.0963 0.0193 0.3155 0.4810 0.3155 0.0193 -0.0963 -0.0172 0.0483 0.0140 -0.0260 -0.0104 0.0135 0.0068 -0.0064 -0.0039 0.0026 0.0020 -0.0011 -0.0013] In addition to the above-mentioned applications of the filters, the baseband signalprocessor 400 may include decimation filters as well. The purpose of the decimation filtersis to reduce the sampling rate of the signal. The frequency components of the input signal which are higher than half the sampling frequency will cause distortion to the original spectrum. Therefore, it is necessary to perform filtering for the input signal using a filter, which is called anti-aliasingfilter that eliminates the high-frequency components from the input frequency spectrum.Note that, in the traditional implementation of baseband processor, some of these filters are placed before ADCs / DACs and some after them. However, since embodiments disclosed herein eliminate the need for the ADC / DACs, the filters according toembodiments disclosed herein may be realized using memristors in the analog domainand consequently the whole baseband processing may be performed in the analogdomain. To realize a delay for the analog filter 401 an analog delay may be implemented,meaning that there is no need to convert the signal from analog to digital to perform filtering. There are different types of analog delay elements such as “one period time- delay circuit (OPT)”. The baseband signal processor 400 may comprise further baseband signal-processing circuits 402 and the analog channel select filter 401 may be adapted to beoperatively coupled to the further signal processing circuits 402 of the baseband signalprocessor 400. As discussed above, the further signal processing circuits 402 may beanalog circuits or digital circuits. The analog channel select filter 401 may further beadapted to be operatively coupled to an RF circuit 403. In particular, the further signalprocessing circuits 402 and the RF circuit 403 may each be analog circuits. Thus, in someembodiments herein the analog channel select filter 401 is adapted to be operativelycoupled to an analog electronic circuit 402, 403 without analog to digital conversion ordigital to analog conversion. The analog electronic circuit may be an analog RF circuit403 for wireless transmission or reception or both of the wireless communications signals.In some other embodiments, the analog electronic circuit may be an analog basebandsignal-processing circuit 402 comprised in the baseband signal processor 400.The channel select filter 401 is adapted to perform any one or more of the followingfiltering operations: channel selection, self-Interference rejection, out-of-band filtering,decimation filtering, and anti-aliasing filtering. A respective one of the one or more filteringoperations may be implemented as matrix vector multiplication.Figure 4b schematically illustrates another embodiment of the baseband signalprocessor 400 in which the analog channel select filter 401 is coupled to a first basebandsignal-processing circuit 402a and to a second baseband signal-processing circuit402b. In this case the second baseband signal-processing circuit 402b may interface withthe RF circuit 403. In general, the baseband signal processor 400 may be realized viamultiple processing circuits connected together. Figure 4c schematically illustrates another embodiment of the baseband signalprocessor 400 in which the baseband signal processor 400 is comprised in a transmitter410. In Figure 4c the baseband signal processor 400 comprises an encoder 411, aninterleaver 412, a MIMO precoder 413 and an OFDM modulator 414 as well as theanalog channel select filter 401. Figure 4d schematically illustrates another embodiment of the baseband signalprocessor 400 in which the baseband signal processor 400 is comprised in a receiver420. In Figure 4d the baseband signal processor 400 comprises a decoder 421, a de-interleaver 422, a MIMO detector 423, an OFDM de-modulator 424 and a channelestimator 425 as well as the analog channel select filter 401.The OFDM modulator 414 and the OFDM de-modulator 424 may each be implemented as a circuit for discrete Fourier-related transforms. Thus, the baseband signal processor 400 may be part of an electronic device for transmitting or receiving wireless communications signals or both, such as the transmitter410 in Figure 4c, or the receiver 420 in Figure 4d, or a transceiver. In other words, theelectronic device may comprise the baseband signal processor 400. Each of the functions in the transmitter 410 and the receiver 420 may beimplemented by a further analog crossbar array of memristors. Thus, the analogbaseband signal-processing circuit 402 comprised in the baseband signal processor 400may be any one or more of:the encoder 411 or the decoder 421,the interleaver 412 or the de-interleaver 422,the MIMO precoder 413 or the MIMO detector 423,the channel estimator 425,or the circuit for discrete Fourier-related transforms,and the analog baseband signal-processing circuit 402 may comprise the furtheranalog crossbar array of memristors. In some embodiments disclosed herein the electronic device 410, 420 further comprises the RF circuit 403 for wireless transmission or reception or both of the wirelesscommunications signals. As mentioned above, the RF circuit 403 may be analog. Thus, insome embodiments disclosed herein the electronic device 410, 420 further comprises ananalog RF circuit 403 for wireless transmission or reception or both of the wirelesscommunications signals. The analog RF circuit 403 may be operatively coupled to theanalog channel select filter 401 of the baseband signal processor 400. Thus, the analogRF circuit 403 may be directly coupled to the analog channel select filter 401 or indirectlycoupled to the analog channel select filter 401 via for example another electronic circuit,such as a switch. Figure 5 schematically illustrates a network node 511 of a wirelesscommunications network. The network node 511 comprises an electronic device, such asthe transmitter 410, or the receiver 420. Thus, the network node 511 comprises thebaseband signal processor 400 described above.The network node 511 communicates with K UEs 1, 2, 3, …, K through M antennas1,2, …, M of the network node 511.Figure 6 illustrates the network node 511 of Figure 5 in more detail. The networknode 511 comprises the PIM-based baseband signal processor 400 for a multi-usermassive MIMO system, which is used in 5G and beyond 5G systems. Figure 6 includessome functional blocks which are common in the physical layer of most wirelesscommunication standards. The communication is performed through L subcarrierfrequencies via uplink and downlink paths, as described below. In the following description of the network node 511 it is assumed that the receivedsignals in the uplink and the transmitted signals in the downlink are passed through an analog front-end before and after the baseband signal processing chain, respectively. Theanalog front-end may include a low noise amplifier (LNA), power amplifiers (PA), mixer,etc., which perform amplifying, down / up conversion, filtering, etc. mainly in the analogdomain.PIM-based Uplink Processing in network node 511The Ues may transmit their messages (information bits) through different subcarrier frequencies using uplink signals, which will be affected by the wireless channel.Therefore, the received signal in the uplink path at each subcarrier may be modelled as^ = ^^^^ ^^ + ^ , (2)where ^ = [^^, ^^, … , ^^]^ is the transmitted vector from the K Ues, ^ = [^^, ^^, … , ^^]^represents the vector of received signals across the M antennas, ^^^ is a systemparameter to control the transmit power, ^ is the corresponding CSI matrix, and ^represents the Independent and identically distributed (i.i.d.) complex Gaussian noisevector.The vector of received signals, ^, includes M entries which are processed using Mseparate processing chains as shown in Figure 6.Filter This process starts by filtering the received signal, which will be performed in theanalog domain according to embodiments herein. To this end, the filter frequencyresponse, ^^^^^^^(⋅), is specified according to the targeted system configuration. Then, the filtering operation will be converted to a matrix-vector multiplication, and the filter coefficients will be programmed to the memristors of the corresponding crossbar array. The output samples of the filter, ^^^^^^^^^ = ^^^^^^^(^) , (3)will be generated in parallel for the received signals. A key feature of this scheme is that, depending on the frequency characteristics of the received signals, it is possible to employ the same crossbar configuration for one, multiple, or even all the received signals.This means that different processing chains in Figure 6 may employ the sameconfiguration for the memristors of corresponding crossbar arrays. If the same crossbarconfiguration is used for one, multiple, or even all of the M receiving signals, it means thatthose signals are filtered in the same manner, i.e., using the same filter characteristics.In a next action, the filtered signals may be demodulated using an OFDM scheme,which transfers the time-domain signals to the corresponding frequency-domain signals.The OFDM demodulation may be realized using discrete Fourier transform (DFT). Thus,for each processing chain in Figure 6, the demodulation action may be done using acrossbar array, which performs the multiplication of the input samples by the matrix of DFT coefficients, ^^^^^^ = ^^^^(^^^^^^^^^) , (4)where ^^^^^^is the vector of frequency-domain analog signals, corresponding to each processing chain of Figure 6. These signals are generated in parallel. Also, theproposed DFT scheme may be adjusted flexibly depending on the required signalproperties such as the DFT length, frequency spacing, etc. Then, the massive MIMO detector will detect the transmitted signals by the Ues.This may be done by using different detection algorithms, which trade between detectionperformance and complexity. Linear detection algorithms are one of the most practicaldetection schemes, which may provide near-optimal performance in massive MIMOsystems. This category includes the following algorithms: ^Matched Filtering (MF) may be expressed mathematically as^ = ^^^ (5)where ^^is the Hermitian of the CSI matrix ^, which is equivalent to transposed complex-conjugation of the CSI matrix ^. ^Zero Forcing (ZF) performs the detection using the following equation, where the matrix ^ = ^^^ is called Gram matrix.^ Minimum Mean Squared Error (MMSE) detection algorithm performs thedetection as ^= (^^^ + ^^)^^^^^= (^ + ^^)^^^^^ (7)where ^ is a regularization parameter related to the signal to noise ration (SNR) and^ is the identity matrix.Thus, the functionality of the detector block can be considered as ^^^^^^^^^^^ = ^^^^^^^^^(^^^^^^) = ^ , (8)where ^ is the vector of detected signals, regardless of the chosen algorithm for thistask. The vector ^ includes the closest values to the vector of transmitted signals by the KUes.According to equations (5), (6), and (7) the fundamental underlying operations in thelinear detectors are Gram matrix (G) computation and matched filtering (MF), which aredescribed below. Matched Filtering The matched filtering operation is expressed as^^^ = ^^^ , (9)which can be realized using the crossbar array 310 such that the memristors areprogrammed by the entries of ^^. To clarify this concept, let’s consider the entries of CSI matrix, ^, and the vector of received signals, ^, are real values. The CSI matrix is represented as which has the size of ^ × ^ and ^^ represents the i-th column of CSI matrix. In order torealize the matched filtering operation in equation (5), the i-th crossbar column isprogrammed by ^^. Thus, the first memristor in the i-th crossbar column is programmed byℎ^,^and the last memristor of this column is programmed by ℎ^,^and so on. Then, the entries of vector ^, will be sent to the crossbar rows as shown in Figure 7. Finally, after one read cycle of the crossbar, all the entries of matched filtering vector, ^^^, will be generated simultaneously. Gram Matrix Computation The Gram matrix (G) computation is expressed as^ = ^^^ , (11)which may be realized using the analog crossbar array 310. Similar to the matchedfiltering scheme, the memristors of the analog crossbar array 310 are programmed by theentries of ^^. Let’s consider the example in equation (10), in which entries of the CSI matrix, ^, are real values. In order to perform Gram matrix computation in equation (5), the i-th crossbar column is programmed by ^^. Thus, the first memristor in the i-th crossbar column is programmed by ℎ^,^and the last memristor of this column is programmed by ℎ^,^and so on. Then, the entries of the i-th column of CSI matrix (^^) will be sent to the crossbar rows as shown in Figure 8. After a read cycle, the output signals of crossbar columns will be extracted, which are equivalent to the i-th column of the Grammatrix (^^). Thus, after K read cycles, the complete Gram matrix is obtained, which isrepresented as ^^,^ ^^,^ … ^^,^^ = ^ ^^,^ ^^,^ … ^^,^…^ = [^^ ^^ … ^^], (12)^^,^ ^^,^ … ^^,^which has the size of ^ × ^. As a result, the output samples of the detector are generatedin parallel and the settings of the proposed detector can be adjusted flexibly depending onthe system configuration and channel conditions. It is worth to point out that, in case of complex-valued CSI matrix and vector of received signals, four crossbar arrays of the same size together with memristive-based adders are used. In this case, the memristors of two crossbars are programmed by the real parts of the entries of ^^, such that one of them receives the real parts of the inputs and the other one receives the imaginary parts of the inputs. The memristors of the other two crossbars are programmed by the imaginary parts of the entries of ^^, such that one of them receives the real parts of the inputs and the other one receives the imaginaryparts of the inputs. Then, the outputs of these crossbars may be combined using simpleadders and subtractors to generate the results of the complex multiplications in (9) and(11). The required adders and subtractors may be realized using memristors in the analogdomain. Having considered the proposed architectures in Figure 7 and Figure 8, the sameanalog crossbar 310 with the same configuration may be used to realize both matchedfiltering and Gram matrix computation since both involve computation of ^^. This is a keyfeature of the proposed scheme, which enables resource sharing to reduce hardware cost of the overall system. The reason behind this feature is that as long as the propagation channel condition remains almost fixed, the Gram matrix will remain unchanged. Thus, there is no need to recompute the Gram matrix for each vector of received signals, ^.However, as while as a new vector of signals, ^, is received, the matched filtering shouldbe performed. Note that, the required CSI matrix for the detection is already estimated through the uplink training using pre-known signals (pilot signals). It’s worth to point out that, thechannel estimation algorithms may be realized using the memristive-based crossbars in asimilar manner as the above-mentioned MIMO detection algorithms. This is due to the factthat the computations of these algorithms may be represented as matrix-vectormultiplications. Also other receiver functions of the baseband signal processor 400 may beimplemented by the analog crossbar array 310 of memristors 311, 312. For example, forthe network node 511 after OFDM demodulation there may be MIMO detection, de-interleaving and decoding which each may be implemented by using the analog crossbararray 310. Thus, each of the decoder 421, the de-interleaver 422, the MIMO detector 423, and the OFDM de-modulator 424 of the network node 511 may comprise the analog crossbar array 310.PIM-based Downlink Processing in network node 511Figure 9 schematically illustrates details of the DL processing in the network node513 according to some embodiments herein. Thus Figure 9 illustrates the basebandsignal processor 400 when comprised in the transmitter 410 of the network node 513.At the downlink side, the information may be sent towards the Ues via multiplesubcarrier frequencies. Then the downlink signal model of the massive MIMO system ateach subcarrier may be expressed as^ = ^^ ^^^ ^ ^ + ^ , (13)where ^ = [^^, ^^ , … , ^^]^ is the vector of received signals by the Ues, ^^^ is the totaltransmit power in the downlink, ^ = [^^, ^^, … , ^^]^represents the transmit signal vectorusing M antennas at the network node 511, and ^ is the i.i.d. complex Gaussian noisevector. Due to the channel reciprocity in the time division duplexing (TDD) mode, thedownlink channel matrix is the transposed version of uplink channel matrix, i.e., ^^ forTDD systems. Thus, the uplink CSI matrix may be used for downlink precoding for TDDsystems. Akey benefit of the proposed scheme is that, there is no need to re-program thecrossbar in order to obtain the transposition of CSI matrix. Let’s consider that the crossbaris already programmed by the CSI matrix, ^. A normal mode of the computation, e.g. ^^,is performed by sending the input vector, ^, to the crossbar rows and after a read cycle,the result of this multiplication will be generated along the crossbar columns. However, if amultiplication by the transposed CSI matrix i.e., ^^^, is needed the input vector may besent to the columns and after a read cycle the multiplication result will be generated alongthe crossbar rows instead. As a result, the same crossbar may be used to performmultiplication by CSI matrix and transposed CSI matrix without re-programming the crossbar array. In order to send information bits (messages) towards the Ues, a precoding(beamforming) scheme is used to equalize the channel effects and separate data streamsfor each UE. This will minimize inter user interference and thus simplifies the basebandprocessing on the battery-operated Ues. To this end, the vector of K symbols ^ = is constructed such that ^^includes the bits, which will be sent to thesecond UE and so on. Then, the vector of transmit signals, vector ^ in equation (13), willbe generated as ^= ^^ , (14)where ^ is the precoding matrix, which will be defined according to the selectedprecoding scheme. Similar to the MIMO detection presented above, it has been shown that a linearalgorithm may be used in massive MIMO systems to perform precoding (beamforming)while achieving a near-optimal performance. Therefore, the precoding matrix may beobtained using any of matched filtering (MF), zero forcing (ZF) or minimum mean squarederror (MMSE) as follows: ^= ^^^^ , (15) ^^ = ^^(^^^ ^^^^^ + ^^) , (17)where as mentioned before ^ in the downlink path is a ^ × ^ matrix, which is thetransposed version of the uplink channel matrix.Similar to the MIMO detection, the common operations in the precoding schemes inequations (15), (16), and (17) are matched filtering and Gram matrix computation.Therefore, the above-mentioned precoding schemes may be realized using the proposedPIM-based architecture disclosed above. It is worth to mention that the required matrix inversion in the ZF and MMSEalgorithms may be realized by iterative methods like Neumann series, which are based onsuccessive matrix multiplications. These methods are well-known in the literature. In a next action, the precoded signals may be modulated using an OFDM scheme,which transfers the frequency-domain signals to the corresponding time-domain signals.The OFDM modulation may be realized using inverse discrete Fourier transform (IDFT).Thus, for each processing chain in Figure 9, the modulation action may be done using acrossbar array, which performs the multiplication of the input samples by the matrix of IDFT coefficients, ^^^^^^^ = ^^^^^(^) , (18)where ^^^^^^^is the vector of time-domain analog signals, corresponding to each processing chain of Figure 9. The vector of time-domain analog signals will then be filtered. The filter frequencyresponse, ^^^^^^^(⋅), may be specified according to the targeted system configuration. Asmentioned before, the filtering operation will be converted to a matrix-vector multiplication, and the filter coefficients will be programmed to the memristors of the correspondingcrossbar array. The output signals of the filter,^^^^^^^^^ = ^^^^^^^(^^^^^^^) , (19)will be generated in parallel and sent to the Ues through the downlink path.It is worth to point out that, most of the wireless communication standards employchannel coding and interleaving schemes to improve the communication performance. Asshown in Figure 4c, the information bits may be interleaved and encoded using theinterleaver 412 and the channel encoder 411, respectively at the transmitter side. At thereceiver side, the detected bits may be de-interleaved and decoded using the de-interleaver 422 and the channel decoder 421, respectively to extract the transmitted bitsby the transmitter. These operations may be considered as matrix-vector multiplications,which may be implemented using crossbar arrays as described above.Similar to the uplink processing, the output signals of different blocks in the proposed PIM-based downlink processing may be generated in parallel. However, thesettings of each functional block, such as the filter 401 or the OFDM modulator 414 maybe adjusted flexibly depending on the system configuration, channel conditions,application requirements, etc. So far, all the above-mentioned algorithms have been described as realized in theanalog domain, which means that there is no need for ADCs and DACs. However, for any reason, it is possible to perform the processing of a specific block(s) in the digital domainby converting the input and output signals of those blocks to digital and analog domain,respectively. In this way, the baseband processor may be realized partially in analog anddigital domains. Inter-Block Optimization The proposed PIM-based baseband processor provides the opportunity of doingoptimization between different blocks within the processing chains in Figures 4c and 4d.This is due to the fact that, in this scheme all the computations are done through matrix- vector multiplications by using the crossbar arrays. Thus, in some cases it is possible to either (1) “combine two (or even more)operations and perform them at once” or (2) “optimize the computation of a certainoperation based on the output of the previous function by adjusting the corresponding values to be programmed into the memristors”. ^An example of the first case is to perform FFT / IFFT together with the samplereordering at once. So, by employing the memristive-based FFT / IFFT there is no need for a separate reordering circuit to sort the output samples of the FFT / IFFT.To this end, the “matrix of FFT / IFFT coefficients” may be combined with the“reordering matrix” and then the entries of the combined matrix may be programmed to a single crossbar array to perform both FFT / IFFT and reordering. ^An example of the second case is joint detection and decoding. In the traditionalreceiver design, detection and decoding are done separately / independently to simplify the whole procedure of receiving data. However, this simplification resultsin performance degradation. By adopting joint detection and decoding, in which soft information is exchanged between the detector and the channel decoder, the performance may be improved. As a result, by providing the extrinsic informationof coded bits (i.e., the likelihood messages), the detector may explore thecorrelation of information bits in a code word and improve its decision based on the knowledge of inter-dependencies of the code word. The implementation of thisidea using the traditional hardware platforms is challenging. But, the proposed memristive-based baseband signal processor 400 enables to realize jointdetection and decoding by adjusting the entries of channel coding matrix andreprogram the corresponding crossbar array accordingly. Figure 10a schematically illustrates a wireless communications device 513,comprising an electronic device, such as the transmitter 410, or the receiver 420 or atransceiver. Thus, the wireless communications device 513 comprises the basebandsignal processor 400 described above. The wireless communications device 513 may bea User Equipment. In Figure 10a the wireless communications device 513 communicateswirelessly with the network node 511. In short, the above description of the different baseband functions are also valid for the wireless communications device 513. Figure 10b illustrates further details of the different functional blocks of the wirelesscommunications device 513. These functional blocks have all been described above whendescribing the baseband signal processor 400 and the network node 513.Figure 11 illustrates a flowchart of a method for filtering wireless communicationssignals according to embodiments herein. The baseband signal processor 400 has beendescribed above in relation to Figures 4a-4d, Figures 5-9 and Figures 10a-10b. Action 1101The method may comprises configuring the memristive devices of the crossbararray 310 according to the matrix coefficients, i.e., according to the filter coefficients.Action 1103 The method comprises filtering the wireless communications signals with an analogchannel select filter 401 of the baseband signal processor 400 by using matrix vectormultiplication, wherein the analog channel select filter 401 comprises an analog crossbararray 310 of memristors 311, 312 and wherein each memristor 311, 312 of the analogcrossbar array represents a respective filter coefficient of a filter function implemented asfilter matrix or filter vector.The filtering may comprise any one or more of the following filtering operations: channel selection, self-Interference rejection, out-of-band filtering, decimation filtering, and anti-aliasing filtering. Scalability and flexibility The number of streams to be transmitted and received in the baseband may bechanged depending on the applications, channel conditions, number of UEs, etc. Thus, asize and a number of required crossbars within each processing chain may be changed.Embodiments disclosed herein address this issue by scaling the size of the crossbararrays and activate / de-activate crossbar arrays within the processing chains in Figures 6,9 and 10b.For example, when the number of UEs is reduced the size of the CSI matrix andaccordingly the size of the Gram matrix will be reduced. In such cases, a number ofcrossbar rows and columns may be de-activated since the crossbars will be programmedwith smaller matrices. Moreover, the PIM-based baseband signal processor 400 is fully flexible in terms ofalgorithm type, architecture (i.e., how many antennas and UEs that are supported), andsystem parameters. In other words, in case of any change in bandwidth, frequency spacing, channel coding scheme, detection algorithm, size of OFDM, modulation order,etc. the baseband signal processor 400 may be adapted accordingly. This may be doneby changing the values to be programmed into the memristors of the corresponding crossbar array. Realizing an algorithm using multiple crossbars with different shapes and sizesSometimes a size of a corresponding matrix, which describes a targeted functionwithin the baseband processing chain, is large such that it cannot be programmed to asingle crossbar array. In these cases, the corresponding matrix may be divided intoseveral sub-matrices, which may be programmed to multiple crossbar arrays as detailedin a flowchart depicted in Figure 12 and explained below.If a size of a permutation matrix (K×L) is larger than a size of the crossbar array it may be programmed to ɑ = m×n crossbars, where m = Ceil(L / M) and n =Ceil(K / N). Thus, the targeted matrix, A, may be divided into ɑ sub-matrices, i.e., ^^,^, eachof which has the size of M×N. To this end, the first sub-matrix, ^^,^, is picked up from theupper left corner of the matrix A such that its upper left entry is ^^,^ and its lower rightentry is ^^,^. The next one, ^^,^, is picked up from ^^,^^^to ^^,^^and so on. Asmentioned in the flowchart of Figure 12, if ^ ≠ ^ / ^ or ^ ≠ ^ / ^ the remaining entries of^^,^ may be considered as zero. As a result, ɑ sub-matrices, ^^,^, of size N×M may begenerated, which may be programmed into ɑ crossbar arrays of the same size Tothis end, k-th row of ^^,^is mapped to k-th column of (j, i)-th crossbar array. To clarify this concept, an example of a matrix 1310 of size K=20, L=20 isillustrated in Figure 13a, where it is assumed that the size of crossbar array is M=20,N=4. Thus, the matrix 1310 is divided into ɑ = 5 sub-matrices, i.e.,^^,^, ^^,^, ^^,^, ^^,^, ^^,^ ,which are specified by different fill patterns in Figure 13a.These sub-matrices will be programmed to the corresponding crossbar arrays 1320,which are shown by corresponding fill patterns in Figure 13b. In the presented example in Figure 13a, the size of sub-matrices and consequently the size of crossbars are the same. However, it is possible to map a matrix into multiple crossbars, which have different size and shape. This concept is demonstrated using anexample in Figure 13b, in which a matrix of size 20x20 is mapped into three crossbars ofsize 20x4 and one crossbar of size 20x8. Bit-Serial Inputs In some cases, the output analog signal of either a certain functional block or outputof the entire processing chain may be converted to the digital domain using an ADC block.A supported bit resolution of ADCs determines the quantization error; the highersupported bit resolution the lower the quantization error and hence the betterperformance. Therefore, in case that either the ADCs 305 do not support the requiredresolution or in order to improve the performance for a certain functional block, each inputsample, which is a binary word, may be sent to the DACs 304 in a bit-serial manner.Thus, at each time instance, which corresponds to the read cycle of the crossbar array,one bit of all input binary-words is applied to the corresponding DACs 304.The i-th bit of j-th input and output words are shown by ^^^and ^^^, respectively..Therefore, after W read cycles, the computation is completed where W is the number ofbits per input binary-word (input sample). In order to calculate the final result in the bit-serial scheme, multiple “Shift and Add” circuits may be used after the ADCs 305 for eachcrossbar column. Thus, for the bit-serial adapted method, “Shift and Add” circuits may be used to calculate the final results of each crossbar column. Thus, the baseband signal processor400 may further comprise one or more digital shift and add circuits 1440 connected toa respective output of the one or more ADCs 305 in Figure 14. In other words, thebaseband signal processor 400 may further comprise a respective digital shift and addcircuit 1440 after the ADCs 305 for each output conductor.A bit-serial example will be given now. In the example the baseband signalprocessor 400 comprises a crossbar array with 3 rows and one column programmed byC1, C2, C3. The inputs are represented by two bits. In this example, in the first read cycle one bit of the inputs enter to thecorresponding row and the resulting first output from the column is Out1 = (0 / 1)xC1 +(0 / 1)xC2 + (0 / 1)xC3. In the second cycle, the second bit of inputs enter, and the resultingsecond output from the column is Out2 = (0 / 1)xC1 + (0 / 1)xC2 + (0 / 1)xC3.So far, the mentioned computations were done by the memristors. The final result isOut1 + 2xOut2. This computation is performed by adding and shifting, for example by theone or more digital shift and add circuits 1440. In this specific example, one shift and addcircuit is enough since the crossbar has only one column. In general, one shift and addcircuit per column may be needed unless they are time multiplexed between multiplecolumns to reduce the hardware cost. Note that the second output is multiplied by twobecause the second bit-position of a binary word has twice weight as the first bit-position (LSB). Baseband Processor with Word Slicing Scheme In order to improve the performance of the baseband processor 400 and / or to reduce the hardware cost by using simpler and cheaper memristive devices, it is possible to assign more than one memristor to every coefficient / parameter. To this end, each entryof a matrix, which corresponds to a coefficient / parameter of the target function / algorithm,may be divided into multiple parts. Then, each part of the coefficient / parameter may beprogrammed to a separate device. Thus, each entry of the target matrix will be mappedinto multiple devices in a crossbar row. For example, let’s consider the precoding block, where each entry of a precodingmatrix is represented by 8 bits, i.e., ^^ = ^^^^^^^^^^^^^^^^^^^^^^^^. Similar to as explainedabove, a precoding weight ^^ is programmed into one memristor. However, in thecoefficient slicing scenario, the precoding weight ^^is programmed into more than one memristor. Assuming two memristors per coefficient, ^^^^^^^^^^^^is programmed to one memristor and ^^^^^^^^^^^^ will be programmed to a second memristor.It is worth to mention that similar to the bit-serial input scenario, a “Shift & Add”block is employed to calculate the output samples of the precoder by combining the outputs of the corresponding crossbar columns. The flexibility of embodiments herein provide the opportunity to employ differenttypes of algorithms like different channel coding scheme and detection algorithms.Embodiments may be employed to implement processing blocks of any wireless communication system including 5G and beyond 5G systems. Figure 15 illustrates further optional details of the network node 511. Figure 16illustrates further optional details of the wireless device 513. The network node 511 andthe wireless device 513 are configured to perform the method actions of Figure 11 above.The embodiments herein may be implemented through a processor or one ormore processors, such as the processor 1504, 1604 of a processing circuitry in thenetwork node 511 and the wireless device 513 respectively, and depicted in Figure 15and 16 together with computer program code for performing the functions and actions ofthe embodiments herein. The program code mentioned above may also be provided as a computer program product, for instance in the form of a data carrier carrying computerprogram code for performing the embodiments herein when being loaded into the networknode 511 and the wireless device 513 respectively. One such carrier may be in the formof a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on aserver and downloaded to the network node 511 and the wireless device 513 respectively.The network node 511 and the wireless device 513 respectively may furthercomprise a memory 1502, 1602 comprising one or more memory units. The memorycomprises instructions executable by the processor in the network node 511 and thewireless device 513 respectively. The respective memory 1502, 1602 is arranged to be used to store e.g. information,data, configurations, and applications to perform the methods herein when beingexecuted in the network node 511 and the wireless device 513 respectively.In some embodiments, a computer program 1503, 1603 comprises instructions,which when executed by the at least one processor, cause the at least one processor ofthe network node 511 and the wireless device 513 respectively to perform the actionsabove. In some embodiments, a carrier 1505, 1605 comprises the computer program,wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium. The network node 511 and the wireless device 513 respectively may furthercomprise an input and output interface, I / O, 1506, 1606 configured to communicate withother devices. The input and output interface 1506, 1606 may comprise a receiver, suchas a wireless receiver, (not shown) and a transmitter, such as a wireless transmitter, (not shown). Those skilled in the art will also appreciate that the units described above may refer to a combination of analog and digital circuits, and / or one or more processors configuredwith software and / or firmware, e.g. stored in the network node 511 and the wirelessdevice 513 respectively, that when executed by the respective one or more processors such as the processors described above. One or more of these processors, as well as the other digital hardware, may be included in a single Application-Specific Integrated Circuitry (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).Figure 15 illustrates a wireless communications network 170 in whichembodiments herein may be implemented. The wireless communications network 170 may use a number of differenttechnologies, such as Wi-Fi, Long Term Evolution (LTE), LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile communications / enhanced Data rate for GSM Evolution (GSM / EDGE), Worldwide Interoperability for Microwave Access (WiMax), or Ultra Mobile Broadband (UMB), just to mention a few possible implementations. Embodiments herein relate to recent technology trends that are of particular interest in a 5G context. However, embodiments are also applicable in further development of other existing wireless communication systems such as e.g. WCDMA and LTE and in future wireless communication systems, such as 6G systems. Network nodes operate in the wireless communications network 170 such as thenetwork node 511. The network node 511 provides radio coverage over a geographicalarea, a service area referred to as a cell 15, which may also be referred to as a beam or a beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi or similar.There may be more than one cell. For example, there may be a second cell 16 as well.The network node 511 may be a NR-RAN node, transmission and reception point e.g. abase station, a radio access node such as a Wireless Local Area Network (WLAN) access point or an Access Point Station (AP STA), an access controller, a base station, e.g. a radio base station such as a NodeB, an evolved Node B (eNB, eNode B), a gNB, a base transceiver station, a radio remote unit, an Access Point Base Station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point or any other network unit capable of communicating with a wireless device within the servicearea depending e.g. on the radio access technology and terminology used. Therespective network node 511 may be referred to as a serving radio access node andcommunicates with a UE with Downlink (DL) transmissions to the UE and Uplink (UL) transmissions from the UE. A number of wireless communications devices operate in the wireless communication network 10, such as the wireless communications device 513. The wireless communications device 12 may be a mobile station, a non-accesspoint (non-AP) STA, a STA, a user equipment and / or a wireless terminal, that communicate via one or more Access Networks (AN), e.g. RAN, e.g. via the network node511 to one or more core networks (CN) e.g. comprising a CN node 13, for examplecomprising an Access Management Function (AMF). It should be understood by the skilled in the art that “UE” is a non-limiting term which means any terminal, wireless communication terminal, user equipment, Machine Type Communication (MTC) device, Device to Device (D2D) terminal, or node e.g. smart phone, laptop, mobile phone, sensor, relay, mobile tablets or even a small base station communicating within a cell. When using the word "comprise" or “comprising” it shall be interpreted as non- limiting, i.e. meaning "consist at least of". The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used.

Claims

CLAIMS1. A baseband signal processor (400) for wireless communications signals, thebaseband signal processor (400) comprising:an analog channel select filter (401) for filtering the wireless communications signals, wherein the analog channel select filter (401) comprises: an analog crossbar array (310) of memristors (311, 312) wherein each memristor (311, 312) of the analog crossbar array is configured to represent a respective filter coefficient of a filter function implemented as a filter matrix.

2. The baseband signal processor (400) of claim 1, wherein the analog channel selectfilter (401) is adapted to be operatively coupled to an analog electronic circuit (402, 403) without analog to digital conversion or digital to analog conversion.

3. The baseband signal processor (400) of claim 2, wherein the analog electronic circuitis an analog RF circuit (403) for wireless transmission or reception or both of the wireless communications signals.

4. The baseband signal processor (400) of claim 2 or 3, wherein the analog electroniccircuit is an analog baseband signal-processing circuit (402) comprised in the baseband signal processor (400).

5. The baseband signal processor (400) of any of the claims 1-4, wherein the channelselect filter (401) is adapted to perform any one or more of the following filtering operations: channel selection, self-Interference rejection, out-of-band filtering, decimation filtering, and anti-aliasing filtering.

6. The baseband signal processor (400) of claim 5, wherein a respective one of the oneor more filtering operations is implemented as matrix vector multiplication.

7. The baseband signal processor (400) of any of the claims 4-6, wherein the analogbaseband signal-processing circuit (402) comprised in the baseband signal processor(400) is any one or more of: an encoder (411) or a decoder (421), an interleaver (412) or a de-interleaver (422),a Multiple Input Multiple Output, MIMO, precoder (413) or a MIMO detector(423), achannel estimator (425),or acircuit for discrete Fourier-related transforms (414, 424),and wherein the analog baseband signal-processing circuit (402) comprises a furtheranalog crossbar array of memristors.

8. An electronic device (410, 420) for transmitting or receiving wireless communicationssignals or both, the electronic device (410, 420) comprising the baseband signalprocessor (400) of any of the claims 1-7.

9. The electronic device (410, 420) according to claim 8, further comprising an analogRF circuit (403) for wireless transmission or reception or both of the wireless communications signals, wherein the analog RF circuit (403) is operatively coupled to the analog channel select filter (401) of the baseband signal processor (400).

10. The electronic device (410, 420) according to claims 8 or 9, wherein the analog RFcircuit (403) is directly coupled to the analog channel select filter (401) of the baseband signal processor (400).

11. A network node (511) of a wireless communications network (170), the network node(511) comprising the electronic device (410, 420) of any of the claims 8-10.

12. A wireless communications device (513), comprising the electronic device (410, 420)of any of the claims 8-10.

13. The wireless communications device (513) according to claim 12, wherein thewireless communications device (513) is a User Equipment.

14. A method for filtering wireless communications signals with a baseband signalprocessor (400), the method comprising: filtering (1103) the wireless communications signals with an analog channelselect filter (401) of the baseband signal processor (400) by using matrix vector multiplication, wherein the analog channel select filter (401) comprises an analogcrossbar array (310) of memristors (311, 312) and wherein each memristor (311, 312) of the analog crossbar array represents a respective filter coefficient of a filter function implemented as filter matrix.

15. The method of claim 14, wherein filtering comprises any one or more of the followingfiltering operations: channel selection, self-Interference rejection, out-of-band filtering, decimation filtering, and anti-aliasing filtering.

16. A computer program (1403), comprising computer readable code units which whenexecuted on a computer causes the computer to perform the method according to anyone of claims 14-15.

17. A carrier (1405) comprising the computer program according to the preceding claim,wherein the carrier (1405) is one of an electronic signal, an optical signal, a radio signal and a computer readable medium.

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