Storage device, imaging device, and method for inspecting storage device

Abstract

The present invention enables inspection of the writing of One Time Programmable (OTP) memory.　A storage device includes: a memory cell array in which OTP cells are disposed; a bit line which is connected to a first OTP cell in which a first logical value is stored and a second OTP cell in which a first logical value or a second logical value is stored; and a word line which is connected to the first OTP cell and a third OTP cell in which a first logical value or a second logical value is stored. The storage device may further include: a first decoder for decoding the address of the first OTP cell; and a second decoder for decoding the address of the second OTP cell and the third OTP cell.

Description

Storage device, imaging device, and storage device inspection method

[0001] The present technology relates to a memory device, an imaging device, and a method for testing a memory device, and more particularly to a memory device provided with an OTP (One Time Programmable) cell, an imaging device, and a method for testing a memory device.

[0002] OTP memories are sometimes used as nonvolatile semiconductor memory devices that can be written to only once. For example, semiconductor memory devices have been disclosed in which a redundant fuse circuit includes a metal or polysilicon fuse element that is blown by a laser, an antifuse that is made conductive by applying an excess gate voltage to a transistor, an OTP cell, a flash memory cell, or the like (see, for example, Patent Document 1).

[0003] JP 2016-152050 A

[0004] However, in the above-mentioned conventional technology, since the OTP memory can be written only once, it is not possible to perform a screening test that guarantees operation after writing.

[0005] This technology was developed in light of these circumstances, and aims to enable write inspection of OTP memories.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a storage device including: a memory cell array in which OTP (One Time Programmable) cells are arranged; bit lines connected to a first OTP cell in which a first logical value is stored and a second OTP cell in which the first logical value or a second logical value is stored; and word lines connected to the first OTP cell and a third OTP cell in which the first logical value or the second logical value is stored. This brings about an effect that a write check of the OTP memory is performed based on writing to the first OTP cell without writing to the second OTP cell and the third OTP cell.

[0007] In the first aspect, the memory device may further include a first decoder for decoding the address of the first OTP cell and a second decoder for decoding the addresses of the second OTP cell and the third OTP cell, thereby providing an effect that write positions of the first OTP cell, the second OTP cell, and the third OTP cell are specified.

[0008] In the first aspect, the first logic value may be written to the second OTP cell and the third OTP cell based on the decoded result of the second decoder, thereby providing an effect that the writing to the second OTP cell and the third OTP cell is performed.

[0009] In the first aspect, a test mode may be provided in which the first logic value is read from the first OTP cell when the second logic value is stored in the second OTP cell and the third OTP cell, thereby providing an effect that shorts in bit lines and word lines connected to the first OTP cell are checked based on the read test of the first OTP cell.

[0010] In the first aspect, the first OTP cells may be arranged in the row direction and the column direction of the memory cell array, thereby making it possible to easily identify the second OTP cells and the third OTP cells and to perform a write test on the OTP memory.

[0011] In addition, in the first aspect, the first OTP cells and the second OTP cells may be alternately arranged in the column direction of the memory cell array, and the first OTP cells and the third OTP cells may be alternately arranged in the row direction of the memory cell array, thereby providing an effect of detecting shorts in bit lines and word lines.

[0012] In the first aspect, the first OTP cells may be arranged diagonally across the memory cell array, thereby providing an effect that a write test of the OTP memory can be performed while suppressing an increase in test time.

[0013] In the first aspect, the first OTP cells may be randomly arranged in the memory cell array, thereby improving tamper resistance and enabling a write check of the OTP memory to be performed.

[0014] In the first aspect, the first OTP cells may be arranged in all rows and all columns of the memory cell array, thereby providing an effect that all bit lines and all word lines of the memory cell array are inspected for short circuits.

[0015] In addition, in the first aspect, the second OTP cell may be arranged adjacent to the first OTP cell in the column direction, and the third OTP cell may be arranged adjacent to the first OTP cell in the row direction. This brings about an effect that short circuits of bit lines and short circuits of word lines are detected while the first OTP cell is arranged according to the layout of the second OTP cell and the third OTP cell.

[0016] In the first aspect, the memory cell array may include a dummy area in which the first OTP cell is arranged, and a user area in which the second OTP cell and the third OTP cell are arranged, thereby enabling a user to access the user area while hiding the dummy area from the user.

[0017] In the first aspect, the memory device may further include a vendor area in which the OTP cell is arranged, thereby providing an effect that writing by a vendor can be performed.

[0018] In the first aspect, the OTP cell may be of a fuse type, an anti-fuse type, or a hot carrier type, thereby providing an effect that writing to the memory cell can be performed only once.

[0019] A second aspect of the present invention is an imaging device including a pixel array unit in which pixels are arranged, and a memory cell array in which OTP (One Time Programmable) cells are arranged, the memory cell array including bit lines connected to a first OTP cell in which a first logical value is stored and a second OTP cell in which the first logical value or a second logical value is stored, and word lines connected to the first OTP cell and a third OTP cell in which the first logical value or the second logical value is stored. This brings about the effect of performing a write test on an OTP memory provided in the imaging device.

[0020] A third aspect is a method for testing a storage device, comprising the steps of: performing a blank check on a memory cell array in which OTP (One Time Programmable) cells are arranged; writing to some of the OTP cells; reading from the written OTP cells; determining pass / fail based on the read results of the written OTP cells; and prohibiting access to the written OTP cells after the pass / fail determination. This provides the effect of performing a write test on the OTP memory based on writing to some of the OTP cells.

[0021] In addition, in the third aspect, among the OTP cells arranged in the memory cell array, access to unwritten OTP cells may be permitted, thereby bringing about an effect that writing to unwritten OTP cells is possible while enabling inspection of the OTP memory based on writing to some of the OTP cells.

[0022] In the third aspect, in the step of writing to the vendor area where the OTP cells are arranged, writing may be performed to a part of the OTP cells, thereby achieving the effect of inspecting the OTP memory without the need for additional inspection items.

[0023] 1 is a block diagram showing an example of the configuration of a storage device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a storage area according to the first embodiment. FIG. 3 is a sequence diagram showing a method of inspecting a vendor area according to the first embodiment. FIG. 4 is a sequence diagram showing a method of inspecting a dummy area according to the first embodiment. FIG. 5 is a flowchart showing a method of inspecting a vendor area according to the first embodiment. FIG. 6 is a flowchart showing a method of inspecting a user area and a dummy area according to the first embodiment. FIG. 7 is a block diagram showing an example of the arrangement of dummy areas according to a second embodiment. FIG. 8 is a block diagram showing an example of the arrangement of dummy areas according to a third embodiment. FIG. 9 is a block diagram showing an example of the arrangement of dummy areas according to a fourth embodiment. FIG. 10 is a block diagram showing an example of the configuration of an imaging device according to a fifth embodiment. FIG. 11 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fifth embodiment. FIG. 12 is a perspective view showing an example of stacking of pixel array units according to the fifth embodiment. FIG. 13 is a block diagram showing a schematic example of the configuration of a vehicle control system. FIG. 14 is an explanatory diagram showing an example of the installation position of an imaging unit.

[0024] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which a dummy area inaccessible to the user is arranged in a memory cell array in which a user-accessible user area is arranged, and the dummy area is used for inspection) 2. Second embodiment (an example in which dummy areas inaccessible to the user are arranged in the row direction and column direction of the memory cell array) 3. Third embodiment (an example in which dummy areas inaccessible to the user are arranged in the diagonal direction of the memory cell array) 4. Fourth embodiment (an example in which dummy areas inaccessible to the user are arranged randomly in the memory cell array) 5. Fifth embodiment (an example in which a memory device provided with dummy areas in which OTP cells are arranged is applied to an imaging device) 6. Application example to a mobile object

[0025] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a storage device according to a first embodiment.

[0026] In the figure, the memory device 100 is applied to a nonvolatile semiconductor memory device that is writable only once. The memory device 100 has a dummy area used for write verification. The dummy area is located in an area that is inaccessible to the user. At this time, the dummy area is set so that it is inaccessible to the user after the write verification. The dummy area can be located in a user area. The user area is an area that is accessible to the user. A write verification is not performed on the user area. At this time, operation after writing to the user area can be compensated based on the write verification of the dummy area.

[0027] The memory device 100 includes a memory cell array 101, a test column decoder 102, a column decoder 103, a test row decoder 104, a row decoder 105, and a sense amplifier 106.

[0028] In the memory cell array 101, OTP cells MC are arranged in a matrix in the row and column directions. Each OTP cell MC is provided with an OTP element 111. Each OTP element 111 can be written to only once. The OTP element 111 may be a fuse type, an anti-fuse type, or a hot carrier type. Each OTP cell MC stores a first logical value or a second logical value. For example, the first logical value may be 1 and the second logical value may be 0, or the first logical value may be 0 and the second logical value may be 1. In the following explanation, an example in which the first logical value is 1 and the second logical value is 0 is shown.

[0029] The memory cell array 101 is also provided with bit lines BL for selecting the OTP cells MC for each column. The bit lines BL are connected to a test column decoder 102 and a column decoder 103 for each column. The memory cell array 101 is also provided with word lines WL for selecting the OTP cells MC for each row. The word lines WL are connected to a test row decoder 104 and a row decoder 105 for each row.

[0030] Here, the OTP cell MC includes OTP cells MC1, MC2, and MC3. OTP cell MC1 stores a value of 1. OTP cell MC1 is arranged in an area inaccessible to the user. However, OTP cell MC1 is accessible during testing. OTP cell MC1 can be arranged in all rows and all columns of the memory cell array 101. OTP cell MC2 is arranged adjacent to OTP cell MC1 in the column direction. OTP cell MC3 is arranged adjacent to OTP cell MC1 in the row direction. In this case, when testing OTP cell MC1, OTP cells MC2 and MC3 store a value of 0. This allows short-circuit defects of each bit line BL and each word line WL to be detected based on testing of OTP cell MC1. By detecting short-circuit defects of each bit line BL and each word line WL, screening of the memory device 100 can be performed efficiently.

[0031] Each of the OTP cells MC2 and MC3 stores a value of 0 or 1. Each of the OTP cells MC2 and MC3 is arranged in an area accessible to the user. Each of the OTP cells MC2 and MC3 can be shipped to the user with a value of 0 stored in it. This allows the user to access each of the OTP cells MC2 and MC3 and write a value of 1 into any of the OTP cells MC2 and MC3 only once. At this time, a value of 1 may be stored in the position adjacent to the OTP cell MC1 in the column direction and the position adjacent to the OTP cell MC1 in the row direction.

[0032] The test column decoder 102 decodes the test column address. At this time, the test column decoder 102 selects the bit line BL connected to the OTP cell MC1 to be written and read based on the test column address. The test column address is used only for write and read inspection of the OTP cell MC1 and can be made invisible to the user.

[0033] The column decoder 103 decodes the column address. At this time, the column decoder 103 selects the bit line BL connected to the OTP cells MC2 and MC3 to be written to and read from based on the column address. Based on the column address, the user can write to each of the OTP cells MC2 and MC3 only once, or read from each of the OTP cells MC2 and MC3 any number of times.

[0034] The test row decoder 104 decodes the test row address. At this time, the test row decoder 104 selects the word line WL connected to the OTP cell MC1 to be written and read, based on the test row address. The test row address is used only for write and read inspections of the OTP cell MC1, and can be made invisible to the user.

[0035] The row decoder 105 decodes the row address. At this time, the row decoder 105 selects the word line WL connected to the OTP cells MC2 and MC3 to be written to and read from based on the row address. Based on the row address, the user can write to each of the OTP cells MC2 and MC3 only once, or read from each of the OTP cells MC2 and MC3 any number of times.

[0036] Here, the test column address and test row address can specify the OTP cell MC1, and the column address and row address can specify the OTP cells MC2 and MC3.

[0037] The sense amplifier 106 detects the data read from the OTP cell MC. At this time, the sense amplifier 106 can determine the data stored in the OTP cell MC based on the potential of the bit line BL.

[0038] FIG. 2 is a block diagram illustrating an example of the configuration of a storage area according to the first embodiment.

[0039] In the figure, the storage device 100 includes a storage area 110. The storage area 110 includes a vendor area 111, a user area 112, and a dummy area 113. An OTP cell is arranged in the vendor area 111. A vendor can write 1 to the OTP cell in the vendor area 111. The vendor can write 1 arbitrarily in the vendor area 111 and perform an inspection based on the dummy area 113 before shipping the storage device 100 to a user. At this time, the vendor area 111 can be made invisible to the user.

[0040] An area accessible to the user is arranged in the user area 112. In the user area 112, OTP cells MC2 and MC3 can be arranged.

[0041] The dummy area 113 is an area that is inaccessible to users. However, vendors can access the dummy area 113. An OTP cell MC1 can be placed in the dummy area 113. In this case, the memory device 100 can be provided with a test mode in which a 1 is written to the OTP cell MC1 when a 0 is stored in the OTP cell MC1, and a 1 is read from the OTP cell MC1 when a 0 is stored in the OTP cells MC2 and MC3. In this test mode, the dummy area 113 can be set so that it is visible to the vendor. In this case, the vendor can access the dummy area 113 via the test column decoder 102 and the test row decoder 104. The vendor can then perform a write test and a read test on the dummy area 113 and ship the memory device 100 that passes the test to the user. When shipping the memory device 100, the vendor can disable the test column decoder 102 and the test row decoder 104 from accepting test column addresses and test row addresses. This makes it possible to make the dummy area 113 invisible to the user.

[0042] FIG. 3 is a sequence diagram showing a method for inspecting a bender area according to the first embodiment.

[0043] At "a" in the figure, a blank check of the vendor area 111 is performed to check the vendor area 111. This blank check checks whether the vendor area 111 is in an unwritten state. In an unwritten state, 0 is stored in the OTP cell. Therefore, the blank check checks whether 0 is read from the entire area.

[0044] Next, as shown by b in the figure, data is written to the vendor area 111. At this time, 1 is stored in the OTP cell of the vendor area 111 to which the data has been written.

[0045] Next, as shown at c in the figure, a read check is performed from the vendor area 111 in which the data has been written.

[0046] Next, as shown by d in the figure, a read inspection is performed on the unwritten pages of the vendor area 111. Then, a pass / fail judgment of the storage device 100 is performed based on the above inspection results.

[0047] FIG. 4 is a sequence diagram showing a method for inspecting a user area and a dummy area according to the first embodiment.

[0048] In the figure, in the inspection of the user area 112, a blank check of the user area 112 is performed. In this blank check, the unwritten state of the user area 112 is inspected. In the blank check of the user area 112, the user area 112 can be accessed via the column decoder 103 and the row decoder 105. At this time, the vendor can provide a column address and a row address to the storage device 100 to specify the user area 112. An OTP cell can be written to only once. For this reason, in the inspection of the user area 112, only a blank check is performed to enable the user to write to it.

[0049] In the inspection of the dummy area 113, a blank check of the dummy area 113 is performed. In this blank check, the unwritten state of the dummy area 113 is inspected. In the blank check of the dummy area 113, the dummy area 113 can be accessed via the test column decoder 102 and the test row decoder 104. At this time, the vendor can provide a test column address and a test row address to the memory device 100 to specify the dummy area 113. Although an OTP cell can be written to only once, in the inspection of the dummy area 113, the dummy area 113 is invisible to the user, so that a write inspection and a read inspection can be performed.

[0050] Next, as shown by b in the figure, 1 is written to the dummy area 113. At this time, 1 is stored in the OTP cell of the dummy area 113. At this time, no writing is performed to the user area 112. Therefore, 0 is stored in the adjacent positions in the column direction and the adjacent positions in the row direction of the dummy area 113.

[0051] Next, as shown in c in the figure, a read test is performed from the dummy area 113 where 1 has been written. At this time, it is possible to detect shorts in the bit lines and shorts in the word lines of the user area 112. Then, a pass / fail determination of the memory device 100 is performed based on the above test results.

[0052] FIG. 5 is a flowchart showing a method for inspecting a bender area according to the first embodiment.

[0053] In the figure, in the inspection of the vendor area 111, a blank check of the vendor area 111 is carried out (S111).

[0054] Next, 1 is written into the OTP cell based on the data written in the vendor area 111 (S112).

[0055] Next, the data is read from the vendor area 111 in which the data has been written (S113).

[0056] Next, a read check is performed on unwritten pages in the vendor area 111 (S114).

[0057] Next, a pass / fail judgment of the storage device 100 is made based on the above inspection results (S115).

[0058] FIG. 6 is a flowchart showing the method for inspecting a dummy area according to the first embodiment.

[0059] In the figure, in the inspection of the dummy area 113, a blank check of the dummy area 113 is carried out (S121).

[0060] Next, 1 is written to the dummy area 113 (S122). At this time, 1 is stored in all the OTP cells of the dummy area 113. At this time, writing to the dummy area 113 can be performed in the writing process of the vendor area 111. This makes it possible to perform a write inspection of the OTP memory without needing to add an inspection item.

[0061] Next, a read inspection is carried out on the dummy area 113 in which 1 has been written (S123).

[0062] Next, a pass / fail judgment of the storage device 100 is made based on the above inspection results (S124).

[0063] Next, access to the dummy area 113 of the storage device 100 for which the pass / fail judgment has been carried out is prohibited (S125). At this time, access to the user area 112 of the storage device 100 for which the pass / fail judgment has been carried out is permitted.

[0064] As described above, in the first embodiment, the dummy area 113 that is inaccessible to the user is arranged in the memory cell array 101 in which the user-accessible user area 112 is arranged, and the dummy area 113 is used for testing. This makes it possible to perform a write test on the OTP memory based on the write to the dummy area 113 without writing to the user area 112. This makes it possible to reduce read failures after the user writes to the OTP memory.

[0065] 2. Second Embodiment In the first embodiment described above, a dummy area 113 inaccessible to the user is arranged in the memory cell array 101 in which a user-accessible user area 112 is arranged, and the dummy area 113 is used for testing. In this second embodiment, the dummy areas inaccessible to the user are arranged in the row and column directions of the memory cell array.

[0066] 7 is a block diagram showing an example of the arrangement of dummy areas according to the second embodiment, which shows the state before writing to the user area 112A.

[0067] In the figure, a memory device 200 includes a memory cell array 101A, a test column decoder 102A, a column decoder 103A, a test row decoder 104A, a row decoder 105A, and a sense amplifier 106.

[0068] The memory cell array 101A is arranged with a user area 112A, a dummy area 113A, and an unused area 114A. OTP cells MC are arranged in an array in the user area 112A. In this case, the OTP cells MC can be arranged regularly in the row and column directions in the user area 112A. The user can freely write data to the user area 112A after inspecting the dummy area 113A. An OTP cell MC1 is provided in the dummy area 113A. An OTP cell MC4 is provided in the unused area 114A. A 0 is stored in the OTP cell MC4, and writing is not performed. The unused area 114A can be made invisible to the user. In this case, the OTP cell MC4 can be arranged in an area that cannot be accessed. The dummy area 113A and the unused area 114A are arranged alternately in the row and column directions of the memory cell array 101A. In this case, the dummy areas 113A and unused areas 114A can be provided in two rows and two columns. Therefore, OTP cells MC1 can be arranged in all rows and all columns of the memory cell array 101A. Furthermore, OTP cells MC4, in which 0 is stored, are arranged adjacent to each OTP cell MC1 in the column direction and in the row direction. Therefore, by performing a write test and a read test on the OTP cells MC1, it is possible to test for shorts in all bit lines and all word lines of the memory cell array 101A.

[0069] The test column decoder 102A selects the bit line BL connected to the OTP cell MC1 in the dummy area 113A to be written and read, based on the test column address. The test column address is used only for write and read inspection of the OTP cell MC1 in the dummy area 113A, and can be made invisible to the user.

[0070] The column decoder 103A selects, based on a column address, a bit line BL connected to an OTP cell MC in the user area 112A to be written or read from. Based on the column address, a user can write to the OTP cell MC in the user area 112A only once, or read from the OTP cell MC in the user area 112A any number of times.

[0071] The test row decoder 104A selects a word line WL connected to the OTP cell MC1 in the dummy area 113A to be written and read, based on the test row address. The test row address is used only for write and read inspections of the OTP cell MC1 in the dummy area 113A, and can be made invisible to the user.

[0072] The row decoder 105A selects, based on a row address, a word line WL connected to an OTP cell MC in the user area 112A to be written or read from. Based on the row address, a user can write to the OTP cell MC in the user area 112A only once, or read from the OTP cell MC in the user area 112A any number of times.

[0073] As described above, in the second embodiment, the dummy areas 113A and unused areas 114A that are inaccessible to the user are alternately arranged in the row and column directions of the memory cell array 101A. This makes it possible to perform a write check of the OTP memory based on the write to the dummy areas 113A without writing to the user areas 112A, and also makes it easier to specify the user areas 112A. This makes it possible to reduce read failures after the user writes to the OTP memory, while eliminating the need for special control of the user areas 112A.

[0074] 3. Third Embodiment In the second embodiment described above, the dummy areas 113A that are inaccessible to the user are arranged in the row and column directions of the memory cell array 101A. In this third embodiment, the dummy areas that are inaccessible to the user are arranged in the diagonal directions of the memory cell array.

[0075] 8 is a block diagram showing an example of the arrangement of dummy areas according to the third embodiment, which shows the state before writing to the user area 112B.

[0076] In the figure, a memory device 300 includes a memory cell array 101B, a test column decoder 102B, a column decoder 103B, a test row decoder 104B, a row decoder 105B, and a sense amplifier 106.

[0077] The memory cell array 101B is arranged with a user area 112B and a dummy area 113B. OTP cells MC are arranged in a triangular shape in the user area 112B. The user area 112B can be freely written by the user after testing the dummy area 113B. The dummy area 113B is arranged diagonally across the memory cell array 101B. OTP cells MC1 are provided in the dummy area 113B. Here, the OTP cells MC1 can be arranged diagonally adjacent to each other in one line. In this case, the dummy area 113B can divide the user area 112B into two triangular areas. Therefore, OTP cells MC1 can be arranged in all rows and all columns of the memory cell array 101B. Furthermore, OTP cells MC storing 0 are arranged at positions adjacent to each OTP cell MC1 in the column direction and in the row direction before writing to the user area 112B. Therefore, by performing a write test and a read test on the OTP cell MC1 before writing to the user area 112B, it is possible to check for shorts in all bit lines and all word lines in the memory cell array 101B.

[0078] In the arrangement method of the dummy area 113B of the third embodiment, the memory capacity of the dummy area 113B can be reduced by half compared to the arrangement method of the dummy area 113A of the second embodiment described above. Therefore, it is possible to perform an inspection of the OTP memory while suppressing an increase in inspection time.

[0079] The test column decoder 102B selects the bit line BL connected to the OTP cell MC1 in the dummy area 113B to be written and read, based on the test column address. The test column address is used only for write and read inspection of the OTP cell MC1 in the dummy area 113B, and can be made invisible to the user.

[0080] The column decoder 103B selects, based on a column address, a bit line BL connected to an OTP cell MC in the user area 112B to be written or read from. Based on the column address, a user can write to the OTP cell MC in the user area 112B only once, or read from the OTP cell MC in the user area 112B any number of times.

[0081] The test row decoder 104B selects a word line WL connected to the OTP cell MC1 in the dummy area 113B to be written and read, based on the test row address. The test row address is used only for write and read inspections of the OTP cell MC1 in the dummy area 113B, and can be made invisible to the user.

[0082] The row decoder 105B selects, based on a row address, a word line WL connected to an OTP cell MC in the user area 112B to be written or read from. Based on the row address, a user can write to the OTP cell MC in the user area 112B only once, or read from the OTP cell MC in the user area 112B any number of times.

[0083] In this way, in the third embodiment described above, the dummy areas 113B that are inaccessible to the user are arranged diagonally across the memory cell array. This makes it possible to perform a write inspection of the OTP memory while suppressing an increase in the capacity of the dummy areas 113B. Therefore, it is possible to suppress an increase in inspection time and reduce read failures after the user writes to the OTP memory.

[0084] 4. Fourth Embodiment In the second embodiment described above, the dummy areas 113A that are inaccessible to the user are arranged in the row and column directions of the memory cell array 101A. In this fourth embodiment, the dummy areas that are inaccessible to the user are arranged randomly in the memory cell array.

[0085] 9 is a block diagram showing an example of the arrangement of dummy areas according to the fourth embodiment, which shows the state before writing to the user area 112C.

[0086] In the figure, a memory device 400 includes a memory cell array 101C, a test column decoder 102C, a column decoder 103C, a test row decoder 104C, a row decoder 105C, and a sense amplifier 106.

[0087] The memory cell array 101C is provided with a user area 112C and a dummy area 113C. An OTP cell MC is arranged in the user area 112C. In this case, the user area 112C can be arranged in a position other than the dummy area 113C. The user can freely write data to the user area 112C after inspecting the dummy area 113C. The dummy area 113C is arranged randomly in the memory cell array 101C. However, the dummy areas 113C can be arranged in all rows and all columns so as not to be adjacent to each other in the row and column directions. An OTP cell MC1 is provided in the dummy area 113C. Furthermore, before writing to the user area 112C, an OTP cell MC storing 0 is arranged at an adjacent position in the column direction and an adjacent position in the row direction to each OTP cell MC1. Therefore, by performing a write test and a read test on the OTP cell MC1 before writing to the user area 112C, it is possible to test for shorts in all bit lines and all word lines in the memory cell array 101C.

[0088] In the arrangement method of the dummy area 113C of the fourth embodiment, the memory capacity of the dummy area 113C can be halved compared to the arrangement method of the dummy area 113A of the second embodiment, while the arrangement positions of the dummy area 113C can be randomized. Therefore, it is possible to perform an inspection of the OTP memory while suppressing an increase in inspection time, and it is possible to improve tamper resistance.

[0089] The test column decoder 102C selects the bit line BL connected to the OTP cell MC1 in the dummy area 113C to be written and read, based on the test column address. The test column address is used only for write and read inspection of the OTP cell MC1 in the dummy area 113C, and can be made invisible to the user.

[0090] The column decoder 103C selects the bit line BL connected to the OTP cell MC in the user area 112C to be written or read, based on the column address. Based on the column address, the user can write to the OTP cell MC in the user area 112C only once, or read from the OTP cell MC in the user area 112C any number of times.

[0091] The test row decoder 104C selects a word line WL connected to the OTP cell MC1 in the dummy area 113C to be written and read, based on the test row address. The test row address is used only for write and read inspections of the OTP cell MC1 in the dummy area 113C, and can be made invisible to the user.

[0092] The row decoder 105C selects, based on the row address, a word line WL connected to the OTP cell MC in the user area 112C to be written or read from. Based on the row address, the user can write to the OTP cell MC in the user area 112C only once, or read from the OTP cell MC in the user area 112C any number of times.

[0093] In this way, in the fourth embodiment described above, the dummy areas 113C that are inaccessible to the user are randomly arranged in the memory cell array 101C, which makes it possible to perform a write check on the OTP memory while suppressing an increase in the capacity of the dummy areas 113C, and also improves tamper resistance.

[0094] 5. Fifth Embodiment In the first embodiment described above, the dummy area 113 that is inaccessible to the user is arranged in the memory cell array 101 in which the user-accessible user area 112 is arranged. In this fifth embodiment, the memory device 100 provided with the dummy area in which the OTP cell MC1 is arranged is applied to an imaging device.

[0095] In the following embodiment, an example is shown in which the storage device 100 of the first embodiment is applied to an imaging device. However, any of the storage devices 200 to 400 of the second to fourth embodiments may also be applied to an imaging device.

[0096] FIG. 10 is a block diagram showing an example of the configuration of an imaging apparatus according to the fifth embodiment.

[0097] In the figure, the imaging device 500 includes an optical system 501, a solid-state imaging device 502, an imaging control unit 503, an image processing unit 504, a storage unit 505, a display unit 506, and an operation unit 507. The imaging control unit 503, the image processing unit 504, the storage unit 505, the display unit 506, and the operation unit 507 are connected to one another via a bus 508. The imaging device 500 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0098] The optical system 501 causes light from a subject to be incident on the solid-state imaging device 502, and forms an optical image on the light-receiving surface of the solid-state imaging device 502. The optical system 501 may include, for example, a focus lens, a zoom lens, an aperture, etc. The optical system 501 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0099] The solid-state imaging device 502 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 502 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 502 may be a lateral overflow integration capacitor (LOFIC) type CMOS image sensor, or may be a charge domain global shutter type or a voltage domain global shutter type.

[0100] The imaging control unit 503 controls imaging by the solid-state imaging device 502 based on instructions from the operation unit 507. At this time, the imaging control unit 503 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 502.

[0101] The image processing unit 504 performs image processing based on the output from the solid-state imaging device 502. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 504 may include a processor that executes processing based on software.

[0102] The storage unit 505 stores images captured by the solid-state imaging device 502, as well as imaging parameters of the solid-state imaging device 502. The storage unit 505 can also store a program that operates the imaging device 500 based on software. The storage unit 505 may include a read-only memory (ROM), a random access memory (RAM), and a memory card. In this case, the storage unit 505 may include the storage device 100. The storage device 100 may store, for example, trimming data and type data of the solid-state imaging device 502.

[0103] The display unit 506 displays captured images and various information that supports the image capturing operation, etc. The display unit 506 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0104] The operation unit 507 provides a user interface for operating the imaging device 500. The operation unit 507 may include, for example, buttons, dials, and switches provided on the imaging device 500. The operation unit 507 may be configured as a touch panel together with the display unit 506.

[0105] Depending on the configuration of the imaging device 500, some of the above functions may not be present, or conversely, the imaging device 500 may further include functions that are not disclosed.

[0106] FIG. 11 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fifth embodiment.

[0107] In the figure, the solid-state imaging device 502 includes a pixel array section 511 , a vertical scanning circuit 512 , a column readout circuit 513 , a column signal processing section 514 , a horizontal scanning circuit 515 , and a control circuit 516 .

[0108] The pixel array unit 511 includes a plurality of pixels 520. These pixels 520 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel 520 can form a source follower with the column readout circuit 513 when reading out a signal.

[0109] Each pixel 520 is connected to a horizontal drive line 531 for each row and to a vertical signal line 532 for each column. The horizontal drive line 531 drives each pixel 520 for each row when reading out a signal from each pixel 120. Each vertical signal line 532 transmits a potential based on a current that flows when reading out a signal from each pixel 520 to the column signal processing unit 514 for each column.

[0110] The pixels 520 may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel 520 may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0111] The vertical scanning circuit 512 scans the pixels 520 to be read in the column direction. The vertical scanning circuit 512 may be configured using vertical registers. The vertical scanning circuit 512 may also include a decoder that specifies the pixels 520 to be read.

[0112] The column readout circuit 513 can form a source follower between itself and each pixel 520 when reading out a signal from the pixel 520. At this time, the column readout circuit 513 can change the potential of each vertical signal line 532 based on the charge held in each pixel 520.

[0113] The column signal processing unit 514 processes signals transmitted in the column direction from each pixel 520. For example, the column signal processing unit 514 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 520. The column signal processing unit 514 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 520, and output an imaging signal Gout.

[0114] The column signal processing unit 514 includes a column ADC unit 514A. The column ADC unit 514A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 514A can perform AD conversion for each column based on the result of comparing the pixel signal read from each pixel 520 with a reference signal.

[0115] The horizontal scanning circuit 515 scans the pixels 520 to be read in the row direction. The horizontal scanning circuit 515 may be configured using a horizontal register.

[0116] The control circuit 516 controls the vertical scanning circuit 512, the column readout circuit 513, the column signal processing unit 514, and the horizontal scanning circuit 515. For example, the control circuit 516 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 513, and the processing timing of the column signal processing unit 514. In this case, the control circuit 516 can coordinate the vertical scanning circuit 512, the column readout circuit 513, the column signal processing unit 514, and the horizontal scanning circuit 515 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0117] The control circuit 516 may include the storage device 100. In this case, the control circuit 516 may control the solid-state imaging device 502 based on the data stored in the storage device 100.

[0118] FIG. 12 is a perspective view showing an example of a stack of pixel array units according to the fifth embodiment.

[0119] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0120] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0121] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, an interface 927, a control circuit 928, and a memory device 929 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The memory device 929 may include any of the memory devices 100 to 400 according to the first to fourth embodiments described above.

[0122] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0123] In this way, in the fifth embodiment described above, the memory device 100 provided with a dummy area in which the OTP cells MC are arranged is applied to the imaging device 500. This makes it possible to implement various settings of the imaging device 500 in accordance with the user's usage environment while reducing defects caused by the OTP memory.

[0124] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0125] FIG. 13 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0126] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 13, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0127] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0128] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0129] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0130] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0131] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0132] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0133] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0134] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0135] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 13, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0136] FIG. 14 is a diagram showing an example of the installation position of the imaging unit 12031.

[0137] In FIG. 14, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0138] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0139] 14 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0140] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0141] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0142] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0143] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0144] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and imaging unit 12031 among the above-described configurations. Specifically, for example, each of the storage devices 100 to 400 in the above-described embodiment can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and imaging unit 12031. Applying the technology disclosed herein to the vehicle control system 12000 can reduce defects caused by the OTP memory while implementing various settings of the vehicle control system 12000 to suit the user's usage environment.

[0145] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0146] The present technology can also be configured as follows: (1) A storage device comprising: a memory cell array in which OTP (One Time Programmable) cells are arranged; bit lines connected to a first OTP cell storing a first logical value and a second OTP cell storing the first logical value or a second logical value; and word lines connected to the first OTP cell and a third OTP cell storing the first logical value or the second logical value. (2) The storage device according to (1), further comprising: a first decoder that decodes the address of the first OTP cell; and a second decoder that decodes the addresses of the second OTP cell and the third OTP cell. (3) The storage device according to (1) or (2), in which the first logical value is written to the second OTP cell and the third OTP cell based on a result of decoding by the second decoder. (4) The storage device according to any one of (1) to (3), comprising a test mode in which the first logical value is read from the first OTP cell when the second logical value is stored in the second OTP cell and the third OTP cell. (5) The storage device according to any one of (1) to (4), in which the first OTP cell is arranged in the row direction and the column direction of the memory cell array. (6) The storage device according to (5), in which the first OTP cell and the second OTP cell are arranged alternately in the column direction of the memory cell array, and the first OTP cell and the third OTP cell are arranged alternately in the row direction of the memory cell array. (7) The storage device according to any one of (1) to (4), in which the first OTP cell is arranged diagonally in the memory cell array. (8) The storage device according to any one of (1) to (4), in which the first OTP cell is arranged randomly in the memory cell array. (9) The memory device according to any one of (1) to (7), wherein the first OTP cells are arranged in all rows and all columns of the memory cell array. (10) The memory device according to any one of (1) to (9), wherein the second OTP cells are arranged adjacent to the first OTP cells in the column direction, and the third OTP cells are arranged adjacent to the first OTP cells in the row direction.(11) The storage device according to any one of (1) to (10), wherein the memory cell array includes: a dummy area where the first OTP cell is arranged; and a user area where the second OTP cell and the third OTP cell are arranged. (12) The storage device according to any one of (1) to (11), further including: a vendor area where the OTP cell is arranged. (13) The storage device according to any one of (1) to (12), wherein the OTP cell is of a fuse type, an antifuse type, or a hot carrier type. (14) An imaging device comprising: a pixel array section in which pixels are arranged; and a memory cell array in which OTP (One Time Programmable) cells are arranged, wherein the memory cell array includes: bit lines connected to a first OTP cell in which a first logical value is stored and a second OTP cell in which the first logical value or a second logical value is stored; and word lines connected to the first OTP cell and a third OTP cell in which the first logical value or the second logical value is stored. (15) A method for inspecting a memory device, comprising: a step of performing a blank check on a memory cell array in which OTP (One Time Programmable) cells are arranged; a step of writing to some of the OTP cells; a step of reading from the written OTP cells; a step of making a pass / fail determination based on a read result of the written OTP cells; and a step of prohibiting access to the written OTP cells after making the pass / fail determination. (16) The method for inspecting a memory device according to (15), further comprising: a step of permitting access to unwritten OTP cells among the OTP cells arranged in the memory cell array. (17) The method for inspecting a memory device according to (15) or (16), wherein writing is performed to some of the OTP cells in the step of writing to a vendor area in which OTP cells are arranged.

[0147] 100 Storage device 101 Memory cell array 102 Test column decoder 103 Column decoder 104 Test row decoder 105 Row decoder 106 Sense amplifier 111 OTP element MC1, MC2, MC3 OTP cell BL Bit line WL Word line

Claims

1. A memory device comprising: a memory cell array in which OTP (One Time Programmable) cells are arranged; a bit line connected to a first OTP cell in which a first logical value is stored and a second OTP cell in which the first logical value or a second logical value is stored; and a word line connected to the first OTP cell and a third OTP cell in which the first logical value or the second logical value is stored.

2. The memory device according to claim 1, further comprising: a first decoder for decoding an address of the first OTP cell; and a second decoder for decoding addresses of the second OTP cell and the third OTP cell.

3. The storage device according to claim 1, wherein the first logic value is written to the second OTP cell and the third OTP cell based on a result of the decoding by the second decoder.

4. The memory device according to claim 1, further comprising a test mode for reading out the first logic value from the first OTP cell when the second logic value is stored in the second OTP cell and the third OTP cell.

5. The memory device according to claim 1, wherein the first OTP cells are arranged in the row direction and the column direction of the memory cell array.

6. The memory device according to claim 5, wherein the first OTP cells and the second OTP cells are arranged alternately in the column direction of the memory cell array, and the first OTP cells and the third OTP cells are arranged alternately in the row direction of the memory cell array.

7. The memory device according to claim 1, wherein the first OTP cells are arranged in a diagonal direction of the memory cell array.

8. The memory device according to claim 1, wherein the first OTP cells are randomly arranged in the memory cell array.

9. The memory device according to claim 1, wherein the first OTP cells are arranged in all rows and all columns of the memory cell array.

10. The memory device according to claim 1, wherein the second OTP cell is disposed adjacent to the first OTP cell in the column direction, and the third OTP cell is disposed adjacent to the first OTP cell in the row direction.

11. The memory device according to claim 1, wherein the memory cell array comprises: a dummy area in which the first OTP cell is arranged; and a user area in which the second OTP cell and the third OTP cell are arranged.

12. The memory device according to claim 1, further comprising: a bender area in which the OTP cell is disposed.

13. The memory device according to claim 1, wherein the OTP cell is of a fuse type, an anti-fuse type, or a hot carrier type.

14. An imaging device comprising: a pixel array section in which pixels are arranged; and a memory cell array in which OTP (One Time Programmable) cells are arranged, the memory cell array comprising: a bit line connected to a first OTP cell in which a first logical value is stored and a second OTP cell in which the first logical value or a second logical value is stored; and a word line connected to the first OTP cell and a third OTP cell in which the first logical value or the second logical value is stored.

15. A method for inspecting a memory device, comprising the steps of: performing a blank check of a memory cell array in which OTP (One Time Programmable) cells are arranged; writing to a portion of the OTP cells; reading from the written OTP cells; making a pass / fail decision based on the read result of the written OTP cells; and prohibiting access to the written OTP cells after making the pass / fail decision.

16. The method for testing a memory device according to claim 15, further comprising the step of permitting access to unprogrammed OTP cells among the OTP cells arranged in the memory cell array.

17. The method for testing a memory device according to claim 15, wherein in the step of writing to a bender area in which an OTP cell is arranged, writing is performed on a part of the OTP cell.

Images