Frequency divider circuit, oscillator, and electronic device

Abstract

The present technology allows for stable operation with respect to fluctuations in power supply voltage.　The present technology provides, among other things, a frequency divider circuit comprising at least: a plurality of input terminals, a plurality of output terminals, a first inverter circuit, a second inverter circuit, a third inverter circuit, a fourth inverter circuit, a first latch circuit, a second latch circuit, and a current-controlled bias circuit, wherein the plurality of input terminals, the first to fourth inverter circuits, the first and second latch circuits, and the plurality of output terminals are connected, and the current-controlled bias circuit is connected to the first and second latch circuits and controls a current flowing to a transistor included in each of the first and second latch circuits.

Description

Frequency divider circuits, oscillators, and electronic devices

[0001] The technology according to the present disclosure (hereinafter also referred to as "the technology") relates to a frequency divider circuit, an oscillator, and an electronic device.

[0002] A frequency divider circuit is a circuit that converts a high-frequency signal into a low-frequency signal and is widely used in electronic devices that use high-frequency signals, such as in CMOS image sensors, processing high-frequency received signals in wireless communications, and processing clock signals in processors such as CPUs (Central Processing Units).

[0003] For example, Patent Document 1 discloses a frequency divider circuit including "an inverter having a transistor and an input circuit that converts a first signal, which is an analog differential signal, into a second signal, which is a differential analog signal for driving the transistor."

[0004] International Publication No. 2022 / 209561

[0005] However, the frequency divider circuit disclosed in Patent Document 1 and the like has room for improvement in terms of stable operation against fluctuations in the power supply voltage.

[0006] Therefore, a main object of the present technology is to provide a frequency divider circuit, an oscillator, and an electronic device that can operate stably against fluctuations in power supply voltage.

[0007] The present technology provides a frequency divider circuit including at least a plurality of input terminals, a plurality of output terminals, a first inverter circuit, a second inverter circuit, a third inverter circuit, and a fourth inverter circuit, a first latch circuit and a second latch circuit, and a current control bias circuit, wherein the plurality of input terminals, the first to fourth inverter circuits, the first to second latch circuits, and the plurality of output terminals are connected to each other, and the current control bias circuit is connected to the first to second latch circuits, and controls a current flowing through a transistor included in each of the first to second latch circuits.each of the first to fourth inverter circuits includes: a first transistor which is a p-type MOSFET and has a source connected to a positive power supply voltage; a second transistor which is a p-type MOSFET and has a source connected to the drain of the first transistor; a third transistor which is an n-type MOSFET and has a drain connected to the drain of the second transistor; and a fourth transistor which is an n-type MOSFET and has a drain connected to the source of the third transistor, a source connected to a negative power supply voltage, and a gate connected to the gate of the first transistor; and each of the first to second latch circuits includes: a fifth transistor which is a p-type MOSFET; a sixth transistor which is a p-type MOSFET and has a source connected to the source of the fifth transistor, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor; and a seventh transistor which is an n-type MOSFET and has a drain connected to the drain of the fifth transistor. the current control bias circuit may comprise: a ninth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage; a tenth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a gate connected to the gate of the ninth transistor, and a drain connected to the sources of the fifth and sixth transistors; an eleventh transistor which is an n-type MOSFET and has a source connected to the negative power supply voltage; and a twelfth transistor which is an n-type MOSFET and has a source connected to the negative power supply voltage, a gate connected to the gate of the eleventh transistor, and a drain connected to the sources of the seventh and eighth transistors; the ninth transistor and the tenth transistor form a current mirror circuit; and the eleventh transistor and the twelfth transistor form a current mirror circuit.the plurality of output terminals include a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, the first output terminal is connected to a gate of the first transistor included in the first inverter circuit, a drain of the second transistor included in the fourth inverter circuit, and a drain of the sixth transistor included in the second latch circuit, and outputs a first output signal; the second output terminal is connected to a gate of the first transistor included in the second inverter circuit, a drain of the second transistor included in the third inverter circuit, and a drain of the fifth transistor included in the second latch circuit, and outputs a second output signal that forms a differential signal with the first output signal; the third output terminal is connected to a gate of the first transistor included in the fourth inverter circuit, a drain of the second transistor included in the second inverter circuit, and a drain of the sixth transistor included in the first latch circuit, and outputs a third output signal that is shifted in phase from the first output signal by a predetermined amount; The fourth output terminal may be connected to the gate of the first transistor of the third inverter circuit, the drain of the second transistor of the first inverter circuit, and the drain of the fifth transistor of the first latch circuit, and may output a fourth output signal that forms a differential signal with the third output signal.The latch circuit may further include: a first capacitor connected between the first input terminal and a terminal connected to the gate of the second transistor included in the third inverter circuit and the gate of the second transistor included in the fourth inverter circuit; a second capacitor connected between the first input terminal and a terminal connected to the gate of the third transistor included in the first inverter circuit and the gate of the third transistor included in the second inverter circuit; a third capacitor connected between the second input terminal and a terminal connected to the gate of the second transistor included in the first inverter circuit and the gate of the second transistor included in the second inverter circuit; and a fourth capacitor connected between the second input terminal and a terminal connected to the gate of the third transistor included in the third inverter circuit and the gate of the third transistor included in the fourth inverter circuit. A current flowing through a transistor included in each of the first to second latch circuits may be variable. The frequency divider circuit may further include a transistor serving as a power gate between the source of the fourth transistor and the source of the twelfth transistor and the negative power supply voltage. The predetermined phase may be π / 2. The frequency divider circuit may generate a signal by dividing a signal input from the input terminal by n (n is an integer greater than or equal to 2 and a power of 2), and output the signal from the output terminal. The present technology also provides an oscillator including the frequency divider circuit and a differential sine wave signal generation circuit that supplies a differential sine wave signal to the frequency divider circuit. The present technology also provides an electronic device including the oscillator.

[0008] According to the present technology, stable operation can be achieved even with fluctuations in power supply voltage. Note that the effects described herein are not necessarily limited to those described herein, and may be any of the effects described in this disclosure.

[0009] FIG. 10 is a schematic diagram showing a configuration example of a divider circuit DIV according to an embodiment of the present technology; FIG. 11 is a graph showing an example of a differential signal input to the divider circuit; FIG. 12 is a circuit diagram showing a configuration example of a divider circuit; FIG. 13 is a circuit diagram showing a configuration example of a divider circuit; FIG. 14 is a circuit diagram showing a configuration example of a divider circuit; FIG. 15 is a circuit diagram showing a configuration example of a divider circuit according to an embodiment of the present technology; FIG. 16 is a graph showing characteristics of the divider circuit shown in FIG. 6; FIG. 17 is a graph showing characteristics of the divider circuit shown in FIG. 7; FIG. 18 is a circuit diagram showing a configuration example of a divider circuit according to an embodiment of the present technology; FIG. 19 is a circuit diagram showing a configuration example of an oscillator according to an embodiment of the present technology; FIG. 19 is a block diagram showing a configuration example of an electronic device according to an embodiment of the present technology;

[0010] Hereinafter, preferred embodiments for implementing the present technology will be described with reference to the drawings. Note that the embodiment described below shows an example of a typical embodiment of the present technology, and does not limit the scope of the present technology. In addition, the present technology can be combined with any of the following examples and their modifications.

[0011] In the following description of the embodiments, configurations may be described using terms including "approximately," such as "approximately parallel" and "approximately perpendicular." For example, "approximately parallel" does not only mean completely parallel, but also means substantially parallel, i.e., including a state where the orientation is deviated from the completely parallel state by, for example, a few percent. The same applies to other terms including "approximately." Furthermore, each figure is a schematic diagram and is not necessarily an accurate depiction. The scale of the drawings has been exaggerated to make the features of the technology easier to understand. Therefore, it should be noted that the scale of the drawings and the scale of the actual device are not necessarily the same.

[0012] Unless otherwise specified, in the drawings, "top" means the top or upper side in the drawing, "bottom" means the bottom or lower side in the drawing, "left" means the left or left side in the drawing, and "right" means the right or right side in the drawing. Furthermore, in the drawings, the same or equivalent elements or members are given the same reference numerals, and redundant explanations will be omitted.

[0013] The description will be given in the following order: 1. Frequency Divider Circuit (1) Overview (2) Operation (3) Influence of Fluctuations in Power Supply Voltage 2. First Embodiment of the Present Technology (Example 1 of Frequency Divider Circuit) (1) Configuration (2) Current Control Bias Circuit (3) Capacitor 3. Second Embodiment of the Present Technology (Example 2 of Frequency Divider Circuit) 4. Third Embodiment of the Present Technology (Example of Oscillator) 5. Fourth Embodiment of the Present Technology (Example of Electronic Device)

[0014] [1. Frequency Divider Circuit] [(1) Overview] A frequency divider circuit according to an embodiment of the present technology will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing a configuration example of a frequency divider circuit DIV according to an embodiment of the present technology.

[0015] As shown in FIG. 1, the frequency divider circuit DIV has an input terminal I and an output terminal O. A differential signal represented by an analog sine wave is input from the input terminal I. That is, the original signal is input from one input terminal I, and an opposite-phase signal is input from the other input terminal I. Because differential signals are transmitted using the potential difference between two signals, they are less susceptible to external noise. As a result, signal quality can be maintained even over long transmission distances.

[0016] The frequency divider circuit DIV generates a signal by dividing the frequency of the signal input from the input terminal I by n (n is an integer that is a power of 2 or greater), and outputs the signal from the output terminal O. For example, in the case of a 2 frequency divider, when the frequency of the input signal is Fin [Hz], the frequency of the output signal will be Fin / 2. In this way, the frequency divider circuit DIV converts a high-frequency signal into a low-frequency signal.

[0017] The differential signal input to the frequency divider circuit DIV will be described with reference to Fig. 2. Fig. 2 is a graph showing an example of a differential signal input to the frequency divider circuit. In Fig. 2, the horizontal axis represents the frequency Fin [Hz] of the differential signal, and the vertical axis represents the lower limit Vin_diff [Vp-p] of the amplitude of the differential signal that can be divided by the frequency divider circuit DIV.

[0018] When the power consumed by the circuit preceding this frequency divider circuit DIV is small, the amplitude of the differential signal input to the frequency divider circuit DIV tends to be small. To reduce the power consumption of the device, it is preferable that the frequency divider circuit DIV be able to divide the differential signal even when the amplitude of the differential signal input to the frequency divider circuit DIV is small. In other words, in this graph, the lower limit value Vin_diff of the differential signal amplitude that can be divided by the frequency divider circuit DIV, shown on the vertical axis, is preferably small. The wider the range of input frequencies that the frequency divider circuit DIV can divide, the better.

[0019] [(2) Operation] The operation of the frequency divider circuit will be described with reference to Figures 3 to 5. Figures 3 to 5 are circuit diagrams showing examples of the configuration of the frequency divider circuit.

[0020] 3, the frequency divider circuit includes a plurality of input terminals I1 and I2, a plurality of output terminals O1 to O4, a first inverter circuit 101, a second inverter circuit 102, a third inverter circuit 103, and a fourth inverter circuit 104, a first latch circuit 201, and a second latch circuit 202.

[0021] A plurality of input terminals I1 and I2, first to fourth inverter circuits 101 to 104, first and second latch circuits 201 and 202, and a plurality of output terminals O1 to O4 are connected to each other.

[0022] The first output terminal O1 and the second output terminal O2 each output, for example, a digital operational clock signal Q. The third output terminal O3 and the fourth output terminal O4 each output, for example, a differential clock signal I that is shifted in phase by a predetermined amount from the clock signal Q. For example, when the frequency divider circuit operates as a divide-by-two circuit, the first output terminal O1 and the second output terminal O2 each output the operational clock signals Q+ / Q-. The third output terminal O3 and the fourth output terminal O4 each output the operational clock signals I+ / I- that are shifted in phase by n / 2 from the operational clock signals Q+ / Q-.

[0023] The first to fourth inverter circuits 101 to 104 each include a first transistor M11, M21, M31, and M41, a second transistor M12, M22, M32, and M42, a third transistor M13, M23, M33, and M43, and a fourth transistor M14, M24, M34, and M44.

[0024] The first transistors M11, M21, M31, and M41 are, for example, p-type MOSFETs, and their sources are connected to the positive power supply voltage Vdd.

[0025] The second transistors M12, M22, M32, and M42 are, for example, p-type MOSFETs, and their sources are connected to the drains of the first transistors M11, M21, M31, and M41.

[0026] The third transistors M13, M23, M33, and M43 are, for example, n-type MOSFETs, and their drains are connected to the drains of the second transistors M12, M22, M32, and M42.

[0027] The fourth transistors M14, M24, M34, and M44 are, for example, n-type MOSFETs, and have drains connected to the sources of the third transistors M13, M23, M33, and M43, sources connected to the negative power supply voltage Vss, and gates connected to the gates of the first transistors M11, M21, M31, and M41.

[0028] Each of the first and second latch circuits 201 and 202 includes fifth transistors M15 and M25, sixth transistors M16 and M26, seventh transistors M17 and M27, and eighth transistors M18 and M28.

[0029] The fifth transistors M15 and M25 are, for example, p-type MOSFETs.

[0030] The sixth transistors M16 and M26 are, for example, p-type MOSFETs, with their sources connected to the positive power supply voltage Vdd, their drains connected to the gates of the fifth transistors M15 and M25, and their gates connected to the drains of the fifth transistors M15 and M25.

[0031] The seventh transistors M17 and M27 are, for example, n-type MOSFETs, and their drains are connected to the drains of the fifth transistors M15 and M25.

[0032] The eighth transistors M18 and M28 are, for example, n-type MOSFETs, and have drains connected to the drains of the sixth transistors M16 and M26 and the gates of the seventh transistors M17 and M27, sources connected to the sources of the seventh transistors M17 and M27, and gates connected to the drains of the seventh transistors M17 and M27.

[0033] The first output terminal O1 is connected to the drain of the second transistor M42 and the drain of the third transistor M43 of the fourth inverter circuit 104, the gate of the first transistor M11 and the gate of the fourth transistor M14 of the first inverter circuit 101, and the drain of the sixth transistor M26 and the drain of the eighth transistor M28 of the second latch circuit 202.

[0034] The Q+ signal output from the fourth inverter circuit 104 based on the input Vp- and Vn+ signals is input to the first inverter circuit 101 and the second latch circuit 202, and is output via the first output terminal O1. When the Vp- and Vn+ signals turn off the second transistor M42 and the third transistor M43 of the fourth inverter circuit 104, the Q+ signal held in the second latch circuit 202 is output.

[0035] The second output terminal O2 is connected to the drains of the second transistor M32 and the third transistor M33 of the third inverter circuit 103, the gates of the first transistor M21 and the fourth transistor M24 of the second inverter circuit 102, and the drains of the fifth transistors M15 and M25 and the drains of the seventh transistors M17 and M27 of the second latch circuit 202.

[0036] The Q- signal output from the third inverter circuit 103 based on the input Vp- and Vn+ signals is input to the second inverter circuit 102 and the second latch circuit 202, and is output via the second output terminal O2. When the Vp- and Vn+ signals turn off the second transistor M32 and the third transistor M33 of the third inverter circuit 103, the Q- signal held in the second latch circuit 202 is output.

[0037] The third output terminal O3 is connected to the drain of the second transistor M22 and the drain of the third transistor M23 of the second inverter circuit 102, the gate of the first transistor M41 and the gate of the fourth transistor M44 of the fourth inverter circuit 104, and the drain of the sixth transistor M16 and the drain of the eighth transistor M18 of the first latch circuit 201.

[0038] The I+ signal output from the second inverter circuit 102 based on the input Vp+ and Vn- signals is input to the fourth inverter circuit 104 and the first latch circuit 201, and is output via the third output terminal O3. When the Vp+ and Vn- signals turn off the second transistor M22 and the third transistor M23 of the second inverter circuit 102, the I+ signal held in the first latch circuit 201 is output.

[0039] The fourth output terminal O4 is connected to the drain of the second transistor M12 and the drain of the third transistor M13 in the first inverter circuit 101, the gate of the first transistor M31 and the gate of the fourth transistor M34 in the third inverter circuit 103, and the drain of the fifth transistor M15 and the drain of the seventh transistor M17 in the first latch circuit 201.

[0040] The I+ signal output from the first inverter circuit 101 based on the input Vp+ and Vn- signals is input to the third inverter circuit 103 and the first latch circuit 201, and is output via the fourth output terminal O4. When the Vp+ and Vn- signals turn off the second transistor M12 and the third transistor M13 of the first inverter circuit 101, the I- signal held in the first latch circuit 201 is output.

[0041] The positive and negative power supply voltages may be general power supply voltages Vdd and Vss. The negative power supply voltage Vss may be connected to a ground point.

[0042] The order of the transistors in each inverter circuit is not limited to the above. For example, the second transistor, the first transistor, the fourth transistor, and the third transistor may be connected to the positive power supply voltage Vdd, and the source of the third transistor may be connected to the negative power supply voltage Vss.

[0043] An input signal is applied to the gates of the first transistors M11, M21, M31, and M41 and the gates of the fourth transistors M14, M24, M34, and M44. An output signal is output from the drains of the second transistors M12, M22, M32, and M42 and the drains of the third transistors M13, M23, M33, and M43.

[0044] As an example, in the initial state shown in FIG. 3, the gate of the first transistor M11 of the first inverter circuit 101 is in a low state, the gate of the second transistor M12 is in a low state, the gate of the third transistor M13 is in a high state, and the gate of the fourth transistor M14 is in a low state.

[0045] The gate of the first transistor M21 of the second inverter circuit 102 is in a high state, the gate of the second transistor M22 is in a low state, the gate of the third transistor M23 is in a high state, and the gate of the fourth transistor M24 is in a high state.

[0046] The gate of the first transistor M31 of the third inverter circuit 103 is in a high state, the gate of the second transistor M32 is in a high state, the gate of the third transistor M33 is in a low state, and the gate of the fourth transistor M34 is in a high state.

[0047] The gate of the first transistor M41 of the fourth inverter circuit 104 is in a low state, the gate of the second transistor M42 is in a high state, the gate of the third transistor M43 is in a low state, and the gate of the fourth transistor M44 is in a low state.

[0048] The gates of the fifth transistors M15 and M25 of the first latch circuit 201 and the second latch circuit 202 are in a low state, the gates of the sixth transistors M16 and M26 are in a high state, the gates of the seventh transistors M17 and M27 are in a low state, and the gates of the eighth transistors M18 and M28 are in a high state.

[0049] The first output terminal O1 is in a low state, the second output terminal O2 is in a high state, the third output terminal O3 is in a low state, and the fourth output terminal O4 is in a high state.

[0050] 4 shows the state when the input signal is inverted. In each of the first inverter circuit 101, the second inverter circuit 102, the third inverter circuit 103, and the fourth inverter circuit 104, the states of the gates of the second transistors M12, M22, M32, and M42, which are input sections for the input signal, and the gates of the third transistors M13, M23, M33, and M43, are inverted.

[0051] The gates of the second transistors M12 and M22 in the first inverter circuit 101 and the second inverter circuit 102 are inverted from a low state to a high state. The gates of the third transistors M13 and M23 in the first inverter circuit 101 and the second inverter circuit 102 are inverted from a high state to a low state. The gates of the second transistors M32 and M42 in the third inverter circuit 103 and the fourth inverter circuit 104 are inverted from a high state to a low state. The gates of the third transistors M33 and M43 in the third inverter circuit 103 and the fourth inverter circuit 104 are inverted from a low state to a high state.

[0052] When the gates of these transistors are inverted, the states of the gates and drains of the transistors in the first latch circuit 201 do not change, but the states of the gates and drains of the transistors in the second latch circuit 202 are inverted.

[0053] The gate of the fifth transistor M25 in the second latch circuit 202 is inverted from a low state to a high state. The gate of the sixth transistor M26 in the second latch circuit 202 is inverted from a high state to a low state. The gate of the seventh transistor M27 in the second latch circuit 202 is inverted from a low state to a high state. The gate of the eighth transistor M28 in the second latch circuit 202 is inverted from a high state to a low state.

[0054] Furthermore, with these inversions, the gate of the first transistor M11 in the first inverter circuit 101 inverts from a low state to a high state. The gate of the fourth transistor M14 in the first inverter circuit 101 inverts from a low state to a high state. The gate of the first transistor M21 in the second inverter circuit 102 inverts from a high state to a low state. The gate of the fourth transistor M24 in the second inverter circuit 102 inverts from a high state to a low state.

[0055] Furthermore, in accordance with these reversals, the first output terminal O1 is reverted from a low state to a high state, the second output terminal O2 is reverted from a high state to a low state, and the states of the third output terminal O3 and the fourth output terminal O4 do not change.

[0056] 5 shows the state when the input signal is further inverted. In each of the first inverter circuit 101, the second inverter circuit 102, the third inverter circuit 103, and the fourth inverter circuit 104, the states of the gates of the second transistors M12, M22, M32, and M42, which are input sections for the input signal, and the gates of the third transistors M13, M23, M33, and M43, are inverted.

[0057] The gates of the second transistors M12 and M22 in the first inverter circuit 101 and the second inverter circuit 102 are inverted from a high state to a low state. The gates of the third transistors M13 and M23 in the first inverter circuit 101 and the second inverter circuit 102 are inverted from a low state to a high state. The gates of the second transistors M32 and M42 in the third inverter circuit 103 and the fourth inverter circuit 104 are inverted from a low state to a high state. The gates of the third transistors M3 and M43 in the third inverter circuit 103 and the fourth inverter circuit 104 are inverted from a high state to a low state.

[0058] When the gates of these transistors are inverted, the states of the gates and drains of the transistors in the second latch circuit 202 do not change, but the states of the gates and drains of the transistors in the first latch circuit 201 are inverted.

[0059] The gate of the fifth transistor M15 in the first latch circuit 201 is inverted from a low state to a high state. The gate of the sixth transistor M16 in the first latch circuit 201 is inverted from a high state to a low state. The gate of the seventh transistor M17 in the first latch circuit 201 is inverted from a low state to a high state. The gate of the eighth transistor M18 in the first latch circuit 201 is inverted from a high state to a low state.

[0060] Furthermore, with these inversions, the gate of the first transistor M31 in the third inverter circuit 103 is inverted from a high state to a low state. The gate of the fourth transistor M34 in the third inverter circuit 103 is inverted from a high state to a low state. The gate of the first transistor M41 in the fourth inverter circuit 104 is inverted from a low state to a high state. The gate of the fourth transistor M44 in the fourth inverter circuit 104 is inverted from a low state to a high state.

[0061] Furthermore, in accordance with these reversals, the third output terminal O3 is reverted from a low state to a high state, the fourth output terminal O4 is reverted from a high state to a low state, and the states of the first output terminal O1 and the second output terminal O2 do not change.

[0062] As described above, every time the input signal is inverted, the output terminal that outputs the operational clock signals Q+ / Q- and the output terminal that outputs the operational clock signals I+ / I- are inverted relative to each other.

[0063] (3) Influence of Fluctuations in Power Supply Voltage An example of the configuration of a frequency divider circuit will be described with reference to Fig. 6. Fig. 6 is a circuit diagram showing an example of the configuration of a frequency divider circuit. As shown in Fig. 6, this frequency divider circuit includes a circuit that is significantly affected by fluctuations in the power supply voltage (Vdd and Vss), a circuit that is less affected by fluctuations in the power supply voltage, and a circuit that is not affected by fluctuations in the power supply voltage.

[0064] The first bias circuit 301 superimposes a bias voltage on the input signals from the input terminals I1 and I2. The first bias circuit 301 is a circuit that is not affected by fluctuations in the power supply voltage.

[0065] In the first bias circuit 301, a current from a constant current source is output by a current mirror circuit located on the left side. The gate potential of this current mirror is the same as the gate potential of transistor M116. Therefore, it also forms a current mirror with transistor M116. This output is connected to the positive power supply voltage Vdd via a capacitor. This voltage is converted to an appropriate voltage by diode-connected transistors and superimposed on the AC component output from the input-side capacitor via the corresponding resistors, generating signal Vn.

[0066] The current of the current mirror is further mirrored in the current mirror circuit located in the next stage. After this, the signal Vp is generated by the same operation as that on the Vn side described above.

[0067] The second bias circuit 302 is connected between the current mirror circuit and a transistor that superimposes a DC component on the clock signal. The second bias circuit 302 has transistors M114 and M214 to whose gates positive and negative power supply voltages are applied. These transistors M114 and M214 have drain currents that flow depending on the power supply voltage, so they are significantly affected by fluctuations in the power supply voltage.

[0068] Specifically, the transistor M114 is, for example, a p-type MOSFET, with its source connected to the positive power supply voltage Vdd, its drain connected to the drain of the transistor M116, and its gate connected to the negative power supply voltage Vss. By connecting the gate to the negative power supply voltage Vss, the transistor M114 operates as a diode that allows current to flow in one direction from the source to the drain. The performance of this diode depends on the power supply voltage due to the connection relationship between the source and gate.

[0069] Similarly, transistor M214 is, for example, an n-type MOSFET, with its source connected to the negative power supply voltage Vss, its drain connected to the drain of transistor M216, and its gate connected to the positive power supply voltage Vdd. By connecting its gate to the positive power supply voltage Vdd, transistor M214 operates as a diode that allows current to flow in one direction from the drain to the source. The performance of this diode depends on the power supply voltage due to the connection relationship between the source and gate.

[0070] In this way, by having the second bias circuit 302 that is affected by fluctuations in the power supply voltage, each of the first to fourth inverter circuits 101 to 104 is driven while being slightly affected by fluctuations in the power supply voltage.

[0071] On the other hand, the first and second latch circuits 201 and 202 are each directly connected to the positive power supply voltage Vdd and the negative power supply voltage Vss. Therefore, the first and second latch circuits 201 and 202 are more susceptible to fluctuations in the power supply voltage than the first to fourth inverter circuits 101 to 104. This may cause the operation of the frequency divider circuit to become unstable. In other words, since the first to fourth inverter circuits, which are less susceptible to fluctuations in the power supply voltage, and the first and second latch circuits 201 and 202, which are more susceptible to fluctuations in the power supply voltage, are both mounted on the same circuit, there is room for improvement in terms of stable operation.

[0072] [2. First Embodiment of the Present Technology (Example 1 of Frequency Divider Circuit)] [(1) Configuration] The present technology provides a frequency divider circuit including at least a plurality of input terminals, a plurality of output terminals, a first inverter circuit, a second inverter circuit, a third inverter circuit, and a fourth inverter circuit, a first latch circuit and a second latch circuit, and a current control bias circuit, wherein the plurality of input terminals, the first to fourth inverter circuits, the first to second latch circuits, and the plurality of output terminals are connected, and the current control bias circuit is connected to the first to second latch circuits, and the frequency divider circuit controls a current flowing through a transistor included in each of the first to second latch circuits.

[0073] A frequency divider circuit according to an embodiment of the present technology will be described with reference to Fig. 7. Fig. 7 is a circuit diagram showing an example configuration of a frequency divider circuit according to an embodiment of the present technology.

[0074] As shown in FIG. 7 , the frequency divider circuit according to this embodiment at least includes a plurality of input terminals (a first input terminal I1 and a second input terminal I2), a plurality of output terminals (a first output terminal O1, a second output terminal O2, a third output terminal O3, and a fourth output terminal O4), a plurality of inverter circuits (a first inverter circuit 101, a second inverter circuit 102, a third inverter circuit 103, and a fourth inverter circuit 104), a plurality of latch circuits (a first latch circuit 201 and a second latch circuit 202), and a current control bias circuit 303. Note that the numbers of the input terminals, the output terminals, the inverter circuits, the latch circuits, and the current control bias circuits are not particularly limited.

[0075] The input terminals, the first to fourth inverter circuits 101 to 104, the first and second latch circuits 201 and 202, and the output terminals O1 to O4 are connected to each other.

[0076] Specifically, the first output terminal O1 is connected to the gate of the first transistor M11 of the first inverter circuit 101, the drain of the second transistor M42 of the fourth inverter circuit 104, and the drain of the sixth transistor M26 of the second latch circuit 202, and outputs a first output signal.

[0077] The second output terminal O2 is connected to the gate of the first transistor M21 of the second inverter circuit 102, the drain of the second transistor M32 of the third inverter circuit 103, and the drain of the fifth transistor M25 of the second latch circuit 202, and outputs a second output signal that forms a differential signal with the first output signal.

[0078] The third output terminal O3 is connected to the gate of the first transistor M41 of the fourth inverter circuit 104, the drain of the second transistor M22 of the second inverter circuit 102, and the drain of the sixth transistor M16 of the first latch circuit 201, and outputs a third output signal that is out of phase with the first output signal by a predetermined phase, for example, π / 2.

[0079] The fourth output terminal O4 is connected to the gate of the first transistor M31 of the third inverter circuit 103, the drain of the second transistor M12 of the first inverter circuit 101, and the drain of the fifth transistor M15 of the first latch circuit 201, and outputs a fourth output signal that forms a differential signal with the third output signal.

[0080] The current control bias circuit 303 is connected to the first and second latch circuits 201 and 202, and controls the current flowing through the transistors in each of the first and second latch circuits 201 and 202. This allows the frequency divider circuit to operate stably against fluctuations in the power supply voltage. This effect also occurs in the other embodiments described below. Therefore, repeated description may be omitted in the explanations of the other embodiments.

[0081] [(2) Current Control Bias Circuit] A specific description will be given of the configuration and connections of the current control bias circuit 303. The current control bias circuit 303 has a ninth transistor M109, tenth transistors M110 and M210, an eleventh transistor M111, and twelfth transistors M112 and M212.

[0082] The ninth transistor M109 is, for example, a p-type MOSFET, and its source is connected to the positive power supply voltage Vdd.

[0083] The tenth transistors M110 and M210 are, for example, p-type MOSFETs, and have sources connected to the positive power supply voltage Vdd, gates connected to the gate of the ninth transistor M109, and drains connected to the sources of the fifth transistors M15 and M25 and the sixth transistors M16 and M26, respectively.

[0084] The eleventh transistor M111 is, for example, an n-type MOSFET, and its source is connected to the negative power supply voltage Vss.

[0085] The twelfth transistors M112 and M212 are, for example, n-type MOSFETs, with their sources connected to the negative power supply voltage Vss, their gates connected to the gate of the eleventh transistor M111, and their drains connected to the sources of the seventh transistors M17 and M27 and the eighth transistors M18 and M28, respectively.

[0086] The ninth transistor M109 and the tenth transistors M110 and M210 form a current mirror circuit. The eleventh transistor M111 and the twelfth transistors M112 and M212 form a current mirror circuit. In this configuration example, the ninth transistor M109 and the eleventh transistor M111 are the mirror source.

[0087] The bias current generated by the left-side current control bias circuit 303, which includes the ninth transistor M109 and the eleventh transistor M111, is not affected by fluctuations in the power supply voltage. Because of the current mirror configuration, the current flowing through the left-side current control bias circuit 303 is copied to the right-side current control bias circuit 303, which includes the tenth transistors M110 and M210 and the twelfth transistors M112 and M212. The gate-source voltages of the two transistors that make up the current mirror circuit are substantially the same. This reduces the effect of fluctuations in the power supply voltage on each of the first and second latch circuits 201 and 202.

[0088] That is, the difference between the influence of fluctuations in the power supply voltage on each of the first to fourth inverter circuits 101 to 104 and the influence of fluctuations in the power supply voltage on each of the first and second latch circuits 201 to 202 is reduced. In other words, the dependency between the first to fourth inverter circuits 101 to 104 and the first and second latch circuits 201 to 202 is increased. Therefore, the frequency divider circuit according to this embodiment can operate stably against fluctuations in the power supply voltage.

[0089] 6, the first and second latch circuits 201 and 202 are directly connected to the positive power supply voltage Vdd and the negative power supply voltage Vss, respectively. Therefore, when the input signal is inverted, only the gates of the transistors in the first and second latch circuits 201 and 202 are inverted. It takes time for the voltage between the gate and source of this transistor to change, which slows down the operation of the first and second latch circuits 201 and 202.

[0090] 7, the tenth transistors M110 and M210 and the twelfth transistors M112 and M212 are connected to the first and second latch circuits 201 and 202. The gate-source voltages of the ninth transistor M109 and the tenth transistors M110 and M210 that constitute the current mirror circuit are approximately the same. The gate-source voltages of the eleventh transistor M111 and the twelfth transistors M112 and M212 that constitute the current mirror circuit are approximately the same. Therefore, when the input signal is inverted, the gate-source voltages of the transistors in the first and second latch circuits 201 and 202 change immediately, thereby speeding up the operation of the first and second latch circuits 201 and 202.

[0091] This will be explained with reference to Figures 8 and 9. Figure 8 is a graph showing the characteristics of the frequency divider circuit shown in Figure 6. Figure 9 is a graph showing the characteristics of the frequency divider circuit shown in Figure 7. In Figures 8 and 9, the horizontal axis represents the frequency of the input signal, and the vertical axis represents the lower limit of the amplitude of the input signal that can be divided.

[0092] As shown in Figure 8, when the frequency of the input signal fluctuates, the lower limit of the divisible input signal amplitude also fluctuates. The line on the graph forms a V shape. The characteristics of the frequency divider circuit fluctuate depending on the value of the positive power supply voltage Vdd. In this example, the line on the graph when Vdd is a high-voltage power supply is far from the line on the graph when Vdd is a low-voltage power supply. This indicates that the frequency divider circuit is significantly affected by fluctuations in the power supply voltage.

[0093] 9, the line on the graph when Vdd is a high-voltage power supply and the line on the graph when Vdd is a low-voltage power supply are almost overlapped, which indicates that the frequency divider circuit according to this embodiment operates stably against fluctuations in the power supply voltage.

[0094] Also, let us consider the case where the lower limit of the divisible input signal amplitude is A [mVp-p]. In the graph shown in Fig. 8, the divisible input signal frequency range is 2 [GHz]. On the other hand, in the graph shown in Fig. 9, the divisible input signal frequency range is 2.9 [GHz]. In other words, the frequency divider circuit according to this embodiment operates stably against fluctuations in the power supply voltage, and therefore the divisible input signal frequency range is wider.

[0095] Furthermore, in the graph shown in Fig. 8, when the lower limit of the amplitude of the divisible input signal is A [mVp-p], the frequency range of the divisible input signal is 6 to 8 [GHz]. On the other hand, in the graph shown in Fig. 9, when the lower limit of the amplitude of the divisible input signal is A [], the frequency range of the divisible input signal is 6.6 to 9.5 [GHz]. In other words, the frequency divider circuit according to this embodiment can divide the input signal at a higher frequency, enabling faster operation.

[0096] [(3) Capacitor] As shown in FIG. 7 , a frequency divider circuit according to an embodiment of the present technology includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4.

[0097] The first capacitor C1 is connected between the first input terminal I1 and a terminal connected to the gate of the second transistor M32 of the third inverter circuit 103 and the gate of the second transistor M42 of the fourth inverter circuit 104. As a result, an AC component is extracted from, for example, an analog input signal IN+ via the first capacitor C1. This AC component is superimposed on the threshold voltages of the gate of the second transistor M32 of the third inverter circuit 103 and the gate of the second transistor M42 of the fourth inverter circuit 104.

[0098] The second capacitor C2 is connected between the first input terminal I1 and a terminal connected to the gate of the third transistor M13 in the first inverter circuit 101 and the gate of the third transistor M23 in the second inverter circuit 102. As a result, for example, an AC component is extracted from the analog input signal IN+ via the second capacitor C2. This AC component is superimposed on the threshold voltages of the gate of the third transistor M13 in the first inverter circuit 101 and the gate of the third transistor M23 in the second inverter circuit 102.

[0099] The third capacitor C3 is connected between the second input terminal I2 and the terminals connected to the gate of the second transistor M12 in the first inverter circuit 101 and the gate of the second transistor M22 in the second inverter circuit 102. As a result, for example, an AC component is extracted from the analog input signal IN− via the third capacitor C3. This AC component is superimposed on the threshold voltages of the gate of the second transistor M12 in the first inverter circuit 101 and the gate of the second transistor M22 in the second inverter circuit 102.

[0100] The fourth capacitor C4 is connected between the second input terminal I2 and a terminal connected to the gate of the third transistor M33 included in the third inverter circuit 103 and the gate of the third transistor M43 included in the fourth inverter circuit 104. As a result, for example, an AC component is extracted from the analog input signal IN− via the fourth capacitor C4. This AC component is superimposed on the threshold voltages of the gate of the third transistor M33 included in the third inverter circuit 103 and the gate of the third transistor M43 included in the fourth inverter circuit 104.

[0101] The second transistors M12, M22, M32, and M42 in each of the first to fourth inverter circuits 101 to 104 preferably have the same characteristics. The third transistors M13, M23, M33, and M43 in each of the first to fourth inverter circuits 101 to 104 preferably have the same characteristics.

[0102] The above description of the frequency divider circuit according to the first embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0103] 3. Second Embodiment of the Present Technology (Example 2 of Frequency Divider Circuit) The current flowing through the transistors included in each of the first and second latch circuits 201 and 202 may be variable. This will be described with reference to FIG. 10. FIG. 10 is a circuit diagram showing an example configuration of a frequency divider circuit according to an embodiment of the present technology.

[0104] 10 , the frequency divider circuit according to this embodiment may further include a first variable transistor M115 and a second variable transistor M215. The gates of the first variable transistor M115 and the second variable transistor M215 are connected to a first bias circuit 301 having a current source. The source of the first variable transistor M115 is connected to the positive power supply voltage Vdd. The source of the second variable transistor M215 is connected to the negative power supply voltage Vss.

[0105] Furthermore, each of the transistor M120 and the transistor M220 included in the first bias circuit 301 may be a variable transistor.

[0106] This configuration makes it possible to vary the current flowing through the transistors in each of the first and second latch circuits 201 and 202. For example, if the frequency divider circuit can divide the frequency even with a small current, it is possible to reduce the current flowing through the transistors in each of the first and second latch circuits 201 and 202. This reduces the current consumption of the frequency divider circuit.

[0107] The frequency divider circuit according to this embodiment may further include transistors M113 and M213 serving as power gates between the sources of the fourth transistors M14, M24, M34, and M44 and the sources of the twelfth transistors M112 and M212 and the negative power supply voltage Vss.

[0108] The sources of the transistors M113 and M213 are connected to the negative power supply voltage Vss. The drains of the transistors M113 and M213 are connected to the sources of the fourth transistors M14, M24, M34, and M44 included in the first to fourth inverter circuits 101 to 104, respectively, and to the sources of the twelfth transistors M112 and M212.

[0109] An enable signal is input to the gates of the transistors M113 and M213. This enable signal turns on / off the current path of the frequency divider circuit. This allows the frequency division function to be stopped, for example, when frequency division is not required. As a result, the power consumption of the frequency divider circuit can be reduced.

[0110] The number of transistors serving as power gates is not particularly limited. In this configuration example, the transistors serving as power gates are connected to the negative power supply voltage Vss, but they may also be connected to the sources of the first transistors M11, M21, M31, and M41, the sources of the tenth transistors M110 and M210 (see FIG. 7), and the positive power supply voltage Vdd.

[0111] The above description of the frequency divider circuit according to the second embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0112] 4. Third Embodiment of the Present Technology (Example of Oscillator) The present technology provides an oscillator including the frequency divider circuit according to any one of the first and second embodiments, and a differential sine wave signal generation circuit that supplies a differential sine wave signal to the frequency divider circuit.

[0113] A configuration example of an oscillator according to an embodiment of the present technology will be described with reference to Fig. 11. Fig. 11 is a circuit diagram showing a configuration example of an oscillator according to an embodiment of the present technology.

[0114] As shown in FIG. 11, the oscillator according to this embodiment includes a differential sine wave signal generating circuit LCOSC, a frequency divider circuit DIV, a reference current supply circuit IREF, and a circuit OUTDIV that further divides the output of the frequency divider circuit DIV.

[0115] The reference current supply circuit IREF supplies the reference current necessary for the operation of the oscillator.

[0116] The differential sine wave signal generating circuit LCOSC generates a differential sine wave signal of a constant frequency based on the reference current supplied by the reference voltage supply circuit IREF, and supplies the differential sine wave signal to the frequency divider circuit DIV.

[0117] The frequency divider circuit DIV divides the frequency of the differential sine wave signal supplied by the differential sine wave signal generation circuit LCOSC based on the reference current supplied by the reference current supply circuit IREF.

[0118] The circuit OUTDIV further divides the output of the divider circuit DIV, and by adjusting the division ratio of the circuit OUTDIV, a wide range of output frequencies can be achieved.

[0119] The above description of the oscillator according to the third embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0120] 5. Fourth embodiment of the present technology (example of electronic device) An oscillator according to the third embodiment of the present technology can be provided in an electronic device. Examples of the electronic device include digital home appliances such as televisions, smartphones, and personal computers, and communication devices such as mobile phones, wireless LANs, and satellite communication devices.

[0121] An example of the configuration of a communication device, which is an example of this electronic device, will be described with reference to Fig. 12. Fig. 12 is a block diagram showing an example of the configuration of an electronic device according to an embodiment of the present technology.

[0122] As shown in FIG. 12, a communication device 1000 , which is an example of an electronic device, includes a power supply unit 1001 , an oscillator 1002 , and a communication unit 1003 .

[0123] A power supply unit 1001 supplies power to an oscillator 1002 and a communication unit 1003. The oscillator 1002 generates a frequency required for communication. The communication unit 1003 transmits and receives radio waves using the frequency required for communication.

[0124] The above description of the electronic device according to the fourth embodiment of the present technology can be applied to other embodiments of the present technology unless there is a particular technical contradiction.

[0125] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology. The specific numerical values, shapes, materials (including compositions), etc. described in each embodiment are merely examples, and the present technology is not limited to these.

[0126] The present technology may also be configured as follows: [1] A frequency divider circuit including at least a plurality of input terminals, a plurality of output terminals, a first inverter circuit, a second inverter circuit, a third inverter circuit, and a fourth inverter circuit, a first latch circuit and a second latch circuit, and a current control bias circuit, wherein the plurality of input terminals, the first to fourth inverter circuits, the first to second latch circuits, and the plurality of output terminals are connected, and the current control bias circuit is connected to the first to second latch circuits and controls a current flowing through a transistor included in each of the first to second latch circuits. [2] Each of the first to fourth inverter circuits includes: a first transistor which is a p-type MOSFET and has a source connected to a positive power supply voltage; a second transistor which is a p-type MOSFET and has a source connected to the drain of the first transistor; a third transistor which is an n-type MOSFET and has a drain connected to the drain of the second transistor; and a fourth transistor which is an n-type MOSFET and has a drain connected to the source of the third transistor, a source connected to a negative power supply voltage, and a gate connected to the gate of the first transistor; and each of the first to second latch circuits includes: a fifth transistor which is a p-type MOSFET; a sixth transistor which is a p-type MOSFET and has a source connected to the source of the fifth transistor, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor; and a seventh transistor which is an n-type MOSFET and has a drain connected to the drain of the fifth transistor. an eighth transistor which is an n-type MOSFET and has a drain connected to the drain of the sixth transistor and the gate of the seventh transistor, a source connected to the source of the seventh transistor, and a gate connected to the drain of the seventh transistor, and the current control bias circuit includes: a ninth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage;10. The frequency divider circuit according to claim 1, comprising: a tenth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a gate connected to the gate of the ninth transistor, and a drain connected to each of the sources of the fifth and sixth transistors; an eleventh transistor which is an n-type MOSFET and has a source connected to the negative power supply voltage; and a twelfth transistor which is an n-type MOSFET and has a source connected to the negative power supply voltage, a gate connected to the gate of the eleventh transistor, and a drain connected to each of the sources of the seventh and eighth transistors, wherein the ninth transistor and the tenth transistor form a current mirror circuit, and the eleventh transistor and the twelfth transistor form a current mirror circuit. [3] The plurality of output terminals include a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, wherein the first output terminal is connected to a gate of the first transistor included in the first inverter circuit, a drain of the second transistor included in the fourth inverter circuit, and a drain of the sixth transistor included in the second latch circuit, and outputs a first output signal, the second output terminal is connected to a gate of the first transistor included in the second inverter circuit, a drain of the second transistor included in the third inverter circuit, and a drain of the fifth transistor included in the second latch circuit, and outputs a second output signal that forms a differential signal with the first output signal, and the third output terminal is connected to a gate of the first transistor included in the fourth inverter circuit, a drain of the second transistor included in the second inverter circuit, and a drain of the sixth transistor included in the first latch circuit, and outputs a third output signal that is shifted in phase from the first output signal by a predetermined amount, [4] The frequency divider circuit according to [2], wherein the fourth output terminal is connected to the gate of the first transistor included in the third inverter circuit, the drain of the second transistor included in the first inverter circuit, and the drain of the fifth transistor included in the first latch circuit, and outputs a fourth output signal that forms a differential signal with the third output signal.the plurality of input terminals include a first input terminal and a second input terminal, and further comprising: a first capacitor connected between the first input terminal and a terminal connected to a gate of the second transistor included in the third inverter circuit and a gate of the second transistor included in the fourth inverter circuit; a second capacitor connected between the first input terminal and a terminal connected to a gate of the third transistor included in the first inverter circuit and a gate of the third transistor included in the second inverter circuit, respectively; a third capacitor connected between the second input terminal and a terminal connected to a gate of the second transistor included in the first inverter circuit and a gate of the second transistor included in the second inverter circuit, respectively; and a fourth capacitor connected between the second input terminal and a terminal connected to a gate of the third transistor included in the third inverter circuit and a gate of the third transistor included in the fourth inverter circuit, respectively. [5] The frequency divider circuit according to any one of [1] to [4], wherein a current flowing through a transistor included in each of the first to second latch circuits is variable. [6] The frequency divider circuit according to any one of [2] to [5], further comprising a transistor serving as a power gate between the source of the fourth transistor and the source of the twelfth transistor and the negative power supply voltage. [7] The frequency divider circuit according to any one of [3] to [6], wherein the predetermined phase is π / 2. [8] The frequency divider circuit according to any one of [1] to [7], which generates a signal by dividing a signal input from the input terminal by n (n is an integer greater than or equal to 2 and a power of 2), and outputs the signal from the output terminal. [9] An oscillator comprising: the frequency divider circuit according to any one of [1] to [8]; and a differential sine wave signal generation circuit that supplies a differential sine wave signal to the frequency divider circuit.

[10] An electronic device comprising the oscillator according to [9].

[0127] 101 First inverter circuit 102 Second inverter circuit 103 Third inverter circuit 104 Fourth inverter circuit 201 First latch circuit 202 Second latch circuit I1 First input terminal I2 Second input terminal O1 First output terminal O2 Second output terminal O3 Third output terminal O4 Fourth output terminal 301 First bias circuit 302 Second bias circuit 303 Current control bias circuit 1000 Communication device 1001 Power supply unit 1002 Oscillator 1003 Communication unit

Claims

1. A frequency divider circuit comprising at least a plurality of input terminals, a plurality of output terminals, a first inverter circuit, a second inverter circuit, a third inverter circuit, and a fourth inverter circuit, a first latch circuit and a second latch circuit, and a current control bias circuit, wherein the plurality of input terminals, the first to fourth inverter circuits, the first to second latch circuits, and the plurality of output terminals are connected to each other, and the current control bias circuit is connected to the first to second latch circuits, and controls the current flowing through a transistor in each of the first to second latch circuits. 2.each of the first to fourth inverter circuits includes: a first transistor which is a p-type MOSFET and has a source connected to a positive power supply voltage; a second transistor which is a p-type MOSFET and has a source connected to a drain of the first transistor; a third transistor which is an n-type MOSFET and has a drain connected to a drain of the second transistor; and a fourth transistor which is an n-type MOSFET and has a drain connected to the source of the third transistor, a source connected to a negative power supply voltage, and a gate connected to the gate of the first transistor; each of the first to second latch circuits includes: a fifth transistor which is a p-type MOSFET; a sixth transistor which is a p-type MOSFET and has a source connected to the source of the fifth transistor, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor; the current control bias circuit comprises: a ninth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage; a tenth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a gate connected to the gate of the ninth transistor and a drain connected to each of the sources of the fifth and sixth transistors; an eleventh transistor which is an n-type MOSFET and has a source connected to the negative power supply voltage; and a twelfth transistor which is an n-type MOSFET and has a source connected to the negative power supply voltage, a gate connected to the gate of the eleventh transistor and a drain connected to each of the sources of the seventh and eighth transistors; the ninth transistor and the tenth transistor form a current mirror circuit; and the eleventh transistor and the twelfth transistor form a current mirror circuit. The frequency divider circuit according to claim 1.

3. The plurality of output terminals include a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, the first output terminal is connected to a gate of the first transistor included in the first inverter circuit, a drain of the second transistor included in the fourth inverter circuit, and a drain of the sixth transistor included in the second latch circuit, and outputs a first output signal, the second output terminal is connected to a gate of the first transistor included in the second inverter circuit, a drain of the second transistor included in the third inverter circuit, and a drain of the fifth transistor included in the second latch circuit, and outputs a second output signal that forms a differential signal with the first output signal, the third output terminal is connected to a gate of the first transistor included in the fourth inverter circuit, a drain of the second transistor included in the second inverter circuit, and a drain of the sixth transistor included in the first latch circuit, and outputs a third output signal that is shifted in phase with the first output signal by a predetermined amount, 3. The frequency divider circuit according to claim 2, wherein the fourth output terminal is connected to a gate of the first transistor included in the third inverter circuit, a drain of the second transistor included in the first inverter circuit, and a drain of the fifth transistor included in the first latch circuit, and outputs a fourth output signal that forms a differential signal with the third output signal.

4. The frequency divider circuit according to claim 2, wherein the multiple input terminals include a first input terminal and a second input terminal, further comprising: a first capacitor connected between the first input terminal and a terminal connected to each of the gates of the second transistor included in the third inverter circuit and the gate of the second transistor included in the fourth inverter circuit; a second capacitor connected between the first input terminal and a terminal connected to each of the gates of the third transistor included in the first inverter circuit and the gate of the third transistor included in the second inverter circuit; a third capacitor connected between the second input terminal and a terminal connected to each of the gates of the second transistor included in the first inverter circuit and the gate of the second transistor included in the second inverter circuit; and a fourth capacitor connected between the second input terminal and a terminal connected to each of the gates of the third transistor included in the third inverter circuit and the gate of the third transistor included in the fourth inverter circuit.

5. The frequency divider circuit according to claim 1, wherein a current flowing through a transistor included in each of said first and second latch circuits is variable.

6. The frequency divider circuit according to claim 2, further comprising a transistor serving as a power gate between the negative power supply voltage and a source of the fourth transistor and a source of the twelfth transistor.

7. The frequency divider circuit according to claim 3, wherein the predetermined phase is π / 2.

8. The frequency divider circuit according to claim 1, which generates a signal by dividing a signal inputted from said input terminal by n (n is an integer equal to or greater than 2 and a power of 2) and outputs the signal from said output terminal.

9. An oscillator comprising: a frequency divider circuit according to claim 1; and a differential sine wave signal generating circuit for supplying a differential sine wave signal to said frequency divider circuit.

10. An electronic device comprising the oscillator according to claim 9.

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