Power semiconductor device and power conversion device including same

Abstract

A power semiconductor device according to an embodiment may comprise: a substrate; a first-conductivity-type epitaxial layer disposed on the substrate; a plurality of second-conductivity-type first wells disposed on the first-conductivity-type epitaxial layer and spaced apart from each other; gates respectively disposed on the second-conductivity-type first wells; an interlayer insulating layer disposed to cover the gates; a JFET area arranged between the gates and between the plurality of second-conductivity-type first wells; a second-conductivity-type second well disposed on the JFET area; a first-conductivity-type second source area disposed on the second-conductivity-type second well; and a second insulating layer disposed on the first-conductivity-type second source area and the interlayer insulating layer.

Description

Power semiconductor devices and power conversion devices including the same

[0001] The embodiment relates to a power semiconductor device and a power conversion device including the same.

[0002] Power semiconductors are one of the key elements that determine the efficiency, speed, durability, and reliability of power electronics systems.

[0003] With the recent development of the power electronics industry, research is actively being conducted on WBG (Wide Bandgap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace the existing silicon (Si) power semiconductors that have reached their physical limits.

[0004] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, resulting in lower intrinsic carrier concentration, higher breakdown field (approximately 4 to 20 times), higher thermal conductivity (approximately 3 to 13 times), and larger electron saturation velocity (approximately 2 to 2.5 times).

[0005] These characteristics enable operation in high-temperature, high-voltage environments, high switching speeds, and low switching losses. Among these, gallium nitride (GaN) power semiconductor devices can be used in low-voltage systems, while silicon carbide (SiC) power semiconductor devices are suitable for high-voltage systems.

[0006]

[0007] Conventional SiC MOSFETs can be classified into trench-type MOSFETs, vertical doubly implanted structure MOSFETs (DIMOSFETs), and lateral diffused structure MOSFETs, depending on their structure. DIMOSFETs are also called planar MOSFETs or VDMOSFETs.

[0008] Meanwhile, there is a problem that voltage spikes occur in devices during switching operations in power circuits, and a free-wheeling diode (FWD) is used to prevent this.

[0009] For example, conventional FWDs have built-in PiN body diodes or external Schottky Barrier diodes (SBDs).

[0010] External SBDs have low turn-on voltage (V SD ) to reduce power loss, and operates as a unipolar device, which has the effect of reducing switching loss due to low reverse recovery charge (Qrr). However, the external SBD increases the size of the power module and has the problem of loss due to parasitic capacitance and stray inductance.

[0011] Meanwhile, a device structure that embeds an SBD inside a MOSFET cell has been proposed, but it has problems in that it has a high leakage current in the MOSFET reverse state and exhibits low short-circuit characteristics due to the barrier lowering phenomenon and thermionic emission occurring in the Schottky contact.

[0012] On the other hand, the built-in PiN diode has the advantage of reducing the size of the power module when used. However, the built-in PiN diode has a high turn-on voltage (V SD ) and power loss occurs, and since it operates as a bipolar device, there is a problem of increased switching loss due to high reverse recovery charge (Qrr) and deterioration of the device due to bipolar degradation.

[0013]

[0014] To address these issues, several MOSFET structures with a built-in channel diode that operates as a unipolar device have been proposed.

[0015]

[0016] For example, the title of the invention of Prior Art Patent 1 (registration number CN110729356B, registration date 2023-03-21) is “SiC MOSFET structure with embedded channel diode.”

[0017] Meanwhile, in prior art patent 1, there is a problem that when a gate bias is applied in the MOSFET turn-on operation, a channel is formed only in the left P-base region, and no channel is formed in the right region, the channel resistance increases, and the on-resistance per unit area is greatly reduced.

[0018] In addition, in prior art patent 1, the threshold voltage (V) of the channel diode SD ) to achieve a low diode gate oxide film (12) thickness. However, in the prior art patent 1, a large electric field is applied to the edge of the oxide film due to the field crowding phenomenon caused by the split gate structure, and there is a problem that leakage current occurs due to FN (Fowler-Nordheim) tunneling due to the large electric field and the thin oxide film.

[0019]

[0020] Next, the title of the invention of prior art patent 2 (registration number US9324807 (B1), registration date: 2016.04.26) is “Silicon carbide MOSFET with integrated MOS diode.”

[0021] Meanwhile, Prior Patent 2 is a Planar MOSFET structure with a built-in channel diode region, and the pitch of the built-in MOS channel diode region is similar to the MOSFET region. Therefore, according to Prior Patent 2, the cell pitch increases significantly, causing damage to the active region and significantly reducing the on-resistance per unit area.

[0022] One of the technical challenges of the embodiment is to implement a MOSFET with a built-in channel diode without reducing the on-resistance per unit area.

[0023] One of the technical challenges of the embodiment is to prevent leakage current in a MOSFET with a built-in channel diode.

[0024] Additionally, the technical challenge of the embodiment is to embed the channel diode into the MOSFET without increasing the cell pitch.

[0025] Additionally, the technical challenge of the embodiment is to reduce the source-drain voltage (Vsd) while improving the reliability of the oxide film.

[0026] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0027] A power semiconductor device according to an embodiment comprises: a substrate (110); an epi layer (115) of a first conductivity type disposed on the substrate (110); a plurality of first wells (130) of a second conductivity type disposed spaced apart from each other on the epi layer (115) of the first conductivity type; a first source region (134) of the first conductivity type disposed on the first well (130) of the second conductivity type; a gate (151) disposed on the first source region (134) of the first conductivity type; an interlayer insulating layer (152) disposed to cover the gate (151); a JFET region (140) disposed between the gates (151) and between the plurality of first wells (130) of the second conductivity type; a second well (142) of a second conductivity type disposed on the JFET region (140); a second source region of the first conductivity type disposed on the second well (142) of the second conductivity type; And it may include a second source region (144) of the first challenge type and a second insulating layer (154) disposed on the interlayer insulating layer (152).

[0028] Additionally, in the embodiment, the lower surface of the second well (142) of the second challenge type may be positioned higher than the upper surface of the gate (151).

[0029] Additionally, in the embodiment, the second insulating layer may include any one of HfO2, TiO2, and Al2O3.

[0030] Additionally, in an embodiment, the thickness of the second insulating layer may be thinner than the thickness of the gate insulating layer.

[0031] Additionally, in the embodiment, the horizontal width of the second well (142) of the second challenge type may be smaller than the spacing between the first wells (130) of the second challenge type.

[0032] Additionally, in an embodiment, the interlayer insulating layer (152) may be positioned between the gate insulating layer (148) and the second insulating layer (154).

[0033] Additionally, in the embodiment, the horizontal width of the JFET region (140) disposed between the first wells (130) of the second conductive type may be greater than the horizontal width of the JFET region disposed between the second wells (142) of the second conductive type.

[0034] In addition, in the embodiment, the second contact region (146) of the second conductive type may be further included in the second source region (144) of the first conductive type, and a source electrode (155) may be included in contact with the first contact region (132) of the second conductive type and the second contact region (146) of the second conductive type.

[0035] Additionally, in the embodiment, the second well (142) of the second challenge type may overlap between the first wells of the plurality of second challenge types.

[0036] Additionally, in the embodiment, the second well (142) of the second challenge type may not overlap with the first well (130) of the second challenge type in the horizontal and vertical directions.

[0037] The second well (142) of the second challenge type may be positioned higher than the upper surface of the interlayer insulating layer.

[0038] A power semiconductor device according to an embodiment and a power conversion device including the same have a technical effect of preventing leakage current in a MOSFET having a built-in channel diode.

[0039] For example, the embodiment can prevent leakage current due to FN tunneling by separating the MOSFET and the channel diode, eliminating the need to form a thin oxide film on the channel diode.

[0040] Additionally, the embodiment has a technical effect of preventing a decrease in channel resistance, thereby preventing a decrease in on-resistance per unit area.

[0041] For example, the embodiment may be configured such that a channel diode is formed on a MOSFET, so that channel regions on both sides of the JFET region are used, thereby preventing a decrease in channel resistance and preventing a decrease in on-resistance per unit area.

[0042] Additionally, the embodiment has the technical effect of incorporating the channel diode into the MOSFET and not increasing the cell pitch.

[0043] For example, embodiments may form the channel diode over the MOSFET region, so that the cell pitch does not increase.

[0044] Additionally, the embodiment has a technical effect of reducing the source-drain voltage (Vsd) while improving the reliability of the oxide film.

[0045] For example, the embodiment can form the gate oxide of the channel diode with a high-k material, thereby forming the gate oxide thick and improving the reliability of the oxide, and can reduce the source-drain voltage (Vsd) due to the high dielectric constant.

[0046] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0047] Figure 1 is an example diagram of the configuration of a power conversion device (1000) according to an embodiment.

[0048] Fig. 2 is a cross-sectional view of a power semiconductor device (100) according to an embodiment.

[0049] Figure 3 is a cross-sectional view of a power semiconductor device according to the first embodiment.

[0050] Figures 4a to 4i are manufacturing process diagrams of a power semiconductor device according to the first embodiment.

[0051] Hereinafter, an invention according to an embodiment for solving the above problem will be described in more detail with reference to the drawings.

[0052] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0053] Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

[0054] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0055] In this application, it should be understood that terms such as “include,” “have,” or “comprising” are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0056] The meaning of “composition A includes at least one of a, b, and / or c” in the specification or claims may include ① cases where composition A includes a, ② cases where composition A includes b, ③ cases where composition A includes c, ④ cases where composition A includes a and b, ⑤ cases where composition A includes b and c, ⑥ cases where composition A includes a and c, and ⑦ cases where composition A includes all of a, b, and c.

[0057] Singular expressions include both singular and plural expressions, unless the context clearly indicates otherwise. For example, the meaning of "composition A includes a structure" can include the meaning of "composition A includes one or more structures."

[0058]

[0059] Figure 1 is an example diagram of the configuration of a power conversion device (1000) according to an embodiment.

[0060] A power conversion device (1000) according to an embodiment can receive DC power from a battery or a fuel cell, convert it into AC power, and supply AC power to a predetermined load. For example, the power conversion device (1000) according to an embodiment can include an inverter, and can receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor (M), and the motor (M) can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0061] A power conversion device (1000) according to an embodiment may include a power semiconductor device (100). The power semiconductor device (100) may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0062] For example, the power conversion device (1000) may include a plurality of power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) and may include a plurality of diodes (not shown). Each of the plurality of diodes may be embedded in the power semiconductor elements (100a, 100b, 100c, 100d, 100e, 100f) in the form of an internal diode, but is not limited thereto, and may be arranged separately.

[0063] The embodiment can convert DC power into AC power through on-off control for a plurality of power semiconductor elements (100a to 100f). For example, the power conversion device (1000) according to the embodiment can supply positive power to the motor (M) by turning on the first power semiconductor element (100a) and turning off the second power semiconductor element (100b) in a first time section of one cycle, and can supply negative power to the motor (M) by turning off the first power semiconductor element (100a) and turning on the second power semiconductor element (100b) in a second time section of one cycle.

[0064] In an embodiment, a group of power semiconductor devices arranged in series on the high-voltage line and the low-voltage line of the input side may be referred to as an arm. For example, a first power semiconductor device (100a) and a second power semiconductor device (100b) may constitute a first arm, a third power semiconductor device (100c) and a fourth power semiconductor device (100d) may constitute a second arm, and a fifth power semiconductor device (100e) and a sixth power semiconductor device (100f) may constitute a third arm.

[0065] In the above arm, the upper power semiconductor element and the lower power semiconductor element can be controlled so as not to be turned on simultaneously. For example, in the first arm, the first power semiconductor element (100a) and the second power semiconductor element (100b) can be turned on and off alternately without being turned on simultaneously.

[0066] Each power semiconductor element (100a to 100f) can receive a high voltage while in an off state. For example, when the second power semiconductor element (100b) is turned off while the first power semiconductor element (100a) is turned on, the input voltage can be applied as is to the second power semiconductor element (100b). The voltage input to the second power semiconductor element (100b) can be a relatively high voltage, and the withstand voltage of each power semiconductor element (100a to 100f) can be designed to be at a high level so as to withstand such a high voltage.

[0067] Each power semiconductor element (100a to 100f) can conduct a high current when turned on. The motor (M) is driven by a relatively high current, and this high current can be supplied to the motor (M) through the turned-on power semiconductor element.

[0068] A high voltage applied to each power semiconductor element (100a to 100f) may cause high switching loss. A high current flowing through the power semiconductor element (100a to 100f) may cause high conduction loss. To dissipate the heat generated by such loss, the power semiconductor elements (100a to 100f) may be packaged into a power semiconductor module including a heat dissipation means.

[0069] The power semiconductor device (100) of the embodiment may be a silicon carbide (SiC) power semiconductor device, and may be capable of operating in a high temperature, high voltage environment and may have a high switching speed and low switching loss.

[0070]

[0071] Meanwhile, the power conversion device (1000) according to the embodiment may include a plurality of power semiconductor modules.

[0072] For example, a plurality of power semiconductor devices (100a to 100f) illustrated in FIG. 1 may be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0073] For example, the first power semiconductor element (100a), the second power semiconductor element (100b), the third power semiconductor element (100c), the fourth power semiconductor element (100d), the fifth power semiconductor element (100e), and the sixth power semiconductor element (100f) illustrated in FIG. 1 can be packaged into one power semiconductor module.

[0074] Additionally, to increase the current capacity, additional power semiconductor devices may be placed in parallel with each power semiconductor device (100a to 100f). In this case, the number of power semiconductor devices included in the power semiconductor module may exceed six.

[0075] The power conversion device (1000) according to the embodiment may include, in addition to the transistor-type power semiconductor elements (100a to 100f), a diode-type power semiconductor element. For example, a first diode (not shown) may be arranged in parallel with a first power semiconductor element (100a), and a second diode (not shown) may be arranged in parallel with a second power semiconductor element (100b). In addition, these diodes may also be packaged together in a single power semiconductor module. In addition, the diodes may be arranged in the form of internal diodes in each power semiconductor element.

[0076] Next, the power semiconductor devices that make up each arm can be packaged into a single power semiconductor module.

[0077] For example, the first power semiconductor element (100a) and the second power semiconductor element (100b) constituting the first arm may be packaged as a first power semiconductor module, the third power semiconductor element (100c) and the fourth power semiconductor element (100d) constituting the second arm may be packaged as a second power semiconductor module, and the fifth power semiconductor element (100e) and the sixth power semiconductor element (100f) constituting the third arm may be packaged as a third power semiconductor module.

[0078] In addition, in order to increase the current capacity, there may be additional power semiconductor elements arranged in parallel with each power semiconductor element (100a to 100f), in which case the number of power semiconductor elements included in each power semiconductor module may be more than two. In addition to the transistor-type power semiconductor elements (100a to 100f), each arm may also include a diode-type power semiconductor element (not shown), and these diodes may also be packaged together in one power semiconductor module. In addition, the diode may be arranged in the form of an internal diode in each power semiconductor element.

[0079]

[0080] Next, FIG. 2 is a cross-sectional view of one of the power semiconductor devices (100) according to the embodiment.

[0081] A power semiconductor device (100) according to an embodiment may include a source electrode (190), a gate electrode (175) disposed on an upper side of a predetermined semiconductor epi layer (120), and a drain electrode (105) disposed on a lower side of the semiconductor epi layer (120).

[0082] In the form of a MOSFET, the source electrode (190) or the gate electrode (175) may include an Al series metal, and the drain electrode (105) may include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, or NiV / Ag, V(vanadium) / Ni / Ag, etc., but is not limited thereto.

[0083]

[0084] Next, FIG. 3 is a cross-sectional view of a power semiconductor device according to an embodiment. Referring to FIG. 3, the power semiconductor device according to the embodiment may include a substrate (110), a first conductive epi layer (115), a first well (130) of a second conductive type, a first source region (134) of a first conductive type, a JFET region (140), a gate (151), an interlayer insulating layer (152), and a source electrode (155). The first conductive type may be N-type, and the second conductive type may be P-type, but is not limited thereto. The substrate (110) and the first conductive epi layer (115) may include SiC (Silicon Carbide). A drain electrode (not shown) may be disposed under the substrate (110).

[0085]

[0086] Meanwhile, research is being conducted on the issue of voltage spikes occurring in components during switching in power circuits such as inverter systems. To prevent this, freewheeling diodes are being used as anti-parallel diodes, and technology is being developed to incorporate internal channel diodes.

[0087] Meanwhile, internal research has shown that in power circuits including channel diodes and MOSFETs, the channel diode is placed in the horizontal direction of the MOSFET, which causes only one channel to be formed during MOSFET operation, increasing channel resistance and reducing the active area.

[0088] Accordingly, to solve the above problem, the embodiment may include a MOSFET structure having a built-in channel diode. Specifically, a channel diode (CD) may be disposed on the JFET region (140). The channel diode (CD) may include a JFET region (140), a second well (142) of a second conductivity type, a second source region (144) of a first conductivity type, a second contact region (146) of a second conductivity type, and a second insulating layer (154).

[0089] The second well (142) of the second conductive type may be positioned on the JFET region (140). In addition, the second well (142) of the second conductive type may be positioned higher than the gate (151). In detail, the lower surface of the second well (142) of the second conductive type may be positioned higher than the upper surface of the gate (151).

[0090] In addition, the thickness of the second insulating layer (154) may be smaller than the thickness of the gate insulating layer (148). In addition, a second source region (144) of the first conductive type may be disposed on the second well (142) of the second conductive type. In addition, a second contact region (146) of the second conductive type may be disposed on the second source region (144) of the first conductive type. In addition, the source electrode (155) may be electrically connected to the second contact region (146) of the second conductive type and the second source region (144) of the first conductive type, and may function as a gate of a channel diode (CD).

[0091]

[0092] Meanwhile, when the power semiconductor device of the embodiment operates as a MOSFET, a bias is applied to the gate (151) and the drain (not shown) like a general planar MOSFET, so that a channel is formed in the first well (130) of the second conductivity type, and current flows through the first conductivity type epilayer (115) to turn on the device. In addition, when the embodiment operates as a MOSFET, the channel diode (CD) may not operate.

[0093] Meanwhile, when the power semiconductor device of the embodiment operates as a free wheeling diode, a source-drain voltage (Vsd) is applied to form a channel in the second well (142) of the second conductivity type, and current flows through the first conductivity type epi layer (115) to turn on the channel diode (CD).

[0094] In the embodiment, when operating in FWD, the gate (151) of the MOSFET can be split to allow current to flow.

[0095] An embedded PIN diode is formed by the junction of the first well (130) of the second challenge type and the first challenge type epi layer (115). When the source-drain voltage (Vsd) of the channel diode (CD) is lower than the turn-on voltage of the embedded PIN diode, the operation of the embedded PIN diode is suppressed and the channel diode (CD) can be turned on.

[0096]

[0097] Accordingly, the embodiment has a technical effect of preventing a decrease in on-resistance per unit area by preventing a decrease in channel resistance because a channel is formed on both sides of the JFET region (140) in the MOSFET region without increasing the cell pitch as the channel diode (CD) is formed on the upper side of the MOSFET region.

[0098] In addition, according to the embodiment, the gate insulating layer (148) of the MOSFET region and the second insulating layer (154) of the channel diode (CD) are formed separately, and accordingly, even if the thickness of the second insulating layer (154) of the channel diode (CD) is formed thinly, the electric field is reduced compared to existing devices in a reverse situation, so there is a technical effect of preventing leakage current due to FN tunneling.

[0099] In addition, the embodiment has a technical effect that when reverse bias is applied to the MOSFET region, a low electric field is applied to the second insulating layer (154) of the channel diode (CD), thereby preventing leakage current due to FN tunneling.

[0100] Meanwhile, in the embodiment, the second insulating layer (154) may include a high-k material. The second insulating layer (154) may include any one of HfO2, TiO2, and Al2O3, but is not limited thereto. Conventionally, in order to lower the source-drain voltage (Vsd), the thickness of the gate insulating layer must be reduced. However, when the thickness of the gate insulating layer is reduced, tunneling current and reliability issues of the insulating layer may occur. On the other hand, in the embodiment, when the second insulating layer (154) includes a high-k material, even if the thickness of the gate insulating layer is formed thick, the source-drain voltage (Vsd) can be lowered, and there is a technical effect of preventing tunneling and reliability issues of the gate insulating layer.

[0101]

[0102] Next, a manufacturing process of a power semiconductor device according to an embodiment will be described with reference to FIGS. 4a to 4i.

[0103] Referring to FIG. 4a, a substrate (110) including a first conductive epi layer (115) is prepared, and a first well (130) of a second conductive type can be formed in the first conductive epi layer (115).

[0104] The above substrate (110) and the first conductive epi layer (115) may include SiC (Silicon Carbide), but are not limited thereto.

[0105] For example, the substrate (110) and the first conductive epi layer (115) may include, but are not limited to, a 4H-SiC material. For example, the substrate (110) and the first conductive epi layer (115) may include, but are not limited to, 3C-SiC or 6H-SiC. The first conductive epi layer (115) may be an N-type drift region, but is not limited thereto.

[0106] In addition, the first conductive epi layer (115) may include multiple layers having different concentrations and may have a current spreading layer (CSL) function. For example, the first conductive epi layer (115) may include a first conductive buffer layer (not shown) and a first conductive drift layer (not shown).

[0107] The first well (130) of the second challenge type above contains about 1×10 P-type dopant. 16 cm -3 About 2×10 19 cm -3 Ions can be implanted at a concentration of . For example, Al or boron can be implanted, but is not limited thereto.

[0108] The first well (130) of the second challenge type may include a plurality of spaced apart from each other, and a first JFET region (140a) may be formed between the plurality of first wells (130) of the second challenge type.

[0109] Additionally, a first source region (134) of the first conductive type and a first contact region (132) of the second conductive type can be formed on the upper side of the first well (130) of the second conductive type.

[0110] For example, the first source region (134) of the first challenge type may contain about 1×10 N-type dopants such as nitrogen or phosphorus. 19 cm -3 About 7×10 19 cm -3 It can be formed by self-aligning ion implantation at a concentration of .

[0111] In addition, the first contact region (132) of the second conductive type can be brought into contact with the source electrode thereafter. In addition, the first contact region (132) of the second conductive type can have the function of maintaining the zero potential of the first well (130) of the second conductive type and can have the function of a body diode.

[0112]

[0113] Next, referring to FIG. 4b, by forming a second JFET region (140b) through epitaxial growth, the second JFET region (140b) can be formed to extend to cover the first source region (134) of the first conductivity type, the first contact region (132) of the second conductivity type, and the first well (130) of the second conductivity type.

[0114] In the following description, the JFET region (140) will be described as including a first JFET region (140a) and a second JFET region (140b). The boundary between the first JFET region (140a) and the second JFET region (140b) may be physically distinct, but may not be distinct.

[0115] Next, referring to FIG. 4c, a second well (142) of a second conductivity type may be formed by ion implantation on the JFET region (140). In addition, a second source region (144) of a first conductivity type may be formed on the second well (142) of the second conductivity type.

[0116] For example, the second source region (144) of the first challenge type may contain about 1×10 N-type dopants such as nitrogen or phosphorus. 19 cm -3About 7×10 19 cm -3 It can be formed by ion implantation at a concentration of .

[0117] The second source region (144) of the first challenge type may be formed thinner than the thickness of the second well (142) of the second challenge type, but is not limited thereto.

[0118] Additionally, a second contact region (146) of the second conductive type may be formed in the second source region (144) of the first conductive type. The second contact region (146) of the second conductive type may be positioned in the center between the first wells (130) of the second conductive type. The second contact region (146) of the second conductive type may then be brought into contact with the source electrode.

[0119] Next, referring to FIG. 4d, a portion of the JFET region (140), the second well (142) of the second conductivity type, and the second source region (144) of the first conductivity type may be etched. Accordingly, the first source region (134) of the first conductivity type and the first contact region (132) of the second conductivity type may be exposed. The width of the second well (142) of the second conductivity type and the second source region (144) of the first conductivity type that remain after etching may be smaller than the separation distance between the plurality of first wells (130) of the second conductivity type. In addition, the width of the JFET region (140) located on the first well (130) of the second conductivity type may be smaller than the width of the JFET region (140) located between the first wells (130) of the second conductivity type.

[0120]

[0121] Next, referring to FIG. 4e, a gate insulating layer (148) may be formed on the structure of FIG. 4d. The gate insulating layer (148) may be arranged to extend over the first source region (134) of the first conductivity type to cover the second source region (144) of the first conductivity type. The gate insulating layer (148) may be a thermal oxide film or a deposition oxide film, but is not limited thereto.

[0122] Additionally, a gate material layer (150) can be formed to cover the gate insulating layer (148). The gate material layer (150) can be formed of polysilicon, but is not limited thereto.

[0123]

[0124] Next, referring to FIG. 4f, the gate material layer may be etched to form a gate (151). The gate (151) may vertically overlap with the first source region (134) of the first conductivity type. Additionally, a portion of the gate (151) may vertically overlap with the JFET region (140).

[0125]

[0126] Next, referring to FIG. 4g, the gate insulating layer (148) covering the second source region (144) of the first conductive type may be removed, and an interlayer insulating layer (152) may be formed to cover the gate (151). The interlayer insulating layer (152) may be formed of an oxide film or a nitride film, but is not limited thereto. In addition, the interlayer insulating layer (152) may include the same material as the gate insulating layer (148), but is not limited thereto. The upper surface of the interlayer insulating layer (152) may be located below the height of the upper surface of the JFET region (140), but is not limited thereto.

[0127]

[0128] Next, referring to FIG. 4h, a second insulating layer (154) may be formed on the interlayer insulating layer (152). The second insulating layer (154) may be arranged to extend over the interlayer insulating layer (152) to cover the second source region (144) of the first conductive type. The second insulating layer (154) may include, but is not limited to, SiO2.

[0129] Meanwhile, in order to lower the source-drain voltage (Vsd), the thickness of the gate insulating layer must be reduced. However, if the thickness of the gate insulating layer is reduced, issues with tunneling current and reliability of the insulating layer may arise.

[0130] Accordingly, the second insulating layer (154) of the embodiment may include a high-k material. Specifically, the second insulating layer (154) may include any one of HfO2, TiO2, and Al2O3. Therefore, the embodiment has a technical effect of being able to lower the source-drain voltage (Vsd) even when the gate insulating layer is formed thickly, and preventing tunneling and reliability issues of the gate insulating layer.

[0131]

[0132] Next, referring to FIG. 4i, a portion of the second insulating layer (154) and the interlayer insulating layer (152) may be etched to expose the first contact region (132) of the second conductive type and the first source region (134) of the first conductive type. In addition, a portion of the second insulating layer (154) disposed on the second source region (144) of the first conductive type may be etched to expose the second contact region (146) of the second conductive type.

[0133] Thereafter, a source electrode (155) may be formed on the second contact region (146) of the second conductive type. In addition, the source electrode (155) may be electrically connected to the first contact region (132) of the second conductive type and the first source region (134) of the first conductive type.

[0134] In addition, the source electrode (155) may include an Al series metal, and the drain electrode (not shown) formed on the lower side of the substrate (110) may include a Ti / Ni / Ag metal including a Ti layer, a Ni layer, and an Ag layer, or NiV / Ag, V(vanadium) / Ni / Ag, etc., but is not limited thereto.

[0135] Accordingly, in the embodiment, a channel diode (CD) can be formed on a MOSFET structure. The source electrode (155) can be used as a source electrode in the MOSFET structure and can be used as a gate in the channel diode (CD). Therefore, in the embodiment, since the channel diode (CD) is built into the MOSFET structure, voltage spikes to the MOSFET can be prevented by the channel diode (CD).

[0136]

[0137] When the power semiconductor device of the embodiment operates as a MOSFET, a bias is applied to the gate (151) and the drain (not shown) like a general planar MOSFET, so that a channel is formed in the first well (130) of the second conductivity type, and current can flow through the first conductivity type epilayer (115) to turn on the device. In addition, when the embodiment operates as a MOSFET, the channel diode (CD) may not operate.

[0138] Meanwhile, when the power semiconductor device of the embodiment operates as a free wheeling diode, a source-drain voltage (Vsd) is applied to form a channel in the second well (142) of the second conductivity type, and current can flow through the first conductivity type epilayer (115) to turn on the channel diode (CD). In the embodiment, during FWD operation, the gate (151) of the MOSFET can be split so that current can flow.

[0139] An embedded PIN diode is formed by the junction of the first well (130) of the second challenge type and the first challenge type epi layer (115). When the source-drain voltage (Vsd) of the channel diode (CD) is lower than the turn-on voltage of the embedded PIN diode, the operation of the embedded PIN diode is suppressed and the channel diode (CD) can be turned on.

[0140] Accordingly, the embodiment has a technical effect of preventing a decrease in on-resistance per unit area by preventing a decrease in channel resistance because a channel is formed on both sides of the JFET region (140) in the MOSFET region without increasing the cell pitch as the channel diode (CD) is formed on the upper side of the MOSFET region.

[0141] In addition, according to the embodiment, the gate insulating layer (148) of the MOSFET region and the second insulating layer (154) of the channel diode (CD) are formed separately, and accordingly, even if the thickness of the second insulating layer (154) of the channel diode (CD) is formed thinly, the electric field is reduced compared to existing devices in a reverse situation, so there is a technical effect of preventing leakage current due to FN tunneling.

[0142] In addition, the embodiment has a technical effect that when reverse bias is applied to the MOSFET region, a low electric field is applied to the second insulating layer (154) of the channel diode (CD), thereby preventing leakage current due to FN tunneling.

[0143] A power semiconductor device according to an embodiment and a power conversion device including the same have a technical effect of preventing leakage current in a MOSFET having a built-in channel diode.

[0144] For example, the embodiment can prevent leakage current due to FN tunneling by separating the MOSFET and the channel diode and forming the gate insulating film of the channel diode separately from the MOSFET gate insulating film.

[0145] Additionally, the embodiment has a technical effect of preventing a decrease in channel resistance, thereby preventing a decrease in on-resistance per unit area.

[0146] For example, the embodiment may be configured such that a channel diode is formed on a MOSFET, so that channel regions on both sides of the JFET region are used, thereby preventing a decrease in channel resistance and preventing a decrease in on-resistance per unit area.

[0147] Additionally, the embodiment has the technical effect of incorporating the channel diode into the MOSFET and not increasing the cell pitch.

[0148] For example, embodiments may form the channel diode over the MOSFET region, so that the cell pitch does not increase.

[0149] Additionally, the embodiment has a technical effect of reducing the source-drain voltage (Vsd) while improving the reliability of the oxide film.

[0150] For example, the embodiment can form the gate oxide of the channel diode with a high-k material, thereby forming the gate oxide thick and improving the reliability of the oxide, and can reduce the source-drain voltage (Vsd) due to the high dielectric constant.

[0151]

[0152] Although the present invention has been described above with reference to embodiments thereof, it will be readily understood by those skilled in the art that various modifications and changes to the present invention can be made without departing from the spirit and scope of the present invention as set forth in the claims below.

[0153] [Explanation of symbols]

[0154] CD: Channel diode 110: Substrate

[0155] 115: First challenge type epilayer 130: First well of second challenge type

[0156] 132: First contact area of ​​the second challenge type 134: First source area of ​​the first challenge type

[0157] 140: JFET region 142: Second well of second challenge type

[0158] 144: Second source area of ​​the first challenge type 146: Second contact area of ​​the second challenge type

[0159] 148: Gate insulating layer 150: Semiconductor layer

[0160] 151: Gate 152: Interlayer insulation layer

[0161] 154: Second insulating layer 155: Source electrode

[0162] The power conversion device (1000) according to the embodiment may include an inverter. For example, the power conversion device (1000) according to the embodiment may receive DC power from a battery, convert it into three-phase AC power, and supply it to a motor (M), and the motor (M) may provide power to an electric vehicle, a fuel cell vehicle, etc.

[0163] In addition, in the embodiment, the power semiconductor element (100) may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

Claims

1. Substrate; A first challenge type epi layer disposed on the above substrate; A plurality of first wells of the second challenge type arranged spaced apart from each other on the epi layer of the first challenge type; A first source region of the first challenge type disposed on the first well of the second challenge type; A gate disposed on the first source region of the first challenge type; An interlayer insulating layer arranged to cover the above gate; A JFET region disposed between the gates and the plurality of second challenge type first wells; A second well of a second challenge type disposed on the above JFET region; A second source region of the first challenge type disposed on the second well of the second challenge type; and A power semiconductor device comprising a second source region of the first challenge type and a second insulating layer disposed on the interlayer insulating layer.

2. In paragraph 1, A power semiconductor device, wherein the lower surface of the second well of the second challenge type is positioned higher than the upper surface of the gate.

3. In paragraph 1, The second insulating layer is HfO 2 , TiO 2 , Al 2 O 3 A power semiconductor device comprising any one of:

4. In paragraph 1, A power semiconductor device, wherein the thickness of the second insulating layer is thinner than the thickness of the gate insulating layer.

5. In paragraph 1, A power semiconductor device, wherein the horizontal width of the second well of the second challenge type is smaller than the spacing between the first wells of the second challenge type.

6. In paragraph 1, A power semiconductor device, wherein the interlayer insulating layer is located between the gate insulating layer and the second insulating layer.

7. In paragraph 1, A power semiconductor device, wherein the horizontal width of the JFET region disposed between the first wells of the second challenge type is larger than the horizontal width of the JFET region disposed between the second wells of the second challenge type.

8. In paragraph 1, Further comprising a second contact region of the second challenge type arranged in the second source region of the first challenge type, A power semiconductor device comprising a source electrode in contact with a first contact region of the second challenge type and a second contact region of the second challenge type.

9. In paragraph 1, A power semiconductor device, wherein the second well of the second challenge type overlaps between the first wells of the plurality of second challenge types.

10. In paragraph 1, A power semiconductor device, wherein the second well of the second challenge type does not overlap the first well of the second challenge type in the horizontal and vertical directions.

11. In paragraph 1, A power semiconductor device, wherein the second well of the second challenge type is positioned higher than the upper surface of the interlayer insulating layer.

12. A power conversion device comprising a power semiconductor device according to any one of claims 1 to 11.

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