Output circuit

Abstract

A first transistor (P1) has a source connected to VDD1 and a drain connected to an output terminal (1) via a second transistor (P2). A pre-driver (13) receives a signal that changes according to a data input signal (DIN), and applies a gate signal (SG1) that transitions between VDD1 and the potential (VP) of a power supply terminal (4) to the gate of the first transistor (P1). When an assist signal undergoes a first transition corresponding to a transition of the gate signal (SG1) from high to low, or when the assist signal undergoes a second transition corresponding to a transition of the gate signal (SG1) from a low level to a high level, a drive assist circuit (10) performs an assist operation for temporarily lowering the potential of an output node (nc) from VDD2.

Description

Output Circuit

[0001] The present disclosure relates to an output circuit that outputs a signal to the outside of a semiconductor device (LSI (Large Scale Integration)).

[0002] As transistors become smaller, the voltage stress (withstand voltage) that transistors can tolerate is decreasing. As a result, output circuits that use transistors with low withstand voltages and output high-voltage signals are known.

[0003] For example, Patent Document 1 discloses a technology in which a drive assist circuit is provided in an output circuit that performs an assist operation to temporarily lower the potential of the output node when a transition corresponding to a transition of a gate signal from a high level to a low level occurs.

[0004] U.S. Pat. No. 10,355,685

[0005] The output circuit of Patent Document 1 only functions when the gate signal transitions from high to low, i.e., when the data output signal rises. However, in today's world where high-speed circuit operation and reduced power consumption are required, an output circuit with control that functions when the signal transitions both rising and falling is desirable.

[0006] In view of the above-mentioned problems, an object of the present disclosure is to provide an output circuit that performs an assist operation in both rising and falling transitions of a signal.

[0007] In one aspect of the present disclosure, there is provided an output circuit that receives a data input signal and outputs an output signal that changes in response to the data input signal, the output circuit including: an output terminal that outputs the output signal; a P-type first transistor having a source connected to a first power supply that provides a first potential and a drain connected to a first node; a P-type second transistor having a source connected to the first node and a drain connected to the output terminal; a pre-driver that is connected to the first power supply and a power supply end that is supplied with a potential lower than the first potential, and that receives the data input signal or a signal that changes in response to the data input signal and is connected to the first power supply and the power supply end, and that receives a signal output from the level shift circuit and provides a transition signal that transitions between the first potential and a potential of the power supply end in response to the received signal to a gate of the first transistor; a second power supply that provides a second potential lower than the first potential; and a third power supply that provides a third potential lower than the second potential. and a drive assist circuit that supplies the second potential from an output node to the power supply terminal, wherein the drive assist circuit receives the data input signal or a signal that changes according to the data input signal as an assist signal, and performs an assist operation to temporarily lower the potential of the output node from the second potential when the assist signal makes a first transition corresponding to the transition of the gate signal from high level to low level, or when the assist signal makes a second transition corresponding to the transition of the gate signal from low level to high level.

[0008] According to this aspect, in the output circuit, the first transistor has a source connected to a first power supply that provides a first potential and a drain connected to the output terminal. The level shift circuit and the pre-driver are connected to the first power supply and a power supply terminal that is supplied with a potential lower than the first potential, and provide a transition signal that transitions between the first potential and the potential of the power supply terminal to the first transistor as a gate signal in response to a data input signal. The drive assist circuit supplies a second potential from the output node to the power supply terminal. The drive assist circuit also receives the data input signal or a signal that changes in response to the data input signal as an assist signal. When the assist signal makes a first transition corresponding to a transition of the gate signal from high to low, or when the assist signal makes a second transition corresponding to a transition of the gate signal from low to high, the drive assist circuit performs an assist operation to temporarily lower the potential of the output node from the second potential.

[0009] Therefore, when the gate signal transitions from high to low, the assist operation of the drive assist circuit can temporarily increase the gate-source voltage of the first transistor. This improves the driving capability of the first transistor, thereby speeding up the transition of the output signal from low to high. Furthermore, when the assist signal makes a second transition corresponding to the transition of the gate signal from low to high, the drive assist circuit performs an assist operation to temporarily lower the potential of the output node from the second potential. This increases the operating speed of the pre-driver, thereby speeding up the transition of the output signal from high to low.

[0010] According to the present disclosure, it is possible to realize an output circuit that performs an assist operation in both rising and falling transitions of a signal.

[0011] Circuit configuration diagram of an output circuit according to the first embodiment. Circuit configuration diagram of a level shift circuit. Waveform diagram showing the operation of the output circuit of FIG. 1. Circuit configuration diagram of an output circuit according to a second embodiment. Waveform diagram showing the operation of the output circuit of FIG. 4. Circuit configuration diagram of an output circuit according to a third embodiment. Waveform diagram showing the operation of the output circuit of FIG. 6. Circuit configuration diagram of an output circuit according to a modification of the first embodiment.

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] In the circuit diagrams shown below, the illustrations are simplified and focus on the components related to the present disclosure. For example, components shown as being directly connected may actually be indirectly connected to each other in the actual circuit configuration, with other components interposed between them.

[0014] In the following description, common symbols or names may be used for nodes and terminals of a circuit and signals passing through those nodes and terminals, and common symbols may be used for the name of a power supply and the power supply voltage (potential) of that power supply. Furthermore, the voltage of a terminal or node may be written as "(terminal name or node name) = (symbol indicating voltage)." Specifically, for example, if the voltage of the output node nc is VDD1 (the voltage of the power supply VDD1), it may be written as nc = VDD1.

[0015] <First Embodiment> Fig. 1 is a circuit diagram of an output circuit according to a first embodiment. An output circuit 100 in Fig. 1 receives a data input signal DIN and outputs an output signal DOUT that changes in response to this data input signal DIN. The output signal DOUT is output from an output terminal 1. This output circuit 100 is provided, for example, in a signal output section of an LSI. In this case, an output pad of the LSI corresponds to the output terminal 1.

[0016] The output circuit 100 is connected to a first power supply VDD1 and a second power supply VDD2. The potential of the first power supply VDD1 is higher than the potential of the second power supply VDD2. The data input signal DIN transitions between the ground potential VSS and the second potential VDD2. The output signal DOUT transitions between the ground potential VSS and the first potential VDD1.

[0017] The output circuit 100 includes a level shift circuit 12, inverters 13 and 16, P-type transistors P1 and P2, and N-type transistors N1 and N2. In this disclosure, each transistor is assumed to be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0018] The level shift circuit 12 converts the data input signal DIN into a signal that transitions between the potential VP of the power supply terminal 4 and the first potential VDD 1 , and supplies the signal to the inverter 13 .

[0019] The inverter 13 is composed of a P-type transistor P3 and an N-type transistor N3, whose gates and drains are connected to each other, and is connected to a first power supply VDD1 and a power supply terminal 4 to which a potential VP lower than the first potential VDD1 is supplied. The inverter 13 inverts a signal SG3 received from the level shift circuit 12 and supplies the inverted signal to the gate of the P-type transistor P1 as a gate signal SG1. The gate signal SG1 transitions between the first potential VDD1 and the potential VP of the power supply terminal 4. The inverter 13 is an example of a pre-driver. Note that in a normal state, the second potential VDD2 is supplied as the potential VP.

[0020] The P-type transistor P1 (corresponding to the first transistor) has a source connected to the first power supply VDD1 and a drain connected to the output terminal 1 via the P-type transistor P2. That is, the P-type transistor P1 is cascade-connected to the output terminal 1. More specifically, the P-type transistor P1 has a source connected to the first power supply VDD1 and a drain connected to the first node n1. The P-type transistor P2 (corresponding to the second transistor) has a source connected to the first node n1 and a drain connected to the output terminal 1.

[0021] When the gate signal SG1 transitions from a high level (VDD1) to a low level (VP), the P-type transistor P1 transitions from a non-conductive state to a conductive state, thereby raising the potential of the output signal DOUT toward the first potential VDD1, and the output signal DOUT transitions to a high level (VDD1).

[0022] Inverter 16 inverts data input signal DIN and supplies the inverted signal as gate signal SG2 to the gate of N-type transistor N1. The source of N-type transistor N1 is grounded, and the drain is connected to output terminal 1 via N-type transistor N2. When gate signal SG2 transitions from low level (VSS) to high level (VDD2), N-type transistor N1 changes from a non-conductive state to a conductive state. This pulls down the potential of output signal DOUT toward ground potential VSS, and output signal DOUT transitions to low level (VSS).

[0023] The output circuit 100 further includes a drive assist circuit 10. The drive assist circuit 10 is connected to a second power supply VDD2 and supplies a potential VP from an output node nc. The output node nc is connected to the power supply terminal 4 and also to the gate of a P-type transistor P2. When the drive assist circuit 10 is not performing an assist operation (described later), it outputs a second potential VDD2 as the potential VP from the output node nc. At this time, the second potential VDD2 is supplied from the drive assist circuit 10 to the power supply terminal 4, and therefore the gate signal SG1 output from the inverter 13 becomes a signal that transitions between the first potential VDD1 and the second potential VDD2. Furthermore, when a data input signal DIN (corresponding to an assist signal) transitions from low level to high level, the drive assist circuit 10 performs an assist operation to temporarily lower the potential VP of the output node nc from the second potential VDD2. Here, the transition of the data input signal DIN from low level to high level corresponds to the transition of the gate signal SG 1 output from the inverter 13 from high level to low level.

[0024] The drive assist circuit 10 includes N-type transistors N4 and N5 whose sources are grounded to the ground VSS, a resistor string RR, and a pulse generating circuit 20. The drains of the N-type transistors N4 and N5 are connected to a connection node nd.

[0025] The resistor string RR is made up of resistor units R1 and R2 connected in series and is provided between the second power supply VDD2 and a connection node nd. The connection node of the resistor units R1 and R2 serves as the output node nc of the drive assist circuit 10.

[0026] The pulse generating circuit 20 includes inverters 21 and 24 that receive the data input signal DIN, a delay circuit 22 that receives the output signal of the inverter 21, a delay circuit 25 that receives the output signal of the inverter 24, an AND gate 23, and a NOR gate 26.

[0027] The AND gate 23 receives the data input signal DIN and the output of the delay circuit 22 as inputs, and provides its output na to the gate of the N-type transistor N4. The output na remains high for a predetermined time after the data input signal DIN transitions from low to high. In this way, the inverter 21, delay circuit 22, and AND gate 23 constitute a circuit that outputs a pulse having a predetermined pulse width when the data input signal DIN transitions from low to high.

[0028] When the output na is at a low level, the N-type transistor N4 is in a non-conductive state. At this time, the potential VP of the output node nc becomes the second potential VDD2. On the other hand, when the output na is at a high level, the N-type transistor N4 is in a conductive state. At this time, the potential VP of the output node nc becomes a potential (here, potential Va) obtained by dividing the second potential VDD2 by the resistance ratio of the resistors R1 and R2. The N-type transistor N4 is an example of a switching element that is in a conductive state when a pulse is output from the output na of the pulse generating circuit 20, and is in a non-conductive state when a pulse is not output from the output na of the pulse generating circuit 20.

[0029] NOR gate 26 receives data input signal DIN and the output of delay circuit 25 as inputs, and provides output nb to the gate of N-type transistor N5. Output nb remains high for a predetermined time after data input signal DIN transitions from high to low. In this way, inverter 24, delay circuit 25, and NOR gate 26 constitute a circuit that outputs a pulse having a predetermined pulse width when data input signal DIN transitions from high to low.

[0030] When the output nb is at a low level, the N-type transistor N5 is in a non-conductive state. At this time, the potential VP of the output node nc becomes the second potential VDD2. On the other hand, when the output nb is at a high level, the N-type transistor N5 is in a conductive state. At this time, the potential VP of the output node nc becomes the potential Va obtained by dividing the second potential VDD2 by the resistance ratio of the resistors R1 and R2. The N-type transistor N5 is an example of a switching element that is in a conductive state when a pulse is output from the output nb of the pulse generating circuit 20, and is in a non-conductive state when a pulse is not output from the output nb of the pulse generating circuit 20.

[0031] 2 is a circuit diagram of the level shift circuit 12. Note that the configuration of the level shift circuit 12 is not limited to the configuration shown in FIG.

[0032] The level shift circuit 12 in FIG. 2 receives the data input signal DIN and outputs a signal SG3 that changes in response to this data input signal DIN.

[0033] The level shift circuit 12 is connected to the first power supply VDD1 and the power supply terminal 4. The potential of the first power supply VDD1 is higher than the potential of the power supply terminal 4. As described above, the data input signal DIN transitions between the ground potential VSS and the second potential VDD2, and the signal SG3 transitions between the potential VP of the power supply terminal 4 and the first potential VDD1.

[0034] The level shift circuit 12 includes P-type transistors P11 to P15, an N-type transistor N11, and an inverter 121.

[0035] The inverter 121 receives the data input signal DIN at its input and outputs an inverted input signal DINB.

[0036] The P-type transistor P11 is provided between the first power supply VDD1 and the node LOUTB, and has its gate connected to the node LOUT. The P-type transistor P13 is provided between the node LOUTB and the power supply terminal 4, and has its gate supplied with a data input signal DIN. That is, the P-type transistors P11 and P13 are provided in series between the first power supply VDD1 and the power supply terminal 4.

[0037] The P-type transistor P12 is provided between the first power supply VDD1 and the node LOUT, and has its gate connected to the node LOUTB. The P-type transistor P14 is provided between the node LOUT and the power supply terminal 4, and has its gate supplied with the inverted input signal DINB. That is, the P-type transistors P12 and P14 are provided in series between the first power supply VDD1 and the power supply terminal 4.

[0038] The P-type transistor P15 and the N-type transistor N11 are connected in series between the first power supply VDD1 and the power supply terminal 4, and their gates and drains are connected to each other to form a waveform shaping inverter. The waveform shaping inverter receives a signal from the node LOUT, inverts the signal, and outputs it as a signal SG3.

[0039] 1 and 2 will be described using the waveform diagram in Fig. 3. For ease of understanding, Fig. 3 shows only the potential VP of the output node nc, with its change emphasized approximately three times as compared to other signals and potentials. In Fig. 3, the solid lines are waveform diagrams showing the operation of the circuit of this embodiment, and the dashed lines are waveform diagrams showing an example of the operation of the circuit of Patent Document 1.

[0040] When the data input signal DIN is at a low level, the gate signal SG1 output from the inverter 13 is at a high level (VDD1), and the P-type transistor P1 is in a non-conductive state. On the other hand, the gate signal SG2 output from the inverter 16 is at a high level (VDD2), and the N-type transistor N1 is in a conductive state. As a result, the output signal DOUT is at a low level (VSS).

[0041] In the drive assist circuit 10, the outputs na and nb are at low level (VSS), and the N-type transistors N4 and N5 are non-conductive, so that the potential VP of the output node nc is maintained at the second potential VDD2.

[0042] (Part 1) When the data input signal DIN transitions from low to high, the gate signal SG1 output from the inverter 13 transitions from high to low, and the P-type transistor P1 begins to pull up the potential of the output signal DOUT. At this time, however, in the drive assist circuit 10, the output na remains high for a predetermined period of time. When the output na is high, the N-type transistor N4 is conductive, and the potential VP of the output node nc drops from the second potential VDD2 toward the potential Va. As a result, the power supply terminal 4 drops from the second potential VDD2, and the potential of the gate signal SG1 output from the inverter 13 further drops from the second potential VDD2. When the output na returns to low, the N-type transistor N4 is non-conductive, and the potential VP of the output node nc returns to the second potential VDD2, and the potential of the gate signal SG1 also returns to the second potential VDD2. At this time, the output nb remains at a low level, and the N-type transistor N5 is off.

[0043] In the level shift circuit 12, when the data input signal DIN transitions from low to high, the inverted input signal DINB transitions from high to low, turning on the P-type transistor P14. This causes the potential of the node LOUT to transition to the voltage Va of the power supply terminal 4, making it possible to sufficiently increase the gate-source voltage Vgs of the P-type transistor P15, thereby improving the driving capability of the P-type transistor P15. This accelerates the transition of the signal SG3 from low to high.

[0044] As described above, when the data input signal DIN transitions from low to high, the potential of the gate signal SG1 received by the P-type transistor P1 is further reduced from the second potential VDD2 supplied from the external power supply for a predetermined time. This temporarily increases the gate-source voltage of the P-type transistor P1, thereby improving the driving capability of the output signal DOUT by the P-type transistor P1. Furthermore, as described above, in the level shift circuit 12, the gate-source voltage Vgs of the P-type transistor P15 can be increased sufficiently, thereby improving the driving capability of the P-type transistor P15. This allows the output signal DOUT to transition from low to high at a faster rate (see the solid line in FIG. 3 ).

[0045] (Part 2) Next, when the data input signal DIN transitions from high to low, the gate signal SG2 output from the inverter 16 transitions from low to high, and the N-type transistor N1 begins to pull down the potential of the output signal DOUT. The P-type transistor P1 also begins to transition from a conductive state to a non-conductive state. At this time, in the drive assist circuit 10, the output nb becomes high for a predetermined time. When the output nb is high, the N-type transistor N5 is conductive, and the potential VP of the output node nc decreases from the second potential VDD2 toward the potential Va. As a result, the power supply terminal 4 drops from the second potential VDD2, and the potential of the signal SG3 output from the level shift circuit 12 to the inverter 13 further drops from the second potential VDD2. When the output nb returns to a low level, the N-type transistor N5 becomes non-conductive, so that the potential VP of the output node nc returns to the second potential VDD2 and the potential of the signal SG3 also returns to the second potential VDD2. At this time, the output na remains at a low level and the N-type transistor N4 is off.

[0046] In the level shift circuit 12, when the data input signal DIN transitions from high to low, the P-type transistor P13 turns on. This causes the potential of the node LOUTB to transition to the voltage Va of the power supply terminal 4, making it possible to sufficiently increase the gate-source voltage Vgs of the P-type transistor P12, thereby improving the driving capability of the P-type transistor P12. This accelerates the transition of the potential of the node LOUT from low to high and the transition of the signal SG3 from high to low.

[0047] As described above, when the data input signal DIN transitions from high to low, the potential of the signal SG3 received by the inverter 13 is further reduced from the second potential VDD2 supplied from the external power supply for a predetermined time. This temporarily increases the gate-source voltage of the P-type transistor P3 of the inverter 13, thereby improving the driving capability of the P-type transistor P3. Furthermore, as described above, the gate-source voltage Vgs of the P-type transistor P12 in the level shift circuit 12 can also be increased sufficiently, thereby improving the driving capability of the P-type transistor P12. This increases the operating speed of the level shift circuit 12 and the inverter 13. This increases the speed of the transition of the output signal DOUT from high to low (see the solid line in FIG. 3 ).

[0048] 1 can also accommodate variations in the first potential VDD1 and the second potential VDD2 supplied from an external power supply. That is, when the first potential VDD1 decreases or the second potential VDD2 increases, the gate-source voltage of the P-type transistor P1 decreases, resulting in a decrease in drive capability. However, in this embodiment, the gate-source voltage Vgs of the P-type transistor P1 can be sufficiently increased for a predetermined time after the gate signal SG1 transitions from high to low. Similarly, the gate-source voltage Vgs of the P-type transistor P3 of the inverter 13 can be sufficiently increased for a predetermined time after the gate signal SG1 transitions from low to high, i.e., for a predetermined time after the signal SG3 transitions from high to low.

[0049] Effects of the First Embodiment According to this embodiment, in the output circuit 100, the drive assist circuit 10 performs an assist operation to temporarily lower the potential VP of the output node nc from the second potential VDD2 when the data input signal DIN makes a first transition corresponding to the transition of the gate signal SG1 from high to low. Therefore, when the gate signal SG1 transitions from high to low, causing the P-type transistor P1 to become conductive and drive the output signal DOUT, the assist operation of the drive assist circuit 10 can temporarily increase the gate-source voltage of the P-type transistor P1. This improves the driving capability of the P-type transistor P1, thereby speeding up the transition of the output signal DOUT from low to high. This allows the output circuit 10 to operate at high speed without increasing the size of the P-type transistor P1.

[0050] Furthermore, when the data input signal DIN makes a second transition corresponding to the transition of the gate signal SG1 from low to high, the drive assist circuit 10 performs an assist operation to temporarily lower the potential VP of the output node nc from the second potential VDD2. This increases the operating speed of the inverter 13, thereby speeding up the transition of the output signal DOUT from low to high. Therefore, high-speed operation of the output circuit 100 can be achieved without increasing the size of the P-type transistor P1.

[0051] Furthermore, in this embodiment, a signal that transitions between the first potential VDD1 and the potential VP of the power supply terminal 4 in response to the data input signal DIN is provided to the inverter 13. This improves the operating speed of the level shift circuit 12 both when the data input signal DIN makes the first transition and when it makes the second transition, thereby enabling the output circuit 100 to operate at a high speed.

[0052] 1, the resistor string RR is configured with two resistor sections R1 and R2, but this is not limited to this. For example, the resistor string RR may be configured with a plurality of resistor sections connected in series, and one of the connection nodes between the resistor sections may be used as the output node nc. Furthermore, the resistor sections that make up the resistor string RR may be realized by combining a plurality of resistor elements, or may be realized using transistor resistors.

[0053] In addition, in the configuration of FIG. 1, the level shift circuit 12 receives the first potential VDD1 and the potential VP supplied to the power supply terminal 4, but the level shift circuit 12 may also receive the second potential VDD2 instead of the potential VP supplied to the power supply terminal 4.

[0054] Second Embodiment FIG. 4 is a circuit diagram of an output circuit according to a second embodiment. In FIG. 4, components corresponding to those in FIG. 1 are assigned common reference numerals. The following description will focus on differences from the first embodiment. Note that there is no intention to limit the configurations and various design parameters / process parameters, etc., of blocks and elements (e.g., transistors, resistors, etc.) assigned the same reference numerals in FIGS. 1 and 4 to those elements. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements assigned the same reference numerals in FIGS. 1 and 4 differ from each other. The same applies to the relationships between the other drawings.

[0055] The output circuit 100 of FIG. 4 differs from the output circuit 100 of FIG. 1 in the internal configuration of the drive assist circuit 10.

[0056] 4, the drive assist circuit 10 includes N-type transistors N4, N5, and N6 whose sources are connected to the ground VSS, a resistor string RR, and a pulse generating circuit 20. The drain of the N-type transistor N4 and the drain of the N-type transistor N5 are connected at a connection node nd.

[0057] The resistor string RR is made up of resistor units R1 and R2 connected in series and is provided between the second power supply VDD2 and a connection node nd. The connection node of the resistor units R1 and R2 serves as the output node nc of the drive assist circuit 10.

[0058] The pulse generating circuit 20 includes inverters 21 and 24 that receive a data input signal DIN, two-stage (series-connected) delay circuits 22A and 22B that receive the output signal of the inverter 21, two-stage (series-connected) delay circuits 25A and 25B that receive the output signal of the inverter 24, AND gates 23 and 27, NOR gates 26 and 28, and an OR gate 29.

[0059] The AND gate 23 receives the data input signal DIN and the output of the second-stage delay circuit 22B as inputs, and its output na is provided to the gate of the N-type transistor N4. The output na remains high for a predetermined time after the data input signal DIN transitions from low to high. In this manner, the inverter 21, the delay circuits 22A and 22B, and the AND gate 23 constitute a pulse generation circuit that outputs a pulse having a predetermined pulse width when the data input signal DIN transitions from low to high. As in the first embodiment, the N-type transistor N4 is an example of a switching element that is conductive when a pulse is output from the output na of the pulse generation circuit 20 and is non-conductive when no pulse is output from the output na of the pulse generation circuit.

[0060] The NOR gate 26 receives the data input signal DIN and the output of the second-stage delay circuit 25B as inputs, and its output nb is provided to the gate of the N-type transistor N5. The output nb remains high for a predetermined time after the data input signal DIN transitions from high to low. In this manner, the inverter 24, the delay circuits 25A and 25B, and the NOR gate 26 constitute a circuit that outputs a pulse having a predetermined pulse width when the data input signal DIN transitions from high to low. As in the first embodiment, the N-type transistor N5 is an example of a switching element that is conductive when a pulse is output from the output nb of the pulse generation circuit 20 and is non-conductive when no pulse is output from the output nb of the pulse generation circuit.

[0061] N-type transistor N6 is provided between output node nc and ground VSS. AND gate 27 receives data input signal DIN and the output of first-stage delay circuit 22A as inputs, and its output ne is provided to the input of OR gate 29. NOR gate 28 receives data input signal DIN and the output of first-stage delay circuit 25A as inputs, and its output nf is provided to the input of OR gate 29. OR gate 29 receives outputs ne and nf as inputs, and its output ng is provided to the gate of N-type transistor N6.

[0062] That is, the inverter 21, the delay circuit 22A, and the AND gate 27 constitute a circuit that outputs a second pulse to the node output ne when the data input signal DIN transitions from a low level to a high level. The inverter 24, the delay circuit 25A, and the NOR gate 28 constitute a circuit that outputs a second pulse to the output nf when the data input signal DIN transitions from a high level to a low level. In other words, the inverters 21 and 24, the delay circuits 22A and 25A, the AND gate 27, and the NOR gate 28 constitute a second pulse generating circuit that outputs a second pulse when the data input signal DIN transitions from a low level to a high level or from a high level to a low level. The pulse width of the second pulse output from the second pulse generating circuit is shorter than the pulse width of the pulse output from the pulse generating circuit constituted by the inverters 21 and 24, the delay circuits 22A, 22B, 25A, and 25B, the AND gate 23, and the NOR gate 26.

[0063] The signal obtained by ORing the outputs ne and nf in the OR gate 29 is then applied to the gate of the N-type transistor N6. Therefore, the N-type transistor N6 is an example of a second switching element that is turned on when the second pulse is output from the second pulse generating circuit and is turned off when the second pulse is not output from the second pulse generating circuit.

[0064] In this embodiment, the drive assist circuit 10 lowers the potential VP of the output node nc through two paths, that is, a path via N-type transistors N4 and N5 and a path via N-type transistor N6.

[0065] --Operation of the Output Circuit--(Part 1) First, the operation of the data input signal DIN transitioning from low level to high level will be described.

[0066] As shown in the waveform diagram of FIG. 5 , the output na of the pulse generating circuit 20 remains high for a predetermined time after the data input signal DIN transitions from low to high. The output ne remains high for a shorter time than the output na after the data input signal DIN transitions from low to high. Therefore, when the data input signal DIN initially transitions from low to high, both outputs na and ne are high, causing both N-type transistors N4 and N6 to be conductive. This rapidly reduces the potential VP of the output node nc. After that, when the output ne transitions to low, the N-type transistor N6 becomes non-conductive, and the potential VP of the output node nc is reduced solely by the N-type transistor N4. The potential VP then becomes the potential Va obtained by dividing the second potential VDD2 by the resistance ratio of the resistors R1 and R2.

[0067] (Part 2) Next, the operation of the data input signal DIN transitioning from high level to low level will be described.

[0068] As shown in the waveform diagram of FIG. 5 , the output nb of the pulse generating circuit 20 remains high for a predetermined time after the data input signal DIN transitions from high to low. Furthermore, the output nf remains high for a shorter time than the time of the output nb after the data input signal DIN transitions from high to low. Therefore, when the data input signal DIN initially transitions from low to high, both outputs nb and nf are high, causing both N-type transistors N5 and N6 to become conductive. This causes the potential VP of the output node nc to be rapidly pulled down. After that, when the output nf transitions to low, the N-type transistor N6 becomes non-conductive, and the potential VP of the output node nc is pulled down only by the N-type transistor N5. The potential VP then becomes the potential Va obtained by dividing the second potential VDD2 by the resistance ratio of the resistors R1 and R2.

[0069] Effects of the Second Embodiment: In this embodiment, similar to the first embodiment, when the data input signal DIN makes a first transition corresponding to the transition of the gate signal SG1 from high to low, the potential of the gate signal SG1 received by the P-type transistor P1 is further reduced from the second potential VDD2 supplied from the external power supply for a predetermined time. This temporarily increases the gate-source voltage Vgs of the P-type transistor P1, thereby improving the driving capability of the output signal DOUT by the P-type transistor P1. This therefore increases the speed of the transition of the output signal DOUT from low to high.

[0070] Furthermore, in this embodiment, the fall of the output node nc at the beginning of the first transition is accelerated, so that the gate-source voltage and driving capability of the P-type transistor P1 can be increased quickly, thereby increasing the speed of the circuit. Also, the N-type transistor N6 becomes non-conductive midway, making the transition gentler, so that ringing noise caused by a sudden voltage change can be suppressed.

[0071] Furthermore, when the data input signal DIN makes a second transition corresponding to the transition of the gate signal SG1 from low level to high level, the drive assist circuit 10 performs an assist operation to temporarily lower the potential VP of the output node nc from the second potential VDD2. This increases the operating speed of the inverter 13, thereby enabling the output signal DOUT to transition from high level to low level at a higher speed.

[0072] Furthermore, in this embodiment, the fall of the output node nc at the beginning of the first transition is accelerated, so that the gate-source voltage and driving capability of the P-type transistor P3 of the inverter 13 can be increased quickly, thereby increasing the speed of the output circuit 100. Also, the N-type transistor N6 becomes non-conductive midway, making the transition gentler, so that ringing noise caused by a sudden voltage change can be suppressed.

[0073] Furthermore, in this embodiment, the potential VP of the output node nc can be lowered quickly and with high precision. In the configuration of the first embodiment, in order to lower the potential VP quickly, it is necessary to reduce the resistance of the resistor portions R1 and R2 of the resistor string RR. However, in a semiconductor device, reducing the resistance requires increasing the element size, which increases the circuit area. In this embodiment, the potential VP can be lowered quickly by the N-type transistor N6, and the final potential Va can be set with high precision by the resistor string RR. As a result, the resistor portions R1 and R2 of the resistor string RR can have high resistance, thereby suppressing an increase in the circuit area.

[0074] (Third Embodiment) Fig. 6 is a circuit configuration diagram of an output circuit according to a third embodiment. In Fig. 6, components corresponding to those in the output circuit 100 of Fig. 4 are assigned the same reference numerals. The following description will focus on the differences from the second embodiment.

[0075] Compared to the output circuit 100 of FIG. 4 , the output circuit 100 of FIG. 6 has a configuration that feeds back changes in the output signal DOUT to the drive assist circuit 10. Specifically, the output circuit 100 includes a latch circuit 18 that receives the potential of the connection node nh between the N-type transistors N1 and N2, and a delay circuit 19 that receives the output of the latch circuit 18. The signal output from the delay circuit 19 is provided as an additional input to three-input AND gates 23 and 27 and three-input NOR gates 26 and 28 as a monitor signal SM that detects changes in the output signal DOUT. The latch circuit 18 and the delay circuit 19 form a monitor circuit that monitors changes in the output signal DOUT and outputs a monitor signal SM that changes in response to the output signal DOUT. Furthermore, in the drive assist circuit 10 of FIG. 6 , the AND gates 23 and 27 are three-input circuits, and the NOR gates 26 and 28 are three-input circuits.

[0076] As shown in the waveform diagram of FIG. 7 , when the output signal DOUT transitions from low to high, the monitor signal SM transitions from high to low when the potential of the connection node nh rises to a predetermined level. However, the timing of this transition is adjusted by the delay circuit 19. This change in the monitor signal SM indicates that the output signal DOUT has transitioned from low to high. As described in the second embodiment, the potential VP at the output node nc of the drive assist circuit 10 is pulled down after the data input signal DIN transitions from low to high. However, when the monitor signal SM transitions from high to low, the output na of the AND gate 23, the output nb of the NOR gate 26, the output ne of the AND gate 27, and the output nf of the NOR gate 28 are all forced to low, and the potential VP of the output node nc returns to the second potential VDD2.

[0077] Effects of the Third Embodiment According to the third embodiment, similar to the second embodiment, the transition of the output signal DOUT from low to high and from high to low can be accelerated. Furthermore, the potential VP of the output node nc can be reduced quickly and accurately.

[0078] Furthermore, in this embodiment, by feeding back the signal SM to the drive assist circuit 10, when the output signal DOUT is driven at high speed, the assist operation by the drive assist circuit 10 can be stopped. This makes it possible to suppress excess current consumption in the drive assist circuit 10.

[0079] In this embodiment, the potential of the connection node nh between the N-type transistor N1 and the N-type transistor N2 is monitored to detect a change in the output signal DOUT, but the method for detecting a change in the output signal DOUT is not limited to this. For example, the output signal DOUT may be monitored directly, or, if a circuit section that receives the output signal DOUT as an input exists in the LSI, the change in the output signal DOUT may be monitored from that circuit section.

[0080] Other Embodiments The technology of the present disclosure is not limited to the configurations described in the above embodiments, and many modifications, such as changes, substitutions, additions, and omissions, are possible by a person of ordinary skill in the art within the technical spirit of the present disclosure. Furthermore, new embodiments can be created by combining the components described in the above embodiments.

[0081] For example, in the configuration of the first embodiment, a configuration in which a change in the output signal DOUT is fed back as disclosed in the third embodiment may be applied.

[0082] -Modification- Fig. 8 is a circuit diagram of an output circuit according to a modification of the first embodiment. In Fig. 8, components corresponding to those in Fig. 1 are assigned the same reference numerals. The following explanation will focus on the differences from the first embodiment.

[0083] In the first embodiment, a case where the data input signal DIN transitions between the ground potential VSS and the second potential VDD2 has been described. Fig. 8 shows an example of the configuration of the output circuit 100 when a data input signal DIN having an amplitude smaller than the ground potential VSS to the second potential VDD2 is input. Specifically, in the example of Fig. 8, the data input signal DIN transitions between the ground potential VSS and the third potential VDD3 (VDD3<VDD2).

[0084] 8 includes a level shift circuit 11 in addition to the configuration of FIG. 1. The level shift circuit 11 receives a data input signal DIN of low amplitude (for example, transitioning between the ground potential VSS and the third potential VDD3), converts it into a signal SA (corresponding to an assist signal) transitioning between the ground potential VSS and the second potential VDD2, and outputs it. Then, instead of the data input signal DIN of the first embodiment, the signal SA is provided to the level shift circuit 12 and the drive assist circuit 10. The rest of the configuration is the same as in the first embodiment, and the same effects as in the first embodiment can be obtained.

[0085] The present disclosure makes it possible to realize an output circuit capable of high-speed operation without increasing the circuit area, which is effective for increasing the speed and reducing the area of ​​an LSI, for example.

[0086] 1 Output terminal 4 Power supply terminal 10 Drive assist circuit 12 Level shift circuit 20 Pulse generation circuit 13 Inverter (pre-driver) 100 Output circuit DIN Data input signal (assist signal) DOUT Output signal N4 N-type transistor (switching element) N5 N-type transistor (switching element) N6 N-type transistor (second switching element) P1 P-type transistor (first transistor) P2 P-type transistor RR Resistor string SA Signal (assist signal) SM Monitor signal VDD1 First power supply VDD2 Second power supply VP Potential supplied to power supply terminal VSS Ground (third power supply, ground power supply) n1 First node nc Output node

Claims

1. An output circuit that receives a data input signal and outputs an output signal that changes in response to the data input signal, the output circuit comprising: - an output terminal that outputs the output signal; - a P-type first transistor having a source connected to a first power supply that provides a first potential and a drain connected to a first node; - a P-type second transistor having a source connected to the first node and a drain connected to the output terminal; - a level shift circuit that is connected between the first power supply and a power supply terminal to which a potential lower than the first potential is supplied, receives the data input signal or a signal that changes in response to the data input signal, and outputs a signal that transitions between the first potential and the potential of the power supply terminal in response to the data input signal; - a pre-driver that is connected between the first power supply and the power supply terminal, receives the signal output from the level shift circuit, and supplies, as a gate signal, a transition signal that transitions between the first potential and the potential of the power supply terminal in response to the received signal to the gate of the first transistor; - a drive assist circuit that is connected to a second power supply that provides a second potential lower than the first potential and a third power supply that provides a third potential lower than the second potential, and supplies the second potential from an output node to the power supply terminal. - The drive assist circuit receives the data input signal or a signal that changes in response to the data input signal as an assist signal, and performs an assist operation of temporarily lowering the potential of the output node from the second potential when the assist signal makes a first transition corresponding to a transition of the gate signal from a high level to a low level, or when the assist signal makes a second transition corresponding to a transition of the gate signal from a low level to a high level.

2. In the output circuit according to claim 1, the drive assist circuit includes: a pulse generation circuit that receives the assist signal and outputs a pulse having a predetermined pulse width when the assist signal makes the first transition or when the assist signal makes the second transition; a resistor string including a plurality of resistive portions connected in series, one end of which is connected to the second power supply, and any one of the connection nodes between the resistive portions serves as the output node; and a switching element provided between the other end of the resistor string and the ground power supply, which receives the output of the pulse generation circuit and becomes conductive when the pulse is output from the pulse generation circuit and becomes non-conductive when the pulse is not output from the pulse generation circuit. The output circuit is characterized by the above.

3. In the output circuit according to claim 2, the drive assist circuit includes: a second pulse generation circuit that receives the assist signal and outputs a second pulse having a shorter pulse width than the pulse when the assist signal makes the first transition or when the assist signal makes the second transition; and a second switching element provided between the output node and the ground power supply, which receives the output of the second pulse generation circuit and becomes conductive when the second pulse is output from the second pulse generation circuit and becomes non-conductive when the second pulse is not output from the second pulse generation circuit. The output circuit is characterized by the above.

4. In the output circuit according to claim 1, the output circuit includes a monitor circuit that monitors a change in the output signal and outputs a monitor signal that changes according to the output signal. The drive assist circuit receives the monitor signal and stops the assist operation when a change indicating that the output signal has transitioned from a low level to a high level occurs in the monitor signal after the assist operation is started by the first transition of the assist signal, or when a change indicating that the output signal has transitioned from a high level to a low level occurs in the monitor signal after the assist operation is started by the second transition of the assist signal.

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