Solid-state imaging device and electronic apparatus

Abstract

[Problem] To achieve both conversion efficiency and noise reduction. [Solution] This solid-state imaging device comprises: a photoelectric conversion unit for generating, by photoelectric conversion, a charge according to the amount of received light; a charge accumulation unit for accumulating charges generated by the photoelectric conversion unit; a selection transistor for selecting whether or not to output a signal amplified by an amplification transistor; first wiring for electrically connecting the charge accumulation unit and the gate of the amplification transistor; and second wiring on an output signal line side, in the amplification transistor, to which the signal amplified by the amplification transistor is outputted. The second wiring is disposed in at least a portion of a space between the first wiring and a signal line.

Description

Solid-state imaging device and electronic device

[0001] Embodiments of the present disclosure relate to a solid-state imaging device and an electronic device.

[0002] In solid-state imaging devices such as back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensors, the floating diffusion may crosstalk with other wiring. In this case, voltage fluctuations in the other wiring may cause noise. To suppress crosstalk and reduce noise, shield wiring may be provided between the floating diffusion and the other wiring (see Patent Documents 1 and 2).

[0003] Japanese Patent Application Laid-Open No. 2021-106360 Japanese Patent Application Laid-Open No. 2018-207100 Japanese Patent Application Laid-Open No. 2011-138841 International Publication No. 2021 / 100338 Japanese Patent Application Laid-Open No. 2018-182709 Japanese Patent Application Laid-Open No. 2023-22747

[0004] However, the conversion efficiency may be reduced due to capacitive coupling between the floating diffusion and the shield wiring.

[0005] Therefore, the present disclosure provides a solid-state imaging device and electronic device that can achieve both high conversion efficiency and noise reduction.

[0006] In order to solve the above problem, according to the present disclosure, there is provided a solid-state imaging device comprising: a photoelectric conversion unit that generates charges according to the amount of received light through photoelectric conversion; a charge accumulation unit that accumulates the charges generated by the photoelectric conversion unit; an amplification transistor that amplifies a signal based on the charges accumulated in the charge accumulation unit; a first wiring that electrically connects the charge accumulation unit and a gate of the amplification transistor; and a second wiring on the output signal line side of the amplification transistor that outputs the signal amplified by the amplification transistor, wherein the second wiring is arranged at least partially between the first wiring and the signal line.

[0007] The semiconductor device may further include a selection transistor that selects whether or not to output the signal amplified by the amplification transistor, and the second wiring may electrically connect the amplification transistor and the selection transistor.

[0008] The second wiring may be arranged at least partially between the first wiring arranged in a first wiring layer and the signal line arranged in the first wiring layer.

[0009] The second wiring arranged in the first wiring layer may extend in a first direction substantially parallel to the first wiring layer, and may be longer than the length of the first wiring arranged in the first wiring layer.

[0010] The second wiring arranged in the first wiring layer may substantially surround the first wiring arranged in the first wiring layer.

[0011] The first wiring may be arranged across a plurality of wiring layers including the first wiring layer.

[0012] The first wiring may include a plurality of pads arranged on each of a plurality of wiring layers, and vias connecting the pads.

[0013] The second wiring may be arranged in a plurality of wiring layers including the first wiring layer.

[0014] The second wiring may be arranged in wiring layers whose number is one or more greater than the number of wiring layers in which the signal lines are arranged.

[0015] The semiconductor device may further include a first chip on which the photoelectric conversion unit is arranged, and a second chip stacked on the first chip and on which the amplification transistor is arranged, wherein the first wiring connects the first chip and the second chip.

[0016] The signal line and the second wiring may be disposed on the second chip.

[0017] The signal line may be the output signal line or a multi-value signal line to which a plurality of different voltages are applied.

[0018] The image sensor may further include a transfer section that transfers the charges generated by the photoelectric conversion section to the charge accumulation section, and a reset section that resets the charges accumulated in the charge accumulation section.

[0019] The second wiring may be electrically connected to a body of the amplification transistor.

[0020] The semiconductor device may further include an additional capacitance that adds capacitance to the charge storage unit, and a switching unit that switches the connection state between the charge storage unit and the additional capacitance, and the second wiring may not be arranged between the additional capacitance and the signal line.

[0021] The second wiring may be disposed at least partially between the first wiring and the signal line in a direction substantially perpendicular to a substrate on which the charge accumulation section is provided.

[0022] The semiconductor device may further include a third wiring to which a control signal or a fixed potential is supplied, the third wiring being disposed at least partially between the second wiring and the signal line.

[0023] According to the present disclosure, there is provided an electronic device comprising: a photoelectric conversion unit that generates charges according to the amount of received light through photoelectric conversion; a charge accumulation unit that accumulates the charges generated by the photoelectric conversion unit; an amplification transistor that amplifies a signal based on the charges accumulated in the charge accumulation unit; a first wiring that electrically connects the charge accumulation unit and a gate of the amplification transistor; and a second wiring on the output signal line side of the amplification transistor that outputs the signal amplified by the amplification transistor, wherein the second wiring is arranged at least partially between the first wiring and a signal line.

[0024] 1 is a block diagram showing a schematic configuration of an imaging device according to an embodiment; FIG. 2 is an equivalent circuit diagram of a sensor pixel and a readout circuit; FIG. 3 is a cross-sectional view of a sensor pixel and a readout circuit according to a first embodiment; FIG. 4 is a plan view of a sensor pixel and a readout circuit according to a second embodiment; FIG. 5 is a plan view of a sensor pixel and a readout circuit according to a third embodiment; FIG. 6 is a plan view of a sensor pixel and a readout circuit according to a fourth embodiment; FIG. 7 is a plan view of a sensor pixel and a readout circuit according to a fifth embodiment; FIG. 8 is a plan view of a sensor pixel and a readout circuit according to a sixth embodiment; FIG. 9 is a plan view of a sensor pixel and a readout circuit according to a seventh embodiment; FIG. 10 is a plan view of a sensor pixel and a readout circuit according to an eleventh embodiment; FIG. 12 is a plan view of a sensor pixel and a readout circuit according to a thirteenth embodiment; FIG. 13 is a plan view of a sensor pixel and a readout circuit according to a fourteenth embodiment; FIG. 14 is a plan view of a sensor pixel and a readout circuit according to a fifteenth embodiment; and FIG. 15 is a plan view of a sensor pixel and a readout circuit according to a sixteenth embodiment. 16 is a plan view of a sensor pixel and a readout circuit according to a seventeenth embodiment. 17 is a plan view of a sensor pixel and a readout circuit according to an eighteenth embodiment. 18 is a cross-sectional view of a sensor pixel and a readout circuit according to an eighteenth embodiment. 19 is a cross-sectional view of a sensor pixel and a readout circuit according to a nineteenth embodiment. 19 is a cross-sectional view of a sensor pixel and a readout circuit according to a twentieth embodiment. 20 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-first embodiment. 21 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-second embodiment. 22 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-third embodiment. 23 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-fourth embodiment. 24 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-fifth embodiment. 25 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-sixth embodiment. 26 is a cross-sectional view of a sensor pixel and a readout circuit according to a twenty-seventh embodiment.10 is a cross-sectional view of a sensor pixel and a readout circuit according to the 28th embodiment. 11 is a cross-sectional view of a sensor pixel and a readout circuit according to the 29th embodiment. 12 is a cross-sectional view of a sensor pixel and a readout circuit according to the 30th embodiment. 13 is a cross-sectional view of a sensor pixel and a readout circuit according to the 31st embodiment. 14 is a cross-sectional view of a sensor pixel and a readout circuit according to the 32nd embodiment. 15 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 33rd embodiment. 16 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 34th embodiment. 17 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 35th embodiment. 18 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 36th embodiment. 19 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 37th embodiment. 19 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 38th embodiment. 20 is an equivalent circuit diagram of a sensor pixel and a readout circuit according to the 39th embodiment. 21 is a plan view of a sensor pixel and a readout circuit according to the 40th embodiment. 22 is a cross-sectional view of a sensor pixel and a readout circuit according to the 41st embodiment. 23 is a plan view of a sensor pixel and a readout circuit according to the 42nd embodiment. 24 is a plan view of a sensor pixel and a readout circuit according to the 43rd embodiment. 10 is a plan view of a sensor pixel and a readout circuit according to the 44th embodiment. 11 is a plan view of a sensor pixel and a readout circuit according to the 45th embodiment. 12 is a cross-sectional view of a sensor pixel and a readout circuit according to the 46th embodiment. 13 is a cross-sectional view of a sensor pixel and a readout circuit according to the 47th embodiment. 14 is a cross-sectional view of a sensor pixel and a readout circuit according to the 48th embodiment. 15 is a cross-sectional view of a sensor pixel and a readout circuit according to the 49th embodiment. 16 is a cross-sectional view of a sensor pixel and a readout circuit according to the 50th embodiment. 17 is a cross-sectional view of a sensor pixel and a readout circuit according to the 51st embodiment. 18 is a schematic diagram showing an example of the overall configuration of an electronic device. 19 is a block diagram showing an example of the general configuration of a vehicle control system. 20 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0025] Hereinafter, embodiments of a solid-state imaging device and an electronic device will be described with reference to the drawings. The following description will focus on the main components of the solid-state imaging device and the electronic device, but the solid-state imaging device and the electronic device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0026] First Embodiment Hereinafter, an embodiment of the present disclosure will be described in detail. An imaging device of the present disclosure is, for example, a global shutter back-illuminated image sensor using a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like. The imaging device of the present disclosure receives light from a subject for each pixel, performs photoelectric conversion, and generates a pixel signal, which is an electrical signal.

[0027] The global shutter method is a method in which exposure of all pixels starts and ends simultaneously. Here, "all pixels" refers to all pixels that form a valid image, excluding dummy pixels that do not contribute to image formation. Also, simultaneous exposure is not necessary as long as the image distortion and exposure time difference are small enough to not cause problems. For example, the global shutter method also includes a case in which the operation of simultaneously exposing multiple rows (several dozen rows, for example) is repeated while shifting the rows in units of multiple rows in the row direction. The global shutter method also includes a case in which simultaneous exposure is performed on only a portion of the pixel area.

[0028] A back-illuminated image sensor is an image sensor in which a photoelectric conversion unit such as a photodiode that receives light from a subject and converts it into an electrical signal is arranged for each pixel between a light-receiving surface where light from a subject is incident and a wiring layer where wiring such as transistors that drive each pixel is provided. Note that the present disclosure may also be applicable to image sensors of imaging methods other than CMOS image sensors.

[0029] (Block Configuration of Imaging Device 101) FIG. 1 is a block diagram showing a schematic configuration of an imaging device 101 according to an embodiment of the present disclosure. The imaging device 101 in FIG. 1 is formed on a semiconductor substrate 11, and therefore is technically a solid-state imaging device 101, but will be simply referred to as the imaging device 101 hereinafter. The imaging device 101 in FIG. 1 includes a pixel array unit 111 in which a plurality of sensor pixels 121 that perform photoelectric conversion are arranged in a matrix, i.e., in a two-dimensional plane. The sensor pixels 121 correspond to a specific example of a "pixel" in the present disclosure. Pixel signals photoelectrically converted by the pixel array unit 111 are read out via a readout circuit.

[0030] The imaging device 101 includes, for example, a pixel array section 111, a vertical driving section 112, a ramp wave module 113, a column signal processing section 114, a clock module 115, a data storage section 116, a horizontal driving section 117, a system control section 118, and a signal processing section 119.

[0031] The imaging device 101 is configured with a single or multiple semiconductor substrates 11. For example, the imaging device 101 can be configured by electrically connecting, to a semiconductor substrate 11 on which a pixel array section 111 is formed, another semiconductor substrate 11 on which a vertical drive section 112, a ramp wave module 113, a column signal processing section 114, a clock module 115, a data storage section 116, a horizontal drive section 117, a system control section 118, a signal processing section 119, etc. are formed, by Cu-Cu bonding or the like.

[0032] The pixel array unit 111 has a plurality of sensor pixels 121, each including a photoelectric conversion element that generates and accumulates an electric charge corresponding to the amount of light incident from a subject. The sensor pixels 121 are arranged in both a horizontal direction (row direction) and a vertical direction (column direction), as shown in Fig. 1. In the pixel array unit 111, a pixel drive line 122 is wired along the row direction for each pixel row made up of sensor pixels 121 arranged in a column in the row direction, and a vertical signal line 123 is wired along the column direction for each pixel column made up of sensor pixels 121 arranged in a column direction.

[0033] The vertical drive unit 112 includes a shift register, an address decoder, etc. The vertical drive unit 112 supplies signals and the like to the plurality of sensor pixels 121 via the plurality of pixel drive lines 122, thereby driving all of the plurality of sensor pixels 121 in the pixel array unit 111 simultaneously or driving them in units of pixel rows.

[0034] The ramp module 113 generates a ramp signal used for A / D (Analog / Digital) conversion of the pixel signal and supplies it to the column signal processing unit 114. The column signal processing unit 114 is composed of, for example, a shift register, an address decoder, etc., and performs noise removal processing, correlated double sampling processing, A / D conversion processing, etc. to generate a pixel signal. The column signal processing unit 114 supplies the generated pixel signal to the signal processing unit 119.

[0035] The clock module 115 supplies clock signals for operation to each part of the image capturing apparatus 101 .

[0036] The horizontal driving unit 117 sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 114. Through selective scanning by this horizontal driving unit 117, pixel signals that have been signal-processed for each unit circuit in the column signal processing unit 114 are output to the signal processing unit 119 sequentially.

[0037] The system control unit 118 includes a timing generator that generates various timing signals, etc. The system control unit 118 controls the driving of the vertical driving unit 112, the ramp wave module 113, the column signal processing unit 114, the clock module 115, and the horizontal driving unit 117 based on the timing signals generated by the timing generator.

[0038] The signal processing unit 119 performs signal processing such as arithmetic processing on the pixel signals supplied from the column signal processing unit 114, while temporarily storing data in the data storage unit 116 as necessary, and outputs an image signal consisting of each pixel signal.

[0039] (Circuit Configuration of Readout Circuit 120) FIG. 2 is an equivalent circuit diagram of the sensor pixel 121 and the readout circuit 120. As shown in FIG.

[0040] 2, the readout circuit 120 includes three transfer transistors TRZ, TRX, and TRG, a discharge transistor OFG, a reset transistor RST, a switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. These transistors are N-type MOS transistors. The reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL are formed on and bonded to a semiconductor substrate separate from the semiconductor substrate 11 on which the pixel array section 111 is arranged.

[0041] The following mainly describes an example in which a photodiode PD is used as the photoelectric conversion unit 51. The transfer transistor TRZ is connected to the photodiode PD in the sensor pixel 121, and transfers the charge (pixel signal) photoelectrically converted by the photodiode PD to the transfer transistor TRX. The transfer transistor TRZ is assumed to be a vertical transistor, and has a vertical gate electrode.

[0042] A charge holding unit (MEM) 54 is connected to the transfer transistor TRX. The potential of the charge holding unit (MEM) 54 is controlled by a control signal applied to the gate electrode of the transfer transistor TRX. For example, when the transfer transistor TRX is turned on, the potential of the charge holding unit (MEM) 54 becomes deeper, and when the transfer transistor TRX is turned off, the potential of the charge holding unit (MEM) 54 becomes shallower. Then, for example, when the transfer transistors TRZ and TRX are turned on, the charge stored in the photodiode PD is transferred to the charge holding unit (MEM) 54 via the transfer transistors TRZ and TRX. The drain of the transfer transistor TRX is electrically connected to the source of the transfer transistor TRG, and the gate of the transfer transistor TRX is connected to a pixel drive line.

[0043] The charge holding unit (MEM) 54 is an area that temporarily holds the charge accumulated in the photodiode PD in order to realize a global shutter function. The charge holding unit (MEM) 54 holds the charge transferred from the photodiode PD.

[0044] The transfer transistor TRG is connected between the transfer transistor TRX and the floating diffusion FD, and transfers the charges held in the charge holding unit (MEM) 54 to the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the transfer transistor TRX is turned off and the transfer transistor TRG is turned on, the charges held in the charge holding unit (MEM) 54 are transferred to the floating diffusion FD. The drain of the transfer transistor TRG is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TRG is connected to a pixel drive line.

[0045] The floating diffusion FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD via the transfer transistor TRG. The floating diffusion FD is connected to, for example, a reset transistor RST via a switching transistor FDG, and is also connected to a vertical signal line VSL via an amplification transistor AMP and a selection transistor SEL.

[0046] The drain transistor OFG initializes (resets) the photodiode PD in response to a control signal applied to its gate electrode. The drain of the drain transistor OFG is connected to the power supply line VDD, and the source is connected between the transfer transistor TRZ and the transfer transistor TRX.

[0047] For example, when the transfer transistor TRZ and the drain transistor OFG are turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. That is, the photodiode PD is initialized. Furthermore, the drain transistor OFG forms an overflow path between the transfer transistor TRZ and the power supply line VDD, and drains the charge overflowing from the photodiode PD to the power supply line VDD.

[0048] The reset transistor RST initializes (resets) each region from the charge holding unit (MEM) 54 to the floating diffusion FD in response to a control signal applied to the gate electrode. The drain of the reset transistor RST is connected to the power supply line VDD, and the source is connected to the floating diffusion FD. For example, when the transfer transistor TRG and the reset transistor RST are turned on, the potentials of the charge holding unit (MEM) 54 and the floating diffusion FD are reset to the potential level of the power supply line VDD. In other words, turning on the reset transistor RST initializes the charge holding unit (MEM) 54 and the floating diffusion FD.

[0049] The switching transistor FDG switches the connection state between the floating diffusion FD and an additional capacitance (not shown), thereby switching the conversion efficiency when converting the charge accumulated in the floating diffusion FD into a voltage.

[0050] The amplifier transistor AMP has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as an input part of a source follower circuit that reads out charges obtained by photoelectric conversion in the photodiode PD. That is, the amplifier transistor AMP has a source connected to the vertical signal line VSL via the selection transistor SEL, and thereby forms a source follower circuit together with a constant current source connected to one end of the vertical signal line VSL.

[0051] The selection transistor SEL is connected between the source of the amplification transistor AMP and the vertical signal line VSL, and a control signal is supplied to the gate electrode of the selection transistor SEL as a selection signal. When the control signal is turned on, the selection transistor SEL becomes conductive, and the sensor pixel 121 connected to the selection transistor SEL becomes selected. When the sensor pixel 121 becomes selected, the pixel signal output from the amplification transistor AMP is read out to the column signal processing circuit 22 via the vertical signal line VSL.

[0052] The wiring SELAMP is connected to a node between the amplification transistor AMP and the selection transistor SEL, and electrically connects the amplification transistor AMP and the selection transistor SEL.

[0053] The imaging device 101 further includes a first chip CH1 and a second chip CH2. The second chip CH2 is stacked on the first chip CH1, as will be described later with reference to FIG.

[0054] The first chip CH1 is, for example, a pixel substrate, and includes a photodiode PD, a drain transistor OFG, and transfer transistors TRG, TRX, and TRZ.

[0055] The second chip CH2 is, for example, a pixel transistor substrate. The second chip CH2 includes a reset transistor RST, a switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. The second chip CH2 also includes a vertical signal line VSL and a wiring SELAMP.

[0056] In the example shown in FIG. 2, a floating diffusion FD is provided in each of the first chip CH1 and the second chip CH2.

[0057] The FD wiring FDW is a wiring connected to the floating diffusion FD, and electrically connects the floating diffusion FD and the gate of the amplification transistor.

[0058] (Cross-sectional structure of the imaging device 101) FIG. 3 is a cross-sectional view of the sensor pixel 121 and the readout circuit 120 according to the first embodiment.

[0059] The first chip CH1 and the second chip CH2 are joined at a joining surface S.

[0060] One end of the FD wiring FDW is connected to the floating diffusion FD provided on the first chip CH1. The other end of the FD wiring FDW is connected to the gate of the amplification transistor AMP provided on the second chip CH2. Therefore, the FD wiring FDW is provided to penetrate the first chip CH1 and the second chip CH2, connecting the first chip CH1 and the second chip CH2. The FD wiring FDW provided on the first chip CH1 side and the FD wiring FDW provided on the second chip CH2 side are connected to each other at the bonding surface S by, for example, Cu-Cu bonding.

[0061] The FD wiring FDW is arranged across multiple wiring layers including the first wiring layer L1. The FD wiring FDW includes, for example, multiple pads provided on each of the multiple wiring layers and vias connecting the multiple pads.

[0062] Typically, to suppress noise, it is desirable to minimize the parasitic capacitance of the floating diffusion FD and the FD wiring FDW. However, as shown in FIG. 3 , when the first chip CH1 and the second chip CH2 are connected by the FD wiring FDW, the FD wiring FDW must be long to connect the floating diffusion FD and the gate of the amplification transistor. As a result, the FD wiring FDW is arranged along signal lines such as the vertical signal line VSL. The vertical signal line VSL transmits a potential corresponding to the signal when reading out a signal from another pixel, and the potential of the vertical signal line VSL fluctuates. Crosstalk between the FD wiring FDW and the vertical signal line VSL may propagate potential fluctuations to the FD wiring FDW, resulting in noise. Conversely, potential fluctuations in the FD wiring FDW may propagate to the vertical signal line VSL, resulting in noise.

[0063] The wiring SELAMP is used to suppress noise caused by crosstalk. The wiring SELAMP is provided between the FD wiring and the vertical signal line VSL. The wiring SELAMP functions as a shield wiring. This makes it possible to suppress crosstalk between the FD wiring FDW and the vertical signal line VSL. As a result, noise can be suppressed.

[0064] 4 is a plan view of the sensor pixel 121 and the readout circuit 120 according to the first embodiment. Fig. 4 shows a plan layout of a first wiring layer L1, which is one wiring layer in which the FD wiring, the wiring SELAMP, and the vertical signal line VSL in Fig. 3 are arranged.

[0065] The vertical signal lines VSL are provided to extend in the Y direction.

[0066] The wiring SELAMP is disposed at least partially between the FD wiring FDW disposed in the first wiring layer L1 and the vertical signal line VSL disposed in the first wiring layer L1. The wiring SELAMP disposed in the first wiring layer L1 substantially surrounds the FD wiring FDW disposed in the first wiring layer L1. This makes it possible to further suppress crosstalk between the FD wiring FDW and the vertical signal line VSL.

[0067] (Capacitive Coupling) Fixed potential wiring such as power supply wiring or ground wiring may be used as the shield wiring. In this case, however, capacitive coupling between the FD wiring FDW and the fixed potential wiring increases, resulting in a decrease in conversion efficiency.

[0068] In contrast, in the first embodiment, the potential of the line SELAMP, which functions as a shield line, fluctuates in response to fluctuations in the potential of the FD line FDW. This is because, during source follower driving of the amplifier transistor AMP, the line SELAMP, which is the line on the vertical signal line VSL side of the amplifier transistor AMP, follows the potential of the floating diffusion FD due to the Miller effect. This makes capacitive coupling between the FD line FDW and the line SELAMP less visible, thereby reducing the apparent capacitance. Therefore, it is possible to both suppress a decrease in conversion efficiency due to capacitive coupling and reduce noise due to crosstalk.

[0069] As described above, according to the first embodiment, the wiring SELAMP is a wiring on the vertical signal line VSL side of the amplifier transistor AMP, i.e., a wiring between the amplifier transistor AMP and the vertical signal line VSL. More specifically, the wiring SELAMP electrically connects the amplifier transistor AMP and the select transistor SEL. The wiring SELAMP is disposed at least partially between a portion of the FD wiring FDW disposed in the first wiring layer L1 and the vertical signal line VSL disposed in the first wiring layer L1. This makes it possible to suppress a decrease in conversion efficiency due to capacitive coupling and to reduce noise due to crosstalk.

[0070] The circuits of the sensor pixels 121 and the readout circuit 120 are not limited to the example shown in FIG. 2 . Circuits of embodiments described later may also be used. The imaging device 101 is not limited to, for example, a global shutter system. For example, the charge holding unit (MEM) 54 may not be provided.

[0071] 5 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a second embodiment. In the second embodiment, the configuration of the wiring SELAMP is different from that of the first embodiment.

[0072] The wiring SELAMP is arranged to extend in the Y direction. The two wirings SELAMP are arranged to sandwich the FD wiring FDW therebetween. The wiring SELAMP only needs to be arranged to function as a shield wiring that suppresses capacitive coupling between the FD wiring FDW and the vertical signal line VSL. Therefore, the wiring SELAMP does not necessarily need to be arranged to surround the entire FD wiring FDW.

[0073] For the sake of shielding function, the wiring SELAMP is preferably arranged so as to extend in the Y direction, longer than the length of the FD wiring FDW in the Y direction. That is, the wiring SELAMP arranged in the first wiring layer L1 extends in the first direction, substantially parallel to the first wiring layer L1, longer than the length of the FD wiring FDW arranged in the first wiring layer L1.

[0074] As in the second embodiment, the configuration of the wiring SELAMP may be changed, and in this case, the same effects as in the first embodiment can be obtained.

[0075] 6 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a third embodiment. The third embodiment differs from the first embodiment in that a control line CL is provided instead of the vertical signal line VSL.

[0076] The control line CL is, for example, a multi-value signal line. A multi-value signal line is a signal line to which a plurality of different voltages are applied. Therefore, the line SELAMP functions as a shield line for other signal lines, not limited to the vertical signal line VSL.

[0077] As in the third embodiment, control lines CL may be provided instead of the vertical signal lines VSL, and in this case, the same effects as in the first embodiment can be obtained.

[0078] 7 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a fourth embodiment. The fourth embodiment differs from the second embodiment in that a control line CL is provided instead of the vertical signal line VSL. The fourth embodiment is also a combination of the second and third embodiments.

[0079] As in the fourth embodiment, control lines CL may be provided instead of the vertical signal lines VSL, and in this case, the same effects as in the second embodiment can be obtained.

[0080] 8 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a fifth embodiment. The fifth embodiment differs from the third embodiment in the configuration of the control line CL.

[0081] 6, the control lines CL shown in Fig. 8 are shorter and do not extend to other sensor pixels 121. Therefore, the control lines CL do not need to be connected in row units.

[0082] As in the fifth embodiment, the configuration of the control line CL may be changed, and in this case, the same effects as in the third embodiment can be obtained.

[0083] 9 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a sixth embodiment. The sixth embodiment differs from the third embodiment in the configuration of the control line CL.

[0084] The control lines CL are arranged so as to extend in a mesh pattern, and therefore may be globally wired.

[0085] As in the sixth embodiment, the configuration of the control line CL may be changed, and in this case, the same effects as in the third embodiment can be obtained.

[0086] 10 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a seventh embodiment. The seventh embodiment differs from the first embodiment in that a plurality of signal lines are provided.

[0087] 10, a vertical signal line VSL and a control line CL are provided. The control line CL has two control lines CLA and CLB. The control lines CLA and CLB are arranged so as to sandwich the line SELAMP and the FD line FDW therebetween. The control lines CLA and CLB may receive the same signal or different signals.

[0088] The arrangement of the vertical signal lines VSL and the arrangement of the control lines CLA and CLB may be reversed.

[0089] As in the seventh embodiment, a plurality of signal lines may be provided, and in this case, the same effects as in the first embodiment can be obtained.

[0090] 11 is a plan view of a sensor pixel 121 and a readout circuit 120 according to an eighth embodiment. The eighth embodiment differs from the seventh embodiment in the configuration of the wiring SELAMP. The eighth embodiment is also a combination of the second embodiment and the seventh embodiment.

[0091] As in the eighth embodiment, the configuration of the wiring SELAMP may be changed, and in this case, the same effects as in the seventh embodiment can be obtained.

[0092] 12 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a ninth embodiment. The ninth embodiment differs from the seventh embodiment in the configuration of the control line CL.

[0093] The control lines CLA and CLB are electrically connected to each other. The control lines CL are arranged, for example, in a ladder shape extending in the Y direction. The control lines CL are arranged so as to surround the wiring SELAMP.

[0094] As in the ninth embodiment, the configuration of the control line CL may be changed, and in this case, the same effects as in the seventh embodiment can be obtained.

[0095] 13 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a tenth embodiment. The tenth embodiment differs from the seventh embodiment in the configuration of the control line CL. The tenth embodiment is also a combination of the fifth and seventh embodiments.

[0096] As in the tenth embodiment, the configuration of the control line CL may be changed, and in this case, the same effects as in the seventh embodiment can be obtained.

[0097] 14 is a plan view of a sensor pixel 121 and a readout circuit 120 according to an eleventh embodiment. The eleventh embodiment differs from the first embodiment in that a plurality of signal lines are provided.

[0098] The vertical signal line VSL includes two vertical signal lines VSLA and VSLB. The vertical signal lines VSLA and VSLB are arranged to sandwich the line SELAMP and the FD line FDW therebetween.

[0099] A plurality of signal lines may be provided as in the eleventh embodiment, and in this case, the same effects as in the first embodiment can be obtained.

[0100] 15 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a twelfth embodiment. The twelfth embodiment differs from the eleventh embodiment in the configuration of the wiring SELAMP. The twelfth embodiment is also a combination of the second embodiment and the eleventh embodiment.

[0101] As in the twelfth embodiment, the configuration of the wiring SELAMP may be changed, and in this case, the same effects as in the eleventh embodiment can be obtained.

[0102] 16 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a thirteenth embodiment. The thirteenth embodiment is different from the eleventh embodiment in the configuration of the vertical signal lines VSLA and VSLB.

[0103] The vertical signal lines VSLA and VSLB are arranged adjacent to each other within one sensor pixel 121. The line SELAMP and the FD line FDW are arranged between the vertical signal line VSLB arranged in the sensor pixel 121 and the vertical signal line VSLA arranged in the adjacent sensor pixel 121.

[0104] As in the thirteenth embodiment, the configuration of the vertical signal lines VSLA and VSLB may be changed, and in this case, the same effects as in the eleventh embodiment can be obtained.

[0105] 17 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a fourteenth embodiment. The fourteenth embodiment differs from the first embodiment in that a plurality of signal lines are provided.

[0106] The vertical signal lines VSLA and VSLB are arranged with the line SELAMP sandwiched therebetween.

[0107] The control lines CLA and CLB are arranged with the wiring SELAMP therebetween.

[0108] A plurality of signal lines may be provided as in the eleventh embodiment, and in this case, the same effects as in the first embodiment can be obtained.

[0109] 18 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a 15th embodiment. The 15th embodiment differs from the 14th embodiment in the configuration of the wiring SELAMP. The 15th embodiment is also a combination of the second embodiment and the 14th embodiment.

[0110] As in the fifteenth embodiment, the configuration of the wiring SELAMP may be changed, and in this case, the same effects as in the fourteenth embodiment can be obtained.

[0111] 19 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a sixteenth embodiment. The sixteenth embodiment differs from the fourteenth embodiment in the configuration of the control lines CLA and CLB. The sixteenth embodiment is also a combination of the fifth and fourteenth embodiments.

[0112] As in the sixteenth embodiment, the configuration of the control lines CLA and CLB may be changed, and in this case too, the same effects as in the fourteenth embodiment can be obtained.

[0113] 20 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a seventeenth embodiment. The seventeenth embodiment differs from the fourteenth embodiment in the configuration of the control lines CLA and CLB. The seventeenth embodiment is also a combination of the ninth embodiment and the fourteenth embodiment.

[0114] As in the seventeenth embodiment, the configuration of the control lines CLA and CLB may be changed, and in this case, the same effects as in the fourteenth embodiment can be obtained.

[0115] 21 is a plan view of a sensor pixel 121 and a readout circuit 120 according to an 18th embodiment. Fig. 22 is a cross-sectional view of the sensor pixel 121 and the readout circuit 120 according to the 18th embodiment. In the 18th embodiment, a capacitance for switching the conversion efficiency in the first embodiment is shown.

[0116] The FD wiring FDW has two FD wirings FDWA and FDWB.

[0117] The FD wiring FDWA corresponds to the FD wiring FDW shown in Fig. 2 and is connected to the floating diffusion FDH. The floating diffusion FDH corresponds to the floating diffusion FD shown in Fig. 2.

[0118] The FD wiring FDWB is connected to a floating diffusion FDL. The floating diffusion FDL corresponds to an additional capacitance (not shown) connected to the switching transistor FDG shown in FIG. 2. By switching the switching transistor FDG on and off, the connection between the FD wiring FDWA and the FD wiring FDWB can be switched. This allows the conversion efficiency to be switched.

[0119] The wiring SELAMP is arranged so as to surround the FD wiring FDWA, similarly to the first embodiment.

[0120] The control line CL is arranged to surround the FD wiring FDWB. The wiring SELAMP does not have to be arranged between the FD wiring FDWB arranged in the first wiring layer L1 and the control line CL arranged in the first wiring layer L1. Furthermore, the wiring SELAMP does not have to be arranged between the FD wiring FDWB and the control line CL. This is because the floating diffusion FDL, which reduces the conversion efficiency, does not mind if its capacitance increases due to capacitive coupling. Furthermore, by surrounding the FD wiring FDWB with the control line CL, it is possible to increase LCG (Low Conversion Gain) saturation.

[0121] 23 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 19th embodiment. The 19th embodiment differs from the first embodiment in that the sensor pixel 121 and the readout circuit 120 are configured with a single-layer structure of a chip (substrate) instead of the stacked structure of a first chip CH1 and a second chip CH2.

[0122] The floating diffusion FD and the amplification transistor AMP are disposed on the same substrate.

[0123] In the first wiring layer L1, the wiring SELAMP is arranged between the FD wiring FDW and the vertical signal line VSL.

[0124] Note that, instead of the vertical signal lines VSL, control lines CL may be provided.

[0125] As in the nineteenth embodiment, the sensor pixels 121 and the readout circuit 120 may be configured in a single-layer structure on a chip (substrate). In this case, the same effects as in the first embodiment can be obtained.

[0126] 24 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 20th embodiment. The 20th embodiment differs from the 19th embodiment in that a plurality of vertical signal lines VSL are arranged in one wiring layer.

[0127] At least one vertical signal line VSL may be a control line CL.

[0128] As in the twentieth embodiment, a plurality of vertical signal lines VSL may be arranged in one wiring layer, and in this case, the same effects as those of the nineteenth embodiment can be obtained.

[0129] 25 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 21st embodiment. The 21st embodiment differs from the 19th embodiment in that the wiring SELAMP is arranged in multiple wiring layers.

[0130] The wiring SELAMP is also arranged in a wiring layer one level below the wiring layer in which the vertical signal line VSL is arranged. For example, the two wirings SELAMP are arranged in adjacent wiring layers above and below. This makes it possible to suppress crosstalk between the FD wiring FDW arranged in a wiring layer other than the first wiring layer L1 and the vertical signal line VSL arranged in the first wiring layer L1, thereby further reducing noise caused by the crosstalk.

[0131] That is, the wiring SELAMP is arranged in a plurality of wiring layers including the first wiring layer L1. The wiring SELAMP is preferably arranged in wiring layers whose number is one or more greater than the number of wiring layers in which the vertical signal lines VSL are arranged.

[0132] Furthermore, the two wirings SELAMP arranged in the two wiring layers are electrically connected through vias.

[0133] Note that, instead of the vertical signal lines VSL, control lines CL may be provided.

[0134] As in the twenty-first embodiment, the wiring SELAMP may be arranged in a plurality of wiring layers, and in this case, the same effects as in the nineteenth embodiment can be obtained.

[0135] 26 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 22nd embodiment. The 22nd embodiment differs from the 21st embodiment in that the vertical signal lines VSL are arranged in multiple wiring layers.

[0136] The vertical signal lines VSL are arranged in two wiring layers in which the lines SELAMP are arranged, for example, in adjacent upper and lower wiring layers.

[0137] At least one vertical signal line VSL may be a control line CL.

[0138] As in the twenty-second embodiment, the vertical signal lines VSL may be arranged in a plurality of wiring layers, and in this case, the same effects as those of the twenty-first embodiment can be obtained.

[0139] 27 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 23rd embodiment. The 23rd embodiment differs from the 22nd embodiment in that the vertical signal lines VSL are connected by vias.

[0140] The two vertical signal lines VSL arranged in the two wiring layers are electrically connected to each other through vias.

[0141] Note that, instead of the vertical signal lines VSL, control lines CL may be provided.

[0142] As in the twenty-third embodiment, the vertical signal lines VSL may be connected by vias, and in this case, the same effects as in the twenty-second embodiment can be obtained.

[0143] 28 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 24th embodiment. In the 24th embodiment, similarly to the first embodiment shown in FIG. 3, the wiring SELAMP and the vertical signal line VSL are arranged on the second chip CH2.

[0144] In the example shown in FIG. 28, the wiring SELAMP and the vertical signal line VSL are arranged in one wiring layer.

[0145] 29 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 25th embodiment. The 25th embodiment differs from the first embodiment in that the wiring SELAMP and the vertical signal line VSL are arranged on the first chip CH1.

[0146] In the example shown in FIG. 29, the wiring SELAMP and the vertical signal line VSL are arranged in one wiring layer.

[0147] As in the twenty-fifth embodiment, the wiring SELAMP and the vertical signal line VSL may be arranged on the first chip CH1. In this case, the same effects as those of the first embodiment can be obtained.

[0148] 30 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 26th embodiment. In the 26th embodiment, similar to the first embodiment shown in FIG. 3, the wiring SELAMP is arranged in multiple wiring layers.

[0149] As a result, similar to the 21st embodiment shown in FIG. 25, crosstalk between the FD wiring FDW and the vertical signal line VSL can be further suppressed, and noise caused by crosstalk can be further reduced.

[0150] 31 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 27th embodiment. In the 27th embodiment, similar to the first embodiment shown in FIG. 3, a plurality of vertical signal lines VSL are arranged in one wiring layer.

[0151] At least one vertical signal line VSL may be a control line CL.

[0152] 32 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 28th embodiment. In the 28th embodiment, similar to the first embodiment shown in FIG. 3, the vertical signal lines VSL are arranged in multiple wiring layers.

[0153] At least one vertical signal line VSL may be a control line CL.

[0154] 33 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 29th embodiment. In the 29th embodiment, similar to the first embodiment shown in FIG. 3, a via is provided to electrically connect two vertical signal lines VSL arranged in two wiring layers.

[0155] At least one vertical signal line VSL may be a control line CL.

[0156] 30th Embodiment Fig. 34 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 30th embodiment. In the 30th embodiment, similar to the first embodiment shown in Fig. 3, two wirings SELAMP are provided in wiring layers below and above the vertical signal line VSL.

[0157] The wiring SELAMP is arranged, for example, to cover a part of the vertical signal line VSL in the Z direction, which makes it possible to further suppress crosstalk between the FD wiring FDW and the vertical signal line VSL, and further reduce noise caused by the crosstalk.

[0158] 35 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 31st embodiment. The 31st embodiment differs from the 30th embodiment in that two wirings SELAMP, which are arranged in wiring layers below and above the vertical signal line VSL, are arranged to cover the vertical signal line VSL.

[0159] The wiring SELAMP is arranged, for example, to cover the entire vertical signal line VSL in the Z direction, which makes it possible to further suppress crosstalk between the FD wiring FDW and the vertical signal line VSL, and further reduce noise caused by the crosstalk.

[0160] As in the thirty-first embodiment, two wirings SELAMP arranged in wiring layers below and above the vertical signal line VSL may be arranged to cover the vertical signal line VSL. In this case, the same effects as those of the thirty-first embodiment can be obtained.

[0161] 36 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 32nd embodiment. The 32nd embodiment differs from the first embodiment in that a wiring SELAMP is arranged on and connected to both the first chip CH1 and the second chip CH2.

[0162] The wiring SELAMP is arranged on both the first chip CH1 and the second chip CH2. The wiring SELAMP arranged on the first chip CH1 and the second chip CH2 are connected to each other at the bonding surface S by, for example, Cu-Cu bonding.

[0163] Furthermore, the wiring SELAMP is arranged adjacent to the FD wiring FDW in the X direction and extends in the Z direction with approximately the same length as the FD wiring FDW, thereby making it possible to further suppress crosstalk between the FD wiring FDW and the vertical signal line VSL and further reduce noise caused by crosstalk.

[0164] As in the thirty-second embodiment, the wiring SELAMP may be provided on and connected to both the first chip CH1 and the second chip CH2. In this case, too, the same effects as in the first embodiment can be obtained.

[0165] 37 is an equivalent circuit diagram of a sensor pixel 121 and a readout circuit 120 according to a 33rd embodiment. The 33rd embodiment differs from the first embodiment in that the configuration on the second chip CH2 side is shared by multiple sensor pixels 121.

[0166] The reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL are shared by a plurality of sensor pixels 121 .

[0167] As in the thirty-third embodiment, the configuration on the second chip CH2 side may be shared by a plurality of sensor pixels 121. In this case as well, the same effects as in the first embodiment can be obtained.

[0168] 38 is an equivalent circuit diagram of the sensor pixels 121 and the readout circuit 120 according to the 34th embodiment. The 34th embodiment differs from the first embodiment in that some components of the sensor pixels 121 and the readout circuit 120 are not provided.

[0169] In the example shown in FIG. 38, compared to the first embodiment, the transfer transistors TRX and TRZ, the discharge transistor OFG, the switching transistor FDG, and the charge holding unit (MEM) 54 are not provided.

[0170] As in the thirty-fourth embodiment, some components of the sensor pixels 121 and the readout circuit 120 may not be provided. In this case, the same effects as those of the first embodiment can be obtained.

[0171] 39 is an equivalent circuit diagram of a sensor pixel 121 and a readout circuit 120 according to a 35th embodiment. The 35th embodiment differs from the 34th embodiment in that the potential of the body of the amplification transistor AMP is the source potential of the amplification transistor AMP.

[0172] 2, the body of the amplifier transistor AMP is connected to ground. In this case, the modulation factor of the output of the source follower relative to the input to the gate of the amplifier transistor AMP is lower than 1 (100%). Therefore, the magnitude of fluctuation in the potential of the FD wiring FDW is smaller than the magnitude of fluctuation in the source potential of the amplifier transistor AMP (the potential of the wiring SELAMP).

[0173] In the example shown in FIG. 39 , the wiring SELAMP is electrically connected to the body of the amplifier transistor AMP. This allows the potential of the body (well) of the amplifier transistor AMP to be the source potential of the amplifier transistor AMP, making the back bias less visible. As a result, the fluctuation in the potential of the wiring SELAMP can be made approximately the same as the fluctuation in the potential of the FD wiring FDW. In other words, the modulation factor can be made approximately 1 (100%). This further suppresses capacitive coupling between the FD wiring FDW and the wiring SELAMP, leading to further suppression of a decrease in conversion efficiency due to capacitive coupling.

[0174] As in the thirty-fifth embodiment, the potential of the body of the amplifier transistor AMP may be set to the source potential of the amplifier transistor AMP. In this case, too, the same effects as in the thirty-fourth embodiment can be obtained.

[0175] 40 is an equivalent circuit diagram of the sensor pixels 121 and the readout circuit 120 according to the 36th embodiment. The 36th embodiment differs from the 34th embodiment in that the sensor pixels 121 and the readout circuit 120 are configured by stacking a plurality of substrates (chips).

[0176] As in the thirty-sixth embodiment, the sensor pixels 121 and the readout circuit 120 may be configured by stacking a plurality of substrates (chips). In this case, too, the same effects as in the thirty-fourth embodiment can be obtained.

[0177] As in the thirty-sixth embodiment, the sensor pixels 121 and the readout circuit 120 may be configured by stacking a plurality of substrates (chips). In this case, too, the same effects as in the thirty-fourth embodiment can be obtained.

[0178] 41 is an equivalent circuit diagram of a sensor pixel 121 and a readout circuit 120 according to a 37th embodiment. The 37th embodiment differs from the 36th embodiment in that the reset transistor RST is arranged on the first chip CH1.

[0179] When the switching transistor FDG is provided, the switching transistor FDG may also be disposed on the first chip CH1.

[0180] As in the thirty-seventh embodiment, the reset transistor RST may be disposed on the first chip CH1. In this case, the same effects as those of the thirty-fourth embodiment can be obtained.

[0181] 42 is an equivalent circuit diagram of a sensor pixel 121 and a readout circuit 120 according to the 38th embodiment. The 38th embodiment differs from the 34th embodiment in that the selection transistor SEL is arranged on the drain side of the amplification transistor AMP.

[0182] The select transistor SEL is connected between the amplifier transistor AMP and the power supply line VDD. That is, the select transistor SEL may be arranged on the drain side of the amplifier transistor AMP. In this case, instead of the wiring SELAMP, the wiring on the source side (vertical signal line VSL side) of the amplifier transistor AMP functions as the shield wiring. Therefore, the wiring on the source side of the amplifier transistor AMP is arranged, for example, at least partially between the portion of the FD wiring FDW arranged in the first wiring layer L1 and the vertical signal line VSL arranged in the first wiring layer L1.

[0183] As in the thirty-eighth embodiment, the selection transistor SEL may be disposed on the drain side of the amplification transistor AMP. In this case, too, the same effects as in the thirty-fourth embodiment can be obtained.

[0184] 43 is an equivalent circuit diagram of a sensor pixel 121 and a readout circuit 120 according to a 39th embodiment. The 39th embodiment differs from the 34th embodiment in that a plurality of selection transistors SEL are provided.

[0185] The select transistor SEL includes two select transistors SEL1 and SEL2. The select transistor SEL1 is connected between the amplifier transistor AMP and a vertical signal line VSL1. The select transistor SEL2 is connected between the amplifier transistor AMP and a vertical signal line VSL2.

[0186] By switching the selection transistors SEL1 and SEL2 on and off, it is possible to switch between the vertical signal lines VSL1 and VSL2 to which a signal is output.

[0187] As in the thirty-ninth embodiment, a plurality of select transistors SEL may be provided, and in this case, the same effects as in the thirty-fourth embodiment can be obtained.

[0188] 40th Embodiment Fig. 44 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a 40th embodiment. Fig. 45 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to the 40th embodiment. Fig. 45 is a cross-sectional view corresponding to the cross section taken along line AB in Fig. 44. Fig. 44 is a plan view corresponding to the plane taken along line AB in Fig. 45.

[0189] The fortieth embodiment differs from the first embodiment in that a wiring SHL is further provided.

[0190] The wiring SHL is arranged at least partially between the wiring SELAMP and the vertical signal line VSL. More specifically, the wiring SHL is arranged at least partially between the wiring SELAMP arranged in the first wiring layer L1 and the vertical signal line VSL arranged in the first wiring layer L1.

[0191] The wiring SHL is, for example, a control line, a power supply line, or a ground line. In this case, a control signal or a fixed potential is supplied to the wiring SHL. The wiring SHL functions as a shield wiring.

[0192] When the wiring SELAMP is used as a shield wiring, the wiring SELAMP tends to be designed to be long. However, as the extension of the wiring SELAMP increases, the convergence of VSL settling may deteriorate. For example, a potential fluctuation of the vertical signal line VSL fluctuates the potential of the wiring SELAMP, and this potential fluctuation propagates to the FD wiring FDW, causing the potential of the vertical signal line VSL to fluctuate again, creating a loop. This loop deteriorates the convergence of VSL settling.

[0193] In order to suppress VSL settling, it is necessary to reduce the capacitive coupling between the FD wiring FDW and the wiring SELAMP, or to reduce the capacitive coupling between the wiring SELAMP and the vertical signal line VSL. However, in order to simultaneously suppress the decrease in conversion efficiency and the crosstalk between the FD wiring FDW and the vertical signal line VSL, the layout relationship between the FD wiring FDW, the wiring SELAMP, and the vertical signal line VSL becomes very important.

[0194] Therefore, the FD wiring FDW and the wiring SELAMP are adjacent to each other, but the wiring SHL is arranged between the wiring SELAMP and the vertical signal line VSL, thereby suppressing the capacitive coupling between the SELAMP wiring and the vertical signal line VSL while providing capacitive coupling between the FD wiring FDW and the wiring SELAMP.

[0195] Arranging the FD wiring FDW and the wiring SELAMP adjacent to each other, as in the above embodiment, leads to suppression of a decrease in conversion efficiency. On the other hand, since placing the wiring SELAMP adjacent to the vertical signal line VSL causes potential fluctuations due to capacitive coupling, adding an additional shield wiring between them can suppress VSL settling. This makes it possible to simultaneously suppress a decrease in conversion efficiency, suppress crosstalk between the FD wiring FDW and the vertical signal line VSL, and improve VSL settling.

[0196] As in the fortieth embodiment, a wiring SHL may be further provided. In this case, the same effects as those of the first embodiment can be obtained.

[0197] 41st Embodiment Fig. 46 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 41st embodiment. Fig. 46 is a cross-sectional view corresponding to the cross section taken along line AB in Fig. 44.

[0198] The forty-first embodiment differs from the fortieth embodiment in the arrangement of the wirings SELAMP, SHL, etc.

[0199] As in the forty-first embodiment, the layout of the wirings SELAMP, SHL, etc. may be changed. In this case, the same effects as in the fortieth embodiment can be obtained.

[0200] 47 is a plan view of a sensor pixel 121 and a readout circuit 120 according to the 42nd embodiment. The 42nd embodiment differs from the 40th embodiment in the shape of the wiring SELAMP.

[0201] The wiring SELAMP on the side closer to the vertical signal line VSL is removed, which makes it possible to further suppress capacitive coupling between the wiring SELAMP and the vertical signal line VSL.

[0202] As in the forty-second embodiment, the shape of the wiring SELAMP may be changed. In this case, the same effects as in the fortieth embodiment can be obtained.

[0203] 48 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a 43rd embodiment. In the 43rd embodiment, the shape of the wiring SHL is different from that in the 40th embodiment.

[0204] The wiring SHL is arranged so as to partially surround the wiring SELAMP, which makes it possible to further suppress capacitive coupling between the wiring SELAMP and the vertical signal line VSL.

[0205] As in the forty-third embodiment, the shape of the wiring SHL may be changed. In this case, the same effects as in the fortieth embodiment can be obtained.

[0206] 49 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a 44th embodiment. In the 44th embodiment, the shape of the wiring SHL is different from that in the 40th embodiment.

[0207] The wiring SHL is partially provided at a position where the wiring SELAMP and the vertical signal line VSL are most closely adjacent to each other. The length of the wiring SHL in the Z direction is approximately the same as the length of the wiring SELAMP in the Z direction.

[0208] As in the forty-fourth embodiment, the shape of the wiring SHL may be changed. In this case, the same effects as in the fortieth embodiment can be obtained.

[0209] 50 is a plan view of a sensor pixel 121 and a readout circuit 120 according to a 45th embodiment. The 45th embodiment is different from the 40th embodiment in the number of wirings SHL.

[0210] The wiring SHL has two wirings SHLA and SHLB. The wirings SHLA and SHLB are arranged side by side. The number of wirings SHL is not limited to two, but may be three or more.

[0211] As in the forty-fifth embodiment, the number of wirings SHL may be changed. In this case, the same effects as in the fortieth embodiment can be obtained.

[0212] 51 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to the 46th embodiment. In the 46th embodiment, the shape of the wiring SHL is different from that in the 40th embodiment.

[0213] The wiring SHL is arranged so as to surround the vertical signal line VSL in cross section, thereby making it possible to further suppress capacitive coupling between the wiring SELAMP and the vertical signal line VSL.

[0214] As in the forty-sixth embodiment, the shape of the wiring SHL may be changed. In this case, the same effects as in the fortieth embodiment can be obtained.

[0215] 52 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to the 47th embodiment. The 47th embodiment differs from the 40th embodiment in the shape of the wiring SHL.

[0216] The wiring SHL is arranged so as to surround at least a part of the wiring SELAMP in cross section, thereby making it possible to further suppress capacitive coupling between the wiring SELAMP and the vertical signal line VSL.

[0217] As in the 47th embodiment, the shape of the wiring SHL may be changed. In this case, the same effects as in the 40th embodiment can be obtained.

[0218] 53 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to the 48th embodiment. The 48th embodiment differs from the 40th embodiment in the shape of the wiring SHL.

[0219] The wiring SHL is arranged only at a position (wiring layer) where the wiring SELAMP and the vertical signal line VSL are adjacent in the cross section.

[0220] As in the 47th embodiment, the shape of the wiring SHL may be changed. In this case, the same effects as in the 40th embodiment can be obtained.

[0221] 54 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 49th embodiment. The 49th embodiment differs from the 40th embodiment in that a low dielectric constant layer (low-k layer) LK is provided.

[0222] A low-dielectric layer LK is further provided. The low-dielectric layer LK is provided between the wiring SELAMP and the vertical signal line VSL. The low-dielectric layer LK has a lower dielectric constant than other interlayer insulating films. This makes it possible to further suppress capacitive coupling between the wiring SELAMP and the vertical signal line VSL.

[0223] A low dielectric constant layer LK may be provided as in the forty-ninth embodiment, and in this case, the same effects as in the fortieth embodiment can be obtained.

[0224] 55 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 50th embodiment. The 50th embodiment differs from the 40th embodiment in that a vertical signal line VSL is provided above the FD wiring FDW.

[0225] The FD wiring FDW and the wiring SELAMP are provided in the same wiring layer.

[0226] The wiring SHL is provided in a wiring layer above the wiring layer in which the FD wiring FDW and the wiring SELAMP are provided. The wiring SHL functions as a shield wiring in the vertical direction (Z direction).

[0227] The vertical signal lines VSL are provided in an interconnect layer above the interconnect layer in which the lines SHL are provided. In the example shown in Fig. 55, two vertical signal lines VSL are provided.

[0228] The wiring SELAMP is disposed at least partially between the FD wiring FDW and the vertical signal line VSL in a direction substantially perpendicular to the semiconductor substrate 11 on which the floating diffusion FD is provided.

[0229] The wiring SHL is disposed at least partially between the wiring SELAMP and the vertical signal line VSL in a direction substantially perpendicular to the semiconductor substrate 11 on which the floating diffusion FD is provided.

[0230] As in the 50th embodiment, the vertical signal line VSL may be provided above the FD wiring FDW, and in this case, the same effects as in the 40th embodiment can be obtained.

[0231] 56 is a cross-sectional view of a sensor pixel 121 and a readout circuit 120 according to a 51st embodiment. The 51st embodiment differs from the 50th embodiment in that the wiring layer has a four-layer structure.

[0232] 56, an additional wiring layer is provided in which the wiring SELAMP is provided. The wirings SELAMP are electrically connected to each other between the two wiring layers. The wirings SHL and SELAMP function as shield wiring in the vertical direction (Z direction).

[0233] The structure is not limited to four layers, and may be five or more layers.

[0234] The wiring layer may have a four-layer structure as in the fifty-first embodiment, and in this case, the same effects as in the fifty-first embodiment can be obtained.

[0235] (Application Example to Electronic Device) FIG. 57 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0236] The camera 2000 includes an optical unit 2001 including a lens group and the like, an imaging device 2002 to which the imaging device 101 described above or the like (hereinafter referred to as the imaging device 101, etc.) is applied, and a DSP (Digital Signal Processor) circuit 2003, which is a camera signal processing circuit. The camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008. The DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, the operation unit 2007, and the power supply unit 2008 are connected to one another via a bus line 2009.

[0237] The optical unit 2001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 2002. The imaging device 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0238] The display unit 2005 is formed of a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 2002. The recording unit 2006 records the moving images or still images captured by the imaging device 2002 on a recording medium such as a hard disk or semiconductor memory.

[0239] An operation unit 2007, under the operation of a user, issues operation commands for various functions of the camera 2000. A power supply unit 2008 appropriately supplies various types of power to the DSP circuit 2003, frame memory 2004, display unit 2005, recording unit 2006, and operation unit 2007 as operating power sources.

[0240] As described above, by using the imaging device 101 or the like as the imaging device 2002, it is possible to expect to obtain a good image.

[0241] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0242] FIG. 58 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0243] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 58, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0244] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0245] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0246] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0247] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0248] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0249] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0250] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0251] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0252] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 58, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0253] FIG. 59 is a diagram showing an example of the installation position of the imaging unit 12031.

[0254] In FIG. 59, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0255] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0256] 59 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0257] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0258] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0259] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0260] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0261] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 101 shown in FIG. 1 or the like can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, noise can be suppressed, thereby enabling safer vehicle driving.

[0262] The present technology may have the following configurations: (1) A solid-state imaging device comprising: a photoelectric conversion unit that generates charges according to an amount of received light by photoelectric conversion; a charge accumulation unit that accumulates the charges generated by the photoelectric conversion unit; an amplifier transistor that amplifies a signal based on the charges accumulated in the charge accumulation unit; a first wiring that electrically connects the charge accumulation unit to a gate of the amplifier transistor; and a second wiring of the amplifier transistor on an output signal line side to which the signal amplified by the amplifier transistor is output, wherein the second wiring is arranged at least partially between the first wiring and a signal line. (2) The solid-state imaging device according to (1), further comprising: a selection transistor that selects whether or not to output the signal amplified by the amplifier transistor, wherein the second wiring electrically connects the amplifier transistor to the selection transistor. (3) The solid-state imaging device according to (1) or (2), wherein the second wiring is arranged at least partially between the first wiring arranged in a first wiring layer and the signal line arranged in the first wiring layer. (4) The solid-state imaging device according to (3), wherein the second wiring arranged in the first wiring layer extends in a first direction substantially parallel to the first wiring layer, longer than the length of the first wiring arranged in the first wiring layer. (5) The solid-state imaging device according to (3), wherein the second wiring arranged in the first wiring layer substantially surrounds the first wiring arranged in the first wiring layer. (6) The solid-state imaging device according to any one of (3) to (5), wherein the first wiring is arranged across a plurality of wiring layers including the first wiring layer. (7) The solid-state imaging device according to (6), wherein the first wiring includes: a plurality of pads arranged in each of a plurality of wiring layers; and vias connecting the plurality of pads. (8) The solid-state imaging device according to any one of (3) to (7), wherein the second wiring is arranged in a plurality of wiring layers including the first wiring layer. (9) The solid-state imaging device according to (8), wherein the second wiring is arranged in a number of wiring layers that is one or more greater than the number of wiring layers in which the signal lines are arranged.(10) The solid-state imaging device according to any one of (1) to (9), further comprising: a first chip on which the photoelectric conversion unit is arranged; and a second chip stacked on the first chip on which the amplifying transistor is arranged, wherein the first wiring connects the first chip to the second chip. (11) The solid-state imaging device according to (10), wherein the signal line and the second wiring are arranged on the second chip. (12) The solid-state imaging device according to any one of (1) to (11), wherein the signal line is the output signal line or a multi-value signal line to which a plurality of different voltages are applied. (13) The solid-state imaging device according to any one of (1) to (12), further comprising: a transfer unit that transfers charges generated by the photoelectric conversion unit to the charge accumulation unit; and a reset unit that resets the charges accumulated in the charge accumulation unit. (14) The solid-state imaging device according to any one of (1) to (13), wherein the second wiring is electrically connected to a body of the amplifying transistor. (15) The solid-state imaging device according to any one of (1) to (14), further comprising: an additional capacitance that adds capacitance to the charge accumulation portion; and a switching portion that switches a connection state between the charge accumulation portion and the additional capacitance, wherein the second wiring is not disposed between the additional capacitance and the signal line. (16) The solid-state imaging device according to any one of (1) to (15), wherein the second wiring is disposed at least partially between the first wiring and the signal line in a direction approximately perpendicular to a substrate on which the charge accumulation portion is provided. (17) The solid-state imaging device according to any one of (1) to (16), further comprising: a third wiring to which a control signal or a fixed potential is supplied, wherein the third wiring is disposed at least partially between the second wiring and the signal line.(18) An electronic device comprising: a photoelectric conversion unit that generates charges according to the amount of received light by photoelectric conversion; a charge accumulation unit that accumulates the charges generated by the photoelectric conversion unit; an amplification transistor that amplifies a signal based on the charges accumulated in the charge accumulation unit; a first wiring that electrically connects the charge accumulation unit and a gate of the amplification transistor; and a second wiring on the output signal line side of the amplification transistor that outputs the signal amplified by the amplification transistor, wherein the second wiring is arranged at least partially between the first wiring arranged in a first wiring layer and a signal line arranged in the first wiring layer.

[0263] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0264] 51 Photoelectric conversion unit, 101 Imaging device, 121 Sensor pixel, PD Photodiode, FD Floating diffusion, FDW FD wiring, TRG Transfer transistor, AMP Amplification transistor, SEL Select transistor, RST Reset transistor, SELAMP Wiring, VSL Vertical signal line, L1 First wiring layer, CH1 First chip, CH2 Second chip

Claims

1. A solid-state imaging device comprising: a photoelectric conversion unit that generates an electric charge according to the amount of received light by photoelectric conversion; a charge accumulation unit that accumulates the electric charge generated in the photoelectric conversion unit; an amplifying transistor that amplifies a signal based on the electric charge accumulated in the charge accumulation unit; a first wiring that electrically connects the charge accumulation unit and a gate of the amplifying transistor; and a second wiring on the output signal line side of the amplifying transistor to which the signal amplified by the amplifying transistor is output, wherein the second wiring is located at least partially between the first wiring and a signal line.

2. A solid-state imaging device as described in claim 1, further comprising a selection transistor that selects whether or not to output the signal amplified by the amplification transistor, and the second wiring electrically connects the amplification transistor and the selection transistor.

3. A solid-state imaging device as described in claim 1, wherein the second wiring is arranged at least partially between the first wiring arranged in a first wiring layer and the signal line arranged in the first wiring layer.

4. A solid-state imaging device as described in claim 3, wherein the second wiring arranged in the first wiring layer extends in the first direction substantially parallel to the first wiring layer and is longer than the length of the first wiring arranged in the first wiring layer.

5. A solid-state imaging device as described in claim 3, wherein the second wiring arranged in the first wiring layer substantially surrounds the first wiring arranged in the first wiring layer.

6. The solid-state imaging device according to claim 3, wherein the first wiring is arranged across a plurality of wiring layers including the first wiring layer.

7. The solid-state imaging device according to claim 6, wherein the first wiring has: a plurality of pads arranged in each of a plurality of wiring layers; and vias connecting the plurality of pads.

8. The solid-state imaging device according to claim 3, wherein the second wiring is arranged in a plurality of wiring layers including the first wiring layer.

9. The solid-state imaging device according to claim 8, wherein the second wirings are arranged in wiring layers whose number is one or more greater than the number of wiring layers in which the signal lines are arranged.

10. The solid-state imaging device of claim 1, further comprising: a first chip on which the photoelectric conversion unit is arranged; and a second chip stacked on the first chip and on which the amplifying transistor is arranged, wherein the first wiring connects the first chip and the second chip.

11. The solid-state imaging device according to claim 10, wherein the signal line and the second wiring are arranged on the second chip.

12. The solid-state imaging device according to claim 1, wherein the signal line is the output signal line or a multi-value signal line to which a plurality of different voltages are applied.

13. The solid-state imaging device according to claim 1, further comprising: a transfer section that transfers the charges generated by the photoelectric conversion section to the charge accumulation section; and a reset section that resets the charges accumulated in the charge accumulation section.

14. The solid-state imaging device according to claim 1, wherein the second wiring is electrically connected to a body of the amplifying transistor.

15. The solid-state imaging device of claim 1, further comprising: an additional capacitance that adds capacitance to the charge storage section; and a switching section that switches a connection state between the charge storage section and the additional capacitance, wherein the second wiring is not disposed between the additional capacitance and the signal line.

16. A solid-state imaging device as described in claim 1, wherein the second wiring is disposed at least partially between the first wiring and the signal line in a direction substantially perpendicular to a substrate on which the charge storage section is provided.

17. The solid-state imaging device according to claim 1, further comprising a third wiring to which a control signal or a fixed potential is supplied, the third wiring being disposed at least partially between the second wiring and the signal line.

18. An electronic device comprising: a photoelectric conversion unit that generates an electric charge according to an amount of received light by photoelectric conversion; a charge accumulation unit that accumulates the electric charge generated in the photoelectric conversion unit; an amplifying transistor that amplifies a signal based on the electric charge accumulated in the charge accumulation unit; a first wiring that electrically connects the charge accumulation unit and a gate of the amplifying transistor; and a second wiring on an output signal line side of the amplifying transistor that outputs a signal amplified by the amplifying transistor, wherein the second wiring is arranged at least partially between the first wiring and a signal line.

Images