Delay control circuit

Abstract

The present invention correctly synchronizes and drives a plurality of external devices connected in parallel.　A FPGA 30 is provided with a delay control circuit for delaying PWMs 1, 2, 3 on the basis of Syncs 1, 2, 3. The delay control circuit comprises: a phase difference detection circuit 40 (phase difference detection unit) for detecting a phase difference between the Syncs 1, 2, 3 (input signals), which are inputted from a gate driver / SiC 100; a phase difference time measurement circuit 50 (phase difference time measurement unit) for measuring a phase difference time of the phase difference detected by the phase difference detection circuit 40; a correction rate integration circuit 60 (integration unit) for calculating an integrated value by adding or subtracting the previous phase difference time to or from the current phase difference time measured by the phase difference time measurement circuit 50; a delay time determination circuit 70 (delay time determination unit) for determining a delay time of the PWMs 1, 2, 3 (output signals) on the basis of the integrated value calculated by the correction rate integration circuit 60; and a delay circuit 80 (delay unit) for delaying the PWMs 1, 2, 3 on the basis of the determined delay time.

Description

Delay Control Circuit

[0001] The present invention relates to a delay control circuit.

[0002] Patent Document 1 discloses a technique for connecting external devices to be driven by a gate driver in parallel and driving the devices.

[0003] Patent No. 6915890

[0004] In the parallel driving technology as disclosed in Patent Document 1, there is a demand for a technology that can drive a plurality of external devices connected in parallel in a correctly synchronized manner.

[0005] SUMMARY OF THE INVENTION The present invention provides a delay control circuit that can drive a plurality of external devices connected in parallel in a correct synchronization manner.

[0006] The present invention employs the following solutions to solve the above-mentioned problems. Note that the solutions and the wording in parentheses below are merely examples, and the present invention is not limited thereto. The present invention can be an invention that includes at least one of the invention-specifying matters shown in the solutions below. Furthermore, each invention-specifying matter shown in the solutions below can be made into a subordinate concept by adding an element that limits the invention-specifying matter, or can be made into a superordinate concept by removing an element that limits the invention-specifying matter.

[0007] Solution 1: The delay control circuit of this solution outputs an output signal to each external device of a plurality of external devices connected in parallel, receives an input signal based on the output signal from each external device, and delays the output signal based on the input signal, and is equipped with a phase difference detection unit that detects the phase difference of the input signal input from each external device, a phase difference time measurement unit that measures the phase difference time of the phase difference detected by the phase difference detection unit, an integration unit that calculates an integrated value by adding or subtracting the previous phase difference time to the current phase difference time measured by the phase difference time measurement unit, a delay time determination unit that determines the delay time of the output signal based on the integrated value calculated by the integration unit, and a delay unit that delays the output signal based on the delay time determined by the delay time determination unit.

[0008] According to this solution, the output signal is delayed based on the input signal, so that the phase variations of the external devices can be suppressed, and a plurality of external devices can be driven in correct synchronization.

[0009] Solution 2: The delay control circuit of this solution is a delay control circuit characterized in that, in any of the solutions described above, the integrating unit multiplies the current phase difference time measured by the phase difference time measuring unit by a predetermined correction factor.

[0010] According to this solution, since a correction factor is used, multiple external devices can be loosely synchronized.

[0011] Solution 3: The delay control circuit of this solution is a delay control circuit characterized in that, in any of the solutions described above, the phase difference time measurement unit uses a phase locked loop circuit.

[0012] According to this solution, since a phase locked loop is used, it is possible to measure time and delay signals with a resolution equal to or higher than the maximum operating frequency of the delay control circuit.

[0013] According to the present invention, a plurality of external devices connected in parallel can be driven in correct synchronization.

[0014] 14 is a diagram showing a drive circuit 10 of an embodiment. It is a diagram showing the relationship between Ids and PWM. It is a diagram showing the configuration of a power switching device. It is a diagram showing the configuration of a delay control circuit. It is a diagram showing the timing of each signal of an FPGA. It is a diagram showing details of a delay control circuit. It is a diagram showing details of a phase difference detection circuit 40. It is a diagram showing details of a phase difference time measurement circuit 50. It is a diagram showing details of a correction factor integration circuit 60. It is a diagram showing part of the function of the correction factor integration circuit 60. It is a diagram showing details of a delay time determination circuit 70. It is a diagram showing the concept of the processing content (in the case of two syncs) of the delay time determination circuit 70. It is a diagram showing the concept of the processing content (in the case of three syncs) of the delay time determination circuit 70. It is a diagram showing details of a delay circuit 80. It is a simplified diagram of the delay circuit 80 of FIG. 14. It is a sequence diagram when PWM is detected with CLK1 in the delay circuit 80. It is a sequence diagram when PWM is detected with CLK2 in the delay circuit 80. It is a diagram showing details of a PWM rising CLK selection circuit. It is a diagram showing each signal related to the PWM rising CLK selection circuit. 1 is a diagram showing actual signals related to a PWM rising CLK selection circuit. FIG. 2 is a conceptual diagram showing the processing content of a portion of a delay circuit 80. FIG. 3 is a diagram showing the circuit configuration of an FPGA for triple parallel feedback control. FIG. 4 is a diagram showing the circuit configuration of an FPGA for dual parallel feedback control. FIG. 5 is a diagram showing the circuit configuration of an FPGA for multi-parallel feedback control. FIG. 6 is a diagram showing a modified example of a phase difference time measurement circuit 50. FIG. 7 is a diagram showing the configuration of an operation evaluation circuit for triple parallel feedback control. FIG. 8 is a diagram showing an overview of correction factor processing. FIG. 9 is a diagram showing measurement results when the correction factor is 1.0. FIG. 10 is a diagram showing measurement results when the correction factor is 0.5. FIG. 11 is a diagram showing measurement results of jitter. FIG. 12 is a diagram showing the configuration of a correction limiter. FIG. 13 is a diagram showing measurement results of the correction limiter. FIG. 14 is a diagram showing details of measurement results of the correction limiter.

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a drive circuit 10 according to the embodiment. FIG. 1(A) shows an outline of the drive circuit 10, and FIG. 1(B) shows details of the dotted line portion of FIG. 1(A) and the circuits connected thereto. As shown in FIG. 1(A), the drive circuit 10 includes a power supply 11, a control board 12, three-phase power switching devices 13, 14, and 15, and three coils 16. Each of the three-phase power switching devices 13, 14, and 15 is composed of two power switching devices, one above the other.

[0016] In the drive circuit 10, a control board 12 operates using power from a power supply 11, and the control board 12 gate-controls three-phase power switching devices 13, 14, and 15, thereby driving a motor (not shown) through three coils 16. Note that although the drive circuit 10 drives a motor, it may also be a circuit that drives a device other than a motor.

[0017] 1A, one power switching device is usually sufficient, but in cases where there is insufficient current, multiple power switching devices may be connected in parallel. The delay control circuit of this embodiment is a circuit used when multiple power switching devices are connected in parallel in such a situation. The delay control circuit will be described in detail later.

[0018] 1B, SiC1, SiC2, and SiC3 are connected in parallel as power switching devices. SiC is a power semiconductor that uses a silicon carbide semiconductor, which is a compound.

[0019] SiC1 is connected to a first gate driver 20a, which is connected to a field programmable gate array (FPGA) 30. SiC2 is connected to a second gate driver 20b, which is connected to the FPGA 30. SiC3 is connected to a third gate driver 20c, which is connected to the FPGA 30.

[0020] The FPGA 30 receives a PWM signal from the control board 12 (upper side). The FPGA 30 outputs a PWM signal to the first gate driver 20a, and receives a Sync signal from the first gate driver 20a. The FPGA 30 outputs a PWM signal to the second gate driver 20b, and receives a Sync signal from the second gate driver 20b. The FPGA 30 outputs a PWM signal to the third gate driver 20c, and receives a Sync signal from the third gate driver 20c. PWM (Pulse Width Modulation) is a signal that uses a rectangular wave pulse to control electrical components, etc. Sync (Synchronization) is a signal (synchronization signal) that synchronizes the operations of various devices.

[0021] The first gate driver 20a outputs Vgs1 to SiC1 and receives Vdsps1 as input from SiC1. The second gate driver 20b outputs Vgs2 to SiC2 and receives Vdsps2 as input from SiC2. The third gate driver 20c outputs Vgs3 to SiC3 and receives Vdsps3 as input from SiC3. SiC1, SiC2, and SiC3 output Ids1, Ids2, and Ids3, respectively. Vgs is the gate-source voltage. Vdsps is the voltage between the driver source and power source of the four-terminal power switching device SiC. Ids is the current flowing from drain to source.

[0022] Although not specifically shown, Ids1 output by SiC1 is also input to the first gate driver 20a, Ids2 output by SiC2 is also input to the second gate driver 20b, and Ids3 output by SiC3 is also input to the third gate driver 20c. Each gate driver is equipped with a Sync detection circuit, which detects Sync based on Vdsps (the potential difference between the driver source and the power source) and Ids input to the Sync detection circuit, and can output Syncs 1, 2, and 3 to the FPGA 30.

[0023] The circuit that transmits PWM to the FPGA 30, and the first gate driver 20a, second gate driver 20b, and third gate driver 20c can be implemented as part of the functions of the control board 12. On the other hand, the FPGA 30 can be implemented as a function separate from the control board 12. The delay control circuit of this embodiment is incorporated into the FPGA 30.

[0024] FIG. 2 illustrates the relationship between Ids and PWM. FIG. 2(A) illustrates the case where control by the delay control circuit is not performed, and FIG. 2(B) illustrates the case where control by the delay control circuit is performed. As shown in FIG. 2(A), when control by the delay control circuit is not performed, PWM is input from the control board 12 to the FPGA 30, and the FPGA 30 outputs PWM1, 2, and 3 to the power switching devices via the respective gate drivers at the same timing. In this case, PWM1, 2, and 3 are output at the same timing, but Ids1, 2, and 3 (currents from the power switching devices) have waveforms with different rising and falling timings. This variation is due to individual differences between devices, temperature distribution of the devices, deterioration of the devices over time, etc.

[0025] On the other hand, as shown in FIG. 2B, when control by the delay control circuit is performed, PWM signals are input from the control board 12 to the FPGA 30, and the FPGA 30 outputs PWMs 1, 2, and 3 to the power switching devices via the gate drivers at different timings. In this case, PWMs 1, 2, and 3 are output at different timings, but Ids 1, 2, and 3 have waveforms with consistent rising and falling timings. This is because the output timing of PWMs 1, 2, and 3 is delayed based on the variations shown in FIG. 2A. Control by the delay control circuit eliminates the variations shown in FIG. 2A and balances the currents as shown in FIG. 2B. In other words, control by the delay control circuit forcibly delays PWMs 1, 2, and 3 to align the waveforms of Ids 1, 2, and 3 in order to eliminate current variations.

[0026] 3 is a diagram showing the configuration of a power switching device. In this embodiment, a four-terminal power switching device is used. For example, SCT3040KR (manufactured by ROHM Co., Ltd.) can be used as a four-terminal power switching device. The four terminals are a drain T1, a gate T2, a driver source T3, and a power source T4, and in this embodiment, control is performed based on the potential difference (Vdsps, etc.) between the driver source T3 and the power source T4.

[0027] Generally, the Ls of a power switching device is several nH to several tens of nH, and when dID / dt reaches several A / ns, an electromotive voltage VL of 10 V or more may be generated. Vdsps is the same signal as VL, and by increasing the sensitivity of the "Sync detection circuit," it becomes possible to detect the initial operation of Id. In this embodiment, in order to balance the shunt current when power switching devices are connected in parallel, each signal is controlled to synchronize the timing of the Vdsps signal.

[0028] FIG. 4 is a diagram showing the configuration of the delay control circuit. The delay control circuit is a circuit for triple-parallel feedback control. Note that SiCs 1, 2, and 3 are shown vertically for convenience, but in reality, they are connected in parallel (see FIG. 1). The FPGA 30 detects PWM signals using a detection circuit 91, generates PWM signals 1, 2, and 3 using a first delay circuit 80a, a second delay circuit 80b, and a third delay circuit 80c, and outputs PWM signals 1, 2, and 3 to a first gate driver 20a, a second gate driver 20b, and a third gate driver 20c.

[0029] The FPGA 30 receives Sync1, Sync2, and Sync3 from the first gate driver 20a, the second gate driver 20b, and the third gate driver 20c, and feedback control is performed in the time difference measurement circuit 90, the delay time determination circuit 70, and three delay circuits (the first delay circuit 80a, the second delay circuit 80b, and the third delay circuit 80c). The time difference measurement circuit 90 uses a 250 MHz four-phase shift PLL 51. The time difference measurement circuit 90 can also apply a correction factor (0.25, 0.50, 0.75, 1.00, etc.). The correction factor is preferably a value of 1 or less.

[0030] 5A and 5B are diagrams showing the timing of each signal of the FPGA. As shown in FIG. 5A, the PWM waveform is a signal output from the control board 12 to the FPGA 30. As shown in FIG. 5B, the FPGA 30 outputs PWM1, 2, and 3 based on the PWM. As shown in FIG. 5C, when the FPGA 30 outputs PWM1, 2, and 3, Sync1, 2, and 3 are input to the FPGA 30.

[0031] The FPGA 30 monitors the time difference between Sync1, 2, and 3. The time difference between Sync1, 2, and 3 is reflected in the next PWM1, 2, and 3 (see arrow A1). This is on the turn-on side (rising side), and similarly, the time difference between Sync1, 2, and 3 is monitored on the turn-off side (falling side) and reflected in the next PWM1, 2, and 3 (see arrow A2).

[0032] When the processes indicated by arrows A1 and A2 are performed, Sync1, 2, and 3 are generally aligned, but there may be a slight discrepancy. For this reason, the same process is performed on the next turn-on side. In this case, the signal is delayed by the sum of the previous delay and the current delay (see arrow A3). This is also the case on the turn-off side (see arrow A4). From this point on, this process is performed continuously.

[0033] 6 is a diagram showing the details of the delay control circuit. The FPGA 30 outputs PWM1, 2, and 3 (output signals) to each gate driver SiC of a plurality of gate driver SiCs 100 (external devices) connected in parallel, receives Sync1, 2, and 3 (input signals) based on PWM1, 2, and 3 from each gate driver SiC, and includes a delay control circuit that delays PWM1, 2, and 3 based on Sync1, 2, and 3. Three gate drivers SiC 100 are connected in parallel, one corresponding to the first gate driver 20a and SiC1, the second corresponding to the second gate driver 20b and SiC2, and the third corresponding to the third gate driver 20c and SiC3 (see FIG. 1).

[0034] The delay control circuit of the FPGA 30 includes a phase difference detection circuit 40 (phase difference detection unit), a phase difference time measurement circuit 50 (phase difference time measurement unit), a correction factor integration circuit 60 (integration unit), a delay time determination circuit 70 (delay time determination unit), and a delay circuit 80 (delay unit).

[0035] (1) Phase Difference Detection Circuit 40 The phase difference detection circuit 40 is a circuit that detects the phase difference between Sync1, Sync2, and Sync3 (input signals) input from each gate driver (each external device). Specifically, the phase difference detection circuit 40 detects the phase difference between Sync1 and Sync2, between Sync2 and Sync3, and between Sync3 and Sync1.

[0036] (2) Phase Difference Time Measurement Circuit 50 The phase difference time measurement circuit 50 is a circuit that measures the phase difference time of the phase difference detected by the phase difference detection circuit 40. The phase difference time measurement circuit 50 preferably uses a PLL (phase locked loop). Specifically, the phase difference time measurement circuit 50 measures the phase difference with a resolution of 1 ns.

[0037] (3) Correction Factor Integration Circuit 60 The correction factor integration circuit 60 is a circuit that calculates an integrated value by adding or subtracting the previous phase difference time to the current phase difference time measured by the phase difference time measurement circuit 50. Preferably, the correction factor integration circuit 60 multiplies the current phase difference time measured by the phase difference time measurement circuit 50 by a predetermined correction factor. Specifically, the correction factor integration circuit 60 multiplies the current measurement value by the correction factor and adds or subtracts the result from the previous integrated value.

[0038] (4) Delay Time Determination Circuit 70 The delay time determination circuit 70 is a circuit that determines the delay times of PWM1, 2, and 3 (output signals) based on the integrated value calculated by the correction factor integration circuit 60. Specifically, the delay time determination circuit 70 determines the delay times of PWM1, 2, and 3 from the integrated value.

[0039] (5) Delay Circuit 80 The delay circuit 80 is a circuit that delays PWM1, 2, and 3 based on the delay time determined by the delay time determination circuit 70. Specifically, the delay circuit 80 delays each of PWM1, 2, and 3 by the delay time relative to the PWM input signal.

[0040] PWM1, 2, and 3 are output from FPGA 30 to gate driver SiC100 (PWM1 → first gate driver SiC1, PWM2 → second gate driver SiC2, and PWM3 → third gate driver SiC3). On the other hand, Sync1, 2, and 3 are input from gate driver SiC100 to FPGA 30. The phase difference detection circuit 40, phase difference time measurement circuit 50, and correction factor integration circuit 60 correspond to the time difference measurement circuit 90 (see FIG. 1).

[0041] 7A and 7B are diagrams showing the details of the phase difference detection circuit 40. FIG. 7A shows the circuit configuration, and FIG. 7B shows a timing chart of each signal. As shown in FIG. 7A, the phase difference detection circuit 40 is a circuit that receives Sync1, Sync2, and a PWM rising edge, detects the phase, and outputs a code. Here, Sync1 and Sync2 are explained as representatives, but the same applies to Sync2, Sync3, and Sync3, Sync1.

[0042] When Sync1 and Sync2 are input to the FPGA 30, they are input to the clock portions of the upper and middle flip-flop circuits. The PWM rising edge is also input to the upper and middle flip-flop circuits. Then, data A is output from the upper flip-flop circuit, and data B is output from the middle flip-flop circuit. Data A and data B are input to an exclusive OR circuit to perform phase detection (phase difference detection).

[0043] Sync1 is input to the clock portion of the flip-flop circuit at the lower stage. Data B is inverted by a NOT circuit and input to the flip-flop circuit at the lower stage. A code is then output from the flip-flop circuit at the lower stage.

[0044] As shown in Figure 7(B), Sync1 and Sync2, each with a different waveform, are input. In this case, when the exclusive OR of data A and data B is taken, only the part where Sync1 is High (1) and Sync2 is Low (0) becomes High, which is used as phase detection (phase difference between A and B). Also, the symbol is High in the illustrated example, which means that Sync1 rises first and Sync2 rises later. If Sync2 rises first and Sync1 rises later, the symbol remains Low.

[0045] FIG. 8 is a diagram illustrating the details of the phase difference time measurement circuit 50. FIG. 8(A) shows the circuit configuration, FIG. 8(B) shows a timing chart of each signal in a first example, and FIG. 8(C) shows a timing chart of each signal in a second example. As shown in FIG. 8(A), the phase difference time measurement circuit 50 is a circuit that receives a phase difference and a clock and outputs a phase difference time. The phase difference (phase detection pulse in FIG. 7) is input to the phase difference time measurement circuit 50, and counters 0 to 3 are controlled by CLK0 to CLK3 generated by a PLL 51. Data 0 to 3 are added by an adder circuit 52 to measure the phase difference time. The phase difference time measurement circuit 50 also uses a 250 MHz, four-phase-shift PLL 51 to measure (resolve) the phase difference pulse in 1 ns intervals.

[0046] PLL51 uses a function (circuit) provided in the FPGA. Using PLL51, the clock is increased to 250 ns and a four-phase shift is performed. This makes it possible to generate a continuous clock waveform at 250 MHz. CLK0 to CLK3 are waveforms that are shifted by 90 degrees from each other, with CLK1 shifted by 90 degrees from CLK0, CLK2 shifted by 90 degrees from CLK1, CLK3 shifted by 90 degrees from CLK2, and CLK0 shifted by 90 degrees from CLK3. Since 250 MHz corresponds to 4 ns, a 90-degree shift means that each clock is shifted by 1 ns.

[0047] Each vertical line in Figures 8(B) and (C) corresponds to 1 ns. As shown in Figure 8(B), assume that the phase difference waveform is high for only a short time. In this case, the phase difference waveform is high only when CLK1 is high, so counter 1 corresponding to CLK1 is set to 1. After that, the phase difference waveform becomes low, so this state continues. The values ​​counted by each counter are added together in the final adder circuit 52. As a result, in the example of Figure 8(B), the phase difference time becomes 1 (ns).

[0048] As shown in FIG. 8C, the phase difference waveform remains high for a longer period of time than in FIG. 8B. In this case, since the phase difference waveform remains high for all of CLK0 to CLK3, counters 0 to 3 corresponding to CLK0 to CLK3 count up, respectively. Specifically, counter 0 corresponding to CLK0 counts up to 4, counter 1 corresponding to CLK1 counts up to 4, counter 2 corresponding to CLK2 counts up to 5, and counter 3 corresponding to CLK3 counts up to 4. After that, the phase difference waveform becomes low, and this state continues. The values ​​counted by each counter are added together in the final adder circuit 52. As a result, in the example of FIG. 8C, the phase difference time is 4 + 4 + 5 + 4 = 17 (ns). Note that each counter counts up if the input signal is high when its own clock pulse goes high.

[0049] FIG. 9 is a diagram showing the details of the correction factor integrating circuit 60. FIG. 9(A) shows the circuit configuration, and FIG. 9(B) shows a timing chart of each signal. As shown in FIG. 9(A), the correction factor integrating circuit 60 is a circuit that receives the correction factor, phase difference time, and sign and outputs an integrated value. The correction factor has the role of gradually delaying the phase difference time rather than delaying it all at once. The correction factor integrating circuit 60 multiplies the correction factor by the current phase difference time, adds or subtracts the previous phase difference time to or from the current phase difference time, adds a sign, and outputs an integrated value.

[0050] For example, as shown in Figure 9(B), PWM1, 2, and 3 are output. PWM1, 2, and 3 are in an initial state with no delay. Note that the explanation here is given with a correction factor of 1. In contrast, Sync1, 2, and 3 are input with a delay as shown in the figure.

[0051] In this case, the phase difference times are as follows: (Sync1 → Sync2): Phase difference time of Sync2 as seen from Sync1: +3 (Sync2 → Sync3): Phase difference time of Sync3 as seen from Sync2: +1 (Sync3 → Sync1): Phase difference time of Sync1 as seen from Sync3: -4

[0052] In order to reflect the deviation of each Sync in the next PWMs 1, 2, and 3, it is difficult to speed up the slower Syncs, so the faster Syncs are delayed. In the example shown, Sync 3 is the slowest, so Syncs 1 and 2 are synchronized with Sync 3. Specifically, PWM 1 corresponding to Sync 1 is delayed by 4, and PWM 2 corresponding to Sync 2 is delayed by 1. PWM 3 corresponding to Sync 3 remains unchanged. Then, based on the results of delaying each PWM, the next Syncs 1, 2, and 3 are input.

[0053] In this case, the phase difference times are as follows: (Sync1 → Sync2): Phase difference time of Sync2 as seen from Sync1: +2 (Sync2 → Sync3): Phase difference time of Sync3 as seen from Sync2: -1 (Sync3 → Sync1): Phase difference time of Sync1 as seen from Sync3: -1

[0054] In this case, the integrated value of (Sync1 → Sync2) is 5 (=3+2), the integrated value of (Sync2 → Sync3) is 0 (=1-1), and the integrated value of (Sync3 → Sync1) is -5 (=-4-1).

[0055] FIG. 10 is a diagram illustrating part of the function of the correction factor integration circuit 60. FIG. 10A shows part of the circuit of the correction factor integration circuit 60, and FIG. 10B shows a timing chart of each signal and values ​​of various data. As shown in FIG. 10A, the addition / subtraction circuit receives data A, a code, and a value output from a flip-flop circuit (FF), and outputs a value obtained by adding or subtracting a value in which the code is reflected in data A and the value output from the flip-flop circuit. The flip-flop circuit also receives the value output from the addition / subtraction circuit and a CLK, and outputs the value output from the addition / subtraction circuit as an integrated value, and also outputs the value output from the addition / subtraction circuit to the addition / subtraction circuit. Note that data A is data obtained by multiplying the correction factor of FIG. 9 by the current phase difference time.

[0056] As shown in FIG. 10B, the initial value of data A is "0", the initial value of the code is "+ (e.g., 0)", and the initial value of the integrated value is "0". Furthermore, different values ​​are input to data A and the code as time passes. When CLK is input to the flip-flop circuit, an operation is performed in the addition / subtraction circuit, and an integrated value is output from the flip-flop circuit. An example of the output of the integrated value is as follows:

[0057] At the first rising edge of CLK, data A is "0" and the code is "+", so the integrated value is output as "0 (0 + 0 = 0)". At the second rising edge of CLK, data A is "2" and the code is "+", so the integrated value is output as "2 (0 + 2 = 2)". At the third rising edge of CLK, data A is "1" and the code is "+", so the integrated value is output as "3 (2 + 1 = 3)". At the fourth rising edge of CLK, data A is "2" and the code is "- (for example, 1)", so the integrated value is output as "1 (3 - 2 = 1)".

[0058] At the fifth rising edge of CLK, data A is "1" and the code is "+", so the integrated value is output as "2 (1 + 1 = 2)". At the sixth rising edge of CLK, data A is "2" and the code is "-", so the integrated value is output as "0 (2 - 2 = 0)". At the seventh rising edge of CLK, data A is "1" and the code is "-", so the integrated value is output as "-1 (0 - 1 = -1)". At the eighth rising edge of CLK, data A is "2" and the code is "+", so the integrated value is output as "1 (-1 + 2 = 1)". In this way, the correction factor integration circuit 60 uses a flip-flop circuit to hold the previous phase difference time.

[0059] 11A and 11B are diagrams showing the details of the delay time determination circuit 70. Fig. 11A shows the circuit configuration, and Fig. 11B shows a specific calculation example. As shown in Fig. 11A, the delay time determination circuit 70 is a circuit that receives the integrated value of (Sync1 → Sync2), the integrated value of (Sync2 → Sync3), and the integrated value of (Sync3 → Sync1), and outputs the PWM1 delay time, the PWM2 delay time, and the PWM3 delay time.

[0060] The delay time determination circuit 70 first inverts the sign of the integrated value, then makes positive values ​​positive and converts negative values ​​to 0, and finally compares the values ​​and outputs the larger value, which is used as the delay time for each PWM.

[0061] 11B, for example, the integrated value of (Sync1 → Sync2) is 5, the integrated value of (Sync2 → Sync3) is 0, and the integrated value of (Sync3 → Sync1) is −5. Then, by inverting the plus and minus signs, the integrated value of (Sync1 → Sync3) becomes 5, the integrated value of (Sync2 → Sync1) becomes −5, and the integrated value of (Sync3 → Sync2) becomes 0.

[0062] Next, if we keep the positive accumulated values ​​as positive values ​​and convert the negative values ​​to 0, we get the following results. (Sync1 → Sync2): Sync2 seen from Sync1: 5 → 5 (Sync1 → Sync3): Sync3 seen from Sync1: 5 → 5 (Sync2 → Sync1): Sync1 seen from Sync2: -5 → 0 (Sync2 → Sync3): Sync3 seen from Sync2: 0 → 0 (Sync3 → Sync1): Sync1 seen from Sync3: -5 → 0 (Sync3 → Sync2): Sync2 seen from Sync3: 0 → 0

[0063] Finally, when a comparison is made and the larger value is output, the delay times are as follows. The reason for setting negative values ​​to 0 and selecting the larger value is to synchronize the remaining Syncs with the slowest Sync. PWM1 delay time: 5 PWM2 delay time: 0 PWM3 delay time: 0

[0064] FIG. 12 is a diagram illustrating the concept of the processing performed by the delay time determination circuit 70 (in the case of two Syncs). For example, assume that Sync1 and Sync2, whose waveforms are as shown in FIG. 12A, are input to the FPGA 30. (1) Sync1 leads Sync2 by 5 (Sync1 → Sync2: 5). In this situation, to align Sync1 and Sync2, PWM1 must lag PWM2 by 5. (2) On the other hand, Sync2 lags Sync1 by 5 (Sync2 → Sync1: -5). In this situation, to align Sync1 and Sync2, PWM2 must lead PWM1 by 5.

[0065] (3) Even if both (1) and (2) above are executed, Sync1 and Sync2 will simply be swapped, so either (1) or (2) above must be executed. However, because it is difficult to advance PWM2 in (2) above, this is not executed, and instead the process of delaying PWM1 in (1) above is executed. As a result, the delay time of PWM1 is set to 5, and the delay time of PWM2 is set to 0. Then, as shown in FIG. 12(B), PWM1 is delayed by 5, and PWM2 is left as is (PWM2 is not delayed). In FIG. 11, the negative values ​​set to 0 mean that PWM is left as is (not delayed).

[0066] 13 is a diagram showing the concept of the processing contents (in the case of three Syncs) of the delay time determination circuit 70. For example, assume that Sync1, Sync2, and Sync3 with waveforms as shown in FIG. 13(A) are input to the FPGA 30. Here, Sync2 and Sync3 are delayed by the same time relative to Sync1. The relationship between each Sync is as follows: (Sync1 → Sync2): Sync2: 5 as seen from Sync1 (Sync1 → Sync3): Sync3: 5 as seen from Sync1 (Sync2 → Sync1): Sync1: -5 as seen from Sync2 (Sync2 → Sync3): Sync3: 0 as seen from Sync2 (Sync3 → Sync1): Sync1: -5 as seen from Sync3 (Sync3 → Sync2): Sync2: 0 as seen from Sync3

[0067] The relationship between each PWM is as follows: (PWM1 → PWM2): PWM2: -5 as seen from PWM1 (PWM1 → PWM3): PWM3: -5 as seen from PWM1 (PWM2 → PWM1): PWM1: 5 as seen from PWM2 (PWM2 → PWM3): PWM3: 0 as seen from PWM2 (PWM3 → PWM1): PWM1: 5 as seen from PWM3 (PWM3 → PWM2): PWM2: 0 as seen from PWM3

[0068] From these relationships, the delay time of PWM1 is set to 5, the delay time of PWM2 to 0, and the delay time of PWM3 to 0. Then, PWM1 is delayed by 5, and PWM2 and PWM3 are left as they are (PWM2 and PWM3 are not delayed).

[0069] Also, for example, assume that Sync1, Sync2, and Sync3 having waveforms as shown in Fig. 13B are input to the FPGA 30. Here, Sync2 and Sync3 are delayed by different times relative to Sync1. The relationship between each Sync is as follows: (Sync1 → Sync2): Sync2 as seen from Sync1: 5 (Sync1 → Sync3): Sync3 as seen from Sync1: 5 (Sync2 → Sync1): Sync1 as seen from Sync2: -5 (Sync2 → Sync3): Sync3 as seen from Sync2: -2 (Sync3 → Sync1): Sync1 as seen from Sync3: -3 (Sync3 → Sync2): Sync2 as seen from Sync3: -2

[0070] The relationship between each PWM is as follows: (PWM1 → PWM2): PWM2: -5 as seen from PWM1 (PWM1 → PWM3): PWM3: -3 as seen from PWM1 (PWM2 → PWM1): PWM1: 5 as seen from PWM2 (PWM2 → PWM3): PWM3: 2 as seen from PWM2 (PWM3 → PWM1): PWM1: 3 as seen from PWM3 (PWM3 → PWM2): PWM2: -2 as seen from PWM3

[0071] From these relationships, the delay time of PWM1 is set to 5, the delay time of PWM2 to 0, and the delay time of PWM3 to 2. Then, PWM1 is delayed by 5, PWM2 is left as is (PWM2 is not delayed), and PWM3 is delayed by 2.

[0072] FIG. 14 is a diagram showing the details of the delay circuit 80. The delay circuit 80 receives PWM, CLK0-3, and a PWM1 delay time and outputs PWM1. The delay circuit 80 also includes a PWM rising edge delay circuit 81 and a PWM falling edge delay circuit 82, and the outputs of both circuits are latched (combined) and output. The only difference between the PWM rising edge delay circuit 81 and the PWM falling edge delay circuit 82 is that the PWM rising edge CLK selection is changed to a PWM falling edge CLK selection, so a detailed description of the PWM falling edge delay circuit 82 will be omitted. The illustrated circuit is a delay circuit 80 for PWM1, but delay circuits 80 for PWM2 and PWM3 also exist. The delay circuit 80 for PWM2 and the delay circuit 80 for PWM3 are simply the circuits shown in the figure, with PWM1 replaced with PWM2 and PWM3, and therefore detailed explanations thereof will be omitted.

[0073] In the upper circuit of the PWM rising edge delay circuit 81, the PWM and CLK0 to CLK3 are input to the PWM rising edge CLK selection circuit, which detects the rising edge of the PWM. The PWM rising edge CLK selection circuit selects the clock (CLK0 / CLK1 / CLK2 / CLK3) to which the PWM signal responds first. The detection result is then encoded and added to the two least significant bits of the delay time to create the address of the multiplexer.

[0074] The lower circuit in the PWM rising edge delay circuit 81 detects the PWM edge using edge detection 0-3, rotates counters 0-3 using the upper two bits of the PWM1 delay time, detects the edge of the carry signal using edges 0-3, and outputs a pulse to the multiplexer. The upper circuit determines which pulse to select from the pulses output to the multiplexer. The rising pulse output from the multiplexer is latched with the falling pulse output from the multiplexer in the falling edge delay circuit, and finally, PWM1 reflecting the delay time is output.

[0075] Fig. 15 is a simplified diagram of the delay circuit 80 of Fig. 14. The PWM detection circuit based on each clock detects a PWM signal based on each clock, the multiplexer address calculation circuit calculates the address of the multiplexer, and the PWM delay circuit based on each clock outputs a pulse to the multiplexer based on each clock.

[0076] The delay circuit 80 latches the rising pulse output from the multiplexer and the falling pulse output from the multiplexer of the PWM falling delay circuit, and outputs PWM1 reflecting the delay time. Note that the upper circuit in the PWM rising delay circuit 81 in Fig. 14 corresponds to the PWM detection circuit and multiplexer address calculation circuit based on each clock in Fig. 15, and the lower circuit in the PWM rising delay circuit 81 in Fig. 14 corresponds to the PWM delay circuit and multiplexer based on each clock in Fig. 15.

[0077] 16 is a sequence diagram when PWM is detected by CLK1 in the delay circuit 80. In the example shown, CLK1 rises first after PWM rises. The delay time is determined based on the clock (in this example, CLK1) that first detected the PWM signal.

[0078] When the counter counts 1 (the output value when the counter is set to 1), the output is as follows: Counter 0_1 count carry: delay 3 ns Counter 1_1 count carry: delay 0 ns Counter 2_1 count carry: delay 1 ns Counter 3_1 count carry: delay 2 ns

[0079] When the counter counts 2 (the output value when the counter is set to 2), it is as follows. If you want to delay by 8 ns or more, use a counter of 3 or more. Counter 0_2 count carry: Delay 7 ns Counter 1_2 count carry: Delay 4 ns Counter 2_2 count carry: Delay 5 ns Counter 3_2 count carry: Delay 6 ns

[0080] If the delay time determination results in PWM1 delay time = 5 ns, PWM2 delay time = 0 ns, and PWM3 delay time = 0 ns, for PWM1 delay time = 5 ns, PWM1 is delayed to a point corresponding to "counter 2_2 count carry: delay 5 ns" and output. Also, for PWM2 delay time = 0 ns and PWM3 delay time = 0 ns, PWM2 and PWM3 are output at a point corresponding to "counter 1_1 count carry: delay 0 ns."

[0081] The timing of the reference "Counter 1_1 count carry: delay 0 ns" depends on the processing time of the circuit, but can be set to a timing delayed by 4 ns x N (N = an integer greater than or equal to 1) from the timing when CLK1 detects PWM.

[0082] 17 is a sequence diagram when PWM is detected by CLK2 in the delay circuit 80. In the example shown, CLK2 rises first after PWM rises. The delay time is determined based on the clock (in this example, CLK2) that first detected the PWM signal.

[0083] When the counter counts 1, the following occurs: Counter 0_1 count carry: delay 2 ns Counter 1_1 count carry: delay 3 ns Counter 2_1 count carry: delay 0 ns Counter 3_1 count carry: delay 1 ns

[0084] When the counter counts 2, the delay is as follows: Counter 0_2 count carry: 6 ns delay Counter 1_2 count carry: 7 ns delay Counter 2_2 count carry: 4 ns delay Counter 3_2 count carry: 5 ns delay

[0085] If the delay time determination results in PWM1 delay time = 5 ns, PWM2 delay time = 0 ns, and PWM3 delay time = 0 ns, for PWM1 delay time = 5 ns, PWM1 is delayed to a point corresponding to "counter 3_2 count carry: delay 5 ns" and output. Also, for PWM2 delay time = 0 ns and PWM3 delay time = 0 ns, PWM2 and PWM3 are output at a point corresponding to "counter 2_1 count carry: delay 0 ns."

[0086] The timing of the reference "Counter 2_1 count carry: delay 0 ns" depends on the processing time of the circuit, but can be set to a timing delayed by 4 ns x N (N = an integer greater than or equal to 1) from the timing when CLK2 detects PWM.

[0087] FIG. 18 shows the details of the PWM rising CLK selection circuit. The PWM falling CLK selection circuit is omitted here, as it simply changes the rising edge processing to the falling edge processing. The PWM rising CLK selection circuit receives PWM and a clear signal (CLR) as inputs and outputs SC0 to SC3. The PWM rising CLK selection circuit includes a flip-flop circuit, an AND circuit, an OR circuit, etc., latches at each CLK, and after latching, executes processing using a predetermined logic (e.g., AND of CLK0 and the inverse of CLK3), and outputs SC0 to SC3 indicating which CLK latched the rising edge of the PWM based on the PWM and CLK0 to CLK3.

[0088] CKL0 corresponds to SC0, CKL1 corresponds to SC1, CKL2 corresponds to SC2, and CKL3 corresponds to SC3. For example, when PWM is latched with CLK1, SC1 corresponding to CLK1 becomes High.

[0089] FIG. 19 shows the signals related to the PWM rising CLK selection circuit. CLK0 to CLK3 are displayed at the top of the figure, with the vertical dotted lines corresponding to 1 ns. When the PWM is input to the FPGA 30, it is latched at CLK0 to CLK3. Then, the output values ​​of (1) to (4) and SC0 to SC3 become the values ​​shown in the figure. For example, among the waveforms of (1) to (4) of the PWM rising CLK selection circuit, only (2) momentarily rises to high. This is because (2) goes high when the CLK1 latch is high and the CLK0 latch is low. On the other hand, in the case of CLK1 and CLK2, the CLK2 latch is high and the CLK1 latch is never low, so they are always low. This is also true for the other CLKs.

[0090] Then, we want to hold the rising state of (2), but the timing for holding is the falling edge of (2), which sets SC1 High. "SC1 = High (1)" means that CLK1 corresponding to SC1 first detected PWM. Note that the circuit actually operates at 250 MHz, but to operate it normally, it is preferable to ensure a frequency band of at least 333 MHz (= 250 MHz x 4 / 3) with some margin in mind.

[0091] FIG. 20 shows actual signals related to the PWM rising CLK selection circuit. The signals shown in FIG. 19 are ideal graphs. Flip-flops and other circuits are designed to output data at the same timing as the clock, but delays actually occur. Therefore, the actual waveforms are as shown by the solid lines in FIG. 20. Even with such waveforms, the PWM rising CLK selection circuit in FIG. 18 can output data as "SC1 = High (1)" without any problems. Since the FPGA of this embodiment operates at 500 MHz, the delay is expected to be less than 2 ns. However, even with such a delay, only SC1 can be correctly set to High.

[0092] 21 is a conceptual diagram showing part of the processing contents of the delay circuit 80. The delay circuit 80 encodes SC0 to SC3. The contents of the encoded values ​​are as follows: SC0=1, SC1=0, SC2=0, SC3=0 → encoded value 00 SC0=0, SC1=1, SC2=0, SC3=0 → encoded value 01 SC0=0, SC1=0, SC2=1, SC3=0 → encoded value 10 SC0=0, SC1=0, SC2=0, SC3=1 → encoded value 11

[0093] The delay circuit 80 converts the delay time into a binary value, specifically as follows: Delay time 0 ns → 0000 Delay time 1 ns → 0001 Delay time 2 ns → 0010 Delay time 3 ns → 0011 Delay time 4 ns → 0100 Delay time 5 ns → 0101 Delay time 6 ns → 0110 Delay time 7 ns → 0111

[0094] The delay circuit 80 adds the two least significant bits of the binary delay time to the encoded value to obtain the address of the multiplexer. The delay circuit 80 also adds the two most significant bits of the binary delay time (the bits other than the two least significant bits) to a fixed value of "01" to obtain counter data. The fixed value is a predetermined value, and is set to "01" to ensure that the counter is turned at least once.

[0095] For example, when the delay time is 0 ns, the multiplexer address is 01 and the counter is 01, which corresponds to the location of counter 1-1 (see FIG. 16). Also, when the delay time is 5 ns, the multiplexer address is 10 and the counter is 10, which corresponds to the location of counter 2-2 (see FIG. 16).

[0096] The reason for dividing the upper and lower bits is that the clock has a 4n cycle at 250 MHz, and 4n is equivalent to the square of 2, so if we use 4n as the base, the decimal point will be placed in the second digit.The decimal point determines which address to select, and the integer part determines the counter data.

[0097] Figure 22 is a diagram showing the circuit configuration of an FPGA with triple parallel feedback control. The phase difference detection circuits include a first phase difference detection circuit 40a, a second phase difference detection circuit 40b, and a third phase difference detection circuit 40c. The phase difference time measurement circuits include a first phase difference time measurement circuit 50a, a second phase difference time measurement circuit 50b, and a third phase difference time measurement circuit 50c. The correction factor integration circuits include a first correction factor integration circuit 60a, a second correction factor integration circuit 60b, and a correction factor integration circuit 60c. Only one delay time determination circuit 70 is provided. The delay circuits include a first delay circuit 80a, a second delay circuit 80b, and a third delay circuit 80c.

[0098] In the triple-parallel feedback control FPGA 30, phase difference detection involves detecting the phase difference between Sync1 and Sync2, between Sync2 and Sync3, and between Sync3 and Sync1, measuring the respective phase difference times, integrating correction factors, determining the delay times in the delay time determination circuit 70, and finally outputting PWM1, 2, and 3 from the individual delay circuits. PWM1 is output to the first gate driver SiC1_101, PWM2 is output to the second gate driver SiC2_102, and PWM3 is output to the third gate driver SiC3_103.

[0099] 23 is a diagram showing the circuit configuration of an FPGA with dual parallel feedback control. The phase difference detection circuit is a first phase difference detection circuit 40a. The phase difference time measurement circuit is a first phase difference time measurement circuit 50a. The correction factor integration circuit is a first correction factor integration circuit 60a. Only one delay time determination circuit 70 is provided. The delay circuits are a first delay circuit 80a and a second delay circuit 80b.

[0100] In the dual-parallel feedback control FPGA 30, the phase difference is detected using Sync1 and Sync2, the phase difference time is measured, a correction factor is integrated, the delay time is determined by the delay time determination circuit 70, and finally PWM is output by each delay circuit. PWM1 is output to the first gate driver SiC1_101, and PWM2 is output to the second gate driver SiC2_102.

[0101] FIG. 24 is a diagram showing the circuit configuration of an FPGA for multi-parallel feedback control. The phase difference detection circuits include a first phase difference detection circuit 40a, a second phase difference detection circuit 40b, a third phase difference detection circuit 40c, ..., and an nth phase difference detection circuit 40n. The phase difference time measurement circuits include a first phase difference time measurement circuit 50a, a second phase difference time measurement circuit 50b, a third phase difference time measurement circuit 50c, ..., and an nth phase difference time measurement circuit 50n. The correction factor integrating circuits include a first correction factor integrating circuit 60a, a second correction factor integrating circuit 60b, a correction factor integrating circuit 60c, ..., and a correction factor integrating circuit 60n. Only one delay time determination circuit 70 is provided. The delay circuits include a first delay circuit 80a, a second delay circuit 80b, a third delay circuit 80c, ..., and an nth delay circuit 80n.

[0102] In the multi-parallel feedback control FPGA 30, phase difference detection involves detecting the phase difference between Sync1 and Sync2, Sync2 and Sync3, Syncn-1 and Syncn, and Syncn and Sync1, measuring each phase difference time, integrating correction factors, determining the delay time in the delay time determination circuit 70, and finally outputting PWMs from the individual delay circuits. PWM1 is output to the first gate driver SiC1_101, PWM2 is output to the second gate driver SiC2_102, PWM3 is output to the third gate driver SiC3_103, and PWMn is output to the n-th gate driver SiCn_100n.

[0103] FIG. 25 is a diagram showing a modified example of the phase difference time measurement circuit 50. As shown in FIG. 25, the phase difference time measurement circuit 50A is a circuit that receives a phase difference and a clock and outputs a phase difference time. The phase difference (phase detection pulse in FIG. 7) is input to the phase difference time measurement circuit 50A, and counters 0 to 7 are controlled by CLK0 to CLK7 generated by a PLL 51A. Data 0 to 7 are added by an adder circuit 52A to measure the phase difference time. The phase difference time measurement circuit 50A also uses a 250 MHz, 8-phase-shift PLL 51A to measure (resolve) the phase difference pulse in 0.5 ns intervals. This allows the resolution of the phase difference time measurement circuit 50A to be 0.5 ns, double that of FIG. 8.

[0104] 26 is a diagram showing the configuration of a circuit for evaluating the operation of triple-parallel feedback control. The FPGA 30 shown on the left side of the figure has the same configuration as that shown in FIG. 4. The FPGA delay jig 200 shown on the right side of the figure is a jig for evaluating the FPGA 30. The FPGA delay jig 200 includes a first delay circuit 201a, a second delay circuit 201b, a third delay circuit 201c, and a PLL 202.

[0105] The first delay circuit 201a receives PWM1, delays it by a first delay time that can be set arbitrarily using a switch, etc., and outputs Vdsps1. The second delay circuit 201b receives PWM2, delays it by a second delay time that can be set arbitrarily using a switch, etc., and outputs Vdsps2. The third delay circuit 201c receives PWM3, delays it by a third delay time that can be set arbitrarily using a switch, etc., and outputs Vdsps3. The first delay circuit 201a, the second delay circuit 201b, and the third delay circuit 201c can each have their own delay time setting. The setting range is 0 to 63 ns in 1 ns increments. The PLL 202 receives a 100 MHz clock and operates with a 250 MHz four-phase shift.

[0106] Vdsps1 to Vdsps3 are converted to Sync1 to Vdsps3 by the FPGA delay jig 200 and input to the FPGA 30. PWM1 to PWM3 and Sync1 to PWM3 are measured by an oscilloscope.

[0107] 27A and 27B are diagrams showing an outline of correction factor processing. As shown in Fig. 27A, the phase difference time (delay time change amount) can be converted into a corrected phase difference time (control delay time) by integrating the correction factor.

[0108] 27B, if Sync1 and Sync2 have the same timing and Sync2 is delayed by 10 from Sync1, the phase difference time will be 10 ns. If the correction factor is 1.0, the subsequent calculations will be based on this 10 ns, but if the correction factor is 0.5, the subsequent calculations will be based on 5 ns, which is the 10 ns multiplied by the correction factor.

[0109] Therefore, as shown in FIG. 27(C), assuming that the phase difference time decreases by half from 10 ns with the passage of time, when the correction rate is 0.5, the phase difference time after correction can be gradually decreased from "5 ns (=10 ns×0.5)" to "2.5 ns (=5 ns×0.5)" to "1.25 ns (=2.5 ns×0.5)", and so on.

[0110] FIG. 28 shows the measurement results when the correction factor is 1.0. The delay times in the FPGA delay jig 200 are PWM1: 0 ns, PWM2: 16 ns, and PWM3: 32 ns. The delay times are set only once at the beginning of multiple pulses. As a result, at the rising edge of the first pulse, Sync2 is significantly delayed from Sync1, and Sync3 is significantly delayed from Sync2. However, this delay is used to control the delay of PWM1 to PWM3. Specifically, PWM1 and PWM2 are delayed so that they are synchronized with PWM3, which corresponds to Sync3, which is the most delayed (see arrow B1).

[0111] At the rising edge of the second pulse, Sync1 to Sync3 are almost synchronized. However, there is a slight deviation, so delay control of PWM1 to PWM3 is performed to adjust for this deviation (see arrow B2).

[0112] At the rising edge of the third pulse, Sync1 to Sync3 are almost aligned. However, there is a slight deviation, so delay control of PWM1 to PWM3 is performed to adjust for this deviation. In this way, with a correction factor of 1.0, the deviation of Sync1 to Sync3 is mostly eliminated by the time the third pulse rises.

[0113] Figure 29 shows the measurement results when the correction factor is 0.5. The measurement conditions other than the correction factor are the same as those in Figure 28. When the correction factor is 0.5, at the rising edge of the first pulse, Sync2 is significantly delayed from Sync1, and Sync3 is significantly delayed from Sync2. This delay is used to perform delay control of PWM1 to PWM3. Specifically, PWM1 and PWM2 are delayed so that they are synchronized with PWM3, which corresponds to Sync3, which is the most delayed (see arrow C1).

[0114] At the rising edge of the second pulse, Sync2 is delayed from Sync1, and Sync3 is delayed from Sync2. This delay is used to control the delay of PWM1 to 3. Specifically, PWM1 and 2 are delayed so that they are synchronized with PWM3, which corresponds to Sync3, which is the most delayed (see arrow C2).

[0115] At the rising edge of the third pulse, Sync2 is slightly delayed from Sync1, and Sync3 is slightly delayed from Sync2. This delay is used to perform delay control of PWM1 to 3. Specifically, PWM1 and 2 are delayed so that they are synchronized with PWM3, which corresponds to Sync3, which is the most delayed (see arrow C3).

[0116] At the rising edge of the fourth pulse, Sync2 is slightly delayed from Sync1, and Sync3 is slightly delayed from Sync2. This delay is used to perform delay control of PWM1 to 3. Specifically, PWM1 and 2 are delayed so that they are synchronized with PWM3, which corresponds to Sync3, which is the most delayed (see arrow C4).

[0117] At the rising edge of the fifth pulse, Syncs 1 to 3 are nearly aligned. However, there is a slight deviation, so delay control of PWMs 1 to 3 is performed to adjust for this deviation. In this way, with a correction factor of 0.5, the deviation of Syncs 1 to 3 is gradually eliminated by the time of the rising edge of the fifth pulse. In this way, if the correction factor is made smaller, it will take more time for the Syncs to align, but it is possible to slowly align the Syncs little by little.

[0118] 30 shows the results of jitter measurement. Here, each signal is overwritten with PWM1 as the reference, and the jitter is measured. As shown in FIG. 30(A), when the correction factor is 1.0, a deviation of 5 ns occurs as jitter. On the other hand, as shown in FIG. 30(B), when the correction factor is 0.5, a deviation of 2.5 ns occurs as jitter.

[0119] As you can see, when the correction factor is reduced, the jitter width becomes smaller. This indicates that variations occur within the circuit, and when these variations are directly controlled, they are controlled in the wrong direction and amplified. This increase in the jitter width can be prevented by adjusting the correction factor. For this reason, even when there is a large change (even when the phase difference time is large), the jitter width can be reduced by making only small changes (by gradually reducing the phase difference time).

[0120] The correction factor may be a predetermined fixed value, or may be a variable value that is increased at the beginning of control and decreased as the control becomes stable. In some cases, the correction factor may be decreased at the beginning of control and increased as the control becomes stable.

[0121] FIG. 31 is a diagram showing the configuration of the correction limiter. The circuit configuration is basically the same as that shown in FIG. 26, but the delay time determination circuit 70 has a correction limiter setting function. The correction limiter is a limiter that determines the maximum value of the delay time. The correction limiter can be set to a fixed value (e.g., 15 ns). Here, the FPGA delay jig 200 delays Sync1 by 32 ns for evaluation.

[0122] 32 is a diagram showing the measurement results of the correction limiter. In FIG. 32, only Sync1 and Sync2 are displayed for PWM1, 2, and 3. At timing No. 0, Sync1 has a delay of 0, and at timing No. 1, Sync1 is forcibly delayed by 32 ns using the FPGA delay jig 200.

[0123] FIG. 33 shows detailed measurement results of the correction limiter. At timing No. 0, Sync1 has a delay of 0. In this case, PWM1, 2, and 3 are synchronized. Sync1 is delayed by 40 ns relative to PWM1 due to internal processing, etc. At timing No. 1, Sync1 is forcibly delayed by 32 ns. Specifically, this is 40 ns + 32 ns, meaning that Sync1 is delayed by 72 ns relative to PWM1. At this point, PWM1, 2, and 3 are synchronized.

[0124] At timing No. 2, the correction limiter is in effect. Ideally, PWM2 and PWM3 would be delayed significantly (16 ns or more) to synchronize Sync2 with the delayed Sync1, but because of the correction limiter, PWM2 and PWM3 are delayed by only a maximum of 15 ns. At timing No. 3, the correction limiter is also in effect. Therefore, PWM2 and PWM3 are delayed by only a maximum of 15 ns. By using this correction limiter function, sudden changes in PWM1, 2, and PWM3 can be avoided.

[0125] As described above, this embodiment has the following advantages. (1) Because the operating frequency of the FPGA 30 is a maximum of several hundred MHz, the time measurement resolution is several nanoseconds. Therefore, it is difficult to measure time with a resolution equal to or higher than the operating frequency (less than 4 nanoseconds). Therefore, this embodiment provides a circuit with improved resolution (a circuit capable of measuring time with a resolution of 1 nanosecond) by using a circuit configuration that uses a PLL.

[0126] (2) Because the operating frequency of the FPGA 30 is a maximum of several hundred MHz, the time unit of the signal delay is several nanoseconds. Therefore, it is difficult to ensure a time unit of the signal delay equal to or greater than the operating frequency (smaller than 4 nanoseconds). Therefore, in this embodiment, a circuit configuration using a PLL can be provided to improve the time unit of the signal delay (a circuit capable of delaying a signal (PWM) in 1 nanosecond units).

[0127] (3) According to this embodiment, PWM1, 2, and 3 (output signals) are delayed based on Sync1, 2, and 3 (input signals). This makes it possible to suppress phase variations in the gate driver SiC, and to drive the gate driver SiC (multiple external devices) in correct synchronization.

[0128] (4) According to this embodiment, since a correction factor is used, it is possible to gently synchronize the gate drivers and SiC (multiple external devices).

[0129] (5) According to this embodiment, since a PLL (phase-locked loop) is used, it is possible to measure time and delay signals with a resolution (resolution of 1 ns or less) higher than the maximum operating frequency (4 ns) of the delay control circuit.

[0130] [Modifications] The present invention is not limited to the above-described embodiment and can be implemented in various modifications. (1) The output signals have been described using examples of PWM1, 2, and 3, but other signals may also be used. The input signals have been described using examples of Sync1, 2, and 3, but other signals may also be used. (2) The correction factor and correction limiter do not need to be used.

[0131] (3) The phase difference time measurement unit does not need to use a phase locked loop. (4) Although the SiC has been described as a four-terminal example, it may also be a three-terminal type. If a three-terminal type is used and the driver source T3 terminal is eliminated, a shunt resistor can be placed next to the coil 16 or the motor, and a waveform (input signal) that replaces Sync can be output to the FPGA from the waveform of the shunt resistor.

[0132] (5) Although explanations of the rising and falling edges, PWM1, 2, 3, and Sync1, 2, 3 are omitted, the control content of one process can be changed to content suitable for the control content of another process and reused.

[0133] (6) In addition, the structures and circuit configurations illustrated in the embodiments are merely preferred examples, and various elements can be added to the basic structure, some of the configurations can be replaced, or some of the configurations can be deleted.

[0134] REFERENCE SIGNS LIST 10 Drive circuit 11 Power supply 12 Control board 13, 14, 15 Power switching device 16 Coil 20a First gate driver 20b Second gate driver 20c Third gate driver 30 FPGA 40 Phase difference detection circuit 50 Phase difference time measurement circuit 51 PLL 60 Correction factor integrating circuit 70 Delay time determination circuit 80 Delay circuit 90 Time difference measurement circuit 91 Detection circuit 100 Gate driver SiC

Claims

1. A delay control circuit that outputs an output signal to each of a plurality of external devices connected in parallel, receives an input signal based on the output signal from each of the external devices, and delays the output signal based on the input signal, comprising: a phase difference detection unit that detects a phase difference of the input signals input from each of the external devices; a phase difference time measurement unit that measures a phase difference time of the phase difference detected by the phase difference detection unit; an integrating unit that calculates an integrated value by adding / subtracting a previous phase difference time to / from the current phase difference time measured by the phase difference time measurement unit; a delay time determination unit that determines the delay time of the output signal based on the integrated value calculated by the integrating unit; and a delay unit that delays the output signal based on the delay time determined by the delay time determination unit.

2. A delay control circuit as claimed in claim 1, wherein said integrating section multiplies the current phase difference time measured by said phase difference time measuring section by a predetermined correction factor.

3. A delay control circuit as claimed in claim 1, characterized in that the phase difference time measuring section uses a phase locked loop circuit.

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