Printed wiring board

Abstract

This printed wiring board is provided with: a first base film having a first main surface and a second main surface; first wiring disposed on the first main surface; an adhesive layer disposed on the first main surface so as to cover the first wiring; a second base film having a third main surface and a fourth main surface and disposed on the adhesive layer so that the third main surface faces the adhesive layer; and second wiring disposed on the fourth main surface. The first wiring comprises a first seed layer disposed on the first main surface, and a first copper layer disposed on the first seed layer. The second wiring comprises a second seed layer disposed on the fourth main surface, and a second copper layer disposed on the second seed layer. The thickness of the second copper layer is greater than the thickness of the first copper layer.

Description

printed wiring board

[0001] This application claims priority to Japanese Patent Application No. 2023-208725, filed December 11, 2023, and incorporates by reference all of the contents of that application.

[0002] For example, Japanese Patent Laid-Open Publication No. 2022-135197 (Patent Document 1) describes a printed wiring board. The printed wiring board described in Patent Document 1 has a base film and wiring. The wiring is disposed on a main surface of the base film. The wiring has an underlayer disposed on the main surface of the base film. The underlayer has a first layer and a second layer disposed on the first layer. The material of the second layer is copper.

[0003] Japanese Patent Application Laid-Open No. 2022-135197

[0004] The printed wiring board of the present disclosure comprises a first base film having a first main surface and a second main surface, a first wiring disposed on the first main surface, an adhesive layer disposed on the first main surface so as to cover the first wiring, a second base film having a third main surface and a fourth main surface and disposed on the adhesive layer so that the third main surface faces the adhesive layer, and a second wiring disposed on the fourth main surface. The first wiring has a first seed layer disposed on the first main surface and a first copper layer disposed on the first seed layer. The second wiring has a second seed layer disposed on the fourth main surface and a second copper layer disposed on the second seed layer. The thickness of the second copper layer is greater than the thickness of the first copper layer.

[0005] FIG. 1 is a first plan view of printed wiring board 100. FIG. 2 is a second plan view of printed wiring board 100. FIG. 3A is a plan view of printed wiring board 100 omitting adhesive layer 30, base film 40, and wiring 60. FIG. 3B is a plan view of printed wiring board 100 omitting adhesive layer 31, base film 50, and wiring 61. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a manufacturing process diagram of printed wiring board 100. FIG. 6 is a cross-sectional view illustrating conductive layer formation step S2. FIG. 7 is a cross-sectional view illustrating resist pattern formation step S3. FIG. 8 is a cross-sectional view illustrating electrolytic plating step S4. FIG. 9 is a cross-sectional view illustrating resist pattern removal step S5. FIG. 10 is a cross-sectional view illustrating etching step S6. FIG. 11 is a cross-sectional view illustrating substrate attachment step S7. FIG. 12 is a cross-sectional view illustrating through-hole formation step S8. FIG. 13 is a cross-sectional view illustrating conductive layer formation step S9. FIG. 14 is a cross-sectional view illustrating resist pattern formation step S10. Fig. 15 is a cross-sectional view illustrating the electrolytic plating step S11. Fig. 16 is a cross-sectional view illustrating the resist pattern removal step S12. Fig. 17 is a cross-sectional view of the printed wiring board 100 according to the second modified example. Fig. 18 is a manufacturing process diagram of the printed wiring board 100 according to the second modified example. Fig. 19 is a cross-sectional view of the printed wiring board 100 according to the third modified example. Fig. 20 is a cross-sectional view of the printed wiring board 100 according to the fourth modified example.

[0006] When attempting to multilayer wiring in the printed wiring board described in Patent Document 1, a base layer is disposed on a main surface of a base film by an adhesive layer. When laminating the base film, the base film may be distorted. One object of the present disclosure is to provide a printed wiring board that can suppress distortion of the laminated base film.

[0007] In the printed wiring board of the present disclosure, distortion of the laminated base film (second base film) can be suppressed.

[0008] First, embodiments of the present disclosure will be listed and described.

[0009] (1) A printed wiring board according to an embodiment of the present disclosure includes a first base film having a first main surface and a second main surface, a first wiring disposed on the first main surface, an adhesive layer disposed on the first main surface so as to cover the first wiring, a second base film having a third main surface and a fourth main surface and disposed on the adhesive layer so that the third main surface faces the adhesive layer, and a second wiring disposed on the fourth main surface. The first wiring includes a first seed layer disposed on the first main surface and a first copper layer disposed on the first seed layer. The second wiring includes a second seed layer disposed on the fourth main surface and a second copper layer disposed on the second seed layer. The thickness of the second copper layer is greater than the thickness of the first copper layer.

[0010] According to the printed wiring board of (1) above, it is possible to suppress distortion of the second base film.

[0011] (2) In the printed wiring board of (1) above, the first copper layer may have a thickness of 0.5 μm or less.

[0012] (3) In the printed wiring board of (1) or (2) above, the second copper layer may have a thickness of 0.5 μm or more and 3.0 μm or less.

[0013] According to the printed wiring board of (3) above, it is possible to suppress distortion of the second base film while maintaining the cross-sectional area of ​​the second wiring.

[0014] (4) In the printed wiring boards of (1) to (3), the second wiring may have a plurality of linear wiring portions arranged at intervals. The pitch of the plurality of wiring portions may be 20 μm or more and 60 μm or less.

[0015] (5) In the printed wiring boards of (1) to (4) above, the height of the second wiring may be 20 μm or more and 100 μm or less.

[0016] (6) In the printed wiring boards of (1) to (5) above, the adhesive layer may be made of an adhesive, and the melt viscosity of the adhesive may be 10,000 Pa-sec or more and 100,000 Pa-sec or less at 150°C.

[0017] According to the printed wiring board of (6) above, the first wiring can be easily embedded in the adhesive layer, and distortion of the second base film can be suppressed.

[0018] [Details of the embodiment of the present disclosure] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The printed wiring board according to the embodiment is referred to as a printed wiring board 100.

[0019] (Configuration of Printed Wiring Board 100) The configuration of the printed wiring board 100 will be described below.

[0020] FIG. 1 is a first plan view of printed wiring board 100. FIG. 2 is a second plan view of printed wiring board 100. FIG. 2 shows a plan view of printed wiring board 100 seen from the opposite side to that of FIG. 1. FIG. 3A is a plan view of printed wiring board 100 omitting adhesive layer 30, base film 40, and wiring 60. FIG. 3B is a plan view of printed wiring board 100 omitting adhesive layer 31, base film 50, and wiring 61. FIG. 3B shows a plan view of printed wiring board 100 seen from the opposite side to that of FIG. 3A. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. As shown in FIGS. 1 to 4, printed wiring board 100 has base film 10, wiring 20 and wiring 21, adhesive layer 30 and adhesive layer 31, base film 40, base film 50, wiring 60, and wiring 61.

[0021] The base film 10 has a main surface 10a and a main surface 10b. The main surfaces 10a and 10b are end surfaces in the thickness direction of the base film 10. The main surface 10b is the surface opposite to the main surface 10a. The material of the base film 10 is a flexible, electrically insulating material, such as polyimide.

[0022] The wiring 20 is disposed on the main surface 10a. In plan view, the wiring 20 is wound in a spiral shape to form a coil portion 20a. The wiring 21 is disposed on the main surface 10b. In plan view, the wiring 21 is wound in a spiral shape to form a coil portion 21a.

[0023] The first end of the wiring 20 is located at the outermost periphery of the coil portion 20a. The second end of the wiring 20 is located at the innermost periphery of the coil portion 20a. The first end of the wiring 21 is located at the outermost periphery of the coil portion 21a. The second end of the wiring 21 is located at the innermost periphery of the coil portion 21a.

[0024] Each of the wirings 20, 21 has an underlayer 22, a conductive layer 23, and an electroplated layer 24. The underlayer 22 has a seed layer 22a and a copper layer 22b. The seed layer 22a is disposed on the main surfaces (main surfaces 10a, 10b) of the base film 10. The seed layer 22a is made of, for example, a nickel-chromium alloy. The copper layer 22b is made of, for example, copper.

[0025] The conductive layer 23 is disposed on the copper layer 22b. A first through hole (not shown) is formed through the base film 10, the underlayer 22 at the second end of the wiring 20, and the underlayer 22 at the second end of the wiring 21. The conductive layer 23 is also formed on the inner wall surface of the first through hole.

[0026] The material of conductive layer 23 is, for example, copper. Electroplated layer 24 is disposed on conductive layer 23. The material of electroplated layer 24 is, for example, copper. The second end of wiring 20 and the second end of wiring 21 are electrically connected to each other by conductive layer 23 disposed on the inner wall surface of the first through hole and electroplated layer 24 disposed on conductive layer 23.

[0027] The adhesive layer 30 is disposed on the main surface 10a so as to cover the wiring 20. The adhesive layer 31 is disposed on the main surface 10b so as to cover the wiring 21. The material of the adhesive layer 30 and the adhesive layer 31 is, for example, an epoxy adhesive.

[0028] The base film 40 has a main surface 40a and a main surface 40b. The main surfaces 40a and 40b are end surfaces of the base film 40 in the thickness direction. The main surface 40a faces the adhesive layer 30. The main surface 40b is the surface opposite to the main surface 40a. The base film 40 is disposed on the adhesive layer 30. The material of the base film 40 is a flexible, electrically insulating material, such as polyimide.

[0029] The base film 50 has a main surface 50a and a main surface 50b. The main surfaces 50a and 50b are end surfaces of the base film 50 in the thickness direction. The main surface 50a faces the adhesive layer 31. The main surface 50b is the surface opposite to the main surface 50a. The base film 50 is disposed on the adhesive layer 31. The material of the base film 50 is a flexible, electrically insulating material, such as polyimide.

[0030] The wiring 60 is disposed on the main surface 40b. In a plan view, the wiring 60 is wound in a spiral shape to form a coil portion 60a. The wiring 61 is disposed on the main surface 50b. In a plan view, the wiring 61 is wound in a spiral shape to form a coil portion 61a.

[0031] The first end of the wiring 60 is located at the outermost periphery of the coil portion 60a. The second end of the wiring 60 is located at the innermost periphery of the coil portion 60a. The first end of the wiring 61 is located at the outermost periphery of the coil portion 61a. The second end of the wiring 61 is located at the innermost periphery of the coil portion 61a.

[0032] Each of the wiring 60 and the wiring 61 has an underlayer 62, a conductive layer 63, and an electrolytic plating layer 64. The underlayer 62 has a seed layer 62a and a copper layer 62b. The seed layer 62a is disposed on the main surfaces (main surfaces 10a and 10b) of the base film 10. The seed layer 62a is made of, for example, a nickel-chromium alloy. The copper layer 62b is made of, for example, copper.

[0033] The conductive layer 63 is disposed on the copper layer 62b. The second through hole 40c is formed by penetrating the adhesive layer 30, the base film 40, and the underlayer 62 at the first end of the wiring 60. The first end of the wiring 20 is exposed from the second through hole 40c. The third through hole (not shown) is formed by penetrating the adhesive layer 31, the base film 50, and the underlayer 62 at the first end of the wiring 61. The conductive layer 63 is also formed on the inner wall surface of the second through hole 40c and the inner wall surface of the third through hole.

[0034] The conductive layer 63 is made of, for example, copper. The electrolytic plating layer 64 is disposed on the conductive layer 63. The electrolytic plating layer 64 is made of, for example, copper. The first end of the wiring 60 and the first end of the wiring 20 are electrically connected to each other by the conductive layer 63 disposed on the inner wall surface of the second through hole 40c and the electrolytic plating layer 64 disposed on the conductive layer 63. The first end of the wiring 61 and the first end of the wiring 21 are electrically connected to each other by the conductive layer 63 disposed on the inner wall surface of the third through hole and the electrolytic plating layer 64 disposed on the conductive layer 63.

[0035] The wiring 20 has a plurality of linear wiring portions 20b arranged at intervals. The wiring 21 has a plurality of linear wiring portions 21b arranged at intervals. The wiring 60 has a plurality of linear wiring portions 60b arranged at intervals. The wiring 61 has a plurality of linear wiring portions 61b arranged at intervals.

[0036] The pitch of wiring portion 20b is defined as pitch P1, and the pitch of wiring portion 21b is defined as pitch P2. The pitch of wiring portion 60b is defined as pitch P3, and the pitch of wiring portion 61b is defined as pitch P4. The pitch of wiring portions is the distance from the midpoint of the width of a wiring portion to the midpoint of the width of the adjacent wiring portion. Each of pitch P1, pitch P2, pitch P3, and pitch P4 may be 20 μm or more and 60 μm or less.

[0037] The height of the wiring 20 is defined as height H1, and the height of the wiring 21 is defined as height H2. The height of the wiring 60 is defined as height H3, and the height of the wiring 61 is defined as height H4. The height of the wiring is the sum of the thickness of the base layer, the thickness of the conductive layer, and the thickness of the electrolytic plating layer. For example, each of heights H1, H2, H3, and H4 may be 20 μm or more and 100 μm or less.

[0038] The thickness of the copper layer 22b is defined as thickness T1, and the thickness of the copper layer 62b is defined as thickness T2. Thickness T2 is greater than thickness T1. Thickness T1 may be 0.5 μm or less. Thickness T2 may be 0.5 μm or more and 3.0 μm or less.

[0039] The melt viscosity of the material of the adhesive layers 30, 31 may be 10,000 or more and 100,000 or less at 150° C. The melt viscosity is measured by dynamic viscoelasticity measurement.

[0040] The width of wiring 20 is width W1, and the width of wiring 21 is width W2. The width of wiring 60 is width W3, and the width of wiring 61 is width W4. The aspect ratio of wiring 60 is the value obtained by dividing height H3 by width W3. The aspect ratio of wiring 61 is the value obtained by dividing height H4 by width W4. The aspect ratios of wiring 60 and wiring 61 may be 2.17 or less. The distance between adjacent wiring portions 20b is distance DIS1 (see FIG. 3A), and the distance between adjacent wiring portions 61b is distance DIS2 (see FIG. 1).

[0041] (Method of Manufacturing Printed Wiring Board 100) A method of manufacturing the printed wiring board 100 will be described below.

[0042] 5 is a manufacturing process diagram of printed wiring board 100. As shown in Fig. 5, the manufacturing method of printed wiring board 100 includes a preparation step S1, a conductive layer forming step S2, a resist pattern forming step S3, an electrolytic plating step S4, a resist pattern removing step S5, an etching step S6, a substrate attaching step S7, a through-hole forming step S8, a conductive layer forming step S9, a resist pattern forming step S10, an electrolytic plating step S11, a resist pattern removing step S12, and an etching step S13.

[0043] In the preparation step S1, a base film 10 is prepared. An underlayer 22 is disposed on each of the main surface 10a and the main surface 10b of the prepared base film 10. Before the conductive layer formation step S2 is performed, first through holes are formed in the base film 10, the underlayer 22 disposed on the main surface 10a, and the underlayer 22 on the main surface 10b.

[0044] 6 is a cross-sectional view illustrating the conductive layer forming step S2. As shown in FIG. 6, in the conductive layer forming step S2, a conductive layer 23 is formed on the base layer 22. The conductive layer 23 is formed by, for example, electroless plating or sputtering. Although not shown, the conductive layer 23 is also formed on the inner wall surface of the first through hole.

[0045] 7 is a cross-sectional view illustrating the resist pattern forming step S3. As shown in FIG. 7, in the resist pattern forming step S3, a resist pattern 25 is formed on the conductive layer 23. The resist pattern 25 has openings 25a. The conductive layer 23 is exposed through the openings 25a. The resist pattern 25 is formed, for example, by applying a dry film resist to the conductive layer 23 and then exposing and developing the applied dry film resist.

[0046] Fig. 8 is a cross-sectional view illustrating the electrolytic plating step S4. As shown in Fig. 8, in the electrolytic plating step S4, an electrolytic plating layer 24 is formed on the conductive layer 23 exposed from the opening 25a by electrolytic plating. Fig. 9 is a cross-sectional view illustrating the resist pattern removal step S5. As shown in Fig. 9, in the resist pattern removal step S5, the resist pattern 25 is removed from the conductive layer 23.

[0047] 10 is a cross-sectional view illustrating the etching step S6. As shown in FIG. 10, in the etching step S6, the conductive layer 23 and the base layer 22 that were located under the resist pattern 25 are removed by etching.

[0048] 11 is a cross-sectional view illustrating the substrate attaching step S7. As shown in FIG. 11 , in the substrate attaching step S7, the substrate 70 is attached to the base film 10 by the adhesive layer 30, and the substrate 71 is attached to the base film 10 by the adhesive layer 31. In the substrate attaching step S7, first, the substrates 70 and 71 are prepared. The substrate 70 has a base film 40 and an underlayer 62 disposed on the main surface 40b. The substrate 71 has a base film 50 and an underlayer 62 disposed on the main surface 50b.

[0049] Secondly, in the substrate attachment step S7, with the uncured adhesive layer 30 interposed between the substrate 70 and the base film 10 and the uncured adhesive layer 31 interposed between the substrate 71 and the base film 10, the substrates 70 and 71 are pressed and heated toward the base film 10. This hardens the adhesive layers 30 and 31, and the substrate 70 is attached to the main surface 10a of the base film 10, and the substrate 71 is attached to the main surface 10b of the base film 10.

[0050] 12 is a cross-sectional view illustrating the through hole forming step S8. As shown in FIG. 12, in the through hole forming step S8, a second through hole 40c is formed so as to penetrate the adhesive layer 30, the base film 40, and the underlayer 62 on the main surface 40b and expose the wiring 20. The second through hole 40c is formed by irradiating with laser light. Although not shown, in the through hole forming step S8, a third through hole is similarly formed so as to penetrate the adhesive layer 31, the base film 50, and the underlayer 62 on the main surface 50b and expose the wiring 21.

[0051] 13 is a cross-sectional view illustrating the conductive layer forming step S9. As shown in FIG. 13, in the conductive layer forming step S9, a conductive layer 63 is formed on the base layer 62. The conductive layer 63 is formed by, for example, electroless plating or sputtering. The conductive layer 63 is also formed on the inner wall surfaces of the second through holes 40c, the inner wall surfaces of the third through holes, a portion of the wiring 20 exposed from the second through holes 40c, and a portion of the wiring 21 exposed from the third through holes.

[0052] 14 is a cross-sectional view illustrating the resist pattern forming step S10. As shown in FIG. 14, in the resist pattern forming step S10, a resist pattern 65 is formed on a conductive layer 63. The resist pattern 65 has openings 65a. The conductive layer 63 is exposed through the openings 65a. The resist pattern 65 is formed, for example, by applying a dry film resist to the conductive layer 63 and then exposing and developing the applied dry film resist.

[0053] 15 is a cross-sectional view illustrating the electrolytic plating step S11. As shown in FIG. 15, in the electrolytic plating step S11, an electrolytic plating layer 64 is formed on the conductive layer 63 exposed from the opening 65 a by electrolytic plating.

[0054] 16 is a cross-sectional view illustrating the resist pattern removal step S12. As shown in FIG. 16, in the resist pattern removal step S12, the resist pattern 65 is removed from the conductive layer 63. In the etching step S13, the conductive layer 63 and the base layer 62 that were located under the resist pattern 65 are removed by etching. As a result, the printed wiring board 100 having the structure shown in FIGS. 1 to 4 is formed.

[0055] In the above example, the base materials 70 and 71 each have a copper layer 62b with a desired thickness T2. The thickness T2 of the copper layer 62b on the base materials 70 and 71 may be adjusted by etching the copper layer 62b before the base material attaching step S7 is performed or by etching the copper layer 62b after the base material attaching step S7 is performed.

[0056] <Second Modification> Fig. 17 is a cross-sectional view of printed wiring board 100 according to a second modification. As shown in Fig. 17, each of wirings 20, 21 may further include electrolytic plating layer 26. Each of wirings 60, 61 may further include electrolytic plating layer 66. Electrolytic plating layer 26 covers the side surfaces of base layer 22, conductive layer 23, and electrolytic plating layer 24, as well as the upper surface of electrolytic plating layer 24. Electrolytic plating layer 66 covers the side surfaces of base layer 62, conductive layer 63, and electrolytic plating layer 64, as well as the upper surface of electrolytic plating layer 64. The material of electrolytic plating layers 26, 66 is, for example, copper.

[0057] 18 is a manufacturing process diagram of a printed wiring board 100 according to a second modified example. As shown in FIG. 18, an electrolytic plating step S14 is performed after the etching step S6 and before the base material attaching step S7. An electrolytic plating step S15 is performed after the etching step S13.

[0058] In the electrolytic plating step S14, electrolytic plating layer 26 is formed by passing a current through base layer 22, conductive layer 23, and electrolytic plating layer 24 to perform electrolytic plating. In the electrolytic plating step S15, electrolytic plating layer 66 is formed by passing a current through base layer 62, conductive layer 63, and electrolytic plating layer 64 to perform electrolytic plating.

[0059] 19 is a cross-sectional view of printed wiring board 100 according to a third modification. As shown in FIG. 19, printed wiring board 100 may further include adhesive layers 80 and 81, base films 82 and 83, and wirings 84 and 85.

[0060] The adhesive layer 80 is disposed on the main surface 40b of the base film 40 so as to cover the wiring 60. The adhesive layer 81 is disposed on the main surface 50b of the base film 50 so as to cover the wiring 61. The base film 82 is disposed on the adhesive layer 80 so that its main surface 82a faces the adhesive layer 80. The base film 83 is disposed on the adhesive layer 81 so that its main surface 83a faces the adhesive layer 81. The wiring 84 is disposed on the main surface 82b opposite the main surface 82a. The wiring 85 is disposed on the main surface 83b opposite the main surface 83a.

[0061] The wirings 84 and 85 have the same structure as the wirings 60 and 61. That is, the wirings 84 and 85 may have a seed layer, a copper layer disposed on the seed layer, a conductive layer disposed on the copper layer, and an electrolytically plated layer disposed on the conductive layer. The wirings 84 and 85 may have a seed layer, a copper layer, a conductive layer, a first electrolytically plated layer disposed on the conductive layer, and a second electrolytically plated layer covering the first electrolytically plated layer. The thickness of the copper layer of the wirings 84 and 85 is greater than the thickness T1 of the copper layer 22b of the wirings 20 and 21. The thickness of the copper layer of the wirings 84 and 85 may be 0.5 μm or more and 3.0 μm or less. Thus, the number of wiring layers in the printed wiring board 100 is not limited to four, and the number of wiring layers may be six. Although not shown, the number of wiring layers in the printed wiring board 100 may be eight or more.

[0062] <Fourth Modification> Fig. 20 is a cross-sectional view of a printed wiring board 100 according to a fourth modification. As shown in Fig. 20, the printed wiring board 100 does not necessarily have the wiring 21, the adhesive layer 31, the base film 50, and the wiring 61. For example, the printed wiring board 100 is formed by attaching a substrate to one surface of a substrate. Although not shown, in this case, the number of wiring layers in the printed wiring board 100 is not limited to two and may be three or more.

[0063] (Effects of the Printed Wiring Board 100) The effects of the printed wiring board 100 will be described below.

[0064] When the substrate attaching step S7 is performed, the base films 40 and 50 may become distorted. If distortion occurs in the base films 40 and 50, poor conductivity or a short circuit may occur in the wiring 60 and the wiring 61.

[0065] In the printed wiring board 100 of the present disclosure, the thickness T2 of the copper layer 62b of the wiring 60, 61 is greater than the thickness T1 of the copper layer 22b of the wiring 20, 21. Therefore, when the substrate attachment step S7 is performed, the base films 40, 50 are supported by the copper layer 62b, and therefore distortion is less likely to occur in the base films 40, 50. As a result, the printed wiring board 100 can prevent poor conductivity and short circuits from occurring in the wiring 60, 61.

[0066] As the thickness T2 of the copper layer 62b increases, the time required for the etching step S13 increases. If the thickness T2 of the copper layer 62b is too large, the cross-sectional area of ​​the wiring 60, 61 decreases, resulting in an increase in the electrical resistance of the wiring 60, 61. If the electrolytic plating layer 64 is thickened to increase the cross-sectional area of ​​the wiring 60, 61, the occurrence of short-circuit defects increases. When the thickness T2 of the copper layer 62b is 0.5 μm or more, distortion of the base films 40, 50 during the substrate attachment step S7 can be sufficiently suppressed. Therefore, by setting the thickness T2 of the copper layer 62b to 0.5 μm or more and 3.0 μm or less, distortion of the base films 40, 50 can be suppressed while maintaining the cross-sectional area of ​​the wiring 60, 61.

[0067] When the melt viscosity of the material of adhesive layers 30, 31 is 10,000 Pa-sec or more and 100,000 Pa-sec or less at 150° C., the heating temperature in substrate attachment step S7 is low. Therefore, even if the pitch of wiring portions 20 b, 21 b is small, wiring portion 20 b is easily embedded in adhesive layer 30, and wiring portion 21 b is easily embedded in adhesive layer 31. Therefore, as the heating temperature in substrate attachment step S7 becomes lower, distortion of base films 40, 50 in substrate attachment step S7 is suppressed.

[0068] (Example) For Samples 1 to 5, the influence of the relationship between the thickness T1 of the copper layer 22b and the thickness T2 of the copper layer 62b on the distortion of the base film 40 was evaluated. For each sample, 1,000 coil portions as shown in FIG. 1 were confirmed. For Samples 1 to 5, the thickness T1 was constant at 0.4 μm. For Samples 1 to 5, the thickness T2 of the copper layer 62b was changed.

[0069] The rate at which open defects occurred in the wiring 60 was evaluated for Samples 1 to 5. In Table 1, an open defect rate of 30% or less for the wiring 60 was rated as OK, and an open defect rate of more than 30% was rated as NG. The open defect in the wiring 60 is caused by distortion of the base film 40. When distortion of 10 μm or more occurred in the base film 40, it was deemed that the wiring 60 was difficult to conduct, and an open defect in the wiring 60 had occurred. Therefore, the open defect was confirmed by measuring the electrical resistance value of the wiring 60. The amount of distortion in the base film 40 was measured with a micrometer.

[0070] As shown in Table 1, Sample 1 did not satisfy the condition that the thickness T2 of the copper layer 62b was greater than the thickness T1 of the copper layer 22b. On the other hand, Samples 2 to 5 satisfied the condition that the thickness T2 was greater than the thickness T1. Furthermore, while Sample 1 had a high open defect rate for the wiring 60, Samples 2 to 5 had a lower open defect rate for the wiring 60. This comparison revealed that distortion of the base film 40 was reduced if the condition that the thickness T2 was greater than the thickness T1 was satisfied.

[0071]

[0072] The relationship between the thickness T1 of the copper layer 22b and the thickness T2 of the copper layer 62b was evaluated in more detail for Samples 6 to 10. For each sample, 1,000 coil portions, such as those shown in FIG. 1, were confirmed. As shown in Table 2, the thickness T1, pitch P1, and pitch P3 were constant for Samples 6 to 10. The width W1 and distance DIS1 were constant for Samples 6 to 10 after the electroplating step S4, the etching step S6, and the electroplating step S14. The width W3 and distance DIS2 were constant for Samples 6 to 10 after the etching step S13 and the electroplating step S15. The etching amount in the etching step S6, the plating amount in the electroplating step S14, and the plating amount in the electroplating step S15 were constant for Samples 6 to 10.

[0073] On the other hand, thickness T2 was changed in Samples 6 to 10. In Samples 6 to 10, the etching amount in the etching step S13 was changed in accordance with the change in thickness T2. Although the etching amount in the etching step S13 differs in Samples 6 to 10 as described above, width W3 and distance DIS2 after the electroplating step S11 were changed so that width W3 and distance DIS2 after the etching step S13 were constant.

[0074]

[0075] The percentage of short-circuit defects in the wiring 60 and the percentage of open-circuit defects in the wiring 60 were evaluated for Samples 6 to 10. In Table 2, a total of the open-circuit defect rate and short-circuit defect rate for the wiring 60 of 30% or less was rated as OK, and a total of more than 30% was rated as NG. The short-circuit defects in the wiring 60 were caused by an excessive or insufficient amount of etching in the etching step S13, a reduction in the cross-sectional area of ​​the wiring 60, and collapse of the resist used in the electroplating step S11. The short-circuit defects were confirmed by microscopic observation. Note that if the amount of distortion of the base film 40 was 10 μm or more, open-circuit defects in the wiring 60 occurred.

[0076] As the thickness T2 of the copper layer 62b decreases, the base film 40 becomes more likely to distort, and therefore open defects in the wiring 60 become more likely. On the other hand, as the thickness T2 of the copper layer 62b increases, the etching amount in the etching step S13 increases. Therefore, in order to maintain the cross-sectional area of ​​the electrolytic plating layer 64, it is necessary to form a thin resist pattern used in the electrolytic plating step S11. As a result, short defects in the wiring 60 are more likely to occur due to the collapse of the resist pattern or the penetration of the plating solution under the resist pattern.

[0077] Samples 7 to 9 satisfied the conditions that thickness T2 > thickness T1 and 0.5 μm≦thickness T2≦3 μm. Samples 6 and 10 did not satisfy these conditions. In Samples 7 to 9, both the short circuit defect rate and the open circuit defect rate of the wiring 60 were 30 percent or less. In Samples 6 and 10, either the short circuit defect rate or the open circuit defect rate exceeded 30 percent. From this comparison, it was found that by further satisfying the condition that 0.5 μm≦thickness T2≦3 μm, not only open circuit defects but also short circuit defects of the wiring 60 were suppressed.

[0078] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0079] REFERENCE SIGNS 10 Base film (first base film) 10a Main surface (first main surface) 10b Main surface (second main surface) 20, 21 Wiring (first wiring) 20a, 21a Coil portion 20b, 21b Wiring portion 22 Underlayer 22a Seed layer (first seed layer) 22b Copper layer (first copper layer) 23 Conductive layer 24 Electrolytic plating layer 25 Resist pattern 25a Opening 26 Electrolytic plating layer 30, 31 Adhesion layer 40 Base film (second base film) 40a Main surface (third main surface) 40b Main surface (fourth main surface) 40c Second through hole 50 Base film 50a, 50b Main surface 60, 61 Wiring (second wiring) 60a, 61a Coil portion 60b, 61b Wiring portion 62 Underlayer 62a Seed layer (second seed layer) 62b Copper layer (second copper layer) 63 Conductive layer 64 Electrolytic plating layer 65 Resist pattern 65a Opening 66 Electrolytic plating layer 70, 71 Base material 80, 81 Adhesion layer 82 Base film 82a, 82b Main surface 83 Base film 83a, 83b Main surface 84, 85 Wiring 100 Printed wiring board DIS1, DIS2 Distance H1, H2, H3, H4 Height P1, P2, P3, P4 Pitch S1 Preparation step S2 Conductive layer forming step S3 Resist pattern forming step S4 Electrolytic plating step S5 Resist pattern removing step S6 Etching step S7 Base material attaching step S8 Through hole forming step S9 Conductive layer forming step S10 Resist pattern forming step S11 Electrolytic plating process S12 Resist pattern removal process S13 Etching process T1, T2 Thickness W1, W2, W3, W4 Width

Claims

1. A printed wiring board comprising: a first base film having a first main surface and a second main surface; a first wiring arranged on the first main surface; an adhesive layer arranged on the first main surface so as to cover the first wiring; a second base film having a third main surface and a fourth main surface and arranged on the adhesive layer so that the third main surface faces the adhesive layer; and a second wiring arranged on the fourth main surface, wherein the first wiring has a first seed layer arranged on the first main surface and a first copper layer arranged on the first seed layer, and the second wiring has a second seed layer arranged on the fourth main surface and a second copper layer arranged on the second seed layer, and the thickness of the second copper layer is greater than the thickness of the first copper layer.

2. The printed wiring board according to claim 1, wherein the thickness of said first copper layer is 0.5 μm or less.

3. The printed wiring board according to claim 1 or 2, wherein the thickness of the second copper layer is not less than 0.5 μm and not more than 3.0 μm.

4. A printed wiring board as described in any one of claims 1 to 3, wherein the second wiring has a plurality of linear wiring portions arranged at intervals, and the pitch of the plurality of wiring portions is 20 μm or more and 60 μm or less.

5. A printed wiring board according to any one of claims 1 to 4, wherein the height of the second wiring is not less than 20 μm and not more than 100 μm.

6. The printed wiring board according to any one of claims 1 to 5, wherein the adhesive layer is composed of an adhesive, and the melt viscosity of the adhesive is 10,000 Pa sec or more and 100,000 Pa sec or less at 150°C.

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