Method for manufacturing through-electrode substrate and through-electrode substrate

Abstract

This method for manufacturing a through-electrode substrate comprises: a step for preparing a substrate electrode structure part provided with a core substrate including a first substrate surface, a second substrate surface positioned on a side opposite to the first substrate surface, and a through-hole penetrating from the first substrate surface to the second substrate surface, and with a through-electrode positioned in the through hole; a step for transferring and forming, on the first substrate surface, a first wiring structure part to be electrically connected to the through-electrode; and a step for transferring and forming, on the second substrate surface, a second wiring structure part to be electrically connected to the through-electrode.

Description

Manufacturing method of through electrode substrate and through electrode substrate

[0001] FIELD Embodiments of the present disclosure relate to a method for manufacturing a through hole electrode substrate and a through hole electrode substrate.

[0002] Through-hole electrode substrates are used in a variety of applications. A through-hole electrode substrate includes a core substrate having a first substrate surface, a second substrate surface, and through holes, and through electrodes located in the through holes. Through-hole electrode substrates are used, for example, as interposers. An interposer is a member interposed between two electrical components. Through-hole electrode substrates are interposed, for example, between a semiconductor element and a support substrate, or between a semiconductor element and a mounting substrate.

[0003] The through electrode substrate also includes a wiring structure portion. The wiring structure portion is electrically connected to the through electrode. The wiring structure portion includes a wiring layer. The wiring layer performs the function of, for example, relocating pads or terminals of a semiconductor element to another location. Such a wiring layer is also called a rewiring layer. The wiring structure portions are respectively arranged on the first substrate surface and the second substrate surface of the core substrate.

[0004] When manufacturing such a through electrode substrate, first, a substrate electrode structure including a core substrate and through electrodes is prepared. Next, a wiring structure is formed by laminating on the core substrate of the substrate electrode structure. More specifically, an insulating layer and a conductive layer are laminated on a first substrate surface of the core substrate to form a first wiring structure, and an insulating layer and a conductive layer are laminated on a second substrate surface of the core substrate to form a second wiring structure.

[0005] Japanese Patent Application Laid-Open No. 2023-75206

[0006] As described above, when the wiring structure is formed on the core substrate, the warping and distortion of the through hole electrode substrate may become large, particularly in a large through hole electrode substrate, which may result in a decrease in the manufacturing yield of the through hole electrode substrate.

[0007] An object of the embodiments of the present disclosure is to provide a method for manufacturing a through hole electrode substrate and a through hole electrode substrate that can effectively solve such problems.

[0008] Embodiments of the present disclosure relate to the following [1] to

[12] : [1] A method for manufacturing a through electrode substrate, comprising: a step of preparing a substrate electrode structure including a core substrate including a first substrate surface, a second substrate surface opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface, and a through electrode located in the through hole, a step of transferring and forming a first wiring structure on the first substrate surface, the first wiring structure being electrically connected to the through electrode, and a step of transferring and forming a second wiring structure on the second substrate surface.

[0009] [2] The method for manufacturing a through-hole electrode substrate according to [1], wherein a first adhesive layer is interposed between the first substrate surface and the first wiring structure portion, and a second adhesive layer is interposed between the second substrate surface and the second wiring structure portion.

[0010] [3] The method for manufacturing a through-hole electrode substrate according to [1] or [2], wherein the first wiring structure includes a first conductive layer including a first seed layer and a first plating layer located on the first seed layer, the second wiring structure includes a second conductive layer including a second seed layer and a second plating layer located on the second seed layer, the first seed layer is located farther from the first substrate surface than the first plating layer, and the second seed layer is located farther from the second substrate surface than the second plating layer.

[0011] [4] The method for manufacturing a through hole electrode substrate according to any one of [1] to [3], wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located on the opposite side to the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located on the opposite side to the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less.

[0012] [5] The method for manufacturing a through-hole electrode substrate according to any one of [1] to [4], wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located on the opposite side to the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located on the opposite side to the second inner surface, the maximum height roughness Rz of the first outer surface as defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface as defined in JIS B 0601-2001 is 1.5 μm or less.

[0013] [6] The planar area of ​​the through electrode substrate is 25 cm ２ The method for manufacturing a through hole electrode substrate according to any one of [1] to [5] above.

[0014] [7] A through electrode substrate comprising: a core substrate including a first substrate surface, a second substrate surface located opposite the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein a first adhesive layer is interposed between the first substrate surface and the first wiring structure, and a second adhesive layer is interposed between the second substrate surface and the second wiring structure.

[0015] [8] The through-hole electrode substrate according to [7], wherein the first wiring structure includes a first conductive layer including a first seed layer and a first plating layer located on the first seed layer, the second wiring structure includes a second conductive layer including a second seed layer and a second plating layer located on the second seed layer, the first seed layer is located farther from the first substrate surface than the first plating layer, and the second seed layer is located farther from the second substrate surface than the second plating layer.

[0016] [9] The through electrode substrate according to [7] or [8], wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located on the opposite side to the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located on the opposite side to the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less.

[0017]

[10] The through hole electrode substrate according to any one of [7] to [9], wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located on the opposite side to the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located on the opposite side to the second inner surface, the maximum roughness in height Rz of the first outer surface as defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum roughness in height Rz of the second outer surface as defined in JIS B 0601-2001 is 1.5 μm or less.

[0018]

[11] A through electrode substrate comprising: a core substrate including a first substrate surface, a second substrate surface located opposite the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein the first wiring structure includes a first conductive layer including a first seed layer and a first plating layer located on the first seed layer, the second wiring structure includes a second conductive layer including a second seed layer and a second plating layer located on the second seed layer, the first seed layer is located farther from the first substrate surface than the first plating layer, and the second seed layer is located farther from the second substrate surface than the second plating layer.

[0019]

[12] The through hole electrode substrate according to

[11] , wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located on the opposite side to the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located on the opposite side to the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less.

[0020]

[13] The through electrode substrate according to

[11] or

[12] , wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located on the opposite side to the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located on the opposite side to the second inner surface, the first outer surface has a maximum height roughness Rz defined in JIS B 0601-2001 of 1.5 μm or less, and the second outer surface has a maximum height roughness Rz defined in JIS B 0601-2001 of 1.5 μm or less.

[0021]

[14] A through electrode substrate, comprising: a core substrate including a first substrate surface, a second substrate surface located opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite to the first inner surface, and the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite to the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B The through electrode substrate has an arithmetic mean roughness Ra defined by JIS No. 0601-2001 of 1 μm or less.

[0022]

[15] A through electrode substrate, comprising: a core substrate including a first substrate surface, a second substrate surface located opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite to the first inner surface, and the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite to the second inner surface, the maximum height roughness Rz of the first outer surface defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface defined in JIS B A through-hole electrode substrate, wherein the maximum roughness in height Rz as defined in JIS K 0601-2001 is 1.5 μm or less.

[0023]

[16] The planar area of ​​the through electrode substrate is 25 cm ２ The through-hole electrode substrate according to any one of [7] to

[15] above.

[0024] According to the embodiments of the present disclosure, warping and distortion of the through hole electrode substrate can be suppressed.

[0025] 1 is a cross-sectional view showing a through electrode substrate according to an embodiment; FIG. 2 is a partially enlarged cross-sectional view of a first wiring structure included in the through electrode substrate of FIG. 1; FIG. 3 is a partially enlarged cross-sectional view of a second wiring structure included in the through electrode substrate of FIG. 1; FIG. 4 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 5 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 6 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 7 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 8 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 9 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 10 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 11 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; FIG. 12 is a cross-sectional view for explaining a method of manufacturing a through electrode substrate according to an embodiment; 1A and 1B are cross-sectional views for explaining a method for manufacturing a through hole electrode substrate according to a modified example, a partially enlarged cross-sectional view of a first wiring structure portion included in a through hole electrode substrate according to a modified example, and a diagram showing an example of a product on which a through hole electrode substrate is mounted.

[0026] The following describes a through-hole electrode substrate and a method for manufacturing the through-hole electrode substrate with reference to the drawings. The embodiments described below are examples of embodiments of the present disclosure, and the present disclosure is not limited to these embodiments. In this specification, terms such as "substrate," "base material," "sheet," and "film" are not distinguished from one another solely based on differences in name. For example, the concept of "substrate" includes members that may be called sheets or films. "Surface" refers to a surface that coincides with the planar direction of the target plate-like member when viewed holistically and comprehensively. The normal direction used with respect to a plate-like member refers to the normal direction to the surface of the member. As used in this specification, terms such as "parallel" and "orthogonal," as well as length and angle values, that specify shape, geometric conditions, and their degrees, are interpreted without being bound by strict meanings but include a range within which similar functions can be expected.

[0027] In this specification, when multiple upper limit candidates and multiple lower limit candidates are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit candidate with any one lower limit candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or greater, or may be A2 or greater, or A3 or greater. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or greater and A4 or less, or A1 or greater and A5 or less, or A1 or greater and A6 or less. Furthermore, the numerical range of parameter B may be A2 or greater and A4 or less, or A2 or greater and A5 or less, or A2 or greater and A6 or less. Furthermore, the numerical range of parameter B may be A3 or greater and A4 or less, or A3 or greater and A5 or less, or A3 or greater and A6 or less.

[0028] In the drawings referred to in this embodiment, the same parts or parts having similar functions are denoted by the same or similar reference numerals, and repeated explanations thereof may be omitted. Furthermore, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings.

[0029] (Through electrode substrate) Fig. 1 is a cross-sectional view showing a through electrode substrate 10 according to one embodiment. The through electrode substrate 10 is interposed between a semiconductor element (not shown) and a support substrate (not shown), or between the semiconductor element and a mounting substrate (not shown). That is, semiconductor elements such as a CPU, GPU, FPGA, memory, etc. are mounted on the through electrode substrate 10. The through electrode substrate 10 on which the semiconductor element is mounted is supported on a support substrate such as a BGA substrate, or is mounted on a mounting substrate such as a motherboard.

[0030] As shown in FIG. 1 , the through hole electrode substrate 10 includes a substrate electrode structure portion 11 , a first wiring structure portion 30 , and a second wiring structure portion 40 .

[0031] (Substrate Electrode Structure) As shown in FIG. 1 , the substrate electrode structure 11 includes a core substrate 12 and a through electrode 20 .

[0032] The core substrate 12 includes a first substrate surface 13, a second substrate surface 14, and through holes 15. The first substrate surface 13 faces a first wiring structure 30, which will be described later. The second substrate surface 14 is located on the opposite side of the first substrate surface 13. The second substrate surface 14 faces a second wiring structure 40, which will be described later. The first substrate surface 13 and the second substrate surface 14 may each be formed flat. The first substrate surface 13 and the second substrate surface 14 may also be parallel to each other.

[0033] The through hole 15 penetrates from the first substrate surface 13 to the second substrate surface 14. The through hole 15 may extend straight from the first substrate surface 13 to the second substrate surface 14. The through hole 15 may extend along the thickness direction of the core substrate 12. In this specification, the "thickness direction" refers to a direction perpendicular to the first substrate surface 13 or the second substrate surface 14 of the core substrate 12 (normal direction). The through hole 15 may be formed in a cylindrical shape. In this case, the through hole 15 has a circular outline in a plan view. In this specification, the "plan view" refers to observing an object along a direction perpendicular to the first substrate surface 13 or the second substrate surface 14 of the core substrate 12 (normal direction).

[0034] The core substrate 12 may include a plurality of through holes 15. The plurality of through holes 15 may have the same shape and size as one another.

[0035] The diameter of the through hole 15 is, for example, 10 μm or more, or may be 40 μm or more, or 80 μm or more. The diameter of the through hole 15 is, for example, 200 μm or less, or may be 150 μm or less, or may be 100 μm or less. Here, the diameter of the through hole 15 refers to the diameter of the through hole 15 on the first substrate surface 13 or the second substrate surface 14. When the through hole 15 has a circular outline in a plan view, the diameter of the through hole 15 refers to the diameter of the through hole 15 in a plan view. When the through hole 15 has an outline other than a circle in a plan view, the diameter of the through hole 15 is calculated from the diameter of a circle when the through hole 15 in a plan view is converted into a circle having an area equal to the plan view area. In this specification, the term "plan view area" refers to the area within the outline of an object in a plan view.

[0036] The arrangement pitch of the through holes 15 is, for example, 10 μm or more, or may be 40 μm or more, or 80 μm or more. The arrangement pitch of the through holes 15 is, for example, 200 μm or less, or may be 150 μm or less, or may be 100 μm or less. Here, the arrangement pitch of the through holes 15 refers to the distance (arrangement interval) between the through holes 15 on the first substrate surface 13 or the second substrate surface 14.

[0037] The core substrate 12 has insulating properties. The core substrate 12 may be made of a glass material. Examples of glass materials include alkali-free glass. Alkali-free glass is glass that does not contain alkali components such as sodium or potassium. Alkali-free glass contains, for example, boric acid instead of alkali components. Alkali-free glass also contains, for example, alkaline earth metal oxides such as calcium oxide or barium oxide. The core substrate 12 may also be made of a resin material. Examples of resin materials include organic materials such as polyimide, epoxy, acrylic, and polyphenyl ether. The core substrate 12 may also be a glass epoxy resin substrate, which is made by impregnating glass fibers with epoxy resin.

[0038] The thickness of the core substrate 12 is, for example, 100 μm or more, or may be 200 μm or more, or 300 μm or more. The thickness of the core substrate 12 is, for example, 1200 μm or less, or may be 800 μm or less, or may be 500 μm or less.

[0039] The through electrode 20 is located within the through hole 15. The through electrode 20 may be located along the wall surface of the through hole 15. The through electrode 20 may be formed in a cylindrical shape along the wall surface of the through hole 15. A portion of the through electrode 20 may extend from the inside of the through hole 15 onto the first substrate surface 13 of the core substrate 12, and form a portion of the first conductive layer 23 located on the first substrate surface 13. Furthermore, a portion of the through electrode 20 may extend from the inside of the through hole 15 onto the second substrate surface 14 of the core substrate 12, and form a portion of the second conductive layer 25 located on the second substrate surface 14.

[0040] The through electrode 20 is conductive. The through electrode 20 may contain a plating material. Examples of the plating material include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, or alloys using these metals. The majority of the through electrode 20 may be made of the plating material. Although not shown, the through electrode 20 may include a seed layer. Plating may be formed on the seed layer. That is, the seed layer may be located between the wall surface of the through hole 15 and the plating material.

[0041] As shown in FIG. 1, the substrate electrode structure 11 may include a filling member 21, a first insulating layer 22, a first conductive layer 23, a second insulating layer 24, and a second conductive layer 25.

[0042] The filling member 21 is located inside the through electrode 20 within the through hole 15. Here, "inside" refers to the direction from the through electrode 20 toward the center of the through hole 15. The filling member 21 may fill the inside of the through electrode 20. That is, the filling member 21 may fill the inside of the through electrode 20 without leaving any gaps. The filling member 21 has insulating properties. The filling member 21 may be made of a resin material. Examples of resin materials include organic materials such as polyimide, epoxy, acrylic, and polyphenyl ether.

[0043] The first insulating layer 22 is located on the first substrate surface 13 of the core substrate 12. The first insulating layer 22 extends in a plane on the first substrate surface 13. The first insulating layer 22 has insulating properties. The first insulating layer 22 may be made of a resin material. Examples of the resin material include organic materials such as polyimide, epoxy, acrylic, and polyphenyl ether.

[0044] The first conductive layer 23 is located on the first substrate surface 13 of the core substrate 12. The first conductive layer 23 is located within the first insulating layer 22. The first conductive layer 23 contacts one end of the through electrode 20 and is electrically connected to the through electrode 20. The first conductive layer 23 includes wiring and pads. The wiring is a portion that is not exposed from the first insulating layer 22 and extends vertically and horizontally within the first conductive layer 23. The pad is a portion that is exposed from the first insulating layer 22 and is in electrical contact with other members.

[0045] The first conductive layer 23 is conductive. The first conductive layer 23 may contain a plating material. Examples of the plating material include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, or alloys using these metals. A large portion of the first conductive layer 23 may be composed of the plating material. Although not shown, the first conductive layer 23 may include a seed layer. Plating may be formed on the seed layer.

[0046] The second insulating layer 24 is located on the second substrate surface 14 of the core substrate 12. The second insulating layer 24 extends in a plane on the second substrate surface 14. The second insulating layer 24 has insulating properties. The second insulating layer 24 may be made of the same material as the first insulating layer 22.

[0047] The second conductive layer 25 is located on the second substrate surface 14 of the core substrate 12. The second conductive layer 25 is located within the second insulating layer 24. The second conductive layer 25 contacts one end of the through electrode 20 and is electrically connected to the through electrode 20. The second conductive layer 25 includes wiring and pads. The wiring is a portion that is not exposed from the second insulating layer 24 and extends vertically and horizontally within the second insulating layer 24. The pad is a portion that is exposed from the second insulating layer 24 and is in electrical contact with other members.

[0048] The second conductive layer 25 has electrical conductivity. The second conductive layer 25 may be made of the same material as the first conductive layer 23.

[0049] (First wiring structure portion) The first wiring structure portion 30 is located on the first substrate surface 13 of the core substrate 12. More specifically, the first wiring structure portion 30 is located on the first substrate surface 13 via the first insulating layer 22 and the first adhesive layer 50 described below. The first wiring structure portion 30 is electrically connected to the through electrodes 20. The first wiring structure portion 30 electrically connects the through electrodes 20 and the semiconductor element mounted on the through electrode substrate 10 to each other. The first wiring structure portion 30 includes a first wiring layer 31.

[0050] The first wiring layer 31 includes a first insulating layer 32 and a first conductive layer 33. The first insulating layer 32 is located on the first substrate surface 13 of the core substrate 12. More specifically, the first insulating layer 32 is located on the first substrate surface 13 via the first insulating layer 22 and the first adhesive layer 50. The first insulating layer 32 extends in a plane on the first substrate surface 13. The first conductive layer 33 is located within the first insulating layer 32. The first conductive layer 33 is in electrical contact with the first conductive layer 23 and electrically connected to the through electrodes 20. The first conductive layer 33 includes wiring and pads. The wiring is a portion that is not exposed from the first insulating layer 32 and extends vertically and horizontally within the first conductive layer 33. The pad is a portion that is exposed from the first insulating layer 32 and is in electrical contact with other components.

[0051] The first wiring layer 31 may include a plurality of first wiring layers 31A, 31B. The first wiring structure 30 may be configured by stacking a plurality of first wiring layers 31A, 31B. In the example shown, the first wiring layer 31 includes two first wiring layers 31A, 31B stacked on top of each other. The first wiring layer 31 is located closer to the first substrate surface 13 than the first wiring layer 31B. The first wiring layer 31B is located farther from the first substrate surface 13 than the first wiring layer 31A. Although not shown, the first wiring layer 31 may include an additional wiring layer. Each first wiring layer 31 may include a first insulating layer 32 and a first conductive layer 33.

[0052] The first insulating layer 32 has insulating properties and may contain a resin material, such as an organic material such as polyimide, epoxy, acrylic, or polyphenyl ether.

[0053] 2 is a partially enlarged cross-sectional view of the first wiring structure 30. As shown in FIG. 2, the first conductive layer 33 includes a first seed layer 34 and a first plating layer 35. The first seed layer 34 is a layer formed by physical film formation such as sputtering. The first plating layer 35 is a layer formed on the first seed layer 34 by electrolytic plating. The first plating layer 35 is located on the first seed layer 34.

[0054] The first seed layer 34 is located farther from the first substrate surface 13 than the first plating layer 35. The first plating layer 35 is located closer to the first substrate surface 13 than the first seed layer 34. That is, the first seed layer 34 is located outside (above in the figure) the first plating layer 35. The first plating layer 35 is located inside (below in the figure) the first seed layer 34. Here, "outside" refers to a direction away from the core substrate 12. Here, "inside" refers to a direction approaching the core substrate 12.

[0055] The first seed layer 34 is conductive. The first seed layer 34 may contain a metal material. Examples of the metal material include metals such as copper, nickel, titanium, chromium, and zinc, and alloys using these metals. The first plating layer 35 is conductive. The first plating layer 35 contains a plating material. Examples of the plating material include metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, and alloys using these metals.

[0056] The first wiring structure 30 also includes a first inner surface 36 and a first outer surface 37. The first inner surface 36 faces the first substrate surface 13. The first outer surface 37 is located on the opposite side to the first inner surface 36. The first inner surface 36 is located closer to the first substrate surface 13 than the first outer surface 37. The first outer surface 37 is located farther from the first substrate surface 13 than the first inner surface 36. That is, the first inner surface 36 is located more inward (lower in the figure) than the first outer surface 37. The first outer surface 37 is located more outward (upper in the figure) than the first inner surface 36. Here, "outward" refers to a direction away from the core substrate 12. Here, "inward" refers to a direction approaching the core substrate 12. The first outer surface 37 constitutes the outer surface of the through electrode substrate 10.

[0057] The surface roughness of the first outer surface 37 is smaller than the surface roughness of the first inner surface 36. That is, the arithmetic mean roughness Ra of the first outer surface 37 is smaller than the arithmetic mean roughness Ra of the first inner surface 36. The arithmetic mean roughness Ra of the first outer surface 37 is, for example, 0.01 μm or more, or may be 0.05 μm or more, or may be 0.1 μm or more. The arithmetic mean roughness Ra of the first outer surface 37 is, for example, 1 μm or less, or may be 0.5 μm or less, or may be 0.2 μm or less.

[0058] The maximum height roughness Rz of the first outer surface 37 is, for example, 0.05 μm or more, or may be 0.1 μm or more, or 0.2 μm or more. The maximum height roughness Rz of the first outer surface 37 is, for example, 1.5 μm or less, or may be 1.0 μm or less, or may be 0.5 μm or less.

[0059] The arithmetic mean roughness Ra and maximum height roughness Rz are specified in JIS B 0601-2001. A DektakXT-S manufactured by Bruker was used to measure the arithmetic mean roughness Ra and maximum height roughness Rz. In this measurement, the stylus tip curvature was 50 nm, the contact pressure was 1 mg, the scanning speed was 10 μm / s, and the scanning distance was 200 μm.

[0060] The thickness of the first wiring structure 30 is, for example, 20 μm or more, or may be 30 μm or more, or 40 μm or more. The thickness of the first wiring structure 30 is, for example, 100 μm or less, or may be 80 μm or less, or may be 60 μm or less. The thickness of each first wiring layer 31 constituting the first wiring structure 30 is, for example, 5 μm or more, or may be 10 μm or more, or may be 20 μm or more. The thickness of each first wiring layer 31 is, for example, 50 μm or less, or may be 30 μm or less, or may be 15 μm or less.

[0061] The planar area of ​​the first wiring structure 30 may be the same as the planar area of ​​the substrate electrode structure 11. The planar area of ​​the first wiring structure 30 may be the same as the planar area of ​​the through electrode substrate 10 described below.

[0062] 1 , a first adhesive layer 50 is interposed between the first substrate surface 13 and the first wiring structure 30. That is, the first adhesive layer 50 is located between the first substrate surface 13 and the first wiring structure 30. The first adhesive layer 50 bonds the first substrate surface 13 and the first wiring structure 30 to each other. As shown in FIG. 1 , a portion of the first conductive layer 33 of the first wiring structure 30 may extend from the first inner surface 36 and be located within the first adhesive layer 50.

[0063] The first adhesive layer 50 has insulating properties and heat resistance. The first adhesive layer 50 includes an adhesive. The adhesive may be, for example, an epoxy resin adhesive. The thickness of the first adhesive layer 50 is, for example, 0.1 μm or more, or may be 0.2 μm or more, or may be 0.3 μm or more. The thickness of the first adhesive layer 50 is, for example, 1.0 μm or less, or may be 0.8 μm or less, or may be 0.5 μm or less.

[0064] A semiconductor element (not shown) is mounted on the first wiring structure portion 30. The semiconductor element is mounted on the first wiring structure portion 30 and is electrically connected to the first wiring structure portion 30. The semiconductor element is electrically connected to the through electrode 20 via the first conductive layers 23 and 33.

[0065] (Second Wiring Structure Portion) The second wiring structure portion 40 is located on the second substrate surface 14 of the core substrate 12. More specifically, the second wiring structure portion 40 is located on the second substrate surface 14 via the second insulating layer 24 and the second adhesive layer 52 described below. The second wiring structure portion 40 is electrically connected to the through electrodes 20. The second wiring structure portion 40 electrically connects the through electrodes 20 to a support substrate that supports the through electrode substrate 10 or a mounting substrate on which the through electrode substrate 10 is mounted. The second wiring structure portion 40 includes a second wiring layer 41.

[0066] The second wiring layer 41 includes a second insulating layer 42 and a second conductive layer 43. The second insulating layer 42 is located on the second substrate surface 14 of the core substrate 12. More specifically, the second insulating layer 42 is located on the second substrate surface 14 via the second insulating layer 24 and the second adhesive layer 52. The second insulating layer 42 extends in a plane on the second substrate surface 14. The second conductive layer 43 is located within the second insulating layer 42. The second conductive layer 43 is in electrical contact with the second conductive layer 25 and is electrically connected to the through electrode 20. The second conductive layer 43 includes wiring and pads. The wiring is a portion that is not exposed from the second insulating layer 42 and extends vertically and horizontally within the second conductive layer 43. The pad is a portion that is exposed from the second insulating layer 42 and is in electrical contact with other components.

[0067] The second wiring layer 41 may include a plurality of second wiring layers 41A, 41B. The second wiring structure 40 may be configured by stacking a plurality of second wiring layers 41A, 41B. In the example shown, the second wiring layer 41 includes two second wiring layers 41A, 41B stacked on top of each other. The second wiring layer 41A is located closer to the second substrate surface 14 than the second wiring layer 41B. The second wiring layer 41B is located farther from the second substrate surface 14 than the second wiring layer 41A. Although not shown, the second wiring layer 41 may include an additional wiring layer. Each second wiring layer 41 may include a second insulating layer 42 and a second conductive layer 43.

[0068] The second insulating layer 42 has insulating properties and may be made of the same material as the first insulating layer 32.

[0069] 3 is a partially enlarged cross-sectional view of the second wiring structure 40. As shown in FIG. 3, the second conductive layer 43 includes a second seed layer 44 and a second plating layer 45. The second seed layer 44 is a layer formed by physical film formation such as sputtering. The second plating layer 45 is a layer formed on the second seed layer 44 by electrolytic plating. The second plating layer 45 is located on the second seed layer 44.

[0070] The second seed layer 44 is located farther from the second substrate surface 14 than the second plating layer 45. The second plating layer 45 is located closer to the second substrate surface 14 than the second seed layer 44. That is, the second seed layer 44 is located outside (below in the figure) the second plating layer 45. The second plating layer 45 is located inside (above in the figure) the second seed layer 44. Here, "outside" refers to the direction away from the core substrate 12. Here, "inside" refers to the direction approaching the core substrate 12.

[0071] The second seed layer 44 is electrically conductive. The second seed layer 44 may be made of the same material as the first seed layer 34. The second plating layer 45 is electrically conductive. The second plating layer 45 may be made of the same material as the first plating layer 35.

[0072] The second wiring structure 40 also includes a second inner surface 46 and a second outer surface 47. The second inner surface 46 faces the second substrate surface 14. The second outer surface 47 is located on the opposite side to the second inner surface 46. The second inner surface 46 is located closer to the second substrate surface 14 than the second outer surface 47. The second outer surface 47 is located farther from the second substrate surface 14 than the second inner surface 46. That is, the second inner surface 46 is located inside (above in the figure) the second outer surface 47. The second outer surface 47 is located outside (below in the figure) the second inner surface 46. Here, "outside" refers to a direction away from the core substrate 12. Here, "inside" refers to a direction approaching the core substrate 12. The second outer surface 47 constitutes the outer surface of the through electrode substrate 10.

[0073] The surface roughness of the second outer surface 47 is smaller than the surface roughness of the second inner surface 46. That is, the arithmetic mean roughness Ra of the second outer surface 47 is smaller than the arithmetic mean roughness Ra of the second inner surface 46. The arithmetic mean roughness Ra of the second outer surface 47 is, for example, 0.01 μm or more, or may be 0.05 μm or more, or 0.1 μm or more. The arithmetic mean roughness Ra of the second outer surface 47 is, for example, 1 μm or less, or may be 0.5 μm or less, or may be 0.2 μm or less.

[0074] The second outer surface 47 has a maximum height roughness Rz of, for example, 0.05 μm or more, or may have a maximum height roughness Rz of 0.1 μm or more, or may have a maximum height roughness Rz of, for example, 1.5 μm or less, or may have a maximum height roughness Rz of 1.0 μm or less, or may have a maximum height roughness Rz of 0.5 μm or less.

[0075] The thickness of the second wiring structure 40 is, for example, 20 μm or more, optionally 30 μm or more, or 40 μm or more. The thickness of the second wiring structure 40 is, for example, 100 μm or less, optionally 80 μm or less, or optionally 60 μm or less. The thickness of each second wiring layer 41 constituting the second wiring structure 40 is, for example, 5 μm or more, optionally 10 μm or more, or optionally 20 μm or more. The thickness of each second wiring layer 41 is, for example, 50 μm or less, optionally 30 μm or less, or optionally 15 μm or less.

[0076] The planar area of ​​the second wiring structure 40 may be the same as the planar area of ​​the substrate electrode structure 11. The planar area of ​​the second wiring structure 40 may be the same as the planar area of ​​the first wiring structure 30. The planar area of ​​the second wiring structure 40 may be the same as the planar area of ​​the through electrode substrate 10 described below.

[0077] 1 , a second adhesive layer 52 is interposed between the second substrate surface 14 and the second wiring structure 40. That is, the second adhesive layer 52 is located between the second substrate surface 14 and the second wiring structure 40. The second adhesive layer 52 bonds the second substrate surface 14 and the second wiring structure 40 to each other. As shown in FIG. 1 , a portion of the second conductive layer 43 of the second wiring structure 40 may extend from the second inner surface 46 and be located within the second adhesive layer 52.

[0078] The second adhesive layer 52 has insulating properties and heat resistance. The second adhesive layer 52 may be made of the same material as the first adhesive layer 50. The thickness of the second adhesive layer 52 is, for example, 0.1 μm or more, or may be 0.2 μm or more, or may be 0.3 μm or more. The thickness of the second adhesive layer 52 is, for example, 1.0 μm or less, or may be 0.8 μm or less, or may be 0.5 μm or less.

[0079] The through electrode substrate 10 is supported by a support substrate (not shown). The through electrode substrate 10 is supported by the support substrate and electrically connected to the support substrate. The support substrate is electrically connected to the through electrodes 20 via second conductive layers 25, 43. Alternatively, the through electrode substrate 10 is mounted on a mounting substrate (not shown). The through electrode substrate 10 is mounted on the mounting substrate and electrically connected to the mounting substrate. The mounting substrate is electrically connected to the through electrodes 20 via the second conductive layers 25, 43.

[0080] In this way, the through hole electrode substrate 10 electrically connects the semiconductor element and the support substrate, or the semiconductor element and the mounting substrate.

[0081] The through electrode substrate 10 may be a large through electrode substrate. The dimensions of the through electrode substrate 10 in the length and width directions are, for example, 5 cm or more, 10 cm or more, or 20 cm or more. The planar area of ​​the through electrode substrate 10 is, for example, 25 cm. ２ or more, and 100 cm ２ It may be more than 400 cm ２ It may be more than that.

[0082] The dimensions of the above components (thickness, pore diameter, distance, etc.) are calculated based on images taken by a scanning electron microscope.

[0083] (Method for Manufacturing the Through Hole Electrode Substrate) Next, a description will be given of a method for manufacturing the through hole electrode substrate 10. The method for manufacturing the through hole electrode substrate 10 includes a preparation step, a first transfer step, and a second transfer step.

[0084] (Preparation Process) First, a preparation process is carried out. In the preparation process, the substrate electrode structure 11 is prepared. The preparation process may include a core substrate preparation process, a through electrode formation process, a conductive layer formation process, an insulating layer formation process, and a singulation process.

[0085] 4, the core substrate 12 is prepared. As described above, the core substrate 12 includes the first substrate surface 13, the second substrate surface 14, and the through holes 15. The core substrate preparation process may include a through hole formation process.

[0086] In the through hole forming step, the through holes 15 are formed in the core substrate 12. More specifically, first, a resist layer is formed on at least one of the first substrate surface 13 or the second substrate surface 14 of the core substrate 12. Next, openings are formed in the resist layer at positions corresponding to the through holes 15. Next, the core substrate 12 is processed through the openings in the resist layer. The core substrate 12 may be processed by dry etching, wet etching, or the like. In this manner, the through holes 15 are formed in the core substrate 12.

[0087] In the through hole forming step, the core substrate 12 may be irradiated with a laser to form the through holes 15 in the core substrate 12. In this case, a resist layer does not need to be provided. Alternatively, after the core substrate 12 is irradiated with a laser, the through holes 15 may be formed in the core substrate 12 by performing an etching process using a wet etching method.

[0088] 5, in the through electrode forming step, the through electrode 20 is formed in the through hole 15. The through electrode forming step may include a plating step.

[0089] In the plating formation process, plating is formed in the through holes 15. More specifically, first, a seed layer is formed on the first substrate surface 13, the second substrate surface 14 of the core substrate 12, and in the through holes 15. For example, the seed layer is formed by sputtering. Next, a resist layer is formed on the seed layer. The resist layer is formed in a position where the through electrodes 20 will not be formed. Next, plating is formed in the portions of the seed layer that are not covered by the resist layer by electrolytic plating. For example, the core substrate 12 is immersed in an electrolytic plating solution, and a current is passed through the seed layer to deposit plating on the seed layer. Thereafter, the resist layer is removed from the core substrate 12. The seed layer that overlaps the resist layer is also removed. In this manner, the through electrodes 20 are formed in the through holes 15. Furthermore, portions of the through electrodes 20 are formed on the first substrate surface 13 and the second substrate surface 14.

[0090] 6, in the conductive layer forming step, a first conductive layer 23 and a second conductive layer 25 are formed on the first substrate surface 13 and the second substrate surface 14 of the core substrate 12, respectively. The conductive layer forming step may include a first conductive layer forming step and a second conductive layer forming step.

[0091] In the first conductive layer forming process, a first conductive layer 23 is formed on the first substrate surface 13 of the core substrate 12. More specifically, a seed layer is first formed on the first substrate surface 13 of the core substrate 12 by sputtering. Subsequently, a resist layer is formed on the seed layer in a position where the first conductive layer 23 will not be formed. Next, electrolytic plating is used to form plating on the portion of the seed layer that is not covered by the resist layer. Thereafter, the resist layer and the seed layer that overlaps the resist layer are removed from the first substrate surface 13 of the core substrate 12. In this manner, the first conductive layer 23 is formed on the first substrate surface 13 of the core substrate 12. In the second conductive layer forming process, a second conductive layer 25 is formed on the second substrate surface 14 of the core substrate 12 in a similar manner.

[0092] 6, in the insulating layer forming step, a first insulating layer 22 and a second insulating layer 24 are formed on the first substrate surface 13 and the second substrate surface 14 of the core substrate 12, respectively. The insulating layer forming step may include a filling member forming step, a first insulating layer forming step, and a second insulating layer forming step.

[0093] In the filler member forming step, a filler member 21 is filled inside the through electrode 20. In the first insulating layer forming step, a first insulating layer 22 is formed on the first substrate surface 13 of the core substrate 12 so as to straddle the first conductive layer 23. Similarly, in the second insulating layer forming step, a second insulating layer 24 is formed on the second substrate surface 14 of the core substrate 12 so as to straddle the second conductive layer 25. In this manner, the substrate electrode structure 11 can be obtained as shown in FIG.

[0094] 7, the substrate electrode structure 11 is cut along cutting lines CL to separate the substrate electrode structure 11. In this manner, a plurality of substrate electrode structures 11 separated from one another by cutting can be obtained.

[0095] (First Transfer Process) Next, the first transfer process is carried out. In the first transfer process, the first wiring structure 30 is transferred and formed on the first substrate surface 13 of the core substrate 12. The first transfer process includes a first wiring structure formation process and a first wiring structure transfer process.

[0096] In the first wiring structure forming step, the first wiring structure 30 is formed on the carrier substrate 60. The first wiring structure forming step may include a carrier substrate preparing step, a release layer forming step, a first conductive layer forming step, and a first insulating layer forming step.

[0097] 8, a carrier substrate 60 is prepared. The carrier substrate 60 may be, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina substrate, an aluminum nitride substrate, a zirconia oxide substrate, a lithium niobate substrate, a tantalum niobate substrate, etc. The resin substrate may contain an organic material such as an epoxy resin, polyethylene, or polypropylene.

[0098] In the release layer formation step, as shown in FIG. 8 , a release layer 65 is formed on the carrier substrate 60. The release layer 65 is a layer for facilitating the operation of peeling the first wiring structure 30 from the carrier substrate 60. The release layer 65 includes, for example, a resin. The release layer 65 is configured so that adhesion between the release layer 65 and the first wiring structure 30 decreases when some kind of trigger is triggered. The trigger may be irradiation of the release layer 65 with light of a specific wavelength. For example, the release layer 65 may be decomposed by irradiating the release layer 65 with light of a specific wavelength. The trigger may be heating the release layer 65. For example, the release layer 65 may include a thermoplastic resin. The thickness of the release layer 65 is, for example, 0.1 μm or more, 0.2 μm or more, or 0.3 μm or more. The thickness of the release layer 65 is, for example, 1.0 μm or less, 0.8 μm or less, or 0.5 μm or less. In the release layer forming step, first, a solution containing a resin and a solvent is applied onto the carrier substrate 60. Then, for example, the carrier substrate 60 is heated and dried to evaporate the solvent. In this manner, the release layer 65 is formed on the carrier substrate 60.

[0099] In the first conductive layer formation step, as shown in FIG. 9 , a first conductive layer 33 is formed on a carrier substrate 60. More specifically, the first conductive layer 33 is formed on a release layer 65 located on the carrier substrate 60. For example, first, a first seed layer 34 (see FIG. 2 ) is formed on the release layer 65 by sputtering. Next, a resist layer is formed on the first seed layer 34 in a position where the first conductive layer 33 will not be formed. Next, a first plating layer 35 (see FIG. 2 ) is formed on the portion of the first seed layer 34 that is not covered by the resist layer by electroplating. Then, the resist layer and the first seed layer 34 that overlaps the resist layer are removed. In this manner, the first conductive layer 33 is formed on the release layer 65.

[0100] 10 , in the first insulating layer forming step, the first insulating layer 32 is formed on the carrier substrate 60 so as to straddle the first conductive layer 33. More specifically, the first insulating layer 32 is formed on the release layer 65 located on the carrier substrate 60 so as to straddle the first conductive layer 33. In this manner, the first wiring layer 31 including the first insulating layer 32 and the first conductive layer 33 is formed on the carrier substrate 60.

[0101] 11 , by repeatedly performing the first conductive layer forming step and the first insulating layer forming step, a plurality of first wiring layers 31A, 31B stacked on top of each other may be formed on the carrier substrate 60. In this manner, the first wiring structure 30 including the plurality of first wiring layers 31A, 31B can be formed on the carrier substrate 60.

[0102] 11 , in the first wiring structure 30 located on the carrier substrate 60, the first wiring layer 31B is located closer to the carrier substrate 60 than the first wiring layer 31A, and the first wiring layer 31A is located farther from the carrier substrate 60 than the first wiring layer 31B. Also, the first seed layer 34 is located closer to the carrier substrate 60 than the first plating layer 35, and the first plating layer 35 is located farther from the carrier substrate 60 than the first seed layer 34. Also, the outer surface 37 of the first wiring structure 30 faces the carrier substrate 60.

[0103] In the first wiring structure transfer process, the first wiring structure 30 located on the carrier substrate 60 is transferred onto the first substrate surface 13 of the core substrate 12. More specifically, as shown in FIG. 12 , an adhesive for the first adhesive layer 50 is first applied to the first insulating layer 22 located on the first substrate surface 13. Next, the first inner surface 36 of the first wiring structure 30 is faced to the first adhesive layer 50, and as shown in FIG. 13 , the first wiring structure 30 is pressed into the uncured first adhesive layer 50 for pressure bonding. Here, the first conductive layer 33 of the first wiring structure 30 and the first conductive layer 23 of the substrate electrode structure 11 are electrically connected. Next, the first adhesive layer 50 is cured, thereby bonding the first substrate surface 13 and the first wiring structure 30 together. In this manner, the first adhesive layer 50 is interposed between the first substrate surface 13 and the first wiring structure 30. Thereafter, the release layer 65 is irradiated with light of a specific wavelength to decompose the release layer 65 and peel the first wiring structure portion 30 from the carrier substrate 60. The light may pass through the carrier substrate 60 and reach the release layer 65.

[0104] In this way, the first wiring structure 30 can be transferred and formed on the first substrate surface 13 as shown in FIG.

[0105] (Second Transfer Process) Next, the second transfer process is carried out. In the second transfer process, the second wiring structure 40 is transferred and formed on the second substrate surface 14 of the core substrate 12. The second transfer process is similar to the first transfer process described above. The second transfer process includes a second wiring structure formation process and a second wiring structure transfer process.

[0106] In the second wiring structure forming step, the second wiring structure 40 is formed on the carrier substrate 60. The second wiring structure forming step may include a carrier substrate preparing step, a release layer forming step, a second conductive layer forming step, and a second insulating layer forming step.

[0107] In the carrier substrate preparation step, a carrier substrate 60 is prepared in the same manner as in the example shown in FIG.

[0108] In the release layer forming step, a release layer 65 is formed on a carrier substrate 60 in the same manner as in the example shown in FIG.

[0109] In the second conductive layer formation step, similar to the example shown in FIG. 9 , a second conductive layer 43 is formed on a carrier substrate 60. More specifically, the second conductive layer 43 is formed on a release layer 65 located on the carrier substrate 60. For example, first, a second seed layer 44 (see FIG. 3 ) is formed on the release layer 65 by sputtering. Next, a resist layer is formed on the second seed layer 44 in a position where the second conductive layer 43 will not be formed. Next, a second plating layer 45 (see FIG. 3 ) is formed on the portion of the second seed layer 44 that is not covered by the resist layer by electroplating. Then, the resist layer and the second seed layer 44 that overlaps the resist layer are removed. In this manner, the second conductive layer 43 is formed on the release layer 65.

[0110] 10 , in the second insulating layer forming step, the second insulating layer 42 is formed on the carrier substrate 60 so as to straddle the second conductive layer 43. More specifically, the second insulating layer 42 is formed on the release layer 65 located on the carrier substrate 60 so as to straddle the second conductive layer 43. In this manner, the second wiring layer 41 including the second insulating layer 42 and the second conductive layer 43 is formed on the carrier substrate 60.

[0111] 11 , by repeatedly performing the second conductive layer forming step and the second insulating layer forming step, a plurality of second wiring layers 41A, 41B stacked on top of each other may be formed on the carrier substrate 60. In this manner, the second wiring structure 40 including the plurality of second wiring layers 41A, 41B can be formed on the carrier substrate 60.

[0112] 11 , in the second wiring structure 40 located on the carrier substrate 60, the second wiring layer 41B is located closer to the carrier substrate 60 than the second wiring layer 41A, and the second wiring layer 41A is located farther from the carrier substrate 60 than the second wiring layer 41B. Also, the second seed layer 44 is located closer to the carrier substrate 60 than the second plating layer 45, and the second plating layer 45 is located farther from the carrier substrate 60 than the second seed layer 44. Also, the outer surface 47 of the second wiring structure 40 faces the carrier substrate 60.

[0113] In the second wiring structure transfer process, the second wiring structure 40 located on the carrier substrate 60 is transferred onto the second substrate surface 14 of the core substrate 12. More specifically, first, as in the example shown in FIG. 12 , an adhesive for the second adhesive layer 52 is applied to the second insulating layer 24 located on the second substrate surface 14. Next, the second inner surface 46 of the second wiring structure 40 is brought into contact with the second adhesive layer 52 before hardening, and as in the example shown in FIG. 13 , the second wiring structure 40 is pressed and bonded into the uncured second adhesive layer 52. Here, the second conductive layer 43 of the second wiring structure 40 and the second conductive layer 25 of the substrate electrode structure 11 are electrically connected. Next, the second adhesive layer 52 is hardened, thereby bonding the second substrate surface 14 and the second wiring structure 40 together. In this manner, the second adhesive layer 52 is interposed between the second substrate surface 14 and the second wiring structure 40. Thereafter, the release layer 65 is irradiated with light of a specific wavelength to decompose the release layer 65 and peel the second wiring structure portion 40 from the carrier substrate 60. The light may pass through the carrier substrate 60 and reach the release layer 65.

[0114] In this way, the second wiring structure 40 can be transferred and formed on the second substrate surface 14 as shown in FIG.

[0115] In this manner, the through electrode substrate 10 including the core substrate 12, the through electrode 20, the first wiring structure portion 30, and the second wiring structure portion 40 can be manufactured.

[0116] A semiconductor element is mounted on the thus manufactured through electrode substrate 10. The semiconductor element is mounted on the first wiring structure portion 30 and electrically connected to the first wiring structure portion 30. The semiconductor element is electrically connected to the through electrode 20 via the first conductive layers 23, 33.

[0117] Furthermore, the through electrode substrate 10 is supported by a support substrate. The through electrode substrate 10 is supported by the support substrate and electrically connected to the support substrate. The support substrate is electrically connected to the through electrodes 20 via second conductive layers 25, 43. Alternatively, the through electrode substrate 10 is mounted on a mounting substrate. The through electrode substrate 10 is mounted on the mounting substrate and electrically connected to the mounting substrate. The mounting substrate is electrically connected to the through electrodes 20 via the second conductive layers 25, 43.

[0118] In this way, the through hole electrode substrate 10 electrically connects the semiconductor element and the support substrate, or the semiconductor element and the mounting substrate.

[0119] According to this embodiment, in the manufacturing method of the through hole electrode substrate 10, the first wiring structure 30 is transferred and formed on the first substrate surface 13 of the core substrate 12, and the second wiring structure 40 is transferred and formed on the second substrate surface 14 of the core substrate 12. In a typical manufacturing method of a through hole electrode substrate, the first wiring structure is formed by laminating an insulating layer and a conductive layer on the first substrate surface of the core substrate, and the second wiring structure is formed by laminating an insulating layer and a conductive layer on the second substrate surface of the core substrate. When laminating and forming wiring structures on the core substrate in this manner, problems such as increased warping and distortion of the through hole electrode substrate can occur. This can reduce the manufacturing yield of the through hole electrode substrate. In contrast, according to this embodiment, the wiring structures 30, 40 are transferred and formed on both sides of the core substrate 12, thereby avoiding the problems of warping and distortion of the through hole electrode substrate when laminating and forming wiring structures on the core substrate. That is, instead of forming the wiring structures 30, 40 directly on the core substrate 12, for example, by separately forming them on the carrier substrate 60 as described above, the wiring structures 30, 40 can be manufactured with warping and distortion suppressed. Then, by transferring and forming the wiring structures 30, 40 with suppressed warping and distortion onto the core substrate 12, warping and distortion of the entire through hole electrode substrate 10 can be suppressed. As a result, the manufacturing yield of the through hole electrode substrate 10 can be improved.

[0120] Furthermore, according to this embodiment, a first adhesive layer 50 is interposed between the first substrate surface 13 and the first wiring structure 30, and a second adhesive layer 52 is interposed between the second substrate surface 14 and the second wiring structure 40. This allows the wiring structures 30, 40 to be firmly supported on the core substrate 12 even when the wiring structures 30, 40 are transferred onto the core substrate 12. This improves the reliability of the through electrode substrate 10.

[0121] Furthermore, according to this embodiment, the first seed layer 34 is located farther from the first substrate surface 13 than the first plating layer 35, and the second seed layer 44 is located farther from the second substrate surface 14 than the second plating layer 45. When a wiring structure is formed on a core substrate, as in a typical manufacturing method of a through-hole electrode substrate, the plating layer is formed on the seed layer formed on the substrate surface, so the seed layer is located closer to the substrate surface than the plating layer. In contrast, according to this embodiment, the wiring structures 30 and 40 formed separately on the carrier substrate 60 are transferred onto the core substrate 12, so the positional relationship between the seed layers 34 and 44 and the plating layers 35 and 45 is reversed. Therefore, when the wiring structures 30 and 40 are transferred onto the core substrate 12, the seed layers 34 and 44 are located farther from the substrate surfaces 13 and 14 than the plating layers 35 and 45.

[0122] Furthermore, according to this embodiment, the arithmetic mean roughness Ra of the first outer surface 37 of the first wiring structure 30 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface 47 of the second wiring structure 40 is 1 μm or less. Furthermore, the maximum height roughness Rz of the first outer surface 37 of the first wiring structure 30 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface 47 of the second wiring structure 40 is 1.5 μm or less. According to this embodiment, the wiring structures 30, 40 are separately formed on the carrier substrate 60, for example, as described above. In this case, the outer surfaces 37, 47 of the wiring structures 30, 40 face the carrier substrate 60. This improves the flatness of the outer surfaces 37, 47 of the wiring structures 30, 40. That is, the arithmetic mean roughness Ra and / or the maximum height roughness Rz of the outer surfaces 37, 47 of the wiring structures 30, 40 can be reduced. In this way, when the wiring structures 30, 40 are transferred onto the core substrate 12, the flatness of the outer surfaces 37, 47 of the wiring structures 30, 40 can be improved compared to when the wiring structures are laminated on the core substrate (see the examples below). As a result, the quality of the through electrode substrate 10 can be improved.

[0123] Furthermore, the improved flatness of the outer surfaces 37, 47 of the wiring structures 30, 40 facilitates the mounting of semiconductor elements and other wiring substrates. For example, processes such as polishing and cleaning the outer surfaces 37, 47 of the wiring structures 30, 40 to obtain flat surfaces can be eliminated. This makes it possible to manufacture wiring substrates that are easier to mount, and reduces the number of manufacturing steps.

[0124] Furthermore, according to this embodiment, the planar area of ​​the through electrode substrate 10 is 25 cm ２ In particular, in such a large through hole electrode substrate, when a wiring structure is formed on a core substrate, warping and distortion of the through hole electrode substrate can become significant. According to this embodiment, when the planar area of ​​the through hole electrode substrate 10 is 25 cm ２ By applying the above-described method for manufacturing a large through hole electrode substrate 10, warping and distortion of the through hole electrode substrate 10 can be effectively suppressed.

[0125] The above-described embodiment can be modified in various ways. A modified example will be described below with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for the corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in the modified example, the description may be omitted.

[0126] (First Modification) FIG. 16 is a cross-sectional view showing a through electrode substrate 10 according to one modification. In the example shown in FIG. 16, the configuration of the through electrode 20 is different from the example shown in FIG. 1. As shown in FIG. 16, the through electrode 20 may be filled in the through hole 15. That is, the through electrode 20 may fill the through hole 15 without any gaps. The through electrode 20 may be formed in a cylindrical shape in the through hole 15. In this case, the filling member 21 may not be located inside the through hole 15. Furthermore, although not shown, the through electrode 20 may be configured to block a portion of the through hole 15 in the thickness direction. For example, the through electrode 20 may block the center of the through hole 15 in the thickness direction.

[0127] (Second Modification) FIG. 17 is a partially enlarged cross-sectional view of a first wiring structure 30 included in a through electrode substrate 10 according to one modification. In the example shown in FIG. 17 , the configuration of the first conductive layer 33 is different from the example shown in FIG. 2 . As shown in FIG. 17 , the first conductive layer 33 of the first wiring layer 31B, which is the outermost of the multiple first wiring layers 31A, 31B constituting the first wiring structure 30, may include a nickel plating layer 70 and a gold plating layer 71. The nickel plating layer 70 may be located on the first seed layer 34. The nickel plating layer 70 may be located outside the first seed layer 34. The gold plating layer 71 may be located on the nickel plating layer 70. The gold plating layer 71 may be located outside the nickel plating layer 70. The nickel plating layer 70 may be located between the first seed layer 34 and the gold plating layer 71.

[0128] The nickel plating layer 70 facilitates connection with a semiconductor element when the semiconductor element has solder pillars. Furthermore, the gold plating layer 71 has a highly flat surface, which facilitates mounting of the semiconductor element. Furthermore, the gold plating layer 71 has an oxidation suppression function, and the nickel plating layer 70 has a barrier function against solder.

[0129] Although not shown, the second conductive layer 43 of the second wiring layer 41b, which is located outermost among the multiple second wiring layers 41A, 41B that make up the second wiring structure portion 40, may also include a nickel plating layer 70 and a gold plating layer 71.

[0130] (Third Modification) FIG. 18 is a cross-sectional view showing a through electrode substrate 10 according to a third modification. In the example shown in FIG. 18 , the configurations of the first conductive layer 33 and the second conductive layer 43 are different from those of the example shown in FIG. 16 . As shown in FIG. 18 , when the through electrode 20 is filled in the through hole 15, the first conductive layer 33 of the first wiring layer 31A, which is located innermost among the multiple first wiring layers 31A, 31B constituting the first wiring structure 30, may include a first solder layer 72. The first solder layer 72 may be located in the innermost portion of the first conductive layer 33 of the first wiring layer 31A. Furthermore, the second conductive layer 43 of the second wiring layer 41A, which is located innermost among the multiple second wiring layers 41A, 41B constituting the second wiring structure 40, may include a second solder layer 73. The second solder layer 73 may be located in the innermost portion of the second conductive layer 43 of the second wiring layer 41A. In plan view, the first insulating layer 22 may cover the boundary between the core substrate 12 and the through electrode 20. In addition, in plan view, the second insulating layer 24 may cover the boundary between the core substrate 12 and the through electrode 20.

[0131] The first solder layer 72 and the second solder layer 73 may be a low-temperature solder having a low melting point. The first solder layer 72 and the second solder layer 73 may be a Sn—Bi-based solder containing tin (Sn) and bismuth (Bi) as its main components. The first solder layer 72 and the second solder layer 73 may be a Sn—Ag-based solder containing tin (Sn) and silver (Ag) as its main components.

[0132] 19 is a cross-sectional view illustrating a manufacturing method of a through hole electrode substrate 10 according to this modified example. As shown in FIG. 19 , in the first wiring structure transferring step, an adhesive of a first adhesive layer 50 may be applied to a first inner surface 36 of the first wiring structure 30, and the first wiring structure 30 may be transferred onto the first substrate surface 13 of the core substrate 12. Furthermore, although not shown, in the second wiring structure transferring step, an adhesive of a second adhesive layer 52 may be applied to a second inner surface 46 of the second wiring structure 40, and the second wiring structure 40 may be transferred onto the second substrate surface 14 of the core substrate 12.

[0133] The first solder layer 72 can improve the reliability of the connection between the first conductive layer 33 of the first wiring structure 30 and the first conductive layer 23 of the substrate electrode structure 11. If the first solder layer 72 is a low-temperature solder, connection can be achieved at a low temperature of, for example, 250°C or less. Furthermore, the second solder layer 73 can improve the reliability of the connection between the second conductive layer 43 of the second wiring structure 40 and the second conductive layer 25 of the substrate electrode structure 11. If the second solder layer 73 is a low-temperature solder, connection can be achieved at a low temperature of, for example, 250°C or less.

[0134] (Fourth Modification) Fig. 20 is a cross-sectional view showing a through electrode substrate 10 according to one modification. In the example shown in Fig. 20, the configurations of the first conductive layer 33 and the second conductive layer 43 are different from those of the example shown in Fig. 1. As shown in Fig. 20, even when the through electrode 20 is not filled in the through hole 15, the first conductive layer 33 of the first wiring layer 31A located innermost among the multiple first wiring layers 31A, 31B constituting the first wiring structure 30 may include a first solder layer 72. Furthermore, the second conductive layer 43 of the second wiring layer 41A located innermost among the multiple second wiring layers 41A, 41B constituting the second wiring structure 40 may include a second solder layer 73.

[0135] 21 is a cross-sectional view illustrating the manufacturing method of the through hole electrode substrate 10 according to this modification. As shown in FIG. 21 , in the first wiring structure portion transferring step, the adhesive of the first adhesive layer 50 may be applied to the first inner surface 36 of the first wiring structure portion 30, and the first wiring structure portion 30 may be transferred onto the first substrate surface 13 of the core substrate 12.

[0136] 22 is a cross-sectional view illustrating a manufacturing method of the through hole electrode substrate 10 according to this modification. As shown in FIG. 22 , in the second wiring structure portion transferring step, the adhesive of the second adhesive layer 52 may be applied to the second insulating layer 24 located on the second substrate surface 14 of the core substrate 12, and the second wiring structure portion 40 may be transferred onto the second substrate surface 14 of the core substrate 12.

[0137] By such a first wiring structure portion transfer step and a second wiring structure portion transfer step, it is also possible to form a structure that is symmetrical in the thickness direction, as shown in FIG.

[0138] (Fifth Modification) Figure 23 is a partially enlarged cross-sectional view of a first wiring structure 30 included in a through electrode substrate 10 according to one modification. In the example shown in Figure 23, the configuration of the first wiring structure 30 is different from the example shown in Figure 2. As shown in Figure 23, the first wiring structure 30 may include an inorganic layer 75. Each of the first wiring layers 31A and 31B constituting the first wiring structure 30 may include the inorganic layer 75.

[0139] The inorganic layer 75 may be located on the first insulating layer 32. The inorganic layer 75 may cover the first insulating layer 32. The inorganic layer 75 may be in contact with the first insulating layer 32. The first conductive layer 33 may be located on the inorganic layer 75. That is, the inorganic layer 75 may be located between the first insulating layer 32 and the first conductive layer 33. The inorganic layer 75 may be in contact with the first conductive layer 33.

[0140] The inorganic layer 75 includes an inorganic material. Examples of the inorganic material include a metal material, an inorganic oxide, and an inorganic nitride. The inorganic material may have insulating properties. For example, the inorganic material may be an inorganic oxide or an inorganic nitride having insulating properties. Examples of the inorganic oxide include SiO ２ Examples of inorganic nitrides include silicon nitrides such as SiN. The inorganic material may be SiOC, SiC, SiOF, SiON, SiCN, or the like.

[0141] The thermal expansion coefficient of the inorganic material of the inorganic layer 75 is smaller than the thermal expansion coefficient of the organic material of the first insulating layer 32. The thermal expansion coefficient of the inorganic layer 75 is, for example, 10 ppm / °C or less, or may be 8 ppm / °C or less, or may be 5 ppm / °C or less.

[0142] The thickness of the inorganic layer 75 is, for example, 0.1 μm or more, or may be 0.3 μm or more, or 0.5 μm or more. The thickness of the inorganic layer 75 is, for example, 5 μm or less, or may be 3 μm or less, or may be 1 μm or less.

[0143] 23 , the inorganic layer 75 may include multiple layers containing the inorganic materials described above. In the example shown in FIG. 23 , the inorganic layer 75 includes a first inorganic layer 76 and a second inorganic layer 77. The first inorganic layer 76 is located on the second inorganic layer 77. The second inorganic layer 77 is located on the first insulating layer 32.

[0144] The first inorganic layer 76 may have higher adhesion to the first conductive layer 33 than the second inorganic layer 77. The second inorganic layer 77 may have a lower relative dielectric constant than the first inorganic layer 76. For example, the first inorganic layer 76 may contain silicon nitride such as SiN, and the second inorganic layer 77 may contain SiO ２ The silicon oxide may also contain silicon oxide such as silicon dioxide.

[0145] The thickness of the first inorganic layer 76 may be the same as or smaller than the thickness of the second inorganic layer 77. The thickness of the first inorganic layer 76 is, for example, 0.05 μm or more, or may be 0.1 μm or more, or 0.2 μm or more. The thickness of the first inorganic layer 76 is, for example, 2 μm or less, or may be 1 μm or less, or may be 0.5 μm or less. The thickness of the second inorganic layer 77 is, for example, 0.1 μm or more, or may be 0.2 μm or more, or may be 0.5 μm or more. The thickness of the second inorganic layer 77 is, for example, 5 μm or less, or may be 2 μm or less, or may be 1 μm or less.

[0146] In the process of forming the first wiring structure 30, the first insulating layer 32 may be heated. The thermal expansion coefficient of the organic material of the first insulating layer 32 is greater than that of the other components of the first wiring layer 31 (such as the carrier substrate 60 and the first conductive layer 33). After heating, when the temperature of the components of the first wiring layer 31 decreases, stress may be generated due to the difference in the thermal expansion coefficient between the first insulating layer 32 and the other components. In contrast, by including the inorganic layer 75 in the first wiring structure 30, stress caused by the first insulating layer 32 can be prevented from affecting components other than the first insulating layer 32. Therefore, warping and distortion of the first wiring layer 31 and the first wiring structure 30 can be suppressed. As a result, warping and distortion of the through-hole electrode substrate 10 can be suppressed. Furthermore, stress can be suppressed from being generated in the first conductive layer 33, thereby suppressing defects such as deformation and breakage of the first conductive layer 33.

[0147] Although not shown, the second wiring structure 40 may also include an inorganic layer 75 .

[0148] (Other Modifications) The substrate electrode structure 11 may include a plurality of first insulating layers 22 and a plurality of first conductive layers 23. That is, a plurality of first insulating layers 22 and a plurality of first conductive layers 23 may be laminated on the first substrate surface 13 of the core substrate 12. Then, in the first transfer step, the first wiring structure 30 may be transferred to this substrate electrode structure 11. Similarly, the substrate electrode structure 11 may include a plurality of second insulating layers 24 and a plurality of second conductive layers 25. That is, a plurality of second insulating layers 24 and a plurality of second conductive layers 25 may be laminated on the second substrate surface 14 of the core substrate 12. Then, in the second transfer step, the second wiring structure 40 may be transferred to this substrate electrode structure 11.

[0149] The planar area of ​​the first wiring structure 30 may be smaller than the planar area of ​​the substrate electrode structure 11. In this case, the first wiring structure 30 may be transferred onto a portion of the substrate electrode structure 11 rather than onto the entire surface of the substrate electrode structure 11. The first wiring structure 30 may be a bridge connecting two electronic components. A cavity may be formed in the substrate electrode structure 11, and the first wiring structure 30 may be transferred and embedded in this cavity. Alternatively, after the first wiring structure 30 is transferred to the substrate electrode structure 11, the first insulating layer 22 and the first conductive layer 23 may be formed in the portion of the substrate electrode structure 11 where the first wiring structure 30 has not been transferred. Furthermore, multiple first wiring structures 30 may be transferred to the substrate electrode structure 11, and multiple first wiring structures 30 may be arranged on the same plane. The same applies to the second wiring structure 40.

[0150] 24 is a diagram showing an example of a product in which the through hole electrode substrate 10 is mounted. The through hole electrode substrate 10 can be used in a variety of products. For example, it is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0151] Next, the embodiments of the present disclosure will be described in more detail with reference to examples. The embodiments of the present disclosure are not limited to the following examples, as long as they do not depart from the gist of the present disclosure.

[0152] A through-hole electrode substrate according to an example and a through-hole electrode substrate according to a comparative example were prepared. Each through-hole electrode substrate had the same configuration. The vertical dimension of each through-hole electrode substrate was 10 cm. Therefore, the planar area of ​​each through-hole electrode substrate was 100 cm. ２ The core substrate of each through-hole electrode substrate was made of a glass material. The thickness of the core substrate of each through-hole electrode substrate was 400 μm. The wiring structure of each through-hole electrode substrate was made up of four wiring layers stacked on top of each other. The thickness of each wiring layer was 5 μm. Therefore, the thickness of the wiring structure made up of the four wiring layers was 20 μm.

[0153] In the through electrode substrate according to the example, the wiring structure was formed by transferring it onto both surfaces of the core substrate as in the above-described embodiment. In the through electrode substrate according to the comparative example, the wiring structure was formed by laminating it onto both surfaces of the core substrate as in the above-described general manufacturing method of the through electrode substrate.

[0154] In these through hole electrode substrates, the arithmetic mean roughness Ra (specified in JIS B 0601-2001) of the outer surface (surface of the insulating layer) of each wiring structure portion was measured. As described above, a DektakXT-S manufactured by Bruker was used to measure the arithmetic mean roughness Ra. In this measurement, the stylus tip curvature was 50 nm, the contact pressure was 1 mg, the scanning speed was 10 μm / s, and the scanning distance was 200 μm. In the examples and comparative examples, the arithmetic mean roughness Ra of the outer surface (surface of the insulating layer) of each wiring structure portion was measured as follows.

[0155] Example: 0.2 μm Comparative Example: 1.5 μm

[0156] Furthermore, the maximum height roughness Rz (defined in JIS B 0601-2001) of the outer surface (surface of the insulating layer) of each wiring structure portion was measured for these through hole electrode substrates. The measurement conditions for the maximum height roughness Rz were the same as those for the measurement of the arithmetic mean roughness Ra described above. In the examples and comparative examples, the maximum height roughness Rz of the outer surface (surface of the insulating layer) of each wiring structure portion was measured as follows.

[0157] Example: 0.4 μm Comparative Example: 1.7 μm

[0158] Furthermore, in these through hole electrode substrates, the maximum height roughness Rz (defined in JIS B 0601-2001) of the outer surface (surface of the conductive layer) of each wiring structure portion was measured. In the examples and comparative examples, the maximum height roughness Rz of the outer surface (surface of the conductive layer) of each wiring structure portion was measured as follows.

[0159] Example: 0.5 μm Comparative Example: 1.8 μm

[0160] Thus, the arithmetic mean roughness Ra and maximum height roughness Rz of the outer surface of the wiring structure portion of the through hole electrode substrate according to the example were reduced compared to the arithmetic mean roughness Ra and maximum height roughness Rz of the outer surface of the wiring structure portion of the through hole electrode substrate according to the comparative example. Therefore, it was confirmed that when the wiring structure portion is transferred onto the core substrate, the flatness of the outer surface of the wiring structure portion can be improved compared to when the wiring structure portion is laminated onto the core substrate.

Claims

1. A method for manufacturing a through electrode substrate, comprising the steps of: preparing a substrate electrode structure comprising a core substrate including a first substrate surface, a second substrate surface opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface, and a through electrode located in the through hole; transferring and forming a first wiring structure portion electrically connected to the through electrode onto the first substrate surface; and transferring and forming a second wiring structure portion electrically connected to the through electrode onto the second substrate surface.

2. A method for manufacturing a through electrode substrate as described in claim 1, wherein a first adhesive layer is interposed between the first substrate surface and the first wiring structure portion, and a second adhesive layer is interposed between the second substrate surface and the second wiring structure portion.

3. A method for manufacturing a through electrode substrate as described in claim 1, wherein the first wiring structure portion includes a first conductive layer including a first seed layer and a first plating layer located on the first seed layer, the second wiring structure portion includes a second conductive layer including a second seed layer and a second plating layer located on the second seed layer, the first seed layer is located farther from the first substrate surface than the first plating layer, and the second seed layer is located farther from the second substrate surface than the second plating layer.

4. A method for manufacturing a through electrode substrate as described in claim 1, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less.

5. A method for manufacturing a through electrode substrate as described in claim 1, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite the second inner surface, the maximum height roughness Rz of the first outer surface as defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface as defined in JIS B 0601-2001 is 1.5 μm or less.

6. The planar area of ​​the through electrode substrate is 25 cm ２ The method for producing a through hole electrode substrate according to claim 1 .

7. A through electrode substrate comprising: a core substrate including a first substrate surface, a second substrate surface located opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure portion located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure portion located on the second substrate surface and electrically connected to the through electrode, wherein a first adhesive layer is interposed between the first substrate surface and the first wiring structure portion, and a second adhesive layer is interposed between the second substrate surface and the second wiring structure portion.

8. The through electrode substrate of claim 7, wherein the first wiring structure portion includes a first conductive layer including a first seed layer and a first plating layer located on the first seed layer, the second wiring structure portion includes a second conductive layer including a second seed layer and a second plating layer located on the second seed layer, the first seed layer is located farther from the first substrate surface than the first plating layer, and the second seed layer is located farther from the second substrate surface than the second plating layer.

9. The through electrode substrate according to claim 7, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less.

10. The through electrode substrate according to claim 7, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite the second inner surface, the maximum height roughness Rz of the first outer surface as defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface as defined in JIS B 0601-2001 is 1.5 μm or less.

11. A through electrode substrate comprising: a core substrate including a first substrate surface, a second substrate surface located opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein the first wiring structure includes a first conductive layer including a first seed layer and a first plating layer located on the first seed layer, the second wiring structure includes a second conductive layer including a second seed layer and a second plating layer located on the second seed layer, the first seed layer is located farther from the first substrate surface than the first plating layer, and the second seed layer is located farther from the second substrate surface than the second plating layer.

12. The through electrode substrate according to claim 11, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less.

13. The through electrode substrate according to claim 11, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite the first inner surface, the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite the second inner surface, the maximum height roughness Rz of the first outer surface as defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface as defined in JIS B 0601-2001 is 1.5 μm or less.

14. A through electrode substrate comprising: a core substrate including a first substrate surface, a second substrate surface located opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite to the first inner surface, and the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite to the second inner surface, the arithmetic mean roughness Ra of the first outer surface as defined in JIS B 0601-2001 is 1 μm or less, and the arithmetic mean roughness Ra of the second outer surface as defined in JIS B 0601-2001 is 1 μm or less. The through electrode substrate has an arithmetic mean roughness Ra of 1 μm or less as defined by JIS J 0601-2001.

15. A through electrode substrate comprising: a core substrate including a first substrate surface, a second substrate surface located opposite to the first substrate surface, and a through hole penetrating from the first substrate surface to the second substrate surface; a through electrode located in the through hole; a first wiring structure located on the first substrate surface and electrically connected to the through electrode; and a second wiring structure located on the second substrate surface and electrically connected to the through electrode, wherein the first wiring structure includes a first inner surface facing the first substrate surface and a first outer surface located opposite to the first inner surface, and the second wiring structure includes a second inner surface facing the second substrate surface and a second outer surface located opposite to the second inner surface, the maximum height roughness Rz of the first outer surface as defined in JIS B 0601-2001 is 1.5 μm or less, and the maximum height roughness Rz of the second outer surface as defined in JIS B 0601-2001 is 1.5 μm or less. The through electrode substrate has a maximum height roughness Rz of 1.5 μm or less as defined by JIS J 0601-2001.

16. The planar area of ​​the through electrode substrate is 25 cm ２ The through hole electrode substrate according to claim 7 .

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