Power semiconductor module and power conversion device

Abstract

This power semiconductor module comprises: a substrate; a plurality of power semiconductor elements arranged on the substrate; a first terminal connected to first electrodes of the plurality of power semiconductor elements; a second terminal connected to second electrodes of the plurality of power semiconductor elements; and a third terminal connected to third electrodes of the plurality of power semiconductor elements. One or more terminals from among the first to third terminals cross the upper sides of the plurality of power semiconductor elements so as to be commonly and electrically connected to the upper sides of the plurality of power semiconductor elements.

Description

Power semiconductor modules and power conversion devices

[0001] The embodiment relates to a power semiconductor module and a power conversion device.

[0002] Power conversion devices are widely used in most industries. Power conversion devices utilize multiple switching circuits to convert and output power.

[0003] Power conversion devices include power semiconductor modules. Since power semiconductor modules have chips connected to a substrate using wire bonding, defects such as wire breaks can occur.

[0004] When multiple chips are connected to a power semiconductor module, there is a problem that the process time and material cost increase in order to connect numerous wires to the multiple chips.

[0005] The present invention aims to solve the above-mentioned and other problems.

[0006] Another object of the embodiment is to provide a power semiconductor module and a power conversion device having a wireless structure.

[0007] Another object of the present invention is to provide a power semiconductor module and a power conversion device that can reduce process time and material cost.

[0008] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0009] According to one aspect of the embodiment to achieve the above or other objects, a power semiconductor module includes: a substrate; a plurality of power semiconductor elements disposed on the substrate; a first terminal electrically connected to first electrodes of the plurality of power semiconductor elements; a second terminal electrically connected to second electrodes of the plurality of power semiconductor elements; and a third terminal electrically connected to third electrodes of the plurality of power semiconductor elements; wherein at least one terminal of the first to third terminals is electrically connected in common to the upper sides of the plurality of power semiconductor elements across the upper sides of the plurality of power semiconductor elements.

[0010] The first to third terminals may each be configured as a lead frame.

[0011] The first electrodes and the second electrodes are arranged so as to face the substrate, and the third terminal can be connected in common to the third electrodes of the plurality of power semiconductor elements across the third electrodes of the plurality of power semiconductor elements.

[0012] The third terminal has a recessed structure, and the recessed structure includes a first recessed area positioned on the upper side of each of the third electrodes; and a second recessed area positioned between the third electrodes; wherein the first recessed area is positioned lower than the second recessed area, and the first recessed area can be electrically or thermally connected to the upper side of each of the third electrodes.

[0013] The substrate includes a first circuit pattern formation layer; and a second circuit pattern formation layer arranged to be spaced apart from the first circuit pattern formation layer; and the plurality of power semiconductor elements can be arranged on the first circuit pattern formation layer and the second circuit pattern formation layer.

[0014] One side of the first circuit pattern forming layer may be electrically connected in common to the first electrodes, the other side of the first circuit pattern forming layer may be electrically connected to the first terminal, and one side of the second circuit pattern forming layer may be electrically connected in common to the second electrodes, and the other side of the second circuit pattern forming layer may be electrically connected to the second terminal.

[0015] The first electrodes and the second electrodes are arranged so as to face opposite sides of the substrate, the first terminal is electrically connected in common to the first electrodes, and the second terminal can be electrically connected in common to the second electrodes across the upper sides of the plurality of power semiconductor elements.

[0016] The second terminal has a recessed structure, and the recessed structure includes a first recessed region positioned on the upper side of each of the second electrodes; and a second recessed region positioned between the second electrodes; wherein the first recessed region is positioned lower than the second recessed region, and the first recessed region can be electrically or thermally connected to the upper side of each of the third electrodes.

[0017] The substrate includes a circuit pattern forming layer, and the plurality of power semiconductor devices can be arranged on the circuit pattern forming layer.

[0018] One side of the circuit pattern formation layer may be electrically connected in common to the third electrodes of the plurality of power semiconductor elements, and the other side of the circuit pattern formation layer may be electrically connected to the third terminal.

[0019] The first to third terminals may be made of the same material.

[0020] According to another aspect of the embodiment to achieve the above or other objects, a power conversion device includes a plurality of power semiconductor modules for converting power, the power semiconductor modules including: a substrate; a plurality of power semiconductor elements disposed on the substrate; a first terminal electrically connected to first electrodes of the plurality of power semiconductor elements; a second terminal electrically connected to second electrodes of the plurality of power semiconductor elements; and a third terminal electrically connected to third electrodes of the plurality of power semiconductor elements; wherein at least one terminal among the first to third terminals can be electrically connected in common to the upper sides of the plurality of power semiconductor elements across the upper sides of the plurality of power semiconductor elements.

[0021] The effects of the power semiconductor module and power conversion device according to the embodiment are described as follows.

[0022] According to at least one of the embodiments, a plurality of terminals formed of a lead frame connect a plurality of first power semiconductor elements forming a first switching unit and a plurality of second power semiconductor elements forming a second switching unit, so that a defect such as a wire breakage can be prevented because no wire is used.

[0023] According to at least one of the embodiments, a plurality of first power semiconductor elements constituting a first switching unit and a plurality of second power semiconductor elements constituting a second switching unit can be connected using an integral lead frame including a plurality of terminals, thereby significantly reducing process time and material cost.

[0024] According to at least one of the embodiments, one terminal among the plurality of terminals formed of a lead frame may be electrically connected in common to the upper sides of the plurality of first power semiconductor elements constituting the first switching unit by crossing the upper sides of the plurality of first power semiconductor elements. Another terminal among the plurality of terminals formed of a lead frame may be electrically connected in common to the upper sides of the plurality of second power semiconductor elements constituting the second switching unit by crossing the upper sides of the plurality of second power semiconductor elements. In this way, since the terminal is directly and commonly connected to the upper sides of the plurality of power semiconductor elements, an electrical connection failure that occurs when indirectly connecting using wires to a circuit pattern formation layer on a substrate can be prevented. In addition, since a voltage or signal is directly supplied to the plurality of power semiconductor elements through the terminal, current loss is reduced, enabling high-power switching.

[0025] Fig. 1 is a circuit diagram illustrating an inverter according to an embodiment.

[0026] FIG. 2 is a plan view illustrating a power semiconductor module according to the first embodiment.

[0027] Fig. 3 is a cross-sectional view of the power semiconductor module of Fig. 2 taken along line A1-A2.

[0028] Fig. 4 is a cross-sectional view of the power semiconductor module of Fig. 2 taken along line B1-B2.

[0029] Fig. 5 is a cross-sectional view of the power semiconductor module of Fig. 2 taken along line C1-C2.

[0030] Fig. 6 illustrates the arrangement relationship between the substrate and the first-first power semiconductor element in the power semiconductor module according to the first embodiment.

[0031] FIG. 7 is a plan view illustrating an integrated lead frame for forming a plurality of terminals in a power semiconductor module according to the first embodiment.

[0032] Figures 8 to 10 illustrate a manufacturing process of a power semiconductor module according to the first embodiment.

[0033] Fig. 11 is a plan view illustrating a power semiconductor module according to the second embodiment.

[0034] Fig. 12 is a cross-sectional view of the power semiconductor module of Fig. 11 taken along line D1-D2.

[0035] Fig. 13 is a cross-sectional view of the power semiconductor module of Fig. 11 taken along line E1-E2.

[0036] Fig. 14 is a cross-sectional view of the power semiconductor module of Fig. 11 taken along line F1-F2.

[0037] Fig. 15 illustrates the arrangement relationship between the substrate and the 2-1 power semiconductor element in the power semiconductor module according to the second embodiment.

[0038] FIG. 16 is a plan view illustrating an integrated lead frame for forming a plurality of terminals in a power semiconductor module according to the second embodiment.

[0039] Figures 17 to 19 illustrate a manufacturing process of a power semiconductor module according to the second embodiment.

[0040] The sizes, shapes, and dimensions of components depicted in the drawings may differ from the actual components. Furthermore, even if the same components are depicted with different sizes, shapes, and dimensions across drawings, this is merely an example within the drawings, and the same components may have the same sizes, shapes, and dimensions across drawings.

[0041] Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' used for components in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to make it easier to understand the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element or that other intermediate elements may exist therebetween.

[0042] Hereinafter, “module”, “part”, etc. may be composed of “circuit” or “integrated circuit”. “Module”, “part”, etc. may be used interchangeably with “circuit” or “integrated circuit”.

[0043] Fig. 1 is a circuit diagram illustrating an inverter according to the first embodiment.

[0044] Referring to FIG. 1, an inverter (1000) according to an embodiment can be applied to applications such as three-phase motors or compressors. The inverter (1000) can output three-phase power. The inverter (1000) can be a power conversion device or can be included in a power conversion device. The inverter (1000) can include a switching circuit.

[0045] An inverter (1000) according to an embodiment may convert DC power into AC power and supply the converted AC power to a load (1200) to drive the load (1200). In the inverter (1000) according to an embodiment, a converter may be connected to the input side to convert AC power into DC power. In this case, the DC power converted by the converter may be converted into AC power by the inverter (1000) and then used to drive the load (1200). The load (1200) may be a motor or an electric motor, but is not limited thereto.

[0046] The inverter (1000) according to the embodiment may include a three-phase inverter, but is not limited thereto. In this case, a phase difference of 120 degrees may be present between the first phase, the second phase, and the third phase. The inverter (1000) according to the embodiment may include a plurality of legs (100A, 100B, 100C). For example, the first leg (100A), the second leg (100B), and the third leg (100C) may be connected in parallel to the load (1200), i.e., the motor, through the first node (N1), the second node (N2), and the third node (N3), respectively. The first leg (100A) may include a first arm (100a) and a second arm (100b) that are connected in series to each other, the second leg (100B) may include a third arm (100c) and a fourth arm (100d) that are connected in series to each other, and the third leg (100C) may include a fifth arm (100e) and a sixth arm (100f) that are connected in series to each other. Here, the first arm (100a), the third arm (100c), and the fifth arm (100e) may be referred to as upper arms, and the second arm (100b), the fourth arm (100d), and the sixth arm (100f) may be referred to as lower arms. Each of the first arm (100a) to the sixth arm (100f) may be referred to as a switching module, a submodule, or the like.

[0047] The first arm (100a) to the sixth arm (100f) may each include switching units (Q1 to Q6) and diodes (100a-2 to 100f-2). The switching units (Q1 to Q6) and the diodes (100a-2 to 100f-2) may be formed simultaneously using the same semiconductor process. The switching units (Q1 to Q6) may include power semiconductor devices.

[0048] In order for DC power to be converted into AC power by the inverter (1000) according to the embodiment, the switching units (Q1 to Q6) of each of the first arm (100a) to the sixth arm (100f) can be controlled to turn on / off.

[0049] For example, when the first switching unit (Q1) of the first arm (100a) of the first leg (100A) is in the ON state, the fourth switching unit (Q4) of the fourth arm (100d) of the second leg (100B) and / or the sixth switching unit (Q6) of the sixth arm (100f) of the third leg (100C) may be in the ON state. Accordingly, DC power may be supplied to the first phase inductor of the motor.

[0050] For example, when the third switching unit (Q3) of the third arm (100c) of the second leg (100B) is turned on, the sixth switching unit (Q6) of the sixth arm (100f) of the third leg (100C) and / or the second switching unit (Q2) of the second arm (100b) of the first leg (100A) may be turned on. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be 120 degrees behind the first phase.

[0051] For example, when the fifth switching unit (Q5) of the fifth arm (100e) of the third leg (100C) is turned on, the second switching unit (Q2) of the second arm (100b) of the first leg (100A) and / or the fourth switching unit (Q4) of the fourth arm (100d) of the second leg (100B) may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be 120 degrees behind the second phase.

[0052] Accordingly, AC power can be generated by the DC power supplied to each of the first phase inductor, the second phase inductor, and the third inductor.

[0053] Meanwhile, although not shown, in order to increase the internal pressure characteristics, the switching units of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple numbers, each connected in series with each other.

[0054] Although not shown, in order to increase the current characteristics, the switching units of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple units connected in parallel with each other.

[0055] Meanwhile, the switching units (Q1 to Q6) and diodes (100a-2 to 100f-2) constituting the first arm (100a) to the sixth arm (100f) can be packaged to form a power semiconductor module.

[0056] As an example, the first leg (100A), the second leg (100B), and the third leg (100C) can each be configured as power semiconductor modules. That is, the first arm (100a) and the second arm (100b) of the first leg (100A) can be packaged to configure a first power semiconductor module. The third arm (100c) and the fourth arm (100d) of the second leg (100B) can be packaged to configure a second power semiconductor module. The fifth arm (100e) and the sixth arm (100f) of the third leg (100C) can be packaged to configure a third power semiconductor module.

[0057] As another example, the first leg (100A), the second leg (100B), and the third leg (100C) can be configured as a single power semiconductor module. That is, the first arm (100a) and the second arm (100b) of the first leg (100A), the third arm (100c) and the fourth arm (100d) of the second leg (100B), and the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) can be packaged to configure a single power semiconductor module.

[0058] Meanwhile, VDC is the input voltage, which can be, for example, DC voltage. CDC acts as a capacitor and can charge the input voltage (VDC).

[0059]

[0060] [Example 1]

[0061] Fig. 2 is a plan view illustrating a power semiconductor module according to the first embodiment. Fig. 3 is a cross-sectional view of the power semiconductor module of Fig. 2 taken along line A1-A2. Fig. 4 is a cross-sectional view of the power semiconductor module of Fig. 2 taken along line B1-B2. Fig. 5 is a cross-sectional view of the power semiconductor module of Fig. 2 taken along line C1-C2.

[0062] Referring to FIGS. 2 to 5, a power semiconductor module (100) according to the first embodiment may include a substrate (110), a first switching unit (120), a second switching unit (130), and a plurality of terminals (141 to 145).

[0063] In FIG. 2, the power semiconductor module (100) according to the first embodiment is shown as being composed of two switching units (120, 130) and five terminals (141 to 145), but it may also be composed of one switching unit and three terminals.

[0064] In FIG. 2, the power semiconductor module (100) according to the first embodiment shows one leg among the plurality of legs (100A, 100B, 100C) shown in FIG. 1, but may include all of the plurality of legs (100A, 100B, 100C).

[0065] For example, when the power semiconductor module (100) according to the first embodiment includes a first leg (100A), the first switching unit (120) may be the first switching unit (Q1) of the first arm (100a), and the second switching unit (Q2) may be the second switching unit (Q2) of the second arm (100b). Although not shown, the power semiconductor module (100) according to the first embodiment may include a third switching unit (Q3) and a fourth switching unit (Q4) constituting the second leg (100B), and a fifth switching unit (Q5) and a sixth switching unit (Q6) constituting the third leg (100C).

[0066] Meanwhile, the substrate (110) may be a heat dissipation substrate (110). For example, the substrate (110) may be made of DBC (Direct Bonded Copper), AMB (Active Metal Brazed), SMB (Sputtering Metal Bonding), IMC (Inter-Metallic Compound), etc.

[0067] The substrate (110) may include an insulating layer (115), a metal layer (116), and a plurality of circuit pattern forming layers (111 to 114). The insulating layer (115) may be made of an insulating material. For example, the insulating layer (115) may be made of a ceramic material, a plastic material, glass, or the like. The metal layer (116) may be disposed on the lower surface of the insulating layer (115). The metal layer (116) may serve as a heat dissipation layer and may discharge heat generated in the first switching unit (120) and the second switching unit (130) to the outside.

[0068] The plurality of circuit pattern formation layers (111 to 114) may be composed of a metal or a conductive material. For example, the metal layer (116) on the lower surface of the insulating layer (115) may be referred to as a first metal layer, and the plurality of circuit pattern formation layers (111 to 114) on the upper surface of the insulating layer (115) may be referred to as a second metal layer. In this case, the second metal layer may include the plurality of circuit pattern formation layers (111 to 114).

[0069] A plurality of circuit pattern formation layers (111 to 114) may be arranged on the upper surface of the insulating layer (115). The plurality of circuit pattern formation layers (111 to 114) may be arranged lengthwise along a first direction, for example, the X-axis direction. The plurality of circuit pattern formation layers (111 to 114) may be arranged to be spaced apart from each other along a second direction, for example, the Y-axis direction.

[0070] The plurality of circuit pattern formation layers (111 to 114) may be electrically insulated from each other. Although not shown, another insulating layer may be disposed on the plurality of circuit pattern formation layers (111 to 114) to electrically insulate the plurality of circuit pattern formation layers (111 to 114).

[0071] A plurality of circuit pattern formation layers (111 to 114) may serve to supply electric signals, such as current and voltage, provided from the outside to the first switching unit (120) and the second switching unit (130). The circuit pattern formation layers may be referred to as signal patterns, metal patterns, etc.

[0072] The plurality of circuit pattern formation layers (111 to 114) may include a first circuit pattern formation layer (111), a second circuit pattern formation layer (112), a third circuit pattern formation layer (113), and a fourth circuit pattern formation layer (114).

[0073] As illustrated in FIG. 8, the first circuit pattern formation layer (111), the second circuit pattern formation layer (112), the fourth circuit pattern formation layer (114), and the third circuit pattern formation layer (113) may be arranged in the order of the Y-axis direction. In this case, the first circuit pattern formation layer (111), the second circuit pattern formation layer (112), the third circuit pattern formation layer (113), and the fourth circuit pattern formation layer (114) may be symmetrical with respect to an imaginary horizontal line (165) crossing the center of the substrate (110) in the X-axis direction. For example, the first circuit pattern formation layer (111) and the third circuit pattern formation layer (113) may be symmetrical with respect to an imaginary horizontal line (165). For example, the second circuit pattern formation layer (112) and the fourth circuit pattern formation layer (114) may be symmetrical with respect to a virtual horizontal line (165).

[0074] Meanwhile, the first switching unit (120) may be referred to as a first power semiconductor element, and the second switching unit (130) may be referred to as a second power semiconductor element. In an embodiment, the first switching unit (120) and the first power semiconductor element may be used interchangeably, and the second switching unit (130) and the second power semiconductor element may be used interchangeably.

[0075] The first switching unit (120) and the second switching unit (130) may be disposed on the substrate (110). The first switching unit (120) may be disposed on the first circuit pattern formation layer (111) and the second circuit pattern formation layer (112). The second switching unit (130) may be disposed on the third circuit pattern formation layer (113) and the fourth circuit pattern formation layer (114).

[0076] The first electrodes and the second electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) may be in surface contact with the first circuit pattern forming layer (111) and the second circuit pattern forming layer (112), respectively. For example, the first electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) may be connected to the first circuit pattern (111), and the second electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) may be connected to the second circuit pattern (112).

[0077] The first electrodes and the second electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) may be in surface contact with the third circuit pattern forming layer (113) and the fourth circuit pattern forming layer (114), respectively. For example, the first electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) may be connected to the third circuit pattern (113), and the second electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) may be connected to the fourth circuit pattern (114).

[0078] The first switching unit (120) may include a plurality of first power semiconductor elements (121 to 124). Although four first power semiconductor elements (121 to 124) are illustrated in the drawing, more first power semiconductor elements may be provided. The second switching unit (130) may include a plurality of second power semiconductor elements (131 to 134). Although four second power semiconductor elements (131 to 134) are illustrated in the drawing, more second power semiconductor elements may be provided. The first power semiconductor elements (121 to 124) and the second power semiconductor elements (131 to 134) may each be made of SiC, GaN, or the like.

[0079] A plurality of first power semiconductor elements (121 to 124) may be connected in parallel with each other. A plurality of second power semiconductor elements (131 to 134) may be connected in parallel with each other. The first power semiconductor elements (121 to 124) and the second power semiconductor elements (131 to 134) may be MOSFETs (Metal-Oxide-Silicon Field-Effect Transistors). In this case, the first electrodes of the plurality of first power semiconductor elements (121 to 124) may be electrically connected in common, the third electrodes of the plurality of first power semiconductor elements (121 to 124) may be electrically connected in common, and the second electrodes of the plurality of first power semiconductor elements (121 to 124) may be electrically connected in common. The first electrodes of the plurality of second power semiconductor elements (131 to 134) are electrically connected in common, the third electrodes of the plurality of second power semiconductor elements (131 to 134) are electrically connected in common, and the second electrodes of the plurality of second power semiconductor elements (131 to 134) can be electrically connected in common. The first electrode can be a gate electrode, the second electrode can be a source electrode, and the third electrode can be a drain electrode.

[0080] The first switching unit (120) and the second switching unit (130) may be connected in series with each other. The first switching unit (120) and the second switching unit (130) may be connected in series with each other via a second terminal (142). The second electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) may be electrically connected to the third electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) via the second terminal (142).

[0081] The first switching unit (120) and the second switching unit (130) can be switched complementarily. For example, when the first switching unit (120) is turned on, the second switching unit (130) can be turned off. For example, when the first switching unit (120) is turned off, the second switching unit (130) can be turned on.

[0082] Among the plurality of first power semiconductor elements (121 to 124), the 1-1 power semiconductor element (121) is illustrated in FIG. 6, but the 1-2 power semiconductor elements (122) to the 1-4 power semiconductor elements (124) may also have the same structure as the 1-1 power semiconductor element (121) illustrated in FIG. 6, but are not limited thereto. In addition, the plurality of second power semiconductor elements (131 to 134) may also have the same structure as the 1-1 power semiconductor element (121) illustrated in FIG. 6, but are not limited thereto.

[0083] Although FIG. 6 illustrates a first-first power semiconductor element (121) of a flip-chip type, each of the first-second power semiconductor elements (122) to the first-fourth power semiconductor elements (124) and the plurality of second power semiconductor elements (131 to 134) may be flip-chip type power semiconductor elements.

[0084] In the 1-1 power semiconductor element (121) illustrated in FIG. 6, the first electrode (121-1) and the second electrode (121-2) may be arranged to face the substrate (110). In this case, the first electrode (121-1) may be electrically connected to the first circuit pattern formation layer (111), and the second electrode (121-2) may be electrically connected to the second circuit pattern formation layer (112). The 1-1 power semiconductor element (121) may be electrically connected to the first circuit pattern formation layer (111) and the second circuit pattern formation layer (112) using a soldering process or a sintering process. The first electrode (121-1) and the second electrode (121-2) of the 1-1 power semiconductor element (121) can be in surface contact with the first circuit pattern forming layer (111) and the second circuit pattern forming layer (112), respectively. As illustrated in FIGS. 2 and 6, the third terminal (143) is disposed on the upper side of the third electrode (121-3) of the 1-1 power semiconductor element (121), and can be in surface contact with the third electrode (121-3) of the 1-1 power semiconductor element (121).

[0085] Meanwhile, a plurality of terminals (141 to 145) may be arranged on the first switching unit (120) and the second switching unit (130). The plurality of terminals (141 to 145) may be electrically connected to the first switching unit (120) and the second switching unit (130). One terminal among the plurality of terminals (141 to 145), i.e., the second terminal (142), may be electrically connected in common with the first switching unit (120) and the second switching unit (130).

[0086] The plurality of terminals (141 to 145) may be made of the same material. The plurality of terminals (141 to 145) may be made of a metal having excellent electrical conductivity, such as copper (Cu), for example. The plurality of terminals (141 to 145) may be formed of a lead frame. In other words, as illustrated in FIG. 7, the plurality of terminals (141 to 145) may be included in an integrated lead frame (1000). As illustrated in FIG. 10, after the plurality of terminals (141 to 145) are connected to the substrate (110), the first switching unit (120), and the second switching unit (130) using the integrated lead frame, the integrated lead frame (1000) may be cut so that the plurality of terminals (141 to 145) may be physically and electrically separated from each other.

[0087] Some of the plurality of terminals (141 to 145), for example, the second terminal (142) and the third terminal (143), may be arranged across the substrate (110) along the X-axis direction. For example, the second terminal (142) may be arranged across the upper sides of the plurality of second power semiconductor elements (131 to 134). For example, the third terminal (143) may be arranged across the upper sides of the plurality of first power semiconductor elements (121 to 124).

[0088] The plurality of terminals (141 to 145) may include a first terminal (141), a second terminal (142), a third terminal (143), a fourth terminal (144), and a fifth terminal (145).

[0089] The first terminal (141) can be connected to the first switching unit (120). The first terminal (141) can be connected to the first electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120). The first terminal (141) can be electrically connected to the first circuit pattern forming layer (111) through the contact area (151). One side of the first circuit pattern forming layer (111) is commonly electrically connected to the first electrodes of the plurality of first power semiconductor elements (121 to 124), and the other side of the first circuit pattern forming layer (111) can be electrically connected to the first terminal (141) through the contact area (151).

[0090] The second terminal (142) may be electrically connected in common to the first switching unit (120) and the second switching unit (130). The second terminal (142) may be electrically connected in common to the second electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) and the third electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130). The second terminal (142) may be electrically connected in common to the second electrodes of the plurality of first power semiconductor elements (121 to 124) and the third electrodes of the plurality of second power semiconductor elements.

[0091] The second terminal (142) can be electrically connected to the second circuit pattern forming layer (112) through contact areas (156 to 159). Although four contact areas (156 to 159) are illustrated in the drawing, fewer or more contact areas may be provided. One side of the second circuit pattern forming layer (112) can be electrically connected in common to the second electrodes of the plurality of first power semiconductor elements (121 to 124), and the other side of the second circuit pattern forming layer (112) can be electrically connected to the second terminal (142) through the plurality of contact areas (156 to 159). The second terminal (142) can be disposed on the upper sides of the plurality of second power semiconductor elements (131 to 134). The second terminal (142) can be electrically connected in common to the third electrodes of the plurality of second power semiconductor elements (131 to 134) through contact areas (191 to 194) across the upper sides of the plurality of second power semiconductor elements (131 to 134).

[0092] The third terminal (143) may be connected to the first switching unit (120). The third terminal (143) may be electrically connected to third electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120). The third terminal (143) may be electrically connected in common to the third electrodes of the plurality of first power semiconductor elements (121 to 124). The third terminal (143) may be disposed on upper sides of the plurality of first power semiconductor elements (121 to 124). The third terminal (143) may be electrically connected in common to the third electrodes of the plurality of first power semiconductor elements (121 to 124) through contact areas (181 to 184) across the upper sides of the plurality of first power semiconductor elements (121 to 124).

[0093] The fourth terminal (144) may be connected to the second switching unit (130). The fourth terminal (144) may be electrically connected to the first electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130). The fourth terminal (144) may be connected to the third circuit pattern forming layer (113) through the contact area (153). One side of the third circuit pattern forming layer (113) may be electrically connected in common to the first electrodes of the plurality of second power semiconductor elements (131 to 134), and the other side of the third circuit pattern forming layer (113) may be electrically connected to the fourth terminal (144) through the contact area (153).

[0094] The fifth terminal (145) can be connected to the second switching unit (130). The fifth terminal (145) can be connected to the second electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130). The fifth terminal (145) can be electrically connected to the fourth circuit pattern forming layer (114) through the contact area (152). One side of the fourth circuit pattern forming layer (114) is commonly electrically connected to the second electrodes of the plurality of second power semiconductor elements (131 to 134), and the other side of the fourth circuit pattern forming layer (114) can be electrically connected to the fifth terminal (145) through the contact area (152).

[0095] The contact regions (151 to 154, 156 to 159, 181 to 184, and 191 to 194) may be regions in which a plurality of terminals (141 to 145) are connected to the substrate (110), the first switching unit (120), and the second switching unit (130). For example, the contact regions (151 to 159, 181 to 184, and 191 to 194) may be formed by connecting the plurality of terminals (141 to 145) to the substrate (110), the first switching unit (120), and the second switching unit (130) using a soldering process or a sintering process.

[0096] A control signal may be supplied through the first terminal (141) and the fourth terminal (144). The control signal may be referred to as a gate signal, a switching signal, a turn on / off control signal, etc. A first power voltage may be supplied through the third terminal (143). A second power voltage may be supplied through the fifth terminal (145). The first power voltage may be higher than the second power voltage, but is not limited thereto. For example, the fifth terminal (145) may be grounded, but is not limited thereto. An output voltage may be output through the second terminal (142).

[0097] The third terminal (143) and the fifth terminal (145) may be input terminals, and the second terminal (142) may be an output terminal.

[0098] As shown in FIG. 3, the third terminal (143) may have a second protruding structure (1430).

[0099] The second uneven structure (1430) may include a first uneven region (1431) positioned on the upper side of each of the third electrodes of the plurality of first power semiconductor elements (121 to 124) and a second uneven region (1432) positioned between the third electrodes. The second uneven structure (1430) may include a third uneven region (1433) connecting the first uneven region (1431) and the second uneven region (1432). In the drawing, the third uneven region (1433) has an inclined shape, but may also have a shape that is perpendicular to the ground or another shape.

[0100] The first uneven region (1431) can be electrically or thermally connected to the upper side of each of the third electrodes of the first power semiconductor elements (121 to 124). Accordingly, the first power voltage provided through the second uneven structure (1430) of the third terminal (143) is directly supplied to the first power semiconductor elements (121 to 124), so that current loss can be reduced. In addition, heat generated in the first power semiconductor elements (121 to 124) can be dissipated to the outside through the second uneven structure (1430) of the third terminal (143), so that heat dissipation performance can be improved.

[0101] The first uneven region (1431) may be positioned lower than the second uneven region (1432). In this case, the second uneven region (1432) may be positioned closer to each of the third electrodes of the plurality of first power semiconductor elements (121 to 124). Accordingly, the second terminal (142) may be more easily connected to the third electrodes of the plurality of first power semiconductor elements (121 to 124) during a soldering process or a sintering process. In addition, the connected second terminal (142) is not detached from the third electrodes of the plurality of first power semiconductor elements (121 to 124). In addition, a space may be formed between the upper side of each of the plurality of first power semiconductor elements (121 to 124) and the second uneven region (1432) around the first uneven region (1431). Accordingly, since the adhesive material is filled in the space during the soldering process or sintering process, the adhesive material does not move onto the side of each of the plurality of first power semiconductor elements (121 to 124), thereby preventing contamination or electrical short-circuit caused by the adhesive material.

[0102] Meanwhile, as shown in FIG. 4, the second terminal (142) may have a first protruding structure (1420).

[0103] The first uneven structure (1420) may include a first uneven region (1421) positioned on the upper side of each of the third electrodes of the plurality of second power semiconductor elements (131 to 134) and a second uneven region (1422) positioned between the third electrodes. The first uneven structure (1420) may include a third uneven region (1423) connecting the first uneven region (1421) and the second uneven region (1422). In the drawing, the third uneven region (1423) has an inclined shape, but may also have a shape that is perpendicular to the ground or another shape.

[0104] The first uneven region (1421) can be electrically or thermally connected to the upper side of each of the third electrodes of the second power semiconductor elements (131 to 134). Accordingly, since the output voltage provided from the third electrodes of the second power semiconductor elements (131 to 134) is directly output through the first uneven structure (1420) of the second terminal (142), current loss can be reduced. In addition, heat generated in the second power semiconductor elements (131 to 134) can be dissipated to the outside through the first uneven structure (1420) of the second terminal (142), so that heat dissipation performance can be improved.

[0105] The first uneven region (1421) may be positioned lower than the second uneven region (1422). In this case, the second uneven region (1422) may be positioned closer to each of the third electrodes of the plurality of second power semiconductor elements (131 to 134). Accordingly, the second terminal (142) may be more easily connected to the third electrodes of the plurality of second power semiconductor elements (131 to 134) during a soldering process or a sintering process. In addition, the connected second terminal (142) is not detached from the third electrodes of the plurality of second power semiconductor elements (131 to 134). In addition, a space may be formed between the upper side of each of the plurality of second power semiconductor elements (131 to 134) and the second uneven region (1422) around the first uneven region (1421). Accordingly, since the adhesive material is filled in the space during the soldering process or sintering process, the adhesive material does not move onto the side of each of the plurality of second power semiconductor elements (131 to 134), thereby preventing contamination or electrical short-circuit caused by the adhesive material.

[0106] Meanwhile, drawing symbols 160 and 170 may be sensing lines. The sensing line (160) may be formed integrally with the third terminal (143), and the sensing line (170) may be connected to the second circuit pattern formation layer (112) through the contact area (154).

[0107] Meanwhile, the power semiconductor module (100) according to the first embodiment may include a molding structure (150). The molding structure (150) may protect the first switching unit (120), the second switching unit (130), etc. The molding structure (150) may surround the substrate (110), the first switching unit (120), and the second switching unit (130). The molding structure (150) may surround a plurality of terminals (141 to 145). In this case, a portion of each of the plurality of terminals (141 to 145) may protrude laterally from the molding structure (150) and be connected to external signal lines.

[0108] Meanwhile, in the past, the gate electrode and source electrode of the power semiconductor device were arranged so that they faced opposite sides of the substrate (110). In this case, each of the gate electrode and source electrode was connected to the substrate using a wire. Therefore, defects such as wire breakage occurred, and as the number of power semiconductor devices increased, there was a problem that the process time and material cost increased.

[0109] However, according to the first embodiment, a plurality of first power semiconductor elements (121 to 124) and a plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) can be electrically connected by a plurality of terminals (141 to 145) formed of a lead frame. Accordingly, since no wire is used, defects such as wire breakage can be prevented.

[0110] In addition, by using an integrated lead frame including a plurality of terminals (141 to 145), the plurality of terminals (141 to 145) can be connected to the substrate (110), the first switching unit (120), and the second switching unit (130), and then the integrated lead frame (1000) is cut so that the plurality of terminals (141 to 145) can be physically and electrically separated from each other. Therefore, the third electrodes of the plurality of first power semiconductor elements (121 to 124) and the plurality of second power semiconductor elements (131 to 134) do not need to be electrically connected to the substrate (110) one by one using a wire bonding process as in the past, so that the process time and material cost can be significantly reduced.

[0111]

[0112] Figures 8 to 10 illustrate a manufacturing process of a power semiconductor module according to the first embodiment.

[0113] As shown in Fig. 8, a substrate (110) including a plurality of circuit pattern forming layers (111 to 114) may be provided.

[0114] As illustrated in FIG. 9, a first switching unit (120) and a second switching unit (130) may be disposed on a substrate (110). For example, the first switching unit (120) and the second switching unit (130) may be electrically connected to the substrate (110) using a soldering process or a sintering process. For example, the first electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) may be electrically connected to the first circuit pattern forming layer (111), and the second electrodes of the plurality of first power semiconductor elements (121 to 124) of the first switching unit (120) may be electrically connected to the second circuit pattern forming layer (112). For example, the first electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) may be electrically connected to the third circuit pattern forming layer (113), and the second electrodes of the plurality of second power semiconductor elements (131 to 134) of the second switching unit (130) may be electrically connected to the fourth circuit pattern forming layer (114).

[0115] The first switching unit (120) and the second switching unit (130) may be connected in series. The first switching unit (120) may include a plurality of first power semiconductor elements (121 to 124) connected in parallel with each other. The second switching unit (130) may include a plurality of second power semiconductor elements (131 to 134) connected in parallel with each other.

[0116] As illustrated in FIG. 10, after the integrated lead frame (1000) is positioned on the substrate (110), a plurality of terminals (141 to 145) of the integrated lead frame (1000) can be connected to the substrate (110), the first switching unit (120), and the second switching unit (130) using a soldering process or a sintering process.

[0117] Thereafter, the integral lead frame (1000) is cut along the cutting line (310), so that the plurality of terminals (141 to 145) can be physically and electrically separated from each other.

[0118]

[0119] [Example 2]

[0120] Fig. 11 is a plan view illustrating a power semiconductor module according to a second embodiment. Fig. 12 is a cross-sectional view of the power semiconductor module of Fig. 11 taken along line D1-D2. Fig. 13 is a cross-sectional view of the power semiconductor module of Fig. 11 taken along line E1-E2. Fig. 14 is a cross-sectional view of the power semiconductor module of Fig. 11 taken along line F1-F2.

[0121] The second embodiment is similar to the first embodiment except for the arrangement of a plurality of first power semiconductor elements (221 to 224) and a plurality of second power semiconductor elements (231 to 234) having a horizontal type structure, and the arrangement between these first and second power semiconductor elements and a plurality of terminals (241 to 245). Detailed descriptions of components having the same structure, shape, and / or function as those of the first embodiment in the second embodiment are omitted.

[0122] Referring to FIGS. 11 to 14, a power semiconductor module (200) according to the second embodiment may include a substrate (210), a first switching unit (220), a second switching unit (230), and a plurality of terminals (241 to 245).

[0123] In Fig. 11, the power semiconductor module (200) according to the second embodiment is shown as being composed of two switching units (220, 230) and five terminals (241 to 245), but it may also be composed of one switching unit and three terminals.

[0124] In FIG. 11, the power semiconductor module (200) according to the second embodiment shows one leg among the plurality of legs (100A, 100B, 100C) shown in FIG. 1, but may include a plurality of legs (100A, 100B, 100C).

[0125] For example, when the power semiconductor module (200) according to the second embodiment includes a first leg (100A), the first switching unit (220) may be a first switching unit (Q1) of the first arm (100a), and the second switching unit may be a second switching unit (Q2) of the second arm (100b). Although not shown, the power semiconductor module (200) according to the second embodiment may include a third switching unit (Q3) and a fourth switching unit (Q4) constituting the second leg (100B), and a fifth switching unit (Q5) and a sixth switching unit (Q6) constituting the third leg (100C).

[0126] Meanwhile, the substrate (210) may be a heat dissipation substrate (210). The substrate (210) may include an insulating layer (215), a metal layer (216), and a plurality of circuit pattern formation layers (211, 212). The plurality of circuit pattern formation layers may be composed of a metal layer (216). For example, the metal layer (216) on the lower surface of the insulating layer (215) may be referred to as a first metal layer, and the plurality of circuit pattern formation layers (211, 212) on the upper surface of the insulating layer (215) may be referred to as a second metal layer. The circuit pattern formation layer may be referred to as a signal pattern, a metal pattern, etc.

[0127] The plurality of circuit pattern formation layers (211, 212) may include a first circuit pattern formation layer (211) and a second circuit pattern formation layer (212).

[0128] As illustrated in Fig. 17, the first circuit pattern formation layer (211) and the second circuit pattern formation layer (212) may be symmetrical with respect to a virtual horizontal line (265). The virtual horizontal line (265) may cross the center of the substrate (210) in the X-axis direction, i.e., in the longitudinal direction of each of the first to fourth circuit pattern formation layers (114).

[0129] Meanwhile, the first switching unit (220) may be referred to as a first power semiconductor element, and the second switching unit (230) may be referred to as a second power semiconductor element. In an embodiment, the first switching unit (220) and the first power semiconductor element may be used interchangeably, and the second switching unit (230) and the second power semiconductor element may be used interchangeably.

[0130] For example, the first switching unit (220) may be disposed on the first circuit pattern forming layer (211), and the second switching unit (230) may be disposed on the second circuit pattern forming layer (212). For example, the third electrodes (221-3) of the plurality of first power semiconductor elements (221 to 224) of the first switching unit (220) may be electrically connected to the first circuit pattern forming layer (211), and the third electrodes (221-3) of the plurality of second power semiconductor elements (231 to 234) of the second switching unit (230) may be electrically connected to the second circuit pattern forming layer (212).

[0131] The first switching unit (220) and the second switching unit (230) have been described in the first embodiment (Figs. 2 to 6), so a detailed description thereof is omitted.

[0132] The first switching unit (220) may include a plurality of first power semiconductor elements (221 to 224). Although four first power semiconductor elements (221 to 224) are illustrated in the drawing, more first power semiconductor elements may be provided. The second switching unit (230) may include a plurality of second power semiconductor elements (231 to 234). Although four second power semiconductor elements (231 to 234) are illustrated in the drawing, more second power semiconductor elements may be provided. The first power semiconductor elements (221 to 224) and the second power semiconductor elements (231 to 234) may each be made of SiC, GaN, or the like.

[0133] Among the plurality of first power semiconductor elements (221 to 224), the 2-1 power semiconductor element (221) is illustrated in FIG. 15, but the 2-2 power semiconductor elements (222) to the 2-4 power semiconductor elements (224) may also have the same structure as the 2-1 power semiconductor element (221) illustrated in FIG. 15, but are not limited thereto. In addition, the plurality of second power semiconductor elements (231 to 234) may also have the same structure as the 2-1 power semiconductor element (221) illustrated in FIG. 15, but are not limited thereto.

[0134] Although FIG. 15 illustrates a 2-1 power semiconductor element (221) having a horizontal type structure, the 2-2 power semiconductor element (222) to the 2-4 power semiconductor element (224) and the plurality of second power semiconductor elements (231 to 234) may each be horizontal type power semiconductor elements.

[0135] In the 2-1 power semiconductor element (221) illustrated in FIG. 15, the first electrode (221-1) and the second electrode (121-2) may be arranged to face opposite sides of the substrate (210). In this case, the third electrode (221-3) of the 2-1 power semiconductor element (221) may be electrically connected to the first circuit pattern formation layer (211). The 2-1 power semiconductor element (221) may be electrically connected to the first circuit pattern formation layer (211) of the substrate (210) using a soldering process or a sintering process. The third electrode (221-3) of the 2-1 power semiconductor element (221) may be in surface contact with the first circuit pattern formation layer (211) of the substrate (210). As illustrated in FIG. 11 and FIG. 15, the first terminal (241) is disposed on the upper side of the first electrode (221-1) of the 2-1 power semiconductor element (221), and can be in surface contact with the first electrode (221-1) of the 2-1 power semiconductor element (221). The third terminal (243) is disposed on the upper side of the second electrode (221-2) of the 2-1 power semiconductor element (221), and can be in surface contact with the second electrode (221-2) of the 2-1 power semiconductor element (221).

[0136] Meanwhile, a plurality of terminals (241 to 245) may be arranged on the first switching unit (220) and the second switching unit (230). The plurality of terminals (241 to 245) may be electrically connected to the first switching unit (220) and the second switching unit (230). One terminal among the plurality of terminals (241 to 245), i.e., the second terminal (242), may be commonly connected to the first switching unit (220) and the second switching unit (230).

[0137] The plurality of terminals (241 to 245) may be made of the same material. The plurality of terminals (241 to 245) may be made of a metal having excellent electrical conductivity, such as copper (Cu), for example. The plurality of terminals (241 to 245) may be formed of a lead frame. In other words, as illustrated in FIG. 16, the plurality of terminals (241 to 245) may be included in an integrated lead frame (2000). As illustrated in FIG. 19, after the plurality of terminals (241 to 245) are connected to the substrate (210), the first switching unit (220), and the second switching unit (230) using the integrated lead frame, the integrated lead frame (2000) may be cut so that the plurality of terminals (241 to 245) may be physically and electrically separated from each other.

[0138] Some of the terminals (241 to 245), for example, the first terminal (241), the second terminal (242), the fourth terminal (244), and the fifth terminal (245), may be arranged across the substrate (210) along the X-axis direction.

[0139] The plurality of terminals (241 to 245) may include a first terminal (241), a second terminal (242), a third terminal (243), a fourth terminal (244), and a fifth terminal (245).

[0140] The first terminal (241) may be connected to the first switching unit (220). The first terminal (241) may be connected to the first electrodes (221-1) of the plurality of first power semiconductor elements (221 to 224) of the first switching unit (220). The first terminal (241) may be arranged across the first circuit pattern forming layer (211) along the X-axis direction. The first terminal (241) may be commonly electrically connected to the first electrodes (221-1) of the plurality of first power semiconductor elements (221 to 224) through contact areas (281 to 284) on the first circuit pattern forming layer (211). Although four contact areas (281 to 284) are illustrated in the drawing, fewer or more contact areas may be provided.

[0141] The second terminal (242) may be commonly connected to the first switching unit (220) and the second switching unit (230). The second terminal (242) may be commonly connected to the second electrodes of the plurality of first power semiconductor elements (221 to 224) of the first switching unit (220) and the third electrodes (221-3) of the plurality of second power semiconductor elements (231 to 234) of the second switching unit (230). The second terminal (242) may be disposed on the upper sides of the plurality of first power semiconductor elements (221 to 224). The second terminal (242) may be commonly electrically connected to the second electrodes of the plurality of first power semiconductor elements (221 to 224) through the contact areas (285 to 288) across the upper sides of the plurality of first power semiconductor elements (221 to 224).

[0142] The second terminal (242) can be electrically connected to the second circuit pattern formation layer (212) of the substrate (210) through contact areas (256 to 258). One side of the second circuit pattern formation layer (212) is electrically connected to the second terminal (242) through contact areas (256 to 258), and the other side of the second circuit pattern formation layer (212) can be electrically connected to third electrodes (221-3) of a plurality of second power semiconductor elements (231 to 234). Although three contact areas (156 to 159) are illustrated in the drawing, fewer or more contact areas may be provided.

[0143] The third terminal (243) can be connected to the first switching unit (220). The third terminal (243) can be connected to the third electrodes (221-3) of the plurality of first power semiconductor elements (221 to 224) of the first switching unit (220). The third terminal (243) can be electrically connected to the first circuit pattern forming layer (211) of the substrate (210) through the contact area (251). One side of the first circuit pattern forming layer (211) is electrically connected in common to the third electrodes (221-3) of the plurality of first power semiconductor elements (221 to 224), and the other side of the first circuit pattern forming layer (211) can be electrically connected to the third terminal (243) through the contact area (251).

[0144] The fourth terminal (244) may be connected to the second switching unit (230). The fourth terminal (244) may be connected to the first electrodes (221-1) of the plurality of second power semiconductor elements (231 to 234) of the second switching unit (230). The second terminal (242) may be arranged across the second circuit pattern forming layer (212) along the X-axis direction. The fourth terminal (244) may be commonly electrically connected to the second electrodes of the plurality of second power semiconductor elements (231 to 234) through contact areas (291 to 294) on the second circuit pattern forming layer (212). Although four contact areas (291 to 294) are illustrated in the drawing, fewer or more contact areas may be provided.

[0145] The fifth terminal (245) can be connected to the second switching unit (230). The fifth terminal (245) can be arranged on the upper side of the plurality of second power semiconductor elements (231 to 234). The fifth terminal (245) can be electrically connected in common to the second electrodes of the plurality of second power semiconductor elements (231 to 234) through contact areas (295 to 298) across the upper sides of the plurality of second power semiconductor elements (231 to 234).

[0146] The contact areas (251, 252, 256 to 258, 281 to 288, 291 to 298) may be areas where a plurality of terminals (241 to 245) are connected to the substrate (210), the first switching unit (220), and the second switching unit (230). For example, the contact areas (251, 252, 256 to 258, 281 to 288, 291 to 298) may be formed by connecting the plurality of terminals (241 to 245) to the substrate (210), the first switching unit (220), and the second switching unit (230) using a soldering process or a sintering process.

[0147] A control signal may be supplied through the first terminal (241) and the fourth terminal (244). The control signal may be referred to as a gate signal, a switching signal, a turn on / off control signal, etc. A first power voltage may be supplied through the third terminal (243). A first power voltage may be supplied through the fifth terminal (245). The first power voltage may be higher than the second power voltage, but is not limited thereto. For example, the third terminal (243) may be grounded, but is not limited thereto. An output voltage may be output through the second terminal (242).

[0148] The third terminal (243) and the fifth terminal (245) may be input terminals, and the second terminal (242) may be an output terminal.

[0149] Meanwhile, as shown in FIG. 12, the second terminal (242) may have a first protruding structure (2420).

[0150] The first concave-convex structure (2420) may include a first concave-convex region (2421) positioned on the upper side of each of the second electrodes of the plurality of first power semiconductor elements (221 to 224) and a second concave-convex region (2422) positioned between the second electrodes. The first concave-convex structure (2420) may include a third concave-convex region (1423) connecting the first concave-convex region (2421) and the second concave-convex region (2422). In the drawing, the third concave-convex region (1423) has an inclined shape, but may also have a shape that is perpendicular to the ground or another shape.

[0151] The first uneven region (2421) can be electrically or thermally connected to the upper side of each of the second electrodes of the first power semiconductor elements (221 to 224). Accordingly, since the output voltage provided from the second electrodes of the first power semiconductor elements (221 to 224) is directly output through the first uneven structure (2420) of the second terminal (242), current loss can be reduced. In addition, heat generated in the first power semiconductor elements (221 to 224) can be dissipated to the outside through the first uneven structure (2420) of the second terminal (142), so that heat dissipation performance can be improved.

[0152] The first uneven region (2421) may be positioned lower than the second uneven region (2422). In this case, the second uneven region (2422) may be positioned closer to each of the second electrodes of the plurality of first power semiconductor elements (221 to 224). Accordingly, the second terminal (242) may be more easily connected to the second electrodes of the plurality of first power semiconductor elements (221 to 224) during a soldering process or a sintering process. In addition, the connected second terminal (242) is not detached from the second electrodes of the plurality of first power semiconductor elements (221 to 224). In addition, a space may be formed between the upper side of each of the plurality of first power semiconductor elements (221 to 224) and the second uneven region (2422) around the first uneven region (2421). Accordingly, since the adhesive material is filled in the space during the soldering process or sintering process, the adhesive material does not move onto the side of each of the plurality of first power semiconductor elements (221 to 224), thereby preventing contamination or electrical short-circuit caused by the adhesive material.

[0153] As illustrated in FIG. 13, the fifth terminal (245) may have a second protruding structure (2450).

[0154] The second uneven structure (2450) may include a first uneven region (2451) positioned on the upper side of each of the second electrodes of the plurality of second power semiconductor elements (231 to 234) and a second uneven region (2452) positioned between the second electrodes. The second uneven structure (2450) may include a third uneven region (1453) connecting the first uneven region (2451) and the second uneven region (2452). In the drawing, the third uneven region (1453) has an inclined shape, but may also have a shape that is perpendicular to the ground or another shape.

[0155] The first uneven region (2451) can be electrically or thermally connected to the upper side of each of the second electrodes of the second power semiconductor elements (231 to 234). Accordingly, the first power voltage provided through the second uneven structure (2450) of the fifth terminal (245) is directly supplied to the second power semiconductor elements (231 to 234), so that current loss can be reduced. In addition, heat generated in the second power semiconductor elements (231 to 234) can be dissipated to the outside through the second uneven structure (2450) of the fifth terminal (245), so that heat dissipation performance can be improved.

[0156] The first uneven region (2451) may be positioned lower than the second uneven region (2452). In this case, the second uneven region (2452) may be positioned closer to each of the second electrodes of the plurality of second power semiconductor elements (231 to 234). Accordingly, the second terminal (242) may be more easily connected to the second electrodes of the plurality of second power semiconductor elements (231 to 234) during a soldering process or a sintering process. In addition, the connected second terminal (242) is not detached from the second electrodes of the plurality of second power semiconductor elements (231 to 234). In addition, a space may be formed between the upper side of each of the plurality of second power semiconductor elements (231 to 234) and the second uneven region (2452) around the first uneven region (2451). Accordingly, since the adhesive material is filled in the space during the soldering process or sintering process, the adhesive material does not move onto the side of each of the plurality of second power semiconductor elements (231 to 234), thereby preventing contamination or electrical short-circuit caused by the adhesive material.

[0157] Meanwhile, drawing symbols 260 and 270 may be sensing lines. The sensing line (260) may be formed integrally with the second terminal (242), and the sensing line (270) may be electrically connected to the first circuit pattern formation layer (211) through the contact area (252).

[0158] Meanwhile, the power semiconductor module (200) according to the second embodiment may include a molding structure (250). The molding structure (250) may surround the substrate (210), the first switching unit (220), and the second switching unit (230). The molding structure (250) may surround a plurality of terminals (241 to 245). In this case, a portion of each of the plurality of terminals (241 to 245) may protrude laterally from the molding structure (250) and be electrically connected to external signal lines.

[0159] Meanwhile, in the past, the gate electrode and the source electrode of the power semiconductor device were arranged so that the gate electrode and the source electrode of the power semiconductor device faced opposite sides of the substrate (210), and each of them was connected to the substrate (210) using a wire. Therefore, there was a problem that defects such as wire breakage occurred, and as the number of power semiconductor devices increased, the process time and material costs increased.

[0160] However, according to the second embodiment, a plurality of first power semiconductor elements (221 to 224) and a plurality of second power semiconductor elements (231 to 234) of the second switching unit (230) can be electrically connected by a plurality of terminals (241 to 245) formed of a lead frame. Accordingly, since no wires are used, defects such as wire breakage can be prevented.

[0161] In addition, by using an integrated lead frame including a plurality of terminals (241 to 245), the plurality of terminals (241 to 245) can be connected to the substrate (210), the first switching unit (220), and the second switching unit (230), and then the integrated lead frame (2000) can be cut so that the plurality of terminals (241 to 245) can be physically and electrically separated from each other. Therefore, the third electrodes (221-3) of the plurality of first power semiconductor elements (221 to 224) and the plurality of second power semiconductor elements (231 to 234) do not need to be electrically connected to the substrate (210) one by one using a wire bonding process as in the past, so that the process time and material cost can be significantly reduced.

[0162]

[0163] Figures 17 to 19 illustrate a manufacturing process of a power semiconductor module according to the second embodiment.

[0164] As illustrated in Fig. 17, a substrate (210) including a plurality of circuit pattern forming layers (211, 212) may be provided.

[0165] As illustrated in FIG. 18, a first switching unit (220) and a second switching unit (230) may be disposed on a substrate (210). For example, the first switching unit (220) and the second switching unit (230) may be electrically connected to the substrate (210) using a soldering process or a sintering process. The first switching unit (220) and the second switching unit (230) may be connected in series through a second terminal (242). The first switching unit (220) and the second switching unit (230) may include a plurality of first power semiconductor elements (221 to 224) connected in parallel with each other. The second switching unit (230) may include a plurality of second power semiconductor elements (231 to 234) connected in parallel with each other.

[0166] As illustrated in FIG. 19, after the integrated lead frame (2000) is positioned on the substrate (210), a plurality of terminals (241 to 245) of the integrated lead frame (2000) can be connected to the substrate (210), the first switching unit (220), and the second switching unit (230) using a soldering process or a sintering process.

[0167] Thereafter, the integral lead frame (2000) is cut along the cutting line (310), so that the plurality of terminals (241 to 245) can be physically and electrically separated from each other.

[0168]

[0169] The above detailed description should not be construed as limiting in any respect and should be considered illustrative only. The scope of the embodiments should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalency range of the embodiments are intended to be included within the scope of the embodiments.

Claims

1. Substrate; A plurality of power semiconductor elements arranged on the substrate; A first terminal electrically connected to first electrodes of the plurality of power semiconductor elements; a second terminal electrically connected to the second electrodes of the plurality of power semiconductor elements; and A third terminal electrically connected to the third electrodes of the plurality of power semiconductor elements; At least one terminal among the first to third terminals is electrically connected in common to the upper sides of the plurality of power semiconductor elements across the upper sides of the plurality of power semiconductor elements. Power semiconductor modules.

2. In paragraph 1, The first to third terminals are each composed of a lead frame. Power semiconductor modules.

3. In paragraph 1, The first electrodes and the second electrodes are arranged so as to face the substrate, The third terminal is connected in common to the third electrodes of the plurality of power semiconductor elements across the third electrodes of the plurality of power semiconductor elements. Power semiconductor modules.

4. In paragraph 3, The above third terminal has a rough structure, The above rough structure is, a first concave region positioned on the upper side of each of the third electrodes; and a second concave region positioned between the third electrodes; The above first uneven region is positioned lower than the above second uneven region, The above first concave region is electrically or thermally connected to the upper side of each of the third electrodes, Power semiconductor modules.

5. In paragraph 3, The above substrate is, First circuit pattern forming layer; and A second circuit pattern forming layer is disposed so as to be spaced apart from the first circuit pattern forming layer; The above plurality of power semiconductor elements are arranged on the first circuit pattern forming layer and the second circuit pattern forming layer. Power semiconductor modules.

6. In paragraph 5, One side of the first circuit pattern forming layer is electrically connected in common to the first electrodes, and the other side of the first circuit pattern forming layer is electrically connected to the first terminal. One side of the second circuit pattern forming layer is electrically connected in common to the second electrodes, and the other side of the second circuit pattern forming layer is electrically connected to the second terminal. Power semiconductor modules.

7. In paragraph 1, The first electrodes and the second electrodes are arranged so as to face opposite sides of the substrate, The above first terminal is electrically connected in common to the above first electrodes, The second terminal is electrically connected in common to the second electrodes across the upper sides of the plurality of power semiconductor elements. Power semiconductor modules.

8. In paragraph 7, The above second terminal has a rough structure, The above rough structure is, a first concave region positioned on the upper side of each of the second electrodes; and a second concave region positioned between the second electrodes; The above first uneven region is positioned lower than the above second uneven region, The above first concave region is electrically or thermally connected to the upper side of each of the third electrodes, Power semiconductor modules.

9. In paragraph 7, The above substrate includes a circuit pattern forming layer, The above plurality of power semiconductor devices are arranged on the circuit pattern forming layer. Power semiconductor modules.

10. In paragraph 9, One side of the circuit pattern formation layer is electrically connected in common to the third electrodes of the plurality of power semiconductor elements, and the other side of the circuit pattern formation layer is electrically connected to the third terminal. Power semiconductor modules.

11. In paragraph 1, The above first to third terminals are made of the same material. Power semiconductor modules.

12. Contains multiple power semiconductor modules for converting power, The above power semiconductor module, substrate; A plurality of power semiconductor elements arranged on the substrate; A first terminal electrically connected to first electrodes of the plurality of power semiconductor elements; a second terminal electrically connected to the second electrodes of the plurality of power semiconductor elements; and A third terminal electrically connected to the third electrodes of the plurality of power semiconductor elements; At least one terminal among the first to third terminals is electrically connected in common to the upper sides of the plurality of power semiconductor elements across the upper sides of the plurality of power semiconductor elements. Power conversion device.

13. In paragraph 12, The first electrodes and the second electrodes are arranged so as to face the substrate, The third terminal is connected in common to the third electrodes of the plurality of power semiconductor elements across the third electrodes of the plurality of power semiconductor elements. Power conversion device.

14. In paragraph 13, The above third terminal has a rough structure, The above rough structure is, a first concave region positioned on the upper side of each of the third electrodes; and a second concave region positioned between the third electrodes; The above first uneven region is positioned lower than the above second uneven region, The above first concave region is electrically or thermally connected to the upper side of each of the third electrodes, Power conversion device.

15. In paragraph 13, The above substrate is, First circuit pattern forming layer; and A second circuit pattern forming layer is disposed so as to be spaced apart from the first circuit pattern forming layer; The above plurality of power semiconductor elements are arranged on the first circuit pattern forming layer and the second circuit pattern forming layer. Power conversion device.

16. In paragraph 15, One side of the first circuit pattern forming layer is electrically connected in common to the first electrodes, and the other side of the first circuit pattern forming layer is electrically connected to the first terminal. One side of the second circuit pattern forming layer is electrically connected in common to the second electrodes, and the other side of the second circuit pattern forming layer is electrically connected to the second terminal. Power conversion device.

17. In paragraph 12, The first electrodes and the second electrodes are arranged so as to face opposite sides of the substrate, The above first terminal is electrically connected in common to the above first electrodes, The second terminal is electrically connected in common to the second electrodes across the upper sides of the plurality of power semiconductor elements. Power conversion device.

18. In paragraph 17, The above second terminal has a rough structure, The above rough structure is, a first concave region positioned on the upper side of each of the second electrodes; and a second concave region positioned between the second electrodes; The above first uneven region is positioned lower than the above second uneven region, The above first concave region is electrically or thermally connected to the upper side of each of the third electrodes, Power conversion device.

19. In Article 17, The above substrate includes a circuit pattern forming layer, The above plurality of power semiconductor devices are arranged on the circuit pattern forming layer. Power conversion device.

20. In paragraph 19, One side of the circuit pattern formation layer is electrically connected in common to the third electrodes of the plurality of power semiconductor elements, and the other side of the circuit pattern formation layer is electrically connected to the third terminal. Power conversion device.

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