Three-dimensional flash memory structured to increase channel current

Abstract

The present invention relates to a three-dimensional flash memory structured to increase channel current. Particularly, presented is a three-dimensional flash memory comprising: word lines extended in the horizontal direction on a substrate, and stacked to be spaced apart from each other in the vertical direction; and vertical channel structures that pass through the word lines and extend in the vertical direction on the substrate, wherein a composite vertical channel pattern includes vertical channel patterns and a conductive film interposed between the vertical channel patterns, and thus the area through which a channel current flows is increased and a channel current value itself is also increased, thereby enabling the technical effects of improved channel current characteristics, and both improved leakage current characteristics and enhanced mobility related to the channel current to be achieved.

Description

3D flash memory with a structure that increases channel current

[0001] The following examples describe a technology for a three-dimensional flash memory having a structure that increases channel current.

[0002] Flash memory devices are electrically erasable programmable read-only memories (EEPROM) that control the input and output of data electrically by Fowler-Nordheimtunneling or hot electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In order to meet the high performance and low price demands of consumers, it is necessary to increase the integration density in these flash memory devices, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a memory cell string has been proposed.

[0004] In addition, in order to improve leakage current characteristics in 3D flash memory, a structure using oxide semiconductor materials that have undergone a heat treatment process to implement semiconductor characteristics as a vertical channel pattern has been proposed.

[0005] In such 3D flash memory, the main issue is the increase in channel current as the vertical direction increases.

[0006] Accordingly, a three-dimensional flash memory having a structure that increases channel current by increasing mobility related to channel current is described through the embodiments below.

[0007]

[0008] One embodiment proposes a three-dimensional flash memory having a structure of a composite vertical channel pattern including vertical channel patterns and a conductive film interposed between the vertical channel patterns to improve channel current characteristics.

[0009] In addition, one embodiment proposes a three-dimensional flash memory having a structure of a composite vertical channel pattern including a first vertical channel pattern formed of a silicon-based material, a second vertical channel pattern formed of an oxide semiconductor material, and an interface oxide film interposed between the first vertical channel pattern and the second vertical channel pattern, in order to improve leakage current characteristics while increasing mobility related to channel current.

[0010] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0011] According to one embodiment, a three-dimensional flash memory may include word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in the vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed to contact an outer wall of the composite vertical channel pattern, the data storage pattern and the composite vertical channel pattern forming memory cells corresponding to the word lines, and the composite vertical channel pattern may be characterized in that it includes a conductive film interposed between the vertical channel patterns and the vertical channel patterns.

[0012] According to one aspect, the conductive film may be characterized as being used for the purpose of increasing a current flowing in the composite vertical channel pattern.

[0013] According to another aspect, the conductive film may be formed to a thickness that satisfies conditions for being turned on and off by an electric field caused by a voltage applied to the word lines.

[0014] According to another aspect, the conductive film may be characterized in that it is formed of a material having a carrier concentration higher than that of the vertical channel patterns.

[0015] According to another aspect, the conductive film may be characterized as being used for the purpose of preventing ions from moving between the vertical channel patterns formed of different semiconductor materials.

[0016] According to another aspect, the vertical channel patterns may be formed of materials having different electron mobilities, each of which supplies electrons to the memory cells.

[0017] According to another aspect, one of the vertical channel patterns may be formed of a material that supplies holes to the memory cells, and the remaining one of the vertical channel patterns, excluding the one of the vertical channel patterns, may be formed of a material that supplies electrons to the memory cells.

[0018] According to another aspect, one of the vertical channel patterns may be formed of a material that supplies holes and electrons to the memory cells, and the remaining one of the vertical channel patterns, excluding the one of the vertical channel patterns, may be formed of a material that supplies electrons to the memory cells.

[0019] According to one embodiment, a method for manufacturing a three-dimensional flash memory, comprising: word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in a vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed to contact an outer wall of the composite vertical channel pattern, the data storage pattern and the composite vertical channel pattern forming memory cells corresponding to the word lines, and the composite vertical channel pattern including the vertical channel patterns and a conductive film interposed between the vertical channel patterns; may include a step of forming the composite vertical channel pattern with the vertical channel patterns and the conductive film interposed between the vertical channel patterns.

[0020] According to one aspect, the step of forming the composite vertical channel pattern includes: forming one of the vertical channel patterns on an inner wall of the data storage pattern; forming the conductive film on an inner wall of the one of the vertical channel patterns; and forming one of the vertical channel patterns other than the one of the vertical channel patterns on an inner wall of the conductive film, wherein the step of forming the conductive film may be characterized as a step of forming the conductive film used for the purpose of increasing a current flowing in the composite vertical channel pattern.

[0021] According to one embodiment, a three-dimensional flash memory may include word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in the vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed to contact an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines, wherein the composite vertical channel pattern includes a first vertical channel pattern formed of a silicon-based material, a second vertical channel pattern formed of an oxide semiconductor material, and an interface oxide film interposed between the first vertical channel pattern and the second vertical channel pattern.

[0022] According to one aspect, the interfacial oxide film may be formed by absorbing oxygen in the oxide semiconductor material during a heat treatment process of the oxide semiconductor material, thereby increasing the oxygen vacancy of the second vertical channel pattern.

[0023] According to another aspect, the oxide semiconductor material may be characterized by including a material having lower oxygen affinity than the silicon series material.

[0024] According to another aspect, the concentration of the silicon series material may be determined and controlled so as to absorb oxygen within the oxide semiconductor material during the process of forming the interfacial oxide film.

[0025] According to another aspect, the interfacial oxide film may be characterized by increasing the mobility of the second vertical channel pattern by increasing the oxygen vacancies of the second vertical channel pattern.

[0026] One embodiment proposes a three-dimensional flash memory having a structure of a composite vertical channel pattern including vertical channel patterns and a conductive film interposed between the vertical channel patterns, thereby achieving a technical effect of improving channel current characteristics by increasing the area through which channel current flows while simultaneously increasing the channel current value itself.

[0027] In addition, one embodiment proposes a three-dimensional flash memory having a structure of a composite vertical channel pattern including a first vertical channel pattern formed of a silicon-based material, a second vertical channel pattern formed of an oxide semiconductor material, and an interface oxide film interposed between the first vertical channel pattern and the second vertical channel pattern, thereby achieving a technical effect of improving leakage current characteristics while increasing mobility related to channel current.

[0028] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0029] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0030] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to one embodiment.

[0031] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0032] FIG. 4 is a cross-sectional view showing an enlarged area of ​​a complex vertical channel pattern to explain a complex vertical channel pattern of a three-dimensional flash memory according to one embodiment.

[0033] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0034] FIG. 6 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

[0035] FIG. 7 is a cross-sectional view illustrating the structure of a three-dimensional flash memory to explain the function of an interface oxide film included in a composite vertical channel pattern according to one embodiment.

[0036] FIG. 8 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0037] FIG. 9 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0039] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents of this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used in this specification do not exclude the presence or addition of one or more other components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0040] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0041] Hereinafter, with reference to the drawings, a three-dimensional flash memory and a manufacturing method thereof that improve channel current characteristics by increasing the area through which channel current flows while simultaneously increasing the channel current value itself are described in detail.

[0042]

[0043] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to embodiments.

[0044] Referring to FIG. 1, an array of a three-dimensional flash memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

[0045] The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0046] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be commonly connected to the common source line (CSL) provided between the bit lines (BL0, BL1, BL2) and one common source line (CSL). At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may be two-dimensionally arranged while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). The plurality of common source lines (CSL) may be electrically identically voltage-applied, but the present invention is not limited thereto, and each of the plurality of common source lines (CSL) may be electrically independently controlled so that different voltages may be applied.

[0047] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) disposed between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

[0048] For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, the present invention is not limited thereto, and each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0049] A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from common source lines (CSL). That is, the memory cell transistors (MCT) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT).

[0050] According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) can be commonly connected to the sources of erase control transistors (ECT).

[0051] The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be independently controlled.

[0052] Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along a first direction (D1), are spaced apart from each other in a second direction (D2) and can be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3) and second string selection lines (SSL2-1, SSL2-2, SSL2-3) provided at substantially the same level from common source lines (CSL) can be electrically isolated from each other. In addition, erase control transistors (ECT) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate gate-induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and / or the common source lines (CSL) during an erase operation of the memory cell array, and gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0053] The string selection line (SSL) described above may be represented as an upper selection line (USL), and the ground selection line (GSL) may be represented as a lower selection line.

[0054]

[0055] FIG. 2 is a plan view illustrating a structure of a three-dimensional flash memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIG. 4 is a cross-sectional view illustrating an enlarged area of ​​a complex vertical channel pattern to explain a complex vertical channel pattern of a three-dimensional flash memory according to one embodiment.

[0056] Referring to the drawings, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0057] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0058] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0059] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

[0060] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0061] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0062] Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the longest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0063] Each of the interlayer insulating layers (ILDs) may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than the other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating layers (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0064] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) may be stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0065] A plurality of channel holes (CH) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0066] The rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as illustrated in FIG. 2, twelve vertical channel structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical channel structures (VS) forming the array is not limited or restricted thereto.

[0067] As vertical channel structures (VS) are formed in a plate shape, the array is formed in a horizontal plane of multiple rows and columns of gate electrodes (EL1, EL2, EL3), so that the three-dimensional flash memory can have a structure in which the integration of memory cell strings is improved.

[0068] At this time, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on a horizontal plane and to be misaligned with each other. For example, the vertical channel structures (VS) included in a first column may be arranged in the first and third rows, and the vertical channel structures (VS) included in a second column may be arranged in the second and fourth rows, such that the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string can be further improved compared to the case where the vertical channel structures (VS) included in a pair of adjacent columns are arranged side by side in the same row on a horizontal plane.

[0069] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0070] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a composite vertical channel pattern (CVCP), a vertical filling pattern (VFP), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the composite vertical channel pattern (CVCP) may have a pipe shape or a macaroni shape with an open bottom, and the vertical filling pattern (VFP) may have a shape that fills an inner space of the composite vertical channel pattern (CVCP). However, without being limited thereto, the composite vertical channel pattern (CVCP) may also have a pipe shape or a macaroni shape with a closed bottom.

[0071] The data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the composite vertical channel pattern (CVCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. Accordingly, regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) may form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2) together with regions corresponding to the second gate electrodes (EL2) of the composite vertical channel pattern (CVCP). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0072] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by a voltage applied through the second gate electrodes (EL2), or by maintaining the state of electrons (e.g., the polarization state of charges). For example, an ONO (tunnel oxide-nitride-blocking oxide) layer or a ferroelectric layer can be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent a binary data value or a multi-valued data value by a change in the trapped charge or hole, or can represent a binary data value or a multi-valued data value by a change in the state of charges.

[0073] Although the above data storage pattern (DSP) is described as being vertically connected and extended, it is not limited to this and may be segmented into multiple pieces and formed only in the portion corresponding to the second gate electrodes (EL), thereby forming memory cells together with the regions corresponding to the second gate electrodes (EL2) among the composite vertical channel pattern (CVCP).

[0074] A composite vertical channel pattern (CVCP) is a component that supplies electrons or holes to transfer charges to a data storage pattern (DSP). The composite vertical channel pattern (CVCP) may be formed to extend in a vertical direction (e.g., a third direction (D3)) while covering an inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage. More specifically, the composite vertical channel pattern (CVCP) may be composed of a plurality of vertical channel patterns (VCP1, VCP2) and a conductive film (CD) interposed between the vertical channel patterns (VCP1, VCP2). Accordingly, the composite vertical channel pattern (CVCP) may have a structure that increases the area itself through which a channel current flows.

[0075] Hereinafter, the composite vertical channel pattern (CVCP) is described as including two vertical channel patterns (VCP1, VCP2), but is not limited thereto and may include three or more vertical channel patterns. In this case, two conductive films (CDs) may be respectively arranged in two spaces between the three or more vertical channel patterns.

[0076] A conductive film (CD) can be used to increase the current flowing in a composite vertical channel pattern (CVCP) based on the characteristic that the carrier concentration is higher than that of the vertical channel patterns (VCP1, VCP2). For this purpose, the conductive film (CD) is made of a material (e.g., In) having the characteristic that the carrier concentration is higher than that of the vertical channel patterns (VCP1, VCP2). x O y , SnO x or ZnO x (a conductive material including at least one of the above). That is, the conductive film (CD) can be formed of a material having a carrier concentration higher than that of the vertical channel patterns (VCP1, VCP2), thereby increasing the channel current value itself.

[0077] At this time, since the conductive film (CD) must be turned on or off as needed during the memory operation of the 3D flash memory, it can be formed to a thickness (e.g., 1 nm to 3 nm) that satisfies the condition of being able to be turned on and off by an electric field due to a voltage applied to word lines (WLs) during the memory operation of the 3D flash memory.

[0078] The vertical channel patterns (VCP1, VCP2) can be formed of different semiconductor materials.

[0079] For example, one of the vertical channel patterns (VCP1, VCP2) (e.g., the first vertical channel pattern (VCP1) formed in contact with the data storage pattern (DSP)) may be formed of a material that supplies holes to memory cells, and the other of the vertical channel patterns (VCP1, VCP2) (e.g., the second vertical channel pattern (VCP2)) may be formed of a material that supplies electrons to the memory cells. For a more specific example, one of the vertical channel patterns (VCP1) may be formed of a material that supplies holes to the memory cells, and thus may be used as a channel in a hole injection-based erase operation of a three-dimensional flash memory, and the other of the vertical channel patterns (VCP2) may be formed of a material that supplies electrons to the memory cells, and thus may be used as a channel in a program operation or a read operation of the three-dimensional flash memory.

[0080] In this case, the second vertical channel pattern (VCP2) may be formed of a material having a different band gap from the first vertical channel pattern (VCP1) or a material that does not include holes. For example, while the first vertical channel pattern (VCP1) is formed of at least one material among polysilicon or a silicon crystal material, the second vertical channel pattern (VCP2) may be formed of an oxide semiconductor material including at least one metal ion among In, Ga, Zn, Sn, Ni, Cu, Al, or Sr, so that the second vertical channel pattern (VCP2) may have a wider band gap than the first vertical channel pattern (VCP1). For another example, the first vertical channel pattern (VCP1) is formed of at least one material among polysilicon or silicon crystal materials, while the second vertical channel pattern (VCP2) is formed of a compound semiconductor material including at least one among GaAs, InP, ZnO, SiC, or SiGe, so that the second vertical channel pattern (VCP2) can have a narrower band gap than the first vertical channel pattern (VCP1).

[0081] As described, in order for only the second vertical channel pattern (VCP2) to supply electrons to the memory cells in the memory operation, it is desirable to have a condition in which the first vertical channel pattern (VCP1) does not supply electrons to the memory cells.

[0082] In this regard, a situation occurs where current does not flow due to surface scattering within a range of 1 nm from the interface of the data storage pattern (DSP). The first vertical channel pattern (VCP1) is formed with a thickness within a range of 1 nm from the interface of the data storage pattern (DSP) to utilize this principle, so that electrons may not be supplied to the memory cells (current does not flow) during a program operation or a read operation. That is, the first vertical channel pattern (VCP1) may be formed in contact with the data storage pattern (DSP) to a thickness less than or equal to a preset thickness that causes surface scattering. For example, the first vertical channel pattern (VCP1) may be formed with a thickness of 1 nm or less, so that it is included within a range of 1 nm from the interface of the data storage pattern (DSP), so that current does not flow due to surface scattering.

[0083] The formation thickness of the second vertical channel pattern (VCP2) is not limited or restricted to these conditions, but may be formed to a thickness thicker than the first vertical channel pattern (VCP1). For example, the second vertical channel pattern (VCP2) may be formed to a thickness of about 5 nm.

[0084] Accordingly, the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2) can be formed with different thicknesses.

[0085] Above, it has been described that the first vertical channel pattern (VCP1) supplies holes and the second vertical channel pattern (VCP2) supplies electrons, but it is not limited or restricted thereto, and the first vertical channel pattern (VCP1) may supply electrons and the second vertical channel pattern (VCP2) may supply holes.

[0086] The first vertical channel pattern (VCP1) is not limited or restricted to being formed of a material that supplies only holes as described, but may also be formed of a material that supplies electrons. That is, the vertical channel patterns (VCP1, VCP2) may be formed of materials that supply electrons to the memory cells, but have different electron mobilities.

[0087] More specifically, the first vertical channel pattern (VCP1) is formed of a polysilicon or silicon crystal material and is formed in contact with the data storage pattern (DSP) to a thickness exceeding a preset thickness that causes surface scattering, thereby supplying not only holes but also electrons to the memory cells. For example, the first vertical channel pattern (VCP1) is formed to a thickness exceeding 1 nm that causes surface scattering from an interface of the data storage pattern (DSP), thereby supplying electrons (current flow) to the memory cells in a program operation or a read operation.

[0088] In this case, only the first vertical channel pattern (VCP1) that supplies holes is used for the hole injection-based erase operation for the memory cells, and in the program operation or read operation, the first vertical channel pattern (VCP1) that supplies electrons may be used together with the second vertical channel pattern (VCP2) that supplies electrons.

[0089] In this way, the first vertical channel pattern (VCP1) can supply only holes or both holes and electrons depending on the formation thickness.

[0090] Above, it has been described that the first vertical channel pattern (VCP1) supplies holes and electrons and the second vertical channel pattern (VCP2) supplies electrons, but it is not limited or restricted thereto, and the first vertical channel pattern (VCP1) may supply electrons and the second vertical channel pattern (VCP2) may supply holes and electrons.

[0091] As described, if ion movement occurs between the vertical channel patterns (VCP1, VCP2) because the vertical channel patterns (VCP1, VCP2) are formed of different semiconductor materials, the cell current characteristics may deteriorate.

[0092] Therefore, the conductive film (CD) can be formed to prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed with different semiconductor materials in order to prevent degradation of cell current characteristics. For example, the conductive film (CD) may be In x O y , SnO x or ZnO x By forming a conductive material including at least one of the above, ions can be prevented from moving between the vertical channel patterns (VCP1, VCP2).

[0093] However, the vertical channel patterns (VCP1, VCP2) are not limited or restricted as described, and can be formed of the same semiconductor material. In this case, the conductive film (CD) is only used to increase the current flowing in the composite vertical channel pattern (CVCP), and is not used to prevent ion movement between the vertical channel patterns (VCP1, VCP2).

[0094] The upper surface of the composite vertical channel pattern (CVCP) can be substantially coplanar with the upper surface of the vertical buried pattern (VFP), and can be positioned at a higher level than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the composite vertical channel pattern (CVCP) can be positioned between the upper surface and the lower surface of the third gate electrode (EL3). The lower surface of the composite vertical channel pattern (CVCP) can be coplanar with the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD)). However, without being limited thereto, the lower surface of the composite vertical channel pattern (CVCP) can be positioned at a lower level than the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD)).

[0095] The vertically filled pattern (VFP) may be surrounded by a second vertical channel pattern (VCP2) of a composite vertical channel pattern (CVCP). An upper surface of the vertically filled pattern (VFP) may be in contact with a capping layer (CAP), and a lower surface of the vertically filled pattern (VFP) may be in contact with an uppermost surface of a substrate (SUB). The vertically filled pattern (VFP) may be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertically filled pattern (VFP) may be electrically floated from the substrate (SUB).

[0096] Although a structure in which a vertically filled pattern (VFP) is positioned within a composite vertical channel pattern (CVCP) has been described, the 3D flash memory is not limited thereto and may have a structure including a back gate (BG; not shown) instead of the vertically filled pattern (VFP). In this case, the back gate (BG) may be formed to be at least partially surrounded by and in contact with the composite vertical channel pattern (CVCP) and to apply a voltage to the composite vertical channel pattern (CVCP) for a memory operation. For this purpose, the back gate (BG) may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials. In addition, in this case, an insulating film (INS; not shown) is disposed between the back gate (BG) and the composite vertical channel pattern (CVCP), thereby preventing the back gate (BG) from directly contacting the composite vertical channel pattern (CVCP). The insulating film (INS), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide. However, the insulating film (INS) may be omitted depending on the implementation example.

[0097] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0098] A capping layer (CAP) may be provided on an upper surface of a composite vertical channel pattern (CVCP). The capping layer (CAP) may be connected to an upper portion of the composite vertical channel pattern (CVCP). A side wall of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). An upper surface of the capping layer (CAP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILD). A lower surface of the capping layer (CAP) may be located at a level lower than an upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap the third gate electrode (EL3) in a horizontal direction.

[0099] The capping layer (CAP) may be formed of a material (e.g., the same polysilicon or silicon crystal material as the first vertical channel pattern (VCP1)) having a lower contact resistance than the contact resistance that the second vertical channel pattern (VCP2) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP) may reduce the contact resistance between the bit line (BL) and the composite vertical channel pattern (CVCP), which will be described later.

[0100] A separation trench (TR; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR; not shown) may be provided within a substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with a second conductivity type impurity (e.g., an N-type impurity). The common source region (CSR) may correspond to a common source line (CSL) of FIG. 1.

[0101] A common source plug (CSP; not shown) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). An upper surface of the common source plug (CSP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILDs). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which a width in a second direction (D2) increases as it goes in the third direction (D3).

[0102] Insulating spacers (SP; not shown) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided so as to face each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0103] A capping insulating film (CAP-INS) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating film (CAP-INS) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD), an upper surface of the capping layer (CAP), and an upper surface of the common source plug (CSP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0104] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0105] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a composite vertical channel pattern (CVCP) included in the vertical channel structures (VS).

[0106] A three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes gate electrodes (EL1, EL2, EL3) to which voltages for memory operation are applied, a bit line (BL), a common source line (CSL), and a composite vertical channel pattern (CVCP) forming a channel, and a data storage pattern (DSP) for data storage, according to an implementation example.

[0107] In this way, a structure is proposed in which a composite vertical channel pattern (CVCP) includes vertical channel patterns (VCP1, VCP2) and a conductive film (CD) used for increasing current, so that the area through which current (channel current) flows in the composite vertical channel pattern (CVCP) increases, while the value of the current (channel current) itself increases, thereby improving channel current characteristics.

[0108]

[0109] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0110] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 4, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0111] In step (S510), the manufacturing system can form a composite vertical channel pattern (CVCP) with vertical channel patterns (VCP1, VCP2) and a conductive film (CD) interposed between the vertical channel patterns (VCP1, VCP2).

[0112] In more detail, the manufacturing system can form a composite vertical channel pattern (CVCP) in the following order: a first step of forming one of the vertical channel patterns (VCP1, VCP2) on the inner wall of a data storage pattern (DSP) formed in each of the channel holes (C); a second step of forming a conductive film (CD) on the inner wall of one of the vertical channel patterns (VCP1); and a third step of forming one of the vertical channel patterns (VCP2) other than one of the vertical channel patterns (VCP1, VCP2) on the inner wall of the conductive film (CD).

[0113] At this time, in the second stage, the manufacturing system can form a conductive film (CD) that is used to increase the current flowing in the composite vertical channel pattern (CVCP) based on the characteristic that the carrier concentration is higher than that of the vertical channel patterns (VCP1, VCP2).

[0114] To this end, the manufacturing system uses a material (e.g., In) having a carrier concentration higher than the vertical channel patterns (VCP1, VCP2). x O y , SnO x or ZnO x A conductive film (CD) can be formed using a conductive material including at least one of the following.

[0115] Additionally, in the second step, the manufacturing system can form a conductive film (CD) with a thickness (e.g., 1 nm to 3 nm) that satisfies conditions for turning on and off due to an electric field caused by a voltage applied to word lines (WLs).

[0116] In addition, the conductive film (CD) can be used not only to increase the current flowing in the composite vertical channel pattern (CVCP), but also to prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed of different semiconductor materials. That is, in the second step, the manufacturing system can form a conductive film (CD) used to prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed of different semiconductor materials.

[0117] Although not depicted as a separate step, in step (S510), the manufacturing system can form a vertical embedded pattern (VFP) on the inner wall of the second vertical channel pattern (VCP2).

[0118] The manufacturing method described above is for manufacturing a three-dimensional flash memory having a structure including a composite vertical channel pattern (CVCP), and may obviously include manufacturing steps included in a conventional three-dimensional flash memory manufacturing method, while essentially including a step (S510) of forming a composite vertical channel pattern (CVCP).

[0119] For example, when a word line replacement manufacturing method is applied, the manufacturing system performs a manufacturing method including a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of removing the sacrificial layers through the channel holes (CH); a fourth step of forming word lines (WL0-WLn) in the spaces from which the sacrificial layers are removed; a fifth step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); and a sixth step of forming a composite vertical channel pattern (CVCP) on an inner wall of the data storage pattern (DSP) (step S510 described above), or a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); A manufacturing method can be performed, including a fourth step (step S510 described above) of forming a composite vertical channel pattern (CVCP) on an inner wall of a data storage pattern (DSP); a fifth step of forming an isolation trench (TR) in a semiconductor structure; a sixth step of removing sacrificial layers through the isolation trench (TR); and a seventh step of forming word lines (WL0-WLn) in a space from which the sacrificial layers have been removed.

[0120] As another example, when a gate-first manufacturing method is applied, the manufacturing system can perform a manufacturing method including a first step of preparing a semiconductor structure in which word lines (WL0-WLn) and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); and a fourth step of forming a composite vertical channel pattern (CVCP) on an inner wall of the data storage pattern (DSP) (step S510 described above).

[0121]

[0122] Hereinafter, with reference to the drawings, a three-dimensional flash memory having a structure of a composite vertical channel pattern including a first vertical channel pattern formed of a silicon-based material, a second vertical channel pattern formed of an oxide semiconductor material, and an interface oxide film interposed between the first vertical channel pattern and the second vertical channel pattern, in order to improve leakage current characteristics while increasing mobility related to channel current, and a method for manufacturing the same will be described in detail.

[0123]

[0124] FIG. 6 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIG. 7 is a cross-sectional view illustrating the structure of a three-dimensional flash memory to explain the function of an interface oxide film included in a composite vertical channel pattern according to one embodiment.

[0125] Referring to the drawings, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0126] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0127] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0128] Referring back to FIG. 1, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

[0129] Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), gold (Au), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0130] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in multiple numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 1.

[0131] Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the longest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the shortest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it moves away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a plan view.

[0132] Each of the interlayer insulating layers (ILDs) may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than the other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each of the interlayer insulating layers (ILDs) may be different depending on the characteristics of the semiconductor device, or may be set to be the same for all. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0133] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) may be stacked while being spaced apart from each other in the vertical direction (e.g., the third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0134] A plurality of channel holes (CH) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be a plurality of cell strings (CSTR) as illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0135] The rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as illustrated in FIG. 2, twelve vertical channel structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical channel structures (VS) forming the array is not limited or restricted thereto.

[0136] As vertical channel structures (VS) are formed in a plate shape, the array is formed in a horizontal plane of multiple rows and columns of gate electrodes (EL1, EL2, EL3), so that the three-dimensional flash memory can have a structure in which the integration of memory cell strings is improved.

[0137] At this time, the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on a horizontal plane and to be misaligned with each other. For example, the vertical channel structures (VS) included in a first column may be arranged in the first and third rows, and the vertical channel structures (VS) included in a second column may be arranged in the second and fourth rows, such that the vertical channel structures (VS) included in a pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string can be further improved compared to the case where the vertical channel structures (VS) included in a pair of adjacent columns are arranged side by side in the same row on a horizontal plane.

[0138] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical channel structures (VS) is illustrated as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0139] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a composite vertical channel pattern (CVCP), a vertical filling pattern (VFP), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the composite vertical channel pattern (CVCP) may have a pipe shape or a macaroni shape with an open bottom, and the vertical filling pattern (VFP) may have a shape that fills an inner space of the composite vertical channel pattern (CVCP). However, without being limited thereto, the composite vertical channel pattern (CVCP) may also have a pipe shape or a macaroni shape with a closed bottom.

[0140] The data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the composite vertical channel pattern (CVCP) on the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outer side. Accordingly, regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) may form memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through the second gate electrodes (EL2) together with regions corresponding to the second gate electrodes (EL2) of the composite vertical channel pattern (CVCP). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 1.

[0141] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by a voltage applied through the second gate electrodes (EL2), or by maintaining the state of electrons (e.g., the polarization state of charges). For example, an ONO (tunnel oxide-nitride-blocking oxide) layer or a ferroelectric layer can be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent a binary data value or a multi-valued data value by a change in the trapped charge or hole, or can represent a binary data value or a multi-valued data value by a change in the state of charges.

[0142] Although the above data storage pattern (DSP) is described as being vertically connected and extended, it is not limited to this and may be segmented into multiple pieces and formed only in the portion corresponding to the second gate electrodes (EL), thereby forming memory cells together with the regions corresponding to the second gate electrodes (EL2) among the composite vertical channel pattern (CVCP).

[0143] A composite vertical channel pattern (CVCP) is a component that supplies electrons or holes to transfer charges to a data storage pattern (DSP). The composite vertical channel pattern (CVCP) may be formed to extend in a vertical direction (e.g., a third direction (D3)) while covering an inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage. More specifically, the composite vertical channel pattern (CVCP) may be composed of a plurality of vertical channel patterns (VCP1, VCP2) and an interfacial oxide film (IO) interposed between the vertical channel patterns (VCP1, VCP2).

[0144] Among the vertical channel patterns (VCP1, VCP2), the first vertical channel pattern (VCP1) may be formed of a silicon-based material (e.g., polycrystalline silicon material) while in contact with the inner wall of the data storage pattern (DSP).

[0145] Among the vertical channel patterns (VCP1, VCP2), the second vertical channel pattern (VCP2) can be formed of an oxide semiconductor material in the internal space of the first vertical channel pattern (VCP1).

[0146] An interfacial oxide film (IO) is interposed between a first vertical channel pattern (VCP1) and a second vertical channel pattern (VCP2), and may be formed by oxidizing a portion of the interface of the first vertical channel pattern (VCP1) with respect to the second vertical channel pattern (VCP2) during a heat treatment process of an oxide semiconductor material constituting the second vertical channel pattern (VCP2).

[0147] In particular, the interfacial oxide film (IO) is formed by absorbing oxygen in the oxide semiconductor material constituting the second vertical channel pattern (VCP2) during the heat treatment process, thereby increasing the oxygen vacancy of the second vertical channel pattern (VCP2), as illustrated in FIG. 7. Therefore, the interfacial oxide film (IO) can bring about a technical effect of improving the channel current by increasing the mobility of the second vertical channel pattern (VCP2) due to the increase in the oxygen vacancy of the second vertical channel pattern (VCP2).

[0148] In order for the interfacial oxide film (IO) to be formed by absorbing oxygen in the oxide semiconductor material forming the second vertical channel pattern (VCP2) rather than oxygen in the silicon-based material forming the first vertical channel pattern (VCP1), a condition must be satisfied in which the oxide semiconductor material forming the second vertical channel pattern (VCP2) has a lower oxygen affinity than the silicon-based material forming the first vertical channel pattern (VCP1).

[0149] Accordingly, as the oxide semiconductor material forming the second vertical channel pattern (VCP2), a material having a lower oxygen affinity than the silicon-based material forming the first vertical channel pattern (VCP1) (e.g., at least one of InOx, SnOx, or ZnOx) may be used.

[0150] In addition, the concentration of the silicon-based material forming the first vertical channel pattern (VCP1) may affect the formation of the interfacial oxide film (IO) by absorbing oxygen in the oxide semiconductor material forming the second vertical channel pattern (VCP2) rather than oxygen in the silicon-based material forming the first vertical channel pattern (VCP1).

[0151] Accordingly, the concentration of the silicon-based material forming the first vertical channel pattern (VCP1) can be determined and controlled so as to absorb oxygen in the oxide semiconductor material forming the second vertical channel pattern (VCP2), rather than oxygen in the silicon-based material forming the first vertical channel pattern (VCP1), during the process of forming the interfacial oxide film (IO). For example, the concentration of the silicon-based material forming the first vertical channel pattern (VCP1) can be determined and controlled to be 3 wt% or more so as to absorb oxygen in the oxide semiconductor material forming the second vertical channel pattern (VCP2), rather than oxygen in the silicon-based material forming the first vertical channel pattern (VCP1), during the process of forming the interfacial oxide film (IO).

[0152] Here, it is assumed that the heat treatment process of the oxide semiconductor material forming the second vertical channel pattern (VCP2) is performed in an air atmosphere (an atmosphere containing typical atmospheric components such as 78% nitrogen, 21% oxygen, 0.9% argon, and 0.03% carbon dioxide) rather than an oxygen atmosphere. This is because the heat treatment process must be performed in an air atmosphere to form an interface oxide film (IO) that absorbs oxygen within the oxide semiconductor material forming the second vertical channel pattern (VCP2).

[0153] The upper surface of the composite vertical channel pattern (CVCP) can be substantially coplanar with the upper surface of the vertical buried pattern (VFP), and can be positioned at a higher level than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the composite vertical channel pattern (CVCP) can be positioned between the upper surface and the lower surface of the third gate electrode (EL3). The lower surface of the composite vertical channel pattern (CVCP) can be coplanar with the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD)). However, without being limited thereto, the lower surface of the composite vertical channel pattern (CVCP) can be positioned at a lower level than the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating layers (ILD)).

[0154] The vertically filled pattern (VFP) may be surrounded by a second vertical channel pattern (VCP2) of a composite vertical channel pattern (CVCP). An upper surface of the vertically filled pattern (VFP) may be in contact with a capping layer (CAP), and a lower surface of the vertically filled pattern (VFP) may be in contact with an uppermost surface of a substrate (SUB). The vertically filled pattern (VFP) may be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertically filled pattern (VFP) may be electrically floated from the substrate (SUB).

[0155] Although a structure in which a vertically filled pattern (VFP) is positioned within a composite vertical channel pattern (CVCP) has been described, the 3D flash memory is not limited thereto and may have a structure including a back gate (BG; not shown) instead of the vertically filled pattern (VFP). In this case, the back gate (BG) may be formed to be at least partially surrounded by and in contact with the composite vertical channel pattern (CVCP) and to apply a voltage to the composite vertical channel pattern (CVCP) for a memory operation. For this purpose, the back gate (BG) may be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials. In addition, in this case, an insulating film (INS; not shown) is disposed between the back gate (BG) and the composite vertical channel pattern (CVCP), thereby preventing the back gate (BG) from directly contacting the composite vertical channel pattern (CVCP). The insulating film (INS), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide. However, the insulating film (INS) may be omitted depending on the implementation example.

[0156] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to channels of an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT).

[0157] A capping layer (CAP) may be provided on an upper surface of a composite vertical channel pattern (CVCP). The capping layer (CAP) may be connected to an upper portion of the composite vertical channel pattern (CVCP). A side wall of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). An upper surface of the capping layer (CAP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILD). A lower surface of the capping layer (CAP) may be located at a level lower than an upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap the third gate electrode (EL3) in a horizontal direction.

[0158] The capping layer (CAP) may be formed of a material (e.g., a polycrystalline silicon material or a single-crystal silicon material identical to the first vertical channel pattern (VCP1)) having a lower contact resistance than the contact resistance that the second vertical channel pattern (VCP2) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP) may reduce the contact resistance between the bit line (BL) and the composite vertical channel pattern (CVCP), which will be described later.

[0159] A separation trench (TR; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR; not shown) may be provided within a substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with a second conductivity type impurity (e.g., an N-type impurity). The common source region (CSR) may correspond to a common source line (CSL) of FIG. 1.

[0160] A common source plug (CSP; not shown) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). An upper surface of the common source plug (CSP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating layers (ILDs). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which a width in a second direction (D2) increases as it goes in the third direction (D3).

[0161] Insulating spacers (SP; not shown) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided so as to face each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0162] A capping insulating film (CAP-INS) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating film (CAP-INS) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD), an upper surface of the capping layer (CAP), and an upper surface of the common source plug (CSP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0163] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 1, and may be formed by extending along a second direction (D2) using a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0164] A bit line (BL) may be electrically connected to vertical channel structures (VS) via a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to a composite vertical channel pattern (CVCP) included in the vertical channel structures (VS).

[0165] A three-dimensional flash memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes gate electrodes (EL1, EL2, EL3) to which voltages for memory operation are applied, a bit line (BL), a common source line (CSL), and a composite vertical channel pattern (CVCP) forming a channel, and a data storage pattern (DSP) for data storage, according to an implementation example.

[0166]

[0167] FIG. 8 is a flow chart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0168] A three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 2 and FIGS. 6 to 7, and the manufacturing method described below is assumed to be performed by an automated and mechanized manufacturing system.

[0169] In step (S810), the manufacturing system can form a composite vertical channel pattern (CVCP) with a first vertical channel pattern (VCP1) formed of a silicon-based material, a second vertical channel pattern (VCP2) formed of an oxide semiconductor material, and an interface oxide film (IO) interposed between the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2).

[0170] In more detail, the manufacturing system can form a composite vertical channel pattern (CVCP) in the following order: a first step of forming a first vertical channel pattern (VCP1) with a silicon-based material on an inner wall of a data storage pattern (DSP) formed in each of channel holes (CH); a second step of forming a second vertical channel pattern (VCP2) with an oxide semiconductor material on an inner wall of the first vertical channel pattern (VCP1); and a third step of performing a heat treatment process on the second vertical channel pattern (VCP2) to form an interface oxide film (IO) between the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2).

[0171] Therefore, in the third step, the manufacturing system can increase the oxygen vacancy of the second vertical channel pattern (VCP2) by forming an interface oxide film (IO) by absorbing oxygen in the oxide semiconductor material at an interface portion of the first vertical channel pattern (VCP1) with respect to the second vertical channel pattern (VCP2) in the heat treatment process, and the manufacturing system can increase the mobility of the second vertical channel pattern (VCP2) by increasing the oxygen vacancy of the second vertical channel pattern (VCP2) through the third step.

[0172] In the third step, the heat treatment process can be carried out under an air atmosphere rather than an oxygen atmosphere.

[0173] At this time, the manufacturing system may form the second vertical channel pattern (VCP2) with an oxide semiconductor material including a material having a lower oxygen affinity than a silicon-based material in the second step, so that a portion of the interface of the first vertical channel pattern (VCP1) with respect to the second vertical channel pattern (VCP2) absorbs oxygen in the oxide semiconductor material in the third step heat treatment process to form an interface oxide film (IO).

[0174] In addition, the manufacturing system can determine and control the concentration of the silicon-based material forming the first vertical channel pattern (VCP1) in the first step so that a portion of the interface between the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2) absorbs oxygen within the oxide semiconductor material to form an interfacial oxide film (IO) in the heat treatment process in the third step. For example, the manufacturing system can determine and control the concentration of the silicon-based material to be 3 wt% or more so that the oxygen within the oxide semiconductor material, not the silicon-based material, is absorbed during the process of forming the interfacial oxide film.

[0175] Although not depicted as a separate step, in step (S810), the manufacturing system can form a vertical embedded pattern (VFP) on the inner wall of the second vertical channel pattern (VCP2).

[0176] The manufacturing method described above is for manufacturing a three-dimensional flash memory having a structure including a composite vertical channel pattern (CVCP), and may obviously include manufacturing steps included in a conventional three-dimensional flash memory manufacturing method, while essentially including a step (S810) of forming a composite vertical channel pattern (CVCP).

[0177] For example, when a word line replacement manufacturing method is applied, the manufacturing system performs a manufacturing method including a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of removing the sacrificial layers through the channel holes (CH); a fourth step of forming word lines (WL0-WLn) in the spaces from which the sacrificial layers are removed; a fifth step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); and a sixth step of forming a composite vertical channel pattern (CVCP) on an inner wall of the data storage pattern (DSP) (step S810 described above), or a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); A manufacturing method can be performed, including a fourth step (step S810 described above) of forming a composite vertical channel pattern (CVCP) on an inner wall of a data storage pattern (DSP); a fifth step of forming an isolation trench (TR) in a semiconductor structure; a sixth step of removing sacrificial layers through the isolation trench (TR); and a seventh step of forming word lines (WL0-WLn) in a space from which the sacrificial layers have been removed.

[0178] As another example, when a gate-first manufacturing method is applied, the manufacturing system can perform a manufacturing method including a first step of preparing a semiconductor structure in which word lines (WL0-WLn) and interlayer insulating layers (ILDs) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on an inner wall of each of the channel holes (CH); and a fourth step of forming a composite vertical channel pattern (CVCP) on an inner wall of the data storage pattern (DSP) (step S810 described above).

[0179]

[0180] FIG. 9 is a perspective view schematically illustrating an electronic system including a three-dimensional flash memory according to embodiments.

[0181] Referring to FIG. 9, an electronic system (900) including a three-dimensional flash memory according to embodiments may include a main substrate (901), a controller (902) mounted on the main substrate (901), one or more semiconductor packages (903), and a DRAM (904).

[0182] The semiconductor package (903) and DRAM (904) can be connected to the controller (902) by wiring patterns (905) provided on the main substrate (901).

[0183] The main board (901) may include a connector (906) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (906) may vary depending on the communication interface between the electronic system (900) and the external host.

[0184] The electronic system (900) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (900) may operate by power supplied from an external host, for example, through a connector (906). The electronic system (900) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (902) and a semiconductor package (903).

[0185] The controller (902) can write data to the semiconductor package (903) or read data from the semiconductor package (903), and can improve the operating speed of the electronic system (900).

[0186] The DRAM (904) may be a buffer memory to mitigate the speed difference between the semiconductor package (903), which is a data storage space, and an external host. The DRAM (904) included in the electronic system (900) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (903). When the electronic system (900) includes the DRAM (904), the controller (902) may further include a DRAM controller for controlling the DRAM (904) in addition to the NAND controller for controlling the semiconductor package (903).

[0187] The semiconductor package (903) may include first and second semiconductor packages (903a, 903b) spaced apart from each other. The first and second semiconductor packages (903a, 903b) may each be a semiconductor package including a plurality of semiconductor chips (920). Each of the first and second semiconductor packages (903a, 903b) may include a package substrate (910), semiconductor chips (920) on the package substrate (910), adhesive layers (930) disposed on a lower surface of each of the semiconductor chips (920), connection structures (940) electrically connecting the semiconductor chips (920) and the package substrate (910), and a molding layer (950) covering the semiconductor chips (920) and the connection structures (940) on the package substrate (910).

[0188] The package substrate (910) may be a printed circuit board including package upper pads (911). Each of the semiconductor chips (920) may include input / output pads (921). Each of the semiconductor chips (920) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 4 and FIGS. 6 to 7. More specifically, each of the semiconductor chips (920) may include gate stack structures (922) and memory channel structures (923). The memory channel structures (923) may correspond to the vertical channel structures (VS) described above.

[0189] The connection structures (940) may be, for example, bonding wires that electrically connect the input / output pads (921) and the package upper pads (911). Accordingly, in each of the first and second semiconductor packages (903a, 903b), the semiconductor chips (920) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (911) of the package substrate (910). According to embodiments, in each of the first and second semiconductor packages (903a, 903b), the semiconductor chips (920) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (940).

[0190] Unlike the illustration, the controller (902) and the semiconductor chips (920) may be included in one package. The controller (902) and the semiconductor chips (920) may be mounted on a separate interposer substrate different from the main substrate (901), and the controller (902) and the semiconductor chips (920) may be connected to each other by wiring provided on the interposer substrate.

[0191]

[0192] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above description. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0193] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Word lines that are formed extending horizontally on the substrate and are stacked while being spaced apart from each other in the vertical direction; and Vertical channel structures formed to extend in the vertical direction on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend in the vertical direction and a data storage pattern formed in contact with an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines. Including, The above complex vertical channel pattern is, A three-dimensional flash memory characterized by including vertical channel patterns and a conductive film interposed between the vertical channel patterns.

2. In paragraph 1, The above conductive film is, A three-dimensional flash memory characterized by being used for the purpose of increasing current flowing in the above complex vertical channel pattern.

3. In paragraph 2, The above conductive film is, A three-dimensional flash memory characterized in that it is formed with a thickness that satisfies conditions that can be turned on and off by an electric field due to a voltage applied to the above word lines.

4. In paragraph 2, The above conductive film is, A three-dimensional flash memory characterized in that the carrier concentration is formed of a material having a higher characteristic than the vertical channel patterns.

5. In paragraph 1, The above conductive film is, A three-dimensional flash memory characterized in that it is used for the purpose of preventing ions from moving between the vertical channel patterns formed of different semiconductor materials.

6. In paragraph 1, The above vertical channel patterns are, A three-dimensional flash memory characterized in that the memory cells are formed of materials having different electron mobilities, each of which supplies electrons.

7. In paragraph 1, Any one of the above vertical channel patterns, It is formed of a material that supplies holes to the above memory cells, Among the above vertical channel patterns, one vertical channel pattern other than one of the above vertical channel patterns is A three-dimensional flash memory characterized by being formed of a material that supplies electrons to the above memory cells.

8. In paragraph 1, Any one of the above vertical channel patterns, Formed of a material that supplies holes and electrons to the above memory cells, Among the above vertical channel patterns, one vertical channel pattern other than one of the above vertical channel patterns is A three-dimensional flash memory characterized by being formed of a material that supplies electrons to the above memory cells.

9. A method for manufacturing a three-dimensional flash memory, comprising: word lines formed to extend horizontally on a substrate and stacked while being spaced apart from each other in the vertical direction; and vertical channel structures formed to extend vertically on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend vertically and a data storage pattern formed in contact with an outer wall of the composite vertical channel pattern, the data storage pattern and the composite vertical channel pattern forming memory cells corresponding to the word lines, and the composite vertical channel pattern including the vertical channel patterns and a conductive film interposed between the vertical channel patterns, A step of forming the composite vertical channel pattern with vertical channel patterns and a conductive film interposed between the vertical channel patterns. A method for manufacturing a three-dimensional flash memory including:

10. In paragraph 9, The steps of forming the above complex vertical channel pattern are: A step of forming one of the vertical channel patterns on the inner wall of the data storage pattern; A step of forming the conductive film on the inner wall of any one of the above vertical channel patterns; and A step of forming one vertical channel pattern, excluding one of the vertical channel patterns, on the inner wall of the conductive film. Including, The step of forming the conductive film is: A method for manufacturing a three-dimensional flash memory, characterized in that it is a step of forming the conductive film used for the purpose of increasing the current flowing in the above complex vertical channel pattern.

11. Word lines that are formed extending horizontally on the substrate and are stacked while being spaced apart from each other in the vertical direction; and Vertical channel structures formed to extend in the vertical direction on the substrate through the word lines, each of the vertical channel structures including a composite vertical channel pattern formed to extend in the vertical direction and a data storage pattern formed in contact with an outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines. Including, The above complex vertical channel pattern is, A three-dimensional flash memory characterized by including a first vertical channel pattern formed of a silicon series material, a second vertical channel pattern formed of an oxide semiconductor material, and an interface oxide film interposed between the first vertical channel pattern and the second vertical channel pattern.

12. In paragraph 11, The above interfacial oxide film is, A three-dimensional flash memory characterized in that the oxygen vacancy of the second vertical channel pattern is increased by being formed by absorbing oxygen within the oxide semiconductor material during a heat treatment process of the oxide semiconductor material.

13. In paragraph 12, The above oxide semiconductor material is, A three-dimensional flash memory characterized by including a material having lower oxygen affinity than the silicon-based material.

14. In paragraph 12, The concentration of the above silicon series material is, A three-dimensional flash memory characterized in that the interfacial oxide film is formed in a process in which oxygen within the oxide semiconductor material is absorbed and controlled.

15. In paragraph 12, The above interfacial oxide film is, A three-dimensional flash memory characterized by increasing the mobility of the second vertical channel pattern by increasing the oxygen vacancy of the second vertical channel pattern.

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