Observation analog-to-digital converter using multiple clock phases of a sampling clock and timing skew estimation of sampling clock phases

Abstract

An observation analog-to-digital converter (ADC) using multiple clock phases of a sampling clock and timing skew estimation of sampling clock phases. An apparatus for observation of a transmit path includes an ADC configured to sample an analog signal at an observation point in a transmit path and clock phase selection circuitry to provide a sampling clock to the ADC. The clock phase selection circuitry generates a plurality of different phases of an observation clock and provides the observation clock in two or more different phases as the sampling clock to the ADC such that the analog signal is sampled by the ADC at two or more different phases of the observation clock. The post-processing circuitry may estimate a timing skew between the sampling clock in different phases.

Description

Observation analog-to-digital converter using multiple clock phases of a sampling clock and timing skew estimation of sampling clock phasesBackground

[0001] A transmit system often requires observation of an output signal somewhere along the analog or radio frequency (RF) transmit chain for calibration or linearization purposes. Observation analog-to-digital converters (ADCs) may be used for the observation of the output signal even with subsampling approaches while still being able to observe the entire first Nyquist zone of the transmit digital-to-analog converter (DAC). Yet the observable bandwidth is limited by the high-speed sampling clock from which the observation ADC sampling clock is derived.

[0002] Observation ADCs for transmit chains usually require high sampling rates in order to provide the necessary observation bandwidth. The observed bandwidth is limited to one Nyquist zone, but not necessarily limited to the first Nyquist zone. Nyquist zones subdivide the spectrum into regions spaced uniformly at intervals of fs / 2. Each Nyquist zone contains a copy of the spectrum of the desired signal or a mirror image of it. The first Nyquist zone is defined as a signal between 0 and fs / 2, and the second Nyquist zone is defined as a signal between fs / 2 and fs, and so on. Having a full-rate observation ADC is hardware and power intensive. In addition, adequate filtering has to be implemented at its input to avoid aliasing of components outside of the observed Nyquist zone, which can limit the observation dynamic range.

[0003] The concept of irregular sub-sampling on a high-rate clock has been introduced. The observation ADC can sample with an arbitrarily chosen subset of sampling clock edges of the RF clock that is used in the transmitter DAC and still deliver all information in one full Nyquist zone of the DAC. A sub-sampling ADC with irregular sub-sampling still has similar filter requirements and observation bandwidth limitations like the full rate observation ADC, but the power and hardware effort are dramatically reduced for the observation ADC.Brief description of the Figures

[0004] Some examples of apparatuses and / or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

[0005] FIG. 1 is a schematic block diagram of an example apparatus for observation of a transmit path;

[0006] FIG. 2 is a block diagram of an example apparatus for estimating a timing skew between different phases of a sampling clock;

[0007] FIG. 3 shows an example system including a DAC and an observation ADC with variable sampling clock phases;

[0008] FIG. 4 shows an example system with a DAC and a full-rate observation ADC with programmable clock phases;

[0009] FIGS. 5A-5D show an example sampling clock and a transmitter signal and observation samples captured on different sampling clock edges in a system shown in FIG. 4;

[0010] FIG. 6 shows an example system including a DAC and a sub-sampling observation ADC with a programmable clock phase;

[0011] FIG. 7 shows an example system including a DAC and an observation ADC with N available clock phases;

[0012] FIG. 8 shows a model for an example transmit system including a DAC and an observation ADC and digital post-processing for estimating the timing skew between the clock phases;

[0013] FIG. 9 shows an example time-interleaved (TI)-DAC with an observation ADC;

[0014] FIG. 10 is a flow diagram of an example method for observation of a transmit path in a transmitter;

[0015] FIG. 11 is a flow diagram of an example method for estimating a timing skew between different sampling clock phases;

[0016] FIG. 12 illustrates a user device in which the examples disclosed herein may be implemented; and

[0017] FIG. 13 illustrates a base station or infrastructure equipment radio head in which the examples disclosed herein may be implemented.Detailed Description

[0018] Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and / or regions may be exaggerated for clarity.

[0019] Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and willsubsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.

[0020] It will be understood that when an element is referred to as being “connected” or “coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an “or”, this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is “at least one of A and B”. The same applies for combinations of more than 2 elements.

[0021] The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as “a,” “an” and “the” is used and using only a single element is neither explicitly or implicitly defined as being mandatory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multiple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms “comprises,” “comprising,” “includes” and / or “including,” when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and / or any group thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong.

[0023] In a transmitter system, various non-idealities (non-linearities) exist. For example, a DAC might show non-linearity due to mismatch effects, and a transmit power amplifier (PA) might show non-linearity due to the inherently limited linearity of the used devices. Therefore, there is a desire to correct for non-idealities. The non-idealities may be corrected by applying analog calibration or trimming, or by using digital processing to correct the errors in digital domain, as is being done in digital pre-distortion (DPD).

[0024] In order to correct the non-idealities, they have to be measured in some way. This can be done using dedicated chip-external measurement hardware temporarily attached to the transmit system, as is often done during testing and factory calibrations. However, the non-idealities can change over time. Therefore, there is a desire to continuously monitor the nonidealities during normal operation using hardware embedded in the transmit system. For monitoring the non-idealities, an observation path (a feedback path) including an observation ADC is included in the transmit system to measure the non-idealities.

[0025] Examples for implementing an observation ADC using multiple sampling clock phases and estimating timing skew of the multiple sampling clock phases will be explained hereafter. In examples disclosed herein, multiple clock edges derived from the high-speed sampling clock may be used for an observation ADC. Therefore, the observation bandwidth can be extended beyond the first Nyquist zone. The example schemes disclosed herein also include a method for estimating the timing skew between the used multiple sampling clock phases.

[0026] In examples, an observation ADC in an observation path operates with a certain clock frequency that is equal to or a (integer or fractional) division of the transmitter DAC clock rate. The observation ADC may use multiple clock phases of the observation clock (e.g., rising and falling edges of the observation clock). The resulting sampling grid multiplies the virtual observation bandwidth by the number of available clock phases and requires very little additional hardware. A method for determining and digitally cancelling the timing errors inherent in the generated sampling clock phases allows to eliminate the complexity (or even impracticality) associated with the otherwise required extremely high timing accuracy of the sampling clock phases.

[0027] The example schemes disclosed herein significantly increases the observation bandwidth of an observation ADC, decreases hardware effort, relaxes anti-aliasing filter requirements, and, therefore, reduces area and power requirements for the transmitter (TX) observation path.

[0028] FIG. 1 is a schematic block diagram of an example apparatus for observation of a transmit path. The apparatus 100 includes an ADC 110 (observation ADC) and clock phase selection circuitry 120. The ADC 110 is configured to sample an analog signal at an observation point in a transmit path 140. The transmit path 140 may include a DAC to generate the analog signal, a power amplifier for amplifying the analog signal, a filter, or the like (not shown). The clock phase selection circuitry 120 is configured to provide a sampling clock 104 to the ADC 110 such that the ADC 110 samples (digitizes) the analog signal on the transmit path 140 based on the sampling clock 104. The clock phase selection circuitry 120 is configured to generate a plurality of different phases of an observation clock 106 and provide the observation clock 106 in two or more different phases as the sampling clock 104 to the ADC 110 such that the analogsignal is sampled by the ADC 110 at two or more different phases of the observation clock 106. The observation ADC 110 may be a sub-sampling or full rate ADC. The observation clock 106 may have the same frequency as a sampling clock for a DAC in the transmit path 140 that is configured to generate the analog signal based on the input digital data. For example, the observation clock 106 may be an arbitrarily delayed (modulo clock period) version of the DAC sampling clock. Alternatively, the observation clock 106 may be derived from the sampling clock for the DAC. For example, the observation clock 106 may be integer or fractional division of the sampling clock for the DAC. Alternatively, the observation clock 106 may be completely independent from the sampling clock for the DAC.

[0029] In some examples, the clock phase selection circuitry 120 may include a clock divider configured to divide the sampling clock 104 (or the observation clock 106) to a lower rate than the observation clock 106. In examples, the clock phase selection circuitry 120 may include an N-phase generation circuit configured to generate N different phases of the observation clock 106, and a multiplexer configured to select one of the N different phases of the observation clock as the sampling clock 104 for the ADC 110 based on a phase selection signal. In another example, the clock phase selection circuitry 120 may include an inverter configured to invert the observation clock 106, and a multiplexer configured to select either the observation clock or an inverted observation clock based on a phase selection signal.

[0030] The apparatus 100 may optionally further include post-processing circuitry 130 configured to process an output of the ADC 110 and input digital data in the transmit path 140. For example, the post-processing circuitry 130 may process the output of the ADC 110 and the corresponding input digital data to determine the non-linearity of a component(s) in the transmit path 140.

[0031] In some examples, the post-processing circuitry 130 may be configured to estimate a timing skew between the sampling clocks in different phases. The ADC 110 may be clocked by the sampling clock 104 in two or more different phases and the post-processing circuitry 130 may estimate the timing skew between the sampling clocks in two or more different phases. For example, the post-processing circuitry 130 may be configured to estimate a frequency domain channel response of a channel from an input of a component to be observed in the transmit path 140 to an output of the ADC 110 for the two or more different clock phases of the observation clock and determine the timing skew based on the frequency domain channel responses for the different phases of the sampling clock.

[0032] FIG. 2 is a block diagram of an example apparatus for estimating a timing skew between different phases of a sampling clock. The apparatus 200 includes an ADC 210(observation ADC) and post-processing circuitry 220. The observation ADC 210 is configured to sample (digitize) an analog signal in a transmit path 230.

[0033] The post-processing circuitry 220 is configured to process an output of the observation ADC 210 and corresponding input digital data in the transmit path 230 to determine a timing skew between different phases of a sampling clock used for the observation ADC 210 or sub-DACs (not shown) in the transmit chain 230. The DAC (not shown) in the transmit chain may be built of sub-DACs, which may operate in time-interleaved fashion or in IQ-mode or may be segments of a segmented DAC clocked with the same sampling clock. The observation ADC 210 or the sub-DACs in the transmit chain 230 are clocked by the sampling clock in two or more different phases such that the analog signal is sampled by the observation ADC 210, or the sub-DACs generate the analog signal, at two or more different phases of the sampling clock. For example, the post-processing circuitry 220 may be configured to estimate a frequency domain channel response of a channel from an input of a component (e.g., sub-DACs, PA, etc.) to be observed in the transmit path 230 to an output of the observation ADC 210 for the two or more different clock phases of the sampling clock and determine the timing skew based on the frequency domain channel responses of the channel.

[0034] Examples for implementing an observation ADC using multiple sampling clock phases and estimating a timing skew of the multiple sampling clock phases will be explained in detail hereafter.

[0035] FIG. 3 shows an example system 300 including a DAC and an observation ADC with variable sampling clock phases. The system 300 includes a transmit path 362 and an observation path 364. The transmit path 362 includes a DAC 310 and the observation path 361 includes an observation ADC 330. The transmit path 362 may also include additional components such as a power amplifier (PA), a filter, etc. The DAC 310 generates an analog output signal based on input digital data 302. The DAC 310 operates based on the sampling clock 304 at the sampling frequency fs. The observation ADC 330 in the observation path 364 is coupled to the transmit path 362 to observe the analog signal at the observation point of the transmit path 362. In this example, the observation ADC 330 is coupled to the output of the DAC 310 for observing the output of the DAC 310, but it may be coupled to the output of other components, such as a PA in the transmit path 362. The output of the DAC 310 may be filtered by a filter 320 before being supplied to the observation ADC 330. The output 309 of the observation ADC 330 and the input digital data 302 may be processed by the post-processing unit 340. By comparing the (ideal) input digital data 302 of the DAC 310 with the output 309of the observation ADC 330, the non-idealities (non-linearities) of the DAC 310 (or other components in the transmit chain 362) can be measured, i.e., estimated.

[0036] A sampling clock for the observation ADC 330 is derived from the observation clock 306 by the clock phase selection circuitry 350. In examples, the observation ADC 330 may be clocked with multiple different phases of the observation clock 306. The clock phase selection circuitry 350 may provide a sampling clock to the observation ADC 330 with a programmable sampling clock phase (i.e., a sampling clock with different phases). For example, a multiplexer 352 may be used to select either the observation clock 306 or an inverted version of the observation clock 306 by an inverter 354 based on the phase selection signal 308 such that the observation ADC 330 may sample the output of the DAC 310 either at rising edges and / or falling edges of the observation clock 306. The observation clock 306 for the ADC 330 may be the same as the sampling clock 304 of the DAC 310 or may be different. The observation clock 306 may be derived from the sampling clock 304. For example, the observation clock 306 may be integer or fractional division of the sampling clock 304 for the DAC 310. Alternatively, the observation clock 306 may be independent from the sampling clock 304 for the DAC 310. By allowing to use more than one clock phase of the observation clock 306 in the observation ADC 330 the effective observation bandwidth can be extended. Theoretically, the observation bandwidth is multiplied by the number of available clock phases.

[0037] The programming of the observation ADC clock phase in the clock phase selection circuitry 350 defines which clock edge (e.g., rising or falling edges) of the observation clock 306 will be used in the observation ADC 330. This defines the timing grid of the sampling clock. In this example in FIG. 3, the timing grid of the sampling clock can be shifted by half a clock period, yielding doubling of the observation bandwidth of the ADC 330 (assuming the ADC frontend is not bandwidth limiting).

[0038] The observation ADC 330 may be a sub-sampling or full rate ADC. The rate of the observation clock 306 may be the same as the rate of the sampling clock 304. Alternatively, the observation ADC 330 may operate at a sub-sampling frequency of the sampling clock 304. The frequency range in which the DAC errors can be measured is limited by the bandwidth of the observation ADC 330. If the sampling clock of the observation ADC 330 is equal to the sampling clock of the DAC 310, one full Nyquist zone of the DAC 310 can be observed and DAC errors in that same Nyquist zone can be corrected. In a practical implementation, the lower limit for the DAC non-linearity reduction is given by the linearity of the observation path (e.g., a feedback filter, any signal switches in the feedback path, an observation ADC, etc.) since the post-processing, which compares the input digital data 302 and the sampled and quantizedobservation data 309 by the observation ADC 330, cannot distinguish between any nonlinearities generated in the DAC 310 itself and the subsequent observation path 364. The observation (correction) bandwidth does not necessarily have to be the first Nyquist zone of the DAC 310 or the observation ADC 330. If the observation ADC 330 is operated with a fixed clock rate that is lower than the clock rate of the DAC 310, one Nyquist zone of the ADC 330 is the observable bandwidth in which errors can be measured and, therefore, corrected.

[0039] In some examples, irregular sub-sampling may be used for the observation ADC 330. The observation ADC 330 may sample at irregularly spaced sub-sampling instances of the DAC 310. By operating the ADC 330 only on a (irregularly spaced) subset of the entire set of sampling clock edges of the DAC 310, within a certain observation time range, the ADC conversion rate can be reduced significantly, while still maintaining the observation bandwidth of one entire Nyquist zone of the DAC 310, provided that the input circuit of the observation ADC 330 (including its first sample and holding (S / H) circuitry) is sufficiently wideband. To avoid aliasing of spectral components outside of the observation bandwidth, an analog filter 320 may be added in between the DAC output (or any other desired observation point along the transmit chain) and the ADC input. The filter 320 has to be dimensioned to have sufficient attenuation of unwanted spectral components in order for them not to limit the dynamic range of the observation signal. The filter 320 may be a lowpass filter or a bandpass filter whose characteristics are tailored to the actual observation frequency range (comprising one effective Nyquist zone of the observation ADC path).

[0040] FIG. 4 shows an example system with a DAC and a full-rate observation ADC with programmable clock phases. The system 400 includes a transmit path 462 and an observation path 464. The transmit path 462 includes a DAC 410 and the observation path 464 includes an observation ADC 430. The transmit path 462 may also include additional components such as a PA, etc. The DAC 410 generates an analog output signal based on input digital data 402. The DAC 410 operates based on the sampling clock 404 at the sampling frequency fs. The observation ADC 430 in the observation path 464 is coupled to the transmit path 462, e.g., to the output of the DAC 410 for observing the output of the DAC 410 or other components in the transmit path 462. The output of the DAC 410 may be filtered by a filter 420 before being supplied to the observation ADC 430. The output 409 of the observation ADC 430 and the input digital data 402 may be processed by the post-processing unit 440. By comparing the (ideal) input digital data 402 of the DAC 410 with the output 409 of the observation ADC 430, the non-idealities (non-linearities) of the DAC 410 (or other components of the transmit chain 462) can be measured.

[0041] The sampling clock for the observation ADC 430 is derived from the observation clock 404 by the clock phase selection circuitry 450. In this example, the DAC 410 and the observation ADC 430 are clocked by the same sampling clock. The observation ADC 430 may be clocked with multiple different phases of the observation clock 404. The clock phase selection circuitry 450 may provide a sampling clock to the observation ADC 430 with a programmable sampling clock phase (i.e., a sampling clock with different phases). For example, a multiplexer 452 may be used to select either the observation clock 404 or an inverted version of the observation clock 404 by an inverter 454 based on the phase selection signal 408 such that the observation ADC 430 may sample the output of the DAC 410 either at rising edges and / or falling edges of the observation clock 404. In this example way, the observation ADC 430 may be clocked with multiple different phases of the observation clock 404.

[0042] The programming of the observation ADC clock phase in the clock phase selection circuitry 450 defines which clock edge (e.g., rising or falling edges) of the observation clock 404 will be used in the observation ADC 430. This defines the timing grid of the sampling clock. In this example, the timing grid of the sampling clock can be shifted by half a clock period, yielding doubling of the observation bandwidth of the ADC 430 (assuming the ADC frontend is not bandwidth limiting).

[0043] FIGS. 5A-5D show an example sampling clock and a transmitter signal and observation samples captured on different sampling clock edges in a system shown in FIG. 4. FIG. 5 A shows the sampling clock / observation clock 404 for the DAC 410 and the observation ADC 430. As explained above with reference to FIG. 4, the observation ADC 430 is fed with the observation clock 404 or an inverted version of the observation clock 404 such that the ADC 430 captures the output of the DAC 410 either at the rising edge or the falling edge of the observation clock 404. FIG. 5B shows the output signal 506 of the DAC 410 with observation samples captured on the rising clock edges. FIG. 5C shows the output signal 506 of the DAC 410 with observation samples captured on the falling clock edges. FIG. 5D shows the output signal 506 of the DAC 410 with the observation samples captured on varying sampling clock edges. In FIG. 5D, the first set of samples 502 are captured on the falling clock edges of the observation clock 404 and the second set of samples 504 are captured on the rising clock edges of the observation clock 404.

[0044] It can be shown that even with sub-sampling data by the observation ADC the entire spectral information of the transmit system in one particular Nyquist zone can be captured, if enough observation samples are recorded and post-processed together with the corresponding ideal (digital) input data of the DAC. It can also be shown that capturing samples on twodifferent clock edges (e.g., with one clock edge for a first set of samples and the other clock edge for a second set of samples) yields the entire information within a bandwidth of twice the sampling clock frequency, if enough samples are recorded and are post-processed together with the corresponding ideal digital input data.

[0045] FIG. 6 shows an example system including a DAC and a sub-sampling observation ADC with a programmable clock phase. The system 600 includes a transmit path 662 and an observation path 664. The transmit path 662 includes a DAC 610 and the observation path 664 includes an observation ADC 630. The transmit path 662 may also include additional components such as a PA, etc. The DAC 610 generates an analog output signal based on input digital data 602. The DAC 610 operates based on the sampling clock / observation clock 604 at the sampling frequency fs. The observation ADC 630 in the observation path 664 is coupled to the transmit path 662, e.g., to the output of the DAC 610 for observing the output of the DAC 610. The output of the DAC 610 may be filtered by a filter 620 before being supplied to the observation ADC 630. The output 609 of the observation ADC 630 and the input digital data 602 may be processed by the post-processing unit 640. By comparing the (ideal) input digital data 602 of the DAC 610 with the output 609 of the observation ADC 630, the non-idealities (non-linearities) of the DAC 610 (or other components of the transmit chain) can be measured.

[0046] A sampling clock for the observation ADC 630 is derived from the observation clock 604 by the clock phase selection circuitry 650. In this example, the DAC 610 and the observation ADC 630 are fed with the same sampling clock (i.e., the clock 604). The observation ADC 630 may be clocked with multiple different phases of the observation clock 604 but at a lower rate than the sampling frequency of the DAC 610. The clock phase selection circuitry 650 may provide a sampling clock to the observation ADC 630 with a programmable sampling clock phase (i.e., a sampling clock with different phases). For example, a multiplexer 652 may be used to select either the observation clock 604 or an inverted version of the observation clock 604 by an inverter 654 based on the phase selection signal 608 such that the observation ADC 630 may sample the output of the DAC 610 either at rising edges and / or falling edges of the observation clock 604. In this way, the observation ADC 630 may be clocked with multiple different phases of the observation clock 604.

[0047] In this example, the clock phase selection circuitry 650 further includes a divider 670 for dividing the sampling clock. The divider 670 may lower the sampling rate of the observation ADC 630 based on the divider programming signal 612. The divider 670 may be placed at the output of the multiplexer 652 as shown in FIG. 6 or alternatively at the input of the multiplexer 652.

[0048] In some examples, the divider 670 between the clock phase selection circuitry 650 and the observation ADC 630 may have a divider ratio that varies over time, which can yield irregularly sub-sampling the output of the DAC 610 over time. The programming of the observation ADC clock phase in the clock phase selection circuitry 650 defines which clock edge (e.g., rising or falling edges) of the sampling clock will be used. This defines the timing grid of the sampling clock. In this example, the timing grid of the sampling clock can be shifted by half a clock period, yielding the virtual doubling of the observation bandwidth of the ADC (assuming the ADC frontend is not bandwidth limiting).

[0049] The examples are not limited to two different clock phases but can be further extended to N clock phases. FIG. 7 shows an example system including a DAC 710 and an observation ADC 730 with N available clock phases. The system 700 includes a transmit path 762 and an observation path 764. The transmit path 762 includes a DAC 710 and the observation path 764 includes an observation ADC 730. The transmit path 762 may also include additional components such as a PA, etc. The DAC 710 generates an analog output signal based on input digital data 702. The DAC 710 operates based on the sampling clock 704 at the sampling frequency fs. The observation ADC 730 in the observation path 764 is coupled to the transmit path 762, e.g., to the output of the DAC 710 for observing the output of the DAC 710. The output of the DAC 710 may be filtered by a filter 720 before being supplied to the observation ADC 730. The output 709 of the observation ADC 730 and the input digital data 702 may be processed by the post-processing unit 740. By comparing the (ideal) input digital data 702 of the DAC 710 with the output 709 of the observation ADC 730, the non-idealities (nonlinearities) of the DAC 710 (or other components of the transmit chain) can be measured.

[0050] A sampling clock for the observation ADC 730 is derived from the observation clock 706 by the clock phase selection circuitry 750. The observation clock 706 may be same as the sampling clock 704 or may be different. The observation ADC 730 may be clocked with multiple different phases of the observation clock 706. The clock phase selection circuitry 750 may provide a sampling clock to the observation ADC 730 with a programmable sampling clock phase (i.e., a sampling clock with different phases).

[0051] In this example, the clock phase selection circuitry 750 provides a sampling clock with N different phases to the observation ADC 730. For example, the clock phase selection circuitry 750 may include an N-phase generation circuit 754 that is configured to generate N different phases from the observation clock 706, and one of the N different phases of the observation clock signal may be selected by the multiplexer 752 based on the phase selection signal 708.

[0052] The N-phase generation circuit 754 may be an in-phase / quadrature (I / Q) phase generation circuit, a phase interpolator, a digital-to-time converter (DTC), or the like that is configured to generate N different phases from the observation clock 706. An I / Q phase generation circuit may generate clocks in quadrature phase shifts. A phase interpolator is a circuit that can adjust the phase of a sampling clock in very fine increments. N equally spaced clocks may be generated by the phase interpolator. A DTC controls a time delay of an input signal by a digital code. The DTC may generate a sampling clock for the observation ADC 730 at a specific phase. When using a DTC, the N-phase generation and the phase selection may be combined in which only the phase shift would be programmed.

[0053] The programming of the observation ADC clock phase in the clock phase selection circuitry 750 defines which one of the N clock edges of the observation clock 706 will be used in the observation ADC 730. This defines the timing grid of the sampling clock. In this example, the timing grid of the sampling clock can be shifted by a fraction of the clock period.

[0054] Examples for estimating a timing skew between multiple clock phases used for the observation ADC based on digital post-processing are explained hereafter. A timing skew may occur between the multiple clock phases of the sampling clock to the observation ADC. A timing skew of the sampling clock is the difference of the actual time instant of the sampling clock compared to the ideal time instant of the sampling clock. The generation of sampling clocks with different phases for the observation ADC may not yield ideal phase shifts. For example, in the example of using rising and falling clock edges of the observation clock, the duty cycle of the sampling clock might not be exactly 50%. The result would be a timing skew of one clock edge relative to the other. This can impact the observation ADC results. This timing skew, if known, can be corrected in the digital domain, or trimmed in analog fashion (with a discrete phase shift circuit) to have the observation samples time-aligned with the ideal occurrence of the clock edge.

[0055] In order to get an estimate of the timing skew between different phase shifts of the observation clock, the following methods may be used. FIG. 8 shows a model for an example transmit system including a DAC and an observation ADC and digital post-processing for estimating the timing skew between the clock phases. It should be noted that the observation ADC uses sub-sampling in FIG. 8. However, the example is not limited to using sub-sampling, but a full-rate ADC may also be used. It should also be noted that the example will be explained with reference to the case using two observation sampling clock phases (e.g., rising and falling edges of an observation clock). However, the examples can be extended to more than two clock phases.

[0056] The system 800 includes a transmit path 862 and an observation path 864. The transmit path 862 includes a DAC 810 and the observation path 864 includes an observation ADC 830. The transmit path 862 may also include additional components such as a PA, etc. The DAC 810 generates an analog output signal based on input digital data 802. The DAC 810 operates based on the sampling clock at the sampling frequency fs. The observation ADC 830 in the observation path 864 is coupled to the transmit path 862 to observe the analog signal at the observation point in the transmit path 862, e.g., to the output of the DAC 810 for observing the output of the DAC 810. The output 809 of the observation ADC 830 and the input digital data 802 may be processed by the post-processing unit 840.

[0057] The block 805 represents the linear transfer function HLin(s) of the channel from the input of the DAC 810 (more generally, from the input of the component(s) to be observed in the transmit chain) to the output of the observation ADC 830. The linear transfer function HLin(s) can be estimated by post-processing the output of the observation ADC 830 and the ideal input digital data 802 to the DAC 810. The output yo(z) of the observation ADC 830 and the input digital data yi(z) processed by the digital filter 842 and sub-sampling (if the ADC employs sub-sampling) are compared and the error e(z) is fed back to the digital filter 842 (an adaptive filter) to adjust the coefficients of the digital filter 842. For example, least mean square (LMS) optimization of a digital filter HLin(z) may be performed to get a discrete-time estimate of HLin(s). This may also be done on irregularly sub-sampled observation data. The transfer function HLin(s) from the input of the DAC 810 to the output of the observation ADC 830 may be estimated as follows:Equation (1)

[0058] The estimation of the linear transfer function is performed for all observation sampling clock phases, e.g., rising and falling clock edges, as follows: Equation (2)Equation (3)

[0059] The fast Fourier transform (FFT) of the linear transfer function impulse response is calculated for both clock phases to generate frequency domain channel coefficients Cphi and Cph2 for the two clock phases as follows:Equation (4)Cph2 = FFT hUn ph2k) Equation (5)

[0060] The differential phase between the two transfer functions is calculated out of the frequency domain channel coefficients of the impulse responses as follows:Cphi.k = AkelEquation (6)

[0061] The term AT denotes the timing skew between the clock phases and is treated as an additive term to the channel coefficient phase. Out of this relationship, AT can be calculated as a weighted sum of the differential phases as follows: Equation (10)

[0062] Additional weighting of the channel coefficients can be done to limit the estimation of the timing skew to frequencies that have relevant signal content. For example, in a system with a band limited signal one might only observe the band limited signal for the estimation of the timing skew and neglect all other frequencies, avoiding dynamic range problems in the estimation.

[0063] Once the timing skew of the sampling clock phases is determined (estimated), the determined timing skew may be used to either digitally correct for the inaccuracy of the observation ADC output samples or to trim the observation ADC sampling clock phase timing, or both (e.g., coarse analog trim of the observation ADC sampling clock phases, and fine digital trim in the digital backend). As a consequence, since the timing skew between the observation ADC sampling clock phases does not have to be perfect to begin with, the implementation of the clock phase generation for the observation ADC can be drastically simplified, saving area and power.

[0064] The above method for estimating the timing skew can be extended to more than two clock phases. To extend the estimation to more than two clock phases, the above timing skewestimation may be sequentially repeated for every clock phase, e.g., calculating the relative timing skew between the n-th clock phase and the first clock phase.

[0065] The above example for timing skew estimation is not limited to estimating the timing skew of sampling phases within the observation ADC. The above example scheme can be applied to estimating timing skew of sampling clock phases in a time-interleaved DAC or time-interleaved ADC. The basic requirement is that there is a known input sequence, based on which a linear transfer function can be calculated.

[0066] FIG. 9 shows an example time-interleaved (TI)-DAC with an observation ADC. Time-interleaving of DACs is a way to increase the overall system sampling rate by using several DACs (sub-DACs) in parallel. A TI-DAC includes two or more sub-DACs (M sub- DACs) coupled in parallel. The example TI-DAC 910 shown in FIG. 9 includes two sub-DACs 910a, 910b but the TI-DAC may include more than two sub-DACs. Both sub-DACs 910a, 910b are provided with the same sampling clock 904 at frequency fs, but the sampling clock to one of the sub-DACs 910a, 910b is inverted such that the sub-DACs 910a, 910b operate with the same sampling clock but in the opposite phase. Each sub-DAC 910a, 910b generates an analog output signal based on respective input digital data 902a, 902b at different time instances.

[0067] An observation ADC 930 is coupled to the output of the sub-DACs 910a, 910b for observing the output of the TI-DAC 910. The output of the TI-DAC 910 may be filtered by a filter 920 before being supplied to the observation ADC 930. The output 909 of the observation ADC 930 and the input digital data 902a, 902b may be processed by the post-processing unit 940. By comparing the (ideal) input digital data 902a, 902b of the sub-DACs 910a, 910b with the corresponding output 909 of the observation ADC 930, the non-idealities (non-linearities) of the sub-DACs 910a, 910b (or other components of the transmit chain) and the timing skew of the sampling clock 904 in different phases for the sub-DACs 910a, 910b can be measured.

[0068] Assuming that the two sub-DACs 910a, 910b of the TI-DAC 900 can be operated independently, two independent captures for the two sub-DACs 910a, 910b can be made with the observation ADC 930. The observation ADC 930 may be a full-rate ADC or sub-sampling ADC as described above. For example, in a first step, the output of the sub-DAC 910a operated on the rising edge of the sampling clock 904 is captured while the input digital data 902a (datacik) is active and the input digital data 902b(datacikb) is inactive. In a second step, the output of the sub-DAC 910b operated on the falling edge of the sampling clock 904 is captured while the input data 902a (datacik) is inactive and the input data 902b (datacikb) is active. Both sub- DACs 910a, 910b may have a similar transfer function up to the observation ADC 930, except for the time delay introduced by the two different sampling edges of the sampling clock 904 forthe two sub-DACs 910a, 910b. Applying the same principle of estimating two linear transfer functions disclosed above, one per sub-DAC, the timing skew between the time-interleaved sub-DACs can be estimated, similar to the above-described method for estimating the timing skew for different clock phases in the observation ADC. The timing skew information can then be used to trim the sampling clock phases of the TI-DAC, or to digitally correct the DAC input data, or both.

[0069] In some examples, the TI-DAC 910 in FIG. 9 may be a segmented DAC including two or more sub-DACs operating with the sample sampling clock, and the sub-DACs 910a, 910b may be two sub-DACs of the segmented DAC, such as a most-significant bit (MSB) segment and a least significant bit (LSM) segment. The sub-DACs of the segmented DAC may operate with the same sampling clock, but a timing skew may be incurred between the sampling clocks supplied to the sub-DACs of the segmented DAC. The examples disclosed above may be applied to estimate and correct the timing skew between the sampling clocks provided to the sub-DACs of the segmented DAC.

[0070] In some examples, the above-disclosed two approaches (i.e., using different sampling clock edges on the observation ADC, and independently operating a set of sub-DACs on multiple DAC sampling clock phases (e.g., time-interleaved DAC)) may be combined. In that case, the identification of the timing skew errors may be first performed at the observation ADC (with one of the sub-DACs as a reference signal source), and once the (potentially irregularly sampling) observation ADC has the timing skews of its multiple sampling clock edges calibrated, the timing skew calibration of the sub-DAC sampling clock phases may be performed.

[0071] FIG. 10 is a flow diagram of an example method for observation of a transmit path in a transmitter. A plurality of different phases of an observation clock are generated (1002). The observation clock may be same as a sampling clock for a DAC in the transmit path. Alternatively, the observation clock may be derived from the sampling clock for the DAC. The observation clock in one of the plurality of different phases is provided to an ADC in an observation path as a sampling clock for the ADC (1004). An analog signal is sampled by the ADC at an observation point in a transmit path based on the sampling clock such that the analog signal is sampled by the ADC at two or more different phases of the observation clock (1006).

[0072] In some examples, the sampling clock for the ADC may be divided to a lower rate than the observation clock. In some examples, N different phases of the observation clock may be generated and one of the N different phases of the observation clock may be selected based on a phase selection signal. In some examples, the observation clock may be inverted and eitherthe observation clock or the inverted observation clock may be selected based on a phase selection signal. The sampled analog signal and the corresponding input digital data in the transmit path may be processed to determine non-linearity of at least one component in the transmit path.

[0073] In some examples, the method may further include a step that the sampled analog signal and the corresponding input digital data in the transmit path are processed to determine a timing skew between the sampling clock in different phases. In one example, the timing skew is determined by estimating a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the ADC for the two or more different clock phases of the observation clock and determining the timing skew based on the frequency domain channel responses for different phases of the sampling clock.

[0074] FIG. 11 is a flow diagram of an example method for estimating a timing skew between different sampling clock phases. It should also be noted that the method will be explained with reference to the case using two sampling clock phases, but the examples can be extended to more than two clock phases. An analog signal at an observation point in a transmit chain may be sampled (digitized) by an observation ADC (1102). The output of the observation ADC and corresponding input digital data in the transmit chain may be processed to determine a timing skew between different phases of a sampling clock used for the observation ADC or sub-DACs in the transmit chain (1104). The observation ADC or the sub-DACs in the transmit chain are clocked by the same sampling clock in two or more different phases such that the analog signal is sampled by the observation ADC, or the sub-DACs generate the analog signal, at two or more different phases of the sampling clock. For example, a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the observation ADC may be estimated for the two or more different clock phases of the sampling clock. The timing skew may then be determined based on the frequency domain channel responses of the channel.

[0075] FIG. 12 illustrates a user device 1200 in which the examples disclosed herein may be implemented. For example, the examples disclosed herein may be implemented in the radio front-end module 1215, in the baseband module 1210, etc. The user device 1200 may be a mobile device in some aspects and includes an application processor 1205, baseband processor 1210 (also referred to as a baseband module), radio front end module (RFEM) 1215, memory 1220, connectivity module 1225, near field communication (NFC) controller 1230, audio driver 1235, camera driver 1240, touch screen 1245, display driver 1250, sensors 1255, removable memory 1260, power management integrated circuit (PMIC) 1265 and smart battery 1270.

[0076] In some aspects, application processor 1205 may include, for example, one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as serial peripheral interface (SPI), inter-integrated circuit (I2C) or universal programmable serial interface module, real time clock (RTC), timercounters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as secure digital / multi-media card (SD / MMC) or similar, universal serial bus (USB) interfaces, mobile industry processor interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.

[0077] In some aspects, baseband module 1210 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and / or a multi-chip module containing two or more integrated circuits.

[0078] FIG. 13 illustrates a base station or infrastructure equipment radio head 1300 in which the examples disclosed herein may be implemented. For example, the examples disclosed herein may be implemented in the radio front-end module 1315, in the baseband module 1310, etc. The base station radio head 1300 may include one or more of application processor 1305, baseband modules 1310, one or more radio front end modules 1315, memory 1320, power management circuitry 1325, power tee circuitry 1330, network controller 1335, network interface connector 1340, satellite navigation receiver module 1345, and user interface 1350.

[0079] In some aspects, application processor 1305 may include one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD / MMC or similar, USB interfaces, MIPI interfaces and Joint Test Access Group (JTAG) test access ports.

[0080] In some aspects, baseband processor 1310 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.

[0081] In some aspects, memory 1320 may include one or more of volatile memory including dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magneto resistive random access memory (MRAM) and / or a three-dimensional crosspoint memory. Memory 1320 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

[0082] In some aspects, power management integrated circuitry 1325 may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

[0083] In some aspects, power tee circuitry 1330 may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station radio head 1300 using a single cable.

[0084] In some aspects, network controller 1335 may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

[0085] In some aspects, satellite navigation receiver module 1345 may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the global positioning system (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo and / or BeiDou. The receiver 1345 may provide data to application processor 1305 which may include one or more of position data or time data. Application processor 1305 may use time data to synchronize operations with other radio base stations.

[0086] In some aspects, user interface 1350 may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as light emitting diodes (LEDs) and a display screen.

[0087] Another example is a computer program having a program code for performing at least one of the methods described herein, when the computer program is executed on a computer, a processor, or a programmable hardware component. Another example is a machine-readable storage including machine readable instructions, when executed, to implement a method or realize an apparatus as described herein. A further example is a machine-readable medium including code, when executed, to cause a machine to perform any of the methods described herein.

[0088] The examples as described herein may be summarized as follows:

[0089] An example (e.g., example 1) relates to an apparatus for observation of a transmit path. The apparatus may include an ADC configured to sample an analog signal at an observation point in a transmit path, and clock phase selection circuitry configured to provide a sampling clock to the ADC. The clock phase selection circuitry is configured to generate aplurality of different phases of an observation clock and provide the observation clock in two or more different phases as the sampling clock to the ADC such that the analog signal is sampled by the ADC at two or more different phases of the observation clock.

[0090] Another example, (e.g., example 2) relates to a previously described example (e.g., example 1), wherein the clock phase selection circuitry includes a clock divider configured to divide the sampling clock to a lower rate than the observation clock.

[0091] Another example, (e.g., example 3) relates to a previously described example (e.g., any one of examples 1-2), wherein the clock phase selection circuitry may include an N-phase generation circuit configured to generate N different phases of the observation clock, and a multiplexer configured to select one of the N different phases of the observation clock as the sampling clock for the ADC based on a phase selection signal.

[0092] Another example, (e.g., example 4) relates to a previously described example (e.g., any one of examples 1-3), wherein the clock phase selection circuitry may include an inverter configured to invert the observation clock, and a multiplexer configured to select either the observation clock or an inverted observation clock based on a phase selection signal.

[0093] Another example, (e.g., example 5) relates to a previously described example (e.g., any one of examples 1-4), wherein the observation clock is the same as a sampling clock for a DAC in the transmit path that is configured to generate the analog signal based on the input digital data.

[0094] Another example, (e.g., example 6) relates to a previously described example (e.g., any one of examples 1-5), further comprising post-processing circuitry configured to process an output of the ADC and input digital data in the transmit path.

[0095] Another example, (e.g., example 7) relates to a previously described example (e.g., example 6), wherein the post-processing circuitry is configured to estimate a timing skew between the sampling clock in different phases.

[0096] Another example, (e.g., example 8) relates to a previously described example (e.g., example 7), wherein the post-processing circuitry is configured to estimate a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the ADC for the two or more different clock phases of the observation clock and determine the timing skew based on the frequency domain channel responses for different phases of the sampling clock.

[0097] Another example, (e.g., example 9) relates to an apparatus for estimating a timing skew between different phases of a sampling clock. The apparatus may include an observation ADC configured to sample an analog signal at an observation point in a transmit chain, andpost-processing circuitry configured to process an output of the observation ADC and corresponding input digital data in the transmit chain to determine a timing skew between different phases of a sampling clock used for the observation ADC or sub-DACs in the transmit chain. The observation ADC or the sub-DACs in the transmit chain are clocked by the sampling clock in two or more different phases such that the analog signal is sampled by the observation ADC, or the sub-DACs generate the analog signal, at two or more different phases of the sampling clock.

[0098] Another example, (e.g., example 10) relates to a previously described example (e.g., example 9), wherein the post-processing circuitry is configured to estimate a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the observation ADC for the two or more different clock phases of the sampling clock and determine the timing skew based on the frequency domain channel responses of the channel.

[0099] Another example, (e.g., example 11) relates to a method for observation of a transmit path in a transmitter. The method may include generating a plurality of different phases of an observation clock, providing the observation clock in one of the plurality of different phases to an ADC in an observation path as a sampling clock for the ADC, and sampling, by the ADC, an analog signal at an observation point in a transmit path based on the sampling clock such that the analog signal is sampled by the ADC at two or more different phases of the observation clock.

[0100] Another example, (e.g., example 12) relates to a previously described example (e.g., example 11), wherein the method may further include dividing the sampling clock for the ADC to a lower rate than the observation clock.

[0101] Another example, (e.g., example 13) relates to a previously described example (e.g., any one of examples 11-12), wherein the sampling clock is generated by generating N different phases of the observation clock and selecting one of the N different phases of the observation clock based on a phase selection signal.

[0102] Another example, (e.g., example 14) relates to a previously described example (e.g., any one of examples 11-13), wherein the sampling clock is generated by inverting the observation clock, and selecting either the observation clock or an inverted observation clock based on a phase selection signal.

[0103] Another example, (e.g., example 15) relates to a previously described example (e.g., any one of examples 11-14), wherein the observation clock is same as a sampling clock for aDAC in the transmit path that is configured to generate the analog signal based on the input digital data.

[0104] Another example, (e.g., example 16) relates to a previously described example (e.g., any one of examples 11-15), further comprising processing the sampled analog signal and corresponding input digital data in the transmit path to determine non-linearity of at least one component in the transmit path.

[0105] Another example, (e.g., example 17) relates to a previously described example (e.g., any one of examples 11-16), further comprising processing the sampled analog signal and corresponding input digital data in the transmit path to determine a timing skew between the sampling clock in different phases.

[0106] Another example, (e.g., example 18) relates to a previously described example (e.g., example 17), wherein the timing skew is determined by estimating a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the ADC for the two or more different clock phases of the observation clock, and determining the timing skew based on the frequency domain channel responses for different phases of the sampling clock.

[0107] Another example, (e.g., example 19) relates to a method for estimating a timing skew between different phases of a sampling clock. The method may include sampling, by an observation ADC, an analog signal at an observation point in a transmit chain, and processing an output of the observation ADC and corresponding input digital data in the transmit chain to determine a timing skew between different phases of a sampling clock used for the observation ADC or sub-DACs in the transmit chain. The observation ADC or the sub-DACs in the transmit chain are clocked by the sampling clock in two or more different phases such that the analog signal is sampled by the observation ADC, or the sub-DACs generate the analog signal, at two or more different phases of the sampling clock.

[0108] Another example, (e.g., example 20) relates to a previously described example (e.g., example 19), wherein the method may further include estimating a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the observation ADC for the two or more different clock phases of the sampling clock, wherein the timing skew is determined based on the frequency domain channel responses of the channel.

[0109] The aspects and features mentioned and described together with one or more of the previously detailed examples and figures, may as well be combined with one or more of theother examples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

[0110] Examples may further be or relate to a computer program having a program code for performing one or more of the above methods, when the computer program is executed on a computer or processor. Steps, operations or processes of various above-described methods may be performed by programmed computers or processors. Examples may also cover program storage devices such as digital data storage media, which are machine, processor or computer readable and encode machine-executable, processor-executable or computer-executable programs of instructions. The instructions perform or cause performing some or all of the acts of the above-described methods. The program storage devices may comprise or be, for instance, digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard drives, or optically readable digital data storage media. Further examples may also cover computers, processors or control units programmed to perform the acts of the above-described methods or (field) programmable logic arrays ((F)PLAs) or (field) programmable gate arrays ((F)PGAs), programmed to perform the acts of the above-described methods.

[0111] The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0112] A functional block denoted as “means for ...” performing a certain function may refer to a circuit that is configured to perform a certain function. Hence, a “means for s.th.” may be implemented as a “means configured to or suited for s.th ”, such as a device or a circuit configured to or suited for the respective task.

[0113] Functions of various elements shown in the figures, including any functional blocks labeled as “means”, “means for providing a sensor signal”, “means for generating a transmit signal ”, etc., may be implemented in the form of dedicated hardware, such as “a signal provider”, “a signal processing unit”, “a processor”, “a controller”, etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term “processor” or “controller” is by far not limited to hardware exclusively capable of executing software but may include digital signal processor (DSP)hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and / or custom, may also be included.

[0114] A block diagram may, for instance, illustrate a high-level circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.

[0115] It is to be understood that the disclosure of multiple acts, processes, operations, steps or functions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

[0116] Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that - although a dependent claim may refer in the claims to a specific combination with one or more other claims - other examples may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.

Claims

Claims1. An apparatus for observation of a transmit path, comprising: an analog-to-digital converter (ADC) configured to sample an analog signal at an observation point in a transmit path; and clock phase selection circuitry configured to provide a sampling clock to the ADC, wherein the clock phase selection circuitry is configured to generate a plurality of different phases of an observation clock and provide the observation clock in two or more different phases as the sampling clock to the ADC such that the analog signal is sampled by the ADC at two or more different phases of the observation clock.

2. The apparatus of claim 1, wherein the clock phase selection circuitry includes a clock divider configured to divide the sampling clock to a lower rate than the observation clock.

3. The apparatus as in any one of claims 1-2, wherein the clock phase selection circuitry comprises: an N-phase generation circuit configured to generate N different phases of the observation clock; and a multiplexer configured to select one of the N different phases of the observation clock as the sampling clock for the ADC based on a phase selection signal.

4. The apparatus as in any one of claims 1-3, wherein the clock phase selection circuitry comprises: an inverter configured to invert the observation clock; and a multiplexer configured to select either the observation clock or an inverted observation clock based on a phase selection signal.

5. The apparatus as in any one of claims 1-4, wherein the observation clock is the same as a sampling clock for a digital-to-analog converter (DAC) in the transmit path that is configured to generate the analog signal based on the input digital data.

6. The apparatus as in any one of claims 1-5, further comprising post-processing circuitry configured to process an output of the ADC and input digital data in the transmit path.

7. The apparatus of claim 6, wherein the post-processing circuitry is configured to estimate a timing skew between the sampling clock in different phases.

8. The apparatus of claim 7, wherein the post-processing circuitry is configured to estimate a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the ADC for the two or more different clock phases of the observation clock and determine the timing skew based on the frequency domain channel responses for different phases of the sampling clock.

9. An apparatus for estimating a timing skew between different phases of a sampling clock, comprising: an observation analog-to-digital converter (ADC) configured to sample an analog signal at an observation point in a transmit chain; and post-processing circuitry configured to process an output of the observation ADC and corresponding input digital data in the transmit chain to determine a timing skew between different phases of a sampling clock used for the observation ADC or sub-digital-to-analog converters (DACs) in the transmit chain, wherein the observation ADC or the sub-DACs in the transmit chain are clocked by the sampling clock in two or more different phases such that the analog signal is sampled by the observation ADC, or the sub-DACs generate the analog signal, at two or more different phases of the sampling clock.

10. The apparatus of claim 9, wherein the post-processing circuitry is configured to estimate a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the observation ADC for the two or more different clock phases of the sampling clock and determine the timing skew based on the frequency domain channel responses of the channel.

11. A method for observation of a transmit path in a transmitter, comprising: generating a plurality of different phases of an observation clock; providing the observation clock in one of the plurality of different phases to an analog- to-digital converter (ADC) in an observation path as a sampling clock for the ADC; and sampling, by the ADC, an analog signal at an observation point in a transmit path based on the sampling clock such that the analog signal is sampled by the ADC at two or more different phases of the observation clock.

12. The method of claim 11, further comprising: dividing the sampling clock for the ADC to a lower rate than the observation clock.

13. The method as in any one of claims 11-12, wherein the sampling clock is generated by: generating N different phases of the observation clock; and selecting one of the N different phases of the observation clock based on a phase selection signal.

14. The method as in any one of claims 11-13, wherein the sampling clock is generated by: inverting the observation clock; and selecting either the observation clock or an inverted observation clock based on a phase selection signal.

15. The method as in any one of claims 11-14, wherein the observation clock is same as a sampling clock for a digital-to-analog converter (DAC) in the transmit path that is configured to generate the analog signal based on the input digital data.

16. The method as in any one of claims 11-15, further comprising: processing the sampled analog signal and corresponding input digital data in the transmit path to determine non-linearity of at least one component in the transmit path.

17. The method as in any one of claims 11-16, further comprising: processing the sampled analog signal and corresponding input digital data in the transmit path to determine a timing skew between the sampling clock in different phases.

18. The method of claim 17, wherein the timing skew is determined by: estimating a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the ADC for the two or more different clock phases of the observation clock; and determining the timing skew based on the frequency domain channel responses for different phases of the sampling clock.

19. A method for estimating a timing skew between different phases of a sampling clock, comprising: sampling, by an observation analog-to-digital converter (ADC), an analog signal at an observation point in a transmit chain; and processing an output of the observation ADC and corresponding input digital data in the transmit chain to determine a timing skew between different phases of a sampling clock used for the observation ADC or sub-digital-to-analog converters (DACs) in the transmit chain, wherein the observation ADC or the sub-DACs in the transmit chain are clocked by the sampling clock in two or more different phases such that the analog signal is sampled by the observation ADC, or the sub-DACs generate the analog signal, at two or more different phases of the sampling clock.

20. The method of claim 19, comprising estimating a frequency domain channel response of a channel from an input of a component to be observed in the transmit path to an output of the observation ADC for the two or more different clock phases of the sampling clock, wherein the timing skew is determined based on the frequency domain channel responses of the channel.

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