In-SITU carbon liner for improved high aspect ratio ETCH with bow control

Abstract

A method of etching recessed features in a stack below a mask is provided. A plasma formed from an etch gas is provided, wherein the etch gas comprises a halogen containing component. A plasma formed from a sidewall passivation gas is provided, wherein the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component.

Description

IN-SITU CARBON LINER FOR IMPROVED HIGH ASPECT RATIO ETCH WITH BOW CONTROLCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 609,783, filed December 13, 2023, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a carbon containing mask. The stack may be alternating / repeating layers into which the recessed feature is formed, or a thick film of a single layer of material. One example context where such a process may occur is memory applications such as dynamic random access memory (DRAM) and “not and” devices (NAND). Some applications may use stacks of alternating layers of silicon oxide and silicon nitride (ONON). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a carbon containing mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and / or deep depths.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a stack below a mask is provided. A plasma is formed from an etch gas, wherein the etch gas comprises a halogen containing component. A plasma formed from a sidewall passivation gas is provided, wherein the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component.

[0005] In another manifestation, a method of etching recessed features in a stack below a patterned mask forming mask features is provided. An etch gas is provided, wherein the etch gas comprises a halogen containing component. A sidewall passivation gas is provided, wherein thesidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component. The etch gas and sidewall passivation gas are transformed into a plasma by providing a multistate pulsed RF power with two or three states. The stack is exposed to the plasma.

[0006] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0008] FIG. 1 depicts a flow chart describing a method of etching recessed features into a stack below a mask according to various embodiments.

[0009] FIGS. 2A-2D illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.

[0010] FIGS. 3A-D illustrate enlarged views of sidewalls of features, shown in FIG. 2B or FIG. 2C.

[0011] FIG. 4 depicts a flow chart describing a method of etching recessed features into a stack below a mask according to various embodiments.

[0012] FIG. 5 shows a semiconductor processing system that may be used in some embodiments.

[0013] FIG. 6 illustrates a computer system for implementing a controller used in some embodiments.

[0014] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0015] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and / or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0016] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In various embodiments herein, the stack of materials includes one or more layers of one or more materials below a mask. In some embodiments, at least one layer of the stack contains a silicon containing layer. Silicon containing layers may contain silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxy-carbide, polysilicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon (OPOP). In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films (ONON), or single silicon oxide layer, or single silicon layer. In some embodiments, the stack comprises a silicon nitride containing layer. In some embodiments, the mask is a carbon containing mask, comprising at least one of a photoresist, a doped carbon, and an amorphous carbon mask.

[0017] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the ratio of the depth to the lateral critical dimension. As the aspect ratio of such features continues to increase, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, (7) low etch rate, (8) sidewall passivation clogging, and (9) etch stop.

[0018] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the carbon containing mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspect ratio, which causes more issues during the etching of both mask and underlayer materials.

[0019] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array. When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.

[0020] Non-circularity of the features refers to deviations of the bottom hole shape away froma circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.

[0021] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0022] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0023] Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0024] Sidewall passivation clogging occurs when the sidewall passivation closer to the top of an etch feature closes the etch feature so that etchant is not able to reach the remainder of the feature. Too much deposition nearer to the top of the features may cause clogging.

[0025] Etch stop occurs when the etch process is not able to further etch the bottom of the features. If passivation is formed on the bottoms of the features as fast as or faster than the etch process removes the passivation on the bottoms of the features, etch stop may occur.

[0026] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0027] The techniques described herein may be used to etch recessed features into a stack below without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into a stack below a mask with a high stack to mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, with reduced non-uniformity,reduced asymmetric mask shadowing, and sufficient etch rate, while avoiding clogging and etch stop.

[0028] Current high aspect ratio contact (HARC) etch processes in both DRAM and NAND applications require more sidewall protection with increasing aspect ratios. Traditional carbon polymer protection is not self-limiting and has aspect ratio dependence due to neutral shadowing. Thus, more protection is provided on mask tops rather than on HARC feature sidewalls. The greater protection near the mask tops may cause clogging caused by the protection near the mask tops or increase bowing due to the lack of protection of the feature sidewalls. The resulting HARC bow CD can be large due to ion scattering in deep features.

[0029] Some embodiments provide a method and apparatus for providing high quality carbon sidewall passivation. Such sidewall passivation reduces bowing. Some embodiments reduce lateral etching of silicon nitride containing layers.Partial Etch

[0030] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A stack with a mask is provided in a process chamber (step 104). FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments, where the stack is under a patterned mask 216, such as an organic mask, one example of which would be an amorphous carbon mask. The amorphous carbon mask may also include some amount of hydrogen and / or oxygen. The mask 216 has mask features. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack 204 comprises at least one silicon nitride layer. In some embodiments, the stack is a single bulk layer of silicon nitride. In some embodiments, the stack is a plurality of layers. In some embodiments, the stack is a plurality of bilayers, trilayers, or more multiple layers. In some embodiments, the stack 204 comprises a plurality of bilayers 212, where each bilayer 212 includes a layer of silicon oxide 224 and a layer of silicon nitride 228.

[0031] The stack is partially etched (step 108). A plasma formed from an etch gas is provided, where the etch gas comprises a halogen containing component. In some embodiments, an etch gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside ofthe process chamber and then provided into the process chamber. In some embodiments, the etch gas comprises a fluorine containing component. In some embodiments, the etch gas comprises at least one of phosphorous trifluoride (PF3), phosphorous pentafluoride (PFs), hydrogen fluoride (HF), and carbon fluoride (CF). In some embodiments, the etch gas is provided at a pressure of 1 millitorr to 10 torr. In some embodiments, the pressure provided by the etch gas is less than 200 mTorr during the etch.

[0032] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 5-200 kilowatts (kW), for example between about 10-100 kW, or between about 10-65 kW in some embodiments. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three- frequency RF power may be used to generate the plasma.

[0033] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power level, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RFpower is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-10 kilovolts (kV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. In some embodiments, the pulsing may facilitate the deposition of neutrals.

[0034] In some embodiments, a bias in the range of 0 Watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of the stack 204. In some embodiments, a bias in the range of 100 W to 1 kW is provided.

[0035] The stack 204 is exposed to the plasma causing recessed features to be partially etched into the stack 204. FIG. 2B is a schematic cross-sectional view of a stack 204 after the recessed features 240 have been partially etched. FIG. 3A is an enlarged view of Region IIIA, shown in FIG. 2B, schematically illustrating silicon atoms on the sidewall surface of part of a layer of silicon oxide 224 and a layer of silicon nitride 228.Sidewall Passivation

[0036] Next, a carbon sidewall is deposited on the sidewalls of the recessed features (step 112). A plasma formed from the sidewall passivation gas is provided, where the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component. In some embodiments, a passivation gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the hydrocarbon comprises at least one of methane (CH4), ethane (C2H4), ethyne (C2H2), and alkene (C3H4). In some embodiments, the hydrogen scavenger comprises a halogen containing component, such as at least one of hydrogen chloride (HC1), hydrogen bromide (HBr), hydrogen iodide (HI), chlorine (CI2), bromine (B ), and a hydrofluorocarbon. In some embodiments, the hydrogen scavenger is at least one of CI2 and B . In some embodiments, the hydrogen scavenger is CI2. In some embodiments, the sidewall passivation gas is provided at a pressure of 1 millitorr to 10 torr. In some embodiments, thepressure provided by the sidewall passivation gas is less than 800 mTorr.

[0037] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 5-200 kilowatts (kW), for example between about 10-100 kW, or between about 10-65 kW in some embodiments. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three-frequency RF power may be used to generate the plasma.

[0038] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power level, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-10 kilovolts (kV). The maximum ion energy isdetermined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. In some embodiments, the pulsing may facilitate the deposition of neutrals.

[0039] In some embodiments, a bias in the range of 0 Watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of the stack 204. In some embodiments, a bias in the range of 100 W to 1 kW is provided.

[0040] The stack 204 is exposed to the plasma formed from the passivation gas creating a carbon passivation layer along the sidewalls of the recessed features 240. FIG. 2C is a schematic cross-sectional view of a stack 204 after the carbon sidewall deposition (step 112). The carbon passivation layer 248 is schematically illustrated in order to facilitate understanding. In some embodiments, the carbon passivation layer 248 is deposited conformally along the entire exposed surface of the stack 204, as shown. In some embodiments, the carbon passivation layer 248 has a thickness in the range of 0.1 nm to 20 nm. In some embodiments, the carbon passivation layer 248 deposits on the mask 216 increasing the selectivity of the etch of the stack 204 with respect to the mask 216. FIG. 3B is an enlarged view of Region IIIB, shown in FIG. 2C, schematically illustrating the side wall surface of part of a silicon oxide 224 and a layer of silicon nitride 228. When the plasma is formed from a sidewall passivation gas of CH4 and CI2 species of C-H+and CF may be formed. As shown in FIG. 3B, carbon from the C-H+species may bond to silicon atoms of the layer of silicon oxide 224 and of the layer of silicon nitride 228. FIG. 3C is an enlarged view of Region IIIB, schematically illustrating how the Cl" species scavenges H+, leaving carbon bound to silicon. FIG. 3D is an enlarged view of Region IIIB, schematically illustrating carbon from the C-H+species may bond to carbon forming part of a carbon passivation layer 248. The process is continued until the carbon passivation layer 248 reaches a desired thickness.Further Etch

[0041] A plasma formed from an etch gas is provided, where the etch gas comprises a halogen containing component. In some embodiments, an etch gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the etch gas comprises a fluorine containingcomponent. In some embodiments, the etch gas comprises at least one of phosphorous trifluoride (PF3), phosphorous pentafluoride (PF5), hydrogen fluoride (HF), and carbon fluoride (CF). In some embodiments, the etch gas is provided at a pressure of 1 millitorr to 10 torr. In some embodiments, the pressure provided by the etch gas is less than 200 mTorr.

[0042] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 5-200 kilowatts (kW), for example between about 10-100 kW, or between about 10-65 kW in some embodiments. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three- frequency RF power may be used to generate the plasma.

[0043] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power level, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW orlower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-10 kilovolts (kV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. In some embodiments, the pulsing may facilitate the deposition of neutrals.

[0044] In some embodiments, a bias in the range of 0 Watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of the stack 204. In some embodiments, a bias in the range of 100 W to 1 kW is provided.

[0045] The stack 204 is exposed to the plasma causing recessed features to be further etched into the stack 204. The carbon passivation layer 248 prevents or reduces the further etch of the sidewalls of the recessed features 240 in order to prevent or reduce bowing. FIG. 2D is a schematic cross-sectional view of the stack 204 after the stack 204 is further etched (step 116). The carbon passivation layer 248 (shown in FIG. 2C) has been etched away. In some embodiments, the carbon passivation layer 248 may be removed before the etch is completed. In such cases, it is determined that in order to etch more (step 120) the process returns back to the carbon sidewall deposition (step 112). If the etch of the stack 204 is complete (step 120), then the stack 204 may be removed from the substrate support of the process chamber (step 124). In some embodiments, additional steps, such as removing the carbon passivation layer 248 may be performed before the stack 204 is removed from the process chamber (step 124).

[0046] In some embodiments, the substrate is placed on a substrate support in a process chamber. In some embodiments, the substrate support is cooled to a temperature below 0° C. In some embodiments, the partial etch (step 108), the carbon sidewall deposition (step 112), and the further etch (step 1 16) are performed in-situ in the same chamber and mounted on the same substrate support. The ability to perform the process in-situ allows for faster throughput, less contamination, and a wider process window. Some embodiments largely widen the current process window without triggering other tradeoffs by providing more robust sidewall protection.Simultaneous Etch and Passivation Embodiments

[0047] Instead of sequentially etching and passivating, some embodiments may simultaneously etch and passivate. FIG. 3 is a high level flow chart of a process used in some embodiments where etching and passivating are performed simultaneously. A stack with a maskis provided in a process chamber (step 404). The stack is simultaneously etched while forming a carbon passivation layer (step 408). In order to simultaneously etch and form a carbon passivation layer, a plasma formed from an etch gas, where the etch gas comprises a halogen containing component, and a plasma formed from a sidewall passivation gas, where the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component are simultaneously provided. In some embodiments, the etch gas and the sidewall passivation gas are provided and then formed into a plasma. In some embodiments, a remote plasma formed from the etch gas and a remote plasma formed from the sidewall passivation gas are flowed into the process chamber. The simultaneous etching and depositing of the sidewall passivation layer allows for features to be etched while preventing lateral etching and bowing.Cyclical Process Using RF Pulsing

[0048] In some embodiments providing a cyclical process, instead of cyclically pulsing or switching between etch gases and sidewall passivation gases in order to switch between etching and sidewall passivation deposition, the RF power and / or bias power may be pulsed to cause switching between the etching and sidewall passivation deposition. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1 % to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power level, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non-zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-10 kilovolts (kV).

[0049] In some embodiments, the etching and passivating are performed simultaneously by providing the etch gases and sidewall passivation gases simultaneously and additional etching oradditional passivating is pulsed. For example, a simultaneous etching and passivation may be provided, where an additional passivation is pulsed. The additional pulsed passivation may be provided by intermittently increasing the flow of sidewall passivation gases and / or by pulsing the RF and / or bias power. In other embodiments, a simultaneous etching and passivation may be provided, where an additional etching is pulsed. The additional pulsed etching may be provided by intermittently increasing the flow of the etch gases and / or by pulsing the RF and / or bias power.

[0050] Some embodiments provide a high quality carbon rich carbon sidewall passivation. In some embodiments, the high quality carbon rich sidewall passivation is more than 50% carbon by number of moles. In some embodiments, the high quality carbon rich sidewall passivation consists essentially of carbon and hydrogen. In some embodiments, the high quality carbon sidewall passivation has less than 20% hydrogen by number of moles. The use of a hydrogen scavenger reduces the amount of hydrogen in the sidewall passivation layer. By reducing the amount of hydrogen in the sidewall passivation layer the lateral etch of silicon nitride caused by hydrogen is reduced. The reduction of lateral etch provided by the reduction of hydrogen and by the etch resistance of the high quality carbon rich carbon sidewall passivation layer allows for a higher aspect ratio etch. The increased etch selectivity provided by the carbon deposition on the mask further allows for higher aspect ratios and improved resolution provided by allowing thinner masks.

[0051] In some embodiments, the ratio of the hydrocarbon to the hydrogen scavenger, the RF power, the bias power, the pressure, temperature, total gas flow, ratio of etch gas to passivation gas, process time, etch time versus passivation time, and other parameters may be used to optimize the process, such as prevent clogging and etch stop during the formation of the sidewall passivation, by precisely controlling deposition depth and hydrogen percentage.

[0052] One application for the disclosed methods is in the context of forming a vertical NAND. In this case, the material into which the feature is etched may have a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride. In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20- 1000 individual layers). The feature etched into the stack of layers may have a depth between about 2-15 pm, for example between about 5-9 pm. The feature may have a CD width between about 3-500 nm, for example between about 50-100 nm or between about 40-85 nm. In someembodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm. In some embodiments, the stack comprises at least one of a layer of SiN and SiON.

[0053] As used herein, “high aspect ratio” as applied to features in a substrate refers to a depth to width aspect ratio on the order of approximately 60: 1 or higher. More preferably, this range may include ratios greater than 100:1, 120:1, 140: 1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30: 1, or 10:1. In some embodiments the features may have a depth from 3 nm to 10 pm.

[0054] The dimensional / parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions / parameters may also be applicable or used.APPARATUS

[0055] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility.

[0056] Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma- as sis ted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0057] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer toa silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0058] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value.

[0059] FIG. 5 is a schematic view of an etch reactor system 500 that may be used in some embodiments. In some embodiments, an etch reactor system 500 comprises a gas distribution plate 506 providing a gas inlet and an electrostatic chuck (ESC) 508, within an etch (or process) chamber 509, enclosed by a chamber wall 552. Within the etch chamber 509, a stack 204 is positioned over the ESC 508 that is used as a substrate support. A bias may be provided to the ESC 508 from an ESC source 548. A gas source 510 is connected to the etch chamber 509 through the gas distribution plate 506. In some embodiments, the gas source 510 comprises an etch gas source 512, a scavenger gas source 516, and a hydrocarbon gas source 518. An ESC temperature controller 550 is connected to the ESC 508. A radio frequency (RF) source 530 provides RF power to a lower electrode and / or an upper electrode, which in this embodiment are the ESC 508 and the gas distribution plate 506, respectively. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz, 27 MHz power sources make up the RF source 530 and the ESC source 548. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be in separate RF sources or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. A controller 535 is controllably connected to the RF source 530, the ESC source 548, an exhaust pump 520, and the gas source 510. An example of such an etch chamber is the Vantex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0060] FIG. 6 is a high level block diagram showing a computer system 600, which is suitable for implementing the controller 535 used in embodiments. The computer system 600 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 600 includes one or more processors 602 and further can include an electronic display device 604 (for displaying graphics, text, and other data), a main memory 606 (e.g., random access memory (RAM)), storage device 608 (e.g., hard disk drive), removable storage device 610 (e.g., optical disk drive), user interface devices 612 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 614 (e.g., wireless network interface). The communications interface 614 allows software and data to be transferred between the computer system 600 and external devices via a link. The system may also include a communications infrastructure 616 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules are connected.

[0061] Information transferred via communications interface 614 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 614, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communications channels. With such a communications interface 614, it is contemplated that the one or more processors 602 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.

[0062] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0063] In some embodiments, the controller 535 is configured to a) provide a plasma formedfrom an etch gas, wherein the etch gas comprises a halogen containing component, b) provide a plasma formed from a sidewall passivation gas, wherein the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component. In some embodiments steps a and b are provided sequentially. In some embodiments, steps a and b are provided simultaneously. In some embodiments, steps a and b are provided cyclically for at least two cycles.

[0064] It is to be understood that the configurations and / or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.CONCLUSION

[0065] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C.’ Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of etching recessed features in a stack below a mask, comprising: a. providing a plasma formed from an etch gas, wherein the etch gas comprises a halogen containing component; and b. providing a plasma formed from a sidewall passivation gas, wherein the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component.

2. The method of claim 1 , wherein the hydrogen scavenger comprises a halogen containing component.

3. The method of claim 1, wherein the stack comprises silicon nitride.

4. The method of claim 1 , wherein the halogen containing component comprises a fluorine containing component.

5. The method of claim 1 , further comprising: placing the stack over a substrate support; and cooling the substrate support to a temperature below 0° C.

6. The method of claim 1, further comprising providing a pressure of less than 200 mTorr.

7. The method of claim 1, wherein the providing a plasma formed from a sidewall passivation gas comprises: providing a sidewall passivation gas; and providing an RF power, wherein the providing the RF power comprises providing at least one of providing continuous RF power and providing multistate pulsed RF power.

8. The method of claim 1 , wherein the mask is a carbon containing mask.

9. The method of claim 1 , wherein the providing the plasma formed from the etch gas and providing the plasma formed from the sidewall passivation gas are simultaneous.

10. The method of claim 1, wherein the hydrocarbon is at least one of CH4, C2H4, C2H2, and C3H4.

11. The method of claim 1 , wherein the hydrogen scavenger comprises at least one of HC1, HBr, HI, CI2, Br2, and a hydrofluorocarbon.

12. The method of claim 1 , wherein the hydrogen scavenger comprises at least one of Ch and Br2.

13. The method of claim 1, wherein the hydrogen scavenger is CI2.

14. The method of claim 1 , wherein steps a and b are provided sequentially.

15. The method of claim 1, wherein steps a and b are provided cyclically for at least two cycles.

16. The method of claim 1, wherein steps a and b are provided simultaneously.

17. A method of etching recessed features in a stack below a patterned mask forming mask features, comprising: i. providing an etch gas, wherein the etch gas comprises a halogen containing component; ii. providing a sidewall passivation gas, wherein the sidewall passivation gas comprises a hydrocarbon and a hydrogen scavenger containing component; iii. transforming the etch gas and sidewall passivation gas into a plasma by providing a multistate pulsed RF power with two or three states; and iv. exposing the stack to the plasma.

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