Semiconductor layers for voltaic devices

Abstract

A semiconductor layer on a substrate, the semiconductor layer being a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite. Also provided is a method of forming the above semiconductor layer on a substrate, the method including mixing semiconductor particles, cohesion particles and a non-solvent liquefier to form a solid suspension, coating the solid suspension on a substrate and removing liquefier from the as-coated solid suspension to form the above semiconductor layer.

Description

SEMICONDUCTOR LAYERS FOR VOLTAIC DEVICESRELATED APPLICATION

[0001] This application claims convention priority from Australian provisional patent application 2023904192 filed on 22 December 2023, the content of which is incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates to improved semiconductor layers and methods for the formation of such improved semiconductor layers, the semiconductor layers being suitable for use in voltaic devices, such as photovoltaic devices. Although the invention is not to be limited to only these uses, typical uses for such devices include solar cells for producing solar power.BACKGROUND OF THE INVENTION

[0003] Photovoltaic devices rely on the conversion of light into electrical energy using semiconductor materials that exhibit a photovoltaic effect. Semiconductor layers are critical for such devices, with these layers being responsible for the absorption of the incoming radiation (such as sunlight) and generating electron-hole pairs to yield electrical power. Such semiconductor layers are often formed by recrystallization processes, such as the spin coating of dissolved semiconductor chemicals in a solvent, where the active area of single cells produced is often only within the mm2scale.

[0004] Methods such as these can also be limiting in thickness and prone to short circuiting devices, often due to the poor wettability of an underlying substrate and subsequent difficulties in forming semiconductor layers resulting in the formation of pin holes. Additionally, the need for high temperature annealing to crystallise a semiconductor to form a desired atomic structure again leads to limitations in the form of an underlying substrate and / or other layers in a voltaic device.

[0005] The present invention aims to provide an effective semiconductor layer that is scalable to larger surface areas and that can be relatively simply formed on substrates that need not be complex or speciality substrates. In this respect, while emphasis in the following description might sometimes be on the semiconductor layersof the present invention being for use in photovoltaic devices, the invention is not to be so limited. To be clear, the present invention relates to semiconductor layers for all voltaic devices.SUMMARY OF THE INVENTION

[0006] The present invention provides a semiconductor layer on a substrate, the semiconductor layer being a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite.

[0007] The present invention also provides a method of forming a semiconductor layer on a substrate, the method including mixing semiconductor particles, cohesion particles and a non-solvent liquefier to form a solid suspension, coating the solid suspension on a substrate and removing liquefier from the as-coated solid suspension to form the semiconductor layer, wherein the semiconductor layer is a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite.

[0008] Alternatively, the cohesion particles may be 20% to 40% v / v of the solid particulate composite. Further, the cohesion particles may be 25% to 35% v / v of the solid particulate composite. Further still, the cohesion particles may be about 30% v / v of the solid particulate composite.

[0009] The semiconductor layer of the present invention is substrate independent, allowing the use of simple substrates such as glass, foil or polymer. As a result, it has been found that a voltaic device incorporating the semiconductor layer of the present invention can have a structure that is either conventional (substrate, electron transport layer, semiconductor, hole transport layer, top contact) or inverted (substrate, hole transport layer, semiconductor, electron transport layer, top contact), and either with or without transport layers. This is useful because, amongst other reasons, it allows for the presence of a depletion region within the device, the depletion region being a target area for the energy source to hit and create the electron / hole pairs that will generate the current output in the device. Depending on the application of the device, the location of such a depletion region within the device is ideally different since the device can be exposed to the energy source from opposite sides.

[0010] Moreover, the present invention allows the tailoring of the composition of a semiconductor layer, such as by changing the stoichiometry of the semiconductor layer, by doping the semiconductor layer with particles of different composition, or by adopting a thickness for the semiconductor layer to suit the requirements of a final voltaic device.

[0011] Indeed, it will be appreciated that in some forms of the present invention, post-processing steps may also be adopted to further modify the semiconductor layer, such that the resultant properties and / or function of the semiconductor are enhanced, which may change the volume ratio of semiconductor particle to cohesion particle in the semiconductor layer

[0012] Further, it will be appreciated that in some forms of the present invention, it may be desirable to coat a substrate with multiple of the inventive semiconductor layers, such that the method of the invention includes multiple solid suspension coating steps, each time removing the non-solvent liquefier in order to form a new semiconductor layer.

[0013] Further still, and with respect to the use herein of the phrase “a semiconductor layer on a substrate”, a skilled addressee will understand that it may be desirable to include between the substrate and the semiconductor layer a layer of another type. The reference to “on a substrate” must therefore be understood with this in mind.

[0014] The present invention thus provides versatility in terms of substrate used, device configuration, semiconductor composition, thickness and roughness, and device size and shape.

[0015] In relation to preferred general characteristics of the semiconductor layer of the present invention, the layer is preferably of a desired thickness for a given radiation energy. In this respect, the higher the radiation energy, the thicker the desired layer. For low energy photovoltaic devices, such as devices where an incoming photon has an energy in the range of 0.5 to 3.0 eV, the semiconductor layer will be thinner and will ideally have a thickness (a final, dry thickness) in the range of 100 nm to 400 micron. In other forms, the semiconductor layer may have a thickness in the range of 200 nm to 350 micron, or in the range of 200 nm to 200 micron, or in the range of 200 nm to100 micron, or in the range of 200 nm to 50 micron, or in the range of 200 nm to 5 micron.

[0016] Having said that, it will be appreciated that the thickness of the semiconductor layer is also related to the rheology (namely, the viscosity as a function of shear rate) of the solid suspension formed in the method. In this respect, as the concentration of solids in the suspension increases, the viscosity increases (and vice- versa), with the method of the invention preferring a higher viscosity to assist with the coating of the solid suspension on the substrate. In the method of the present invention, a solid fraction in the range of 15% to 30% v / v in the solid suspension is preferred, or in the range of 18% to 25% v / v, 20% to 23% v / v, or more preferably about 21% v / v.

[0017] In one form, and in relation to a preferred viscosity of the solid suspension, it has been found to be advantageous for the solid suspension to be shear-thinning, in the sense that the solid suspension will flow while under shear forces to assist with the coating of the solid suspension on the substrate. In this respect, when the shear force is discontinued, the solid suspension will have an effectively high viscosity to retain its shape and form on the substrate, assisting with preventing further flow of the solid suspension.

[0018] Viscosity is also inversely proportional to particle size, with smaller particles providing higher viscosity for a given solid fraction, so it has been recognised that there is also a balance to be struck in determining ideal particle sizes for of the semiconductor particles and the cohesion particles. In a preferred form, the semiconductor particles and the cohesion particles have a diameter in the range of 200 nm and 5000 nm and are provided to the method in the form of a dry powder.

[0019] In another preferred form, the method may include, either after the liquefier is removed or at the same time as removing the liquefier, compaction of the semiconductor layer. Such compaction will assist to densify the solid particulate composite and / or improve the mechanical strength of the semiconductor layer. The compaction may be provided by known compaction apparatus, such as uniaxial hydraulic presses, roll presses or calendars, which apparatus may or may not provide some degree of heating during compaction.

[0020] In this respect, it will be understood that a preferred aim is to preserve the voltaic performance of the semiconductor particles once formed in the semiconductor layer. To this end, it has been found to be advantageous to include larger particles where the intra-particle performance is maximised relative to inter-particle, which assists with minimising the number of particle-to-particle contacts (inter-) and maximising the amount of internal particle mechanisms (intra-).

[0021] Ideally then, the adoption of a compaction step in the method of the present invention can serve to densify the solid particulate composite to assist with maximising the physical contact between neighbouring particles. Additionally, maximising the particle-to-particle contact also assists with the cohesion role played by the cohesion particles.

[0022] It will thus be understood that the semiconductor layer of the present invention, being formed from a particulate composite, therefore ideally has a non-zero porosity. By way of explanation, a zero-porosity semiconductor layer would be an extreme limit where only intra-, and no inter-, particle mechanisms were present, which would imply a single crystal semiconductor with zero-porosity. However, for the present invention this would be undesirable as it would require the use of the difficult and challenging coating processes referred to above as being problematic.

[0023] It will then be understood that the other extreme would be the use of very small particles where the inter- is maximised, and the intra- is minimised. However, this scenario would tend to provide a semiconductor layer with high porosity and poor performance.

[0024] In the present invention, and in very general terms, the semiconductor layer is a solid particulate composite of semiconductor particles and cohesion particles, which will be understood to thereby ideally have a non-zero porosity. In the present invention, the inter-particle mechanisms are preferably minimised, preferably by using relatively large particles. However, the particles are ideally connected in a network-like structure, relatively densely and such that the porosity is minimised.

[0025] The final semiconductor layer is thus preferably such that it has a desired voltaic function, in the sense that the layer absorbs the incoming radiation and generates electron-hole pairs, then transporting them to electrodes under an internalelectric field, to be extracted from the device to create power. The semiconductor layer preferably also has a desired mechanical strength, permitting strong adhesion to any substrate and strong cohesion such that the layer will not crumble or disintegrate. In this respect, an ideal mechanical strength would be where there is high enough cohesion within the solid particulate composite such that it can withstand any reasonable external mechanical force without degradation.

[0026] In relation to the material of the semiconductor particles in the semiconductor layer of the present invention, preferably the semiconductor particles will be of a material with an electronic bandgap that is intermediate-sized and non-zero and that behaves as an insulator at absolute zero. With this in mind, it will be understood that at a temperature below a semiconductor material’s melting point, electrons can be excited from the top of the valence band into the bottom of the conduction band (across the bandgap) by thermal excitation. In contrast, a material with a large band gap is an insulator (no amount of thermal excitation can excite an electron across the bandgap), while a material with no bandgap is a conductor.

[0027] The semiconductor material may itself be semiconducting in nature (an intrinsic semiconductor) or may require doping of some form to render it semiconducting (an extrinsic semiconductor). In the latter form, typically the doping leads to a reduction in the bandgap such that thermal excitation can excite electrons across the bandgap. Also, more than one semiconductor material can be used, such that the semiconductor layer includes more than one type of semiconductor particle.

[0028] More specifically, the semiconductor material may be one or more materials selected from the groups comprising: i. silicon, germanium, and the like; ii. silicon carbide, gallium nitride, aluminium Nitride, gallium arsenide, diamond, aluminium arsenide, aluminium gallium arsenide, boron nitride, zinc selenide, and the like; iii. N-doped silicon carbide, N-doped gallium nitride, N-doped silicon, and the like; iv. zinc oxide, titanium dioxide, nickel oxide, tin oxide, copper oxide, zinc sulfide, tungsten oxide, molybdenum oxide, and the like;v. perovskite compounds with a crystal structure following the general formula ABX3, including caesium lead tribromide, methylammonium lead triiodide, caesium tin trichloride, and the like and vi. poly(3,4-ethylenedioxythiophene):polystyrenesulfonate, polyaniline:chloride; polypyrrole: perchlorate; polythiophene:chloride; poly(3- hexylthiophene):chloride; poly(3,4-ethylenedioxythiophene):tosylate, and the like.

[0029] In relation to the perovskite compounds, these include a specific mineral ‘perovskite’ following the general formular ABX3. 'A' and 'B' are positively charged ions (cations), usually of different sizes, with X being a negatively charged ion (an anion) that bonds to both cations, and with the 'A' atoms generally being larger than the 'B' atoms. An ideal cubic structure has the B cation in 6-fold coordination, surrounded by an octahedron of anions, and the A cation in 12-fold cuboctahedral coordination. Additional perovskite forms may exist where either or both the A and B sites have a configuration of A1x-iA2xand / or B1y-iB2yand the X may deviate from the ideal coordination configuration as ions within the A and B sites undergo changes in their oxidation states. Natural compounds with this structure are perovskite, loparite, and the silicate perovskite bridgmanite.

[0030] In preferred forms, the semiconductor material will be either the inorganic halide perovskites (for example, CsPbB ) or the hybrid organic-inorganic halide perovskites (for example, MAPbh).

[0031] As mentioned above, the final semiconductor layer is preferably such that it has a desired voltaic function, in the sense that the layer absorbs the incoming radiation and generates electron-hole pairs, then transporting them to electrodes under an internal electric field, to be extracted from the device to create power. Ideally then, the cohesion particles will be of a material that does not inhibit this function, is a solid at room temperature, and that also has an affinity for semiconductor grain boundaries.

[0032] In this respect, the cohesion particles used to form the semiconductor layer will preferably be of a material capable of providing mechanical cohesion to the semiconductor layer without being detrimental to the voltaic performance of a voltaic device incorporating the semiconductor layer. A preferred example is the polyethyleneglycols, which are solids at room temperature. Other suitable cohesion materials are polyamides, epoxies and the like.

[0033] In relation to the liquefier used in the method of the present invention, the reference throughout this specification to the liquefier being a ‘non-solvent’ liquefier is intended to narrow the list of preferred liquefiers to exclude those that might dissolve either the semiconductor particles or the cohesion particles.

[0034] In a preferred form, the non-solvent liquefier used to form the solid suspension will be of a type that allows the solid suspension to flow so as to allow simple film coating processes to be used, such as doctor blade coating, bar coating or slot die coating and the like.

[0035] The non-solvent liquefier will also ideally be of a type that allows the liquefier to be easily removed from the as-coated solid suspension, such as by using relatively low-temperature drying processes, for example being drying temperatures in the order of 40°C to 100°C.

[0036] Suitable liquefiers are envisaged to be glycerol, ethylene glycol, ethyl cellulose, isopropyl alcohol, n-butanol or water and the like, depending upon the material of the semiconductor particles and the cohesion particles as mentioned above.

[0037] From the above description of the present invention, it will thus be appreciated that the improved semiconductor layer is able to retain the chemistry and voltaic performance of the particulate feedstock, without the need for complex solvents or anti-solvents, or for any thermal treatment of the semiconductor to induce desired properties, or for special substrates to accommodate complex semiconductor processing.

[0038] Finally, the present invention of course also provides a voltaic device, such as a photovoltaic device, the voltaic device including a semiconductor layer on a substrate, the semiconductor layer being a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite. Alternatively, the cohesion particles may be 20% to 40% v / v of the solid particulate composite. Further, the cohesionparticles may be 25% to 35% v / v of the solid particulate composite. Further still, the cohesion particles may be about 30% v / v of the solid particulate composite.DESCRIPTION OF PREFERRED EMBODIMENTS

[0039] The present invention will now be described with reference to preferred embodiments as illustrated by various worked examples. However, the following description is not to limit the generality of the above description.

[0040] In a first example of the present invention, prepared for the purposes of comparison with three comparative examples described below, 1.5 g of semiconductor particles of the perovskite compound CsPbB was mixed with 0.15 g of pre-ground cohesion particles of polyethylene glycol (PEG) in a vial and then 1 mL of the nonsolvent liquefier isopropyl alcohol was added. The mixture was stirred with a magnetic stirrer for 30 minutes to produce a solid suspension. The particle diameter of both the semiconductor particles and the cohesion particles was between 200 nm and 5 micron.

[0041] The solid suspension was then coated using a doctor blade coating process on a glass substrate pre-coated with 500 nm of fluorine-doped tin oxide (FTO) and 35 nm of zinc oxide (ZnO) as an electron transport layer. The resultant semiconductor layer was then dried at 60 °C for 1 hour to remove substantially all of the liquefier. The thickness of this semiconductor layer was measured to be 45 micron uniformly covering an area of greater than 20 cm2and the layer was noted to have a non-zero porosity, using a mechanical profilometer. The layer was then overcoated with a hole transport layer (NiOx) of 150 nm and an electrode (Au) of 150 nm to create a voltaic device.

[0042] Before turning to the measured electrical performance of this exemplary voltaic device, it will be appreciated that it would have been possible to have also passed the semiconductor layer, while still warm, through a calendaring process to compact and densify the layer. In this example, this would have resulted in a more densely packed solid particulate composite consisting of about 70% semiconductor particles and about 30% cohesion particles by volume of the solid phase. Due to such packing of particles, the resultant layer would still have had non-zero porosity.

[0043] The electrical performance of the formed voltaic device was characterised using a source meter unit to measure current flowing through the device as a functionof the applied voltage across the two electrodes (FTO and Au). The current-voltage curve was measured when the device was “dark” (no light exposure) and “illuminated” (exposed to a solar simulator). The short circuit current, open circuit voltage, fill factor and efficiency were all determined from the illuminated response, noting the open circuit voltage under dark conditions was 0.10 V. The electrical performance is reported in Table 1.Table 1

[0044] In a first comparative example, a 0.5M solution of semiconductor perovskite compound CsPbBrs was dissolved in dimethylsulfoxide (DMSO) with a 1 :0.1 molar ratio of liquid polyethylene glycol to CsPbBrs. This liquid was spin coated onto 5cm2area FTO coated glass substrates that had been precoated with 30nm of amorphous ZnO as an electron transport layer. Prior to spin coating, the substrates were preheated to 85°C.

[0045] The solution was spin coated at 500 RPM for 10 seconds and then 2000 RPM for 30 seconds. The CsPbB was annealed at 120 to 150°C for 30 minutes to remove the DMSO and crystallise the perovskite compound. The resultant semiconductor layer was 300 nm thick. This layer was then overcoated with NiOx (30nm) and Au (180nm) to again produce a voltaic device, albeit not one in accordance with the present invention.

[0046] The electrical performance was again characterised using a source meter unit to measure the current that flows through the device as a function of the applied voltage across the two electrodes. The current-voltage curve was measured when the device was “dark” (no light exposure) and “illuminated” (exposed to a solar simulator). The short circuit current, open circuit voltage, fill factor and efficiency were all determined from the illuminated response. The electrical performance is reported in Table 2.Table 2

[0047] In a second comparative example, a two step recrystallization process was used. Firstly, 1 M solution of the precursor compound PbBr2 was dissolved in dimethylformamide (DMF) with a 1 :0.05 molar ratio of liquid polyethylene glycol to PbBr2 and stirred at 65 to 80°C for over 4 hours. This liquid was spin coated while at 80°C onto 5 cm2area FTO coated glass substrates that had been precoated with 30nm of amorphous ZnO as an electron transport layer. Prior to spin coating, the substrate was preheated to 80°C.

[0048] The PbBr2 plus PEG layer was spin coated at 80 RPM for 3 sec and then 2000 RPM for 30 sec, and then annealed at 100°C for 1 hour to remove the DMF and crystallise the precursor compound.

[0049] Secondly, a 1 ,5M solution of precursor compound CsBr in water was stirred at 40 to 80°C for 2 hours and then spin coated onto the PbBr2 plus PEG layer at room temperature at 800 RPM for 3 sec and 2000 RPM for 30 sec. The resultant multilayer was annealed at 250°C for 10 min for reaction of the precursors to form the CsPbB plus PEG layer. The resultant semiconductor layer was 620 nm thick. This layer was then overcoated with NiOx (150nm) and Au (150nm) to again produce a voltaic device, albeit not one in accordance with the present invention.

[0050] The electrical performance was again characterised using a source meter unit to measure the current that flows through the device as a function of the applied voltage across the two electrodes. The current-voltage curve was measured when the device was “dark” (no light exposure) and “illuminated” (exposed to a solar simulator). The short circuit current, open circuit voltage, fill factor and efficiency were all determined from the illuminated response. The electrical performance is reported in Table 3.Table 3

[0051] In a third comparative example, 1.4 g of the CsPbBrs was mixed with 0.14 g of PEG in a mortar and was ground until a homogeneous mixture was formed. 750 uL of DMSO as a traditional solvent was then added and grinding was continued for a few seconds to form a solid suspension. The solid suspension was then coated on a glass substrate with 500 nm FTO and 30 nm ZnO using a doctor blade coating process. The resultant coating was then dried at 60 °C for 1 hour. The resultant coating was visibly non-uniform to the eye, with obvious pin holes and defects.

[0052] The CsPbBrs in this comparative example, even with the relatively low amount of DMSO, was completely dissolved and a recrystallization deposition was obtained instead of the coating that can be obtained when using a non-solvent liquefier instead of a solvent.

[0053] The first example of the present invention yielded a functioning voltaic device that overcomes the challenges and problems associated with processing temperatures above 100°C (first and second comparative examples), relatively complex precursor solutions (second comparative example), poor wetting of the substrate (third comparative example), limited coating area (first and second comparative examples), and limited layer thickness (first and second comparative examples).

[0054] Several more specific examples will now additionally be provided, referred to as Examples A to I and described with reference to the accompanying Figures 1 to 12, which are as follows:

[0055] Figures 1 to 3 relate to Example A and are: a. Figure 1 - cross section images of a full device obtained by A) Electron Beam Induced Current (EBIC) (white areas represent current being generated), B) Scanning Electron Microscope (SEM) (lighter areas represent full device);b. Figure 2 - top view images of a full device obtained by A) EBIC (white areas represent current being generated), B) SEM (lighter areas represent full device); and c. Figure 3 - is a dark l-V curve;

[0056] Figure 4 is a dark l-V curve related to Example B;

[0057] Figure 5 is a dark l-V curve related to Example C;

[0058] Figure 6 is a dark l-V curve related to Example D;

[0059] Figure 7 is a dark l-V curve related to Example E;

[0060] Figure 8 is a dark l-V curve related to Example F;

[0061] Figure 9 is a dark-IV curve related to Example G;

[0062] Figure 10 relates to Example H and is a normalised current response obtained under dark and 1 sun conditions; and

[0063] Figures 11 and 12 relate to Example I and are: a. Figure 11 - a dark l-V curve; and b. Figure 12 - a normalised current response obtained under dark and sun 1 conditions.

[0064] Examples A to I will now be described more fully in the following paragraphs.Example A

[0065] Preparation of solid suspension: both cohesion particles and semiconductor particles were milled with a mortar and pestle. In the mortar, 0.064 grams of PEG was mixed with 0.651 grams of CsPbB and ground until a homogeneous mixture was formed. 0.5 mL of isopropyl alcohol was then added to the homogenous mixture to form the CsPbBrs solid suspension in the form of a slurry. The solid suspension was then coated onto the substrate mentioned below using a doctor blade coating process. After coating the solid suspension, samples were left to dry in atmospheric conditions before finishing the voltaic device as below. The average thickness of the depositedsemiconductor layer was 45 .m, while the volume ratio of semiconductor to cohesion particles was 71 / 29.

[0066] Voltaic device structure: being provided in the general form of substrate / contact / ETL / CsPbBrs / HTL / contact, but more specifically in this example being glass / ITO / ZnO / CsRbB / NiOx / Au. All layers were deposited via PVD, except for the CsPbBrs solid suspension that was deposited via blade coating as per above.

[0067] An electrical inspection of the voltaic device in Figure 1A shows the crosssection EBIC image, where white regions represent electrical current being generated, and dark regions represent no electrical current. Figure 1 B is the corresponding SEM image, where the lighter area corresponds to the full device area.

[0068] An electrical inspection of the voltaic device in Figure 2A shows the top view EBIC image, where white regions represent electrical current being generated and dark regions mean no electrical current. Figure 2B is the corresponding SEM image, where the lighter area corresponds to the full device area.

[0069] An electrical inspection of the voltaic device in Figure 3 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scaleExample B

[0070] In this example, the voltaic device fabrication followed the same process and structure as Example A, however the preparation of the solid suspension utilised a different milling process and a calendaring step.

[0071] A 2 mL vial filled with 1.5 mm diameter hardened zirconia grinding media was used for milling the cohesive particles and the semiconductor particles. 0.07 grams of PEG was weighed into the 2 mL vial, with 0.820 mL of isopropyl alcohol. This was placed in a BeadBug 6 homogeniser to grind the cohesion particles for 10 cycles of 2500 rpm for 90 s / cycle with a 30 s dwell between cycles. To this, 0.76 grams of CsPbBrs was weighed into the same 2 mL vial. This was then milled for 10 cycles of 2500 rpm for 90 s / cycle with a 1 s dwell between cycles. The average thickness of the semiconductor layer after calendaring was 20 .m, while with the volume ratio in the layer of semiconductor to cohesion particles was 72 / 28.

[0072] An electrical inspection of the voltaic device in Figure 4 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scale.Example C

[0073] Slurry and device fabrication followed the same as Example B, except the cohesion particles were Nylon 6 instead of PEG.

[0074] An electrical inspection of the voltaic device in Figure 5 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scale.Example D

[0075] Slurry and device fabrication followed the same as Example A, except the semiconductor particles were n-SiC instead of CsPbB . To achieve this, n-SiC particles were prepared by milling an n-SiC wafer (Summit Semiconductors) in a WC ring mill (Rocklabs) with a WC headset. The slurry shown in this example contains a mixture of two different particle sizes achieved by varying the milling time: 30 wt% of n-SiC was milled during 80 s, and 70 wt% was milled for 240 s. The volume ratio in the layer of semiconductor to cohesion particles was 72 / 28.

[0076] Device structure: substrate / LWF contact / n-SiC / HWF contact. All layers were deposited via PVD except for the n-SiC that was deposited via blade coating. (LWF = Low Work Function; HWF = High Work Function).

[0077] An electrical inspection of the voltaic device in Figure 6 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scale.Example E

[0078] Slurry and device fabrication followed the same as Example D, except the semiconductor slurry was drop casted. The slurry used in this example was milled during 40 s. The volume ratio in the layer of semiconductor to cohesion particles was 72 / 28.

[0079] Device structure: substrate / LWF contact / n-SiC / HWF contact. All layers were deposited via PVD except for the n-SiC that was deposited via drop cast.

[0080] An electrical inspection of the voltaic device in Figure 7 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scale.Example F

[0081] Slurry and device fabrication followed the same as Example B, except the mass of PEG cohesion particles was increased to 50% in volume. Therefore, the volume ratio in the layer of semiconductor to cohesion particles was 50 / 50.

[0082] An electrical inspection of the voltaic device in Figure 8 does not show a Dark IV response indicative of a semiconductor layer. That is, a linear increment of the current with voltage in the logarithmic scale is observed.Example G

[0083] Slurry and device fabrication followed the same as Example B, except the mass of PEG cohesion particles was increased to 10% in volume. Therefore, the volume ratio in the layer of semiconductor to cohesion particles was 90 / 10.

[0084] An electrical inspection of the voltaic device in Figure 9 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scale.Example H

[0085] For the device fabricated in Example B, an electrical inspection can be made of the photovoltaic response - shown in Figure 10. That is, when the device is illuminated with simulated solar light (Newport LSH-7320) a significant increase in current is observed (x2000 increase).Example I

[0086] This example follows the same methodology of fabrication as Example B, except that after the semiconductor deposition / calendaring, but prior to the additional layers being added, it is heat treated at 400 °C.

[0087] An electrical inspection of the voltaic device in Figure 11 shows a Dark IV response indicative of a semiconductor layer. That is, a non-linear increment of the current with voltage in the logarithmic scale.

[0088] An electrical inspection can be made of the photovoltaic response - shown in Figure 12. That is, when the device is illuminated with simulated solar light (Newport JSH-7320) a significant increase in current is observed (greater than x2000 increase).

[0089] Finally, it is to be understood that other variations and modifications of the matters described above may also fall within the scope of the present invention.

Claims

The claims defining the invention are as follows:

1. A semiconductor layer on a substrate, the semiconductor layer being a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite.

2. A semiconductor layer according to claim 1 , wherein the cohesion particles may be 20% to 40% v / v of the solid particulate composite, or 25% to 35% v / v of the solid particulate composite, or about 30% v / v of the solid particulate composite.

3. A semiconductor layer according to claim 1 or claim 2, wherein the semiconductor layer is a desired thickness for a given radiation energy, wherein the higher the radiation energy, the thicker the desired layer.

4. A semiconductor layer according to any one of claims 1 to 3, wherein the semiconductor layer will be, or is, incorporated in a low energy photovoltaic device where an incoming photon has an energy in the range of 0.5 to 3.0 eV, and the semiconductor layer has a thickness in the range of 100 nm to 400 micron.

5. A semiconductor layer according to any one of claims 1 to 4, wherein the semiconductor layer has a thickness in the range of 100 nm to 400 micron, or in the range of 200 nm to 350 micron, or in the range of 200 nm to 200 micron, or in the range of 200 nm to 100 micron, or in the range of 200 nm to 50 micron, or in the range of 200 nm to 5 micron.

6. A semiconductor layer according to any one of claims 1 to 5, wherein the semiconductor particles and the cohesion particles have a diameter in the range of 200 nm and 5 micron.

7. A semiconductor layer according to any one of claims 1 to 6, wherein the porosity of the semiconductor layer is non-zero.

8. A semiconductor layer according to any one of claims 1 to 7, wherein the semiconductor layer has a mechanical strength that permits strong adhesion toa substrate and strong cohesion such that the semiconductor layer will not crumble or disintegrate.

9. A semiconductor layer according to any one of claims 1 to 8, wherein the material of the semiconductor particles is a material with an electronic bandgap that is intermediate-sized and non-zero and that behaves as an insulator at absolute zero.

10. A semiconductor layer according to any one of claims 1 to 9, wherein the material of the semiconductor particles is semiconducting in nature (an intrinsic semiconductor) or requires doping to render it semiconducting (an extrinsic semiconductor).

11. A semiconductor layer according to any one of claims 1 to 10, wherein the semiconductor material is one or more materials selected from the groups comprising: i. silicon, germanium, and the like; ii. silicon carbide, gallium nitride, aluminium Nitride, gallium arsenide, diamond, aluminium arsenide, aluminium gallium arsenide, boron nitride, zinc selenide, and the like; iii. N-doped silicon carbide, N-doped gallium nitride, N-doped silicon, and the like; iv. zinc oxide, titanium dioxide, nickel oxide, tin oxide, copper oxide, zinc sulfide, tungsten oxide, molybdenum oxide, and the like; v. perovskite compounds with a crystal structure following the general formula ABX3, including caesium lead tribromide, methylammonium lead triiodide, caesium tin trichloride, and the like; and vi. poly(3,4-ethylenedioxythiophene): polystyrenesulfonate, polyaniline:chloride; polypyrrole: perchlorate; polythiophene:chloride; poly(3- hexylthiophene):chloride; poly(3,4-ethylenedioxythiophene):tosylate, and the like.

12. A semiconductor layer according to claim 11 wherein the semiconductor material is one or more of the perovskite compounds.

13. A semiconductor layer according to claim 12, wherein the perovskite compounds are either inorganic halide perovskites or hybrid organic-inorganic halide perovskites.

14. A semiconductor layer according to claim 13, wherein the perovskite compound is the inorganic halide perovskite CsPbB , or the hybrid organic-inorganic halide perovskite MAPbh.

15. A semiconductor layer according to any one of claims 1 to 14, wherein the material of the cohesion particles is a polyethylene glycol or a polyamide.

16. A method of forming a semiconductor layer on a substrate, the method including mixing semiconductor particles, cohesion particles and a non-solvent liquefier to form a solid suspension, coating the solid suspension on a substrate and removing liquefier from the as-coated solid suspension to form the semiconductor layer, wherein the semiconductor layer is a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite.

17. A method according to claim 16, wherein the cohesion particles may be 20% to 40% v / v of the solid particulate composite, or 25% to 35% v / v of the solid particulate composite, or about 30% v / v of the solid particulate composite.

18. A method according to claim 16 or claim 17, wherein solid suspension has a solid fraction in the range of 15% to 30% v / v, or 18% to 25% v / v, or 20% to 23% v / v, or about 21% v / v.

19. A method according to any one of claims 16 to 18, wherein the semiconductor layer is coated in a desired thickness for a given radiation energy, wherein the higher the radiation energy, the thicker the desired layer.

20. A method according to any one of claims 16 to 19, wherein the semiconductor layer has a thickness in the range of 100 nm to 400 micron, or in the range of 200 nm to 350 micron, or in the range of 200 nm to 200 micron, or in the range of 200 nm to 100 micron, or in the range of 200 nm to 50 micron, or in the range of 200 nm to 5 micron.

21. A method according to any one of claims 16 to 20, wherein the semiconductor particles and the cohesion particles have a diameter in the range of 200 nm and 5000 nm.

22. A method according to any one of claims 16 to 21 , wherein the semiconductor layer has a mechanical strength that permits strong adhesion to a substrate and strong cohesion such that the semiconductor layer will not crumble or disintegrate.

23. A method according to any one of claims 16 to 22, wherein the material of the semiconductor particles is a material with an electronic bandgap that is intermediate-sized and non-zero and that behaves as an insulator at absolute zero.

24. A method according to any one of claims 16 to 23, wherein the material of the semiconductor particles is semiconducting in nature (an intrinsic semiconductor) or requires doping to render it semiconducting (an extrinsic semiconductor).

25. A method according to any one of claims 16 to 24, wherein the semiconductor material is one or more materials selected from the groups comprising: i. silicon, germanium, and the like; ii. silicon carbide, gallium nitride, aluminium Nitride, gallium arsenide, diamond, aluminium arsenide, aluminium gallium arsenide, boron nitride, zinc selenide, and the like; iii. N-doped silicon carbide, N-doped gallium nitride, N-doped silicon, and the like; iv. zinc oxide, titanium dioxide, nickel oxide, tin oxide, copper oxide, zinc sulfide, tungsten oxide, molybdenum oxide, and the like; v. perovskite compounds with a crystal structure following the general formula ABX3, including caesium lead tribromide, methylammonium lead triiodide, caesium tin trichloride, and the like; and vi. poly(3,4-ethylenedioxythiophene): polystyrenesulfonate, polyaniline:chloride; polypyrrole: perchlorate; polythiophene:chloride; poly(3- hexylthiophene):chloride; poly(3,4-ethylenedioxythiophene):tosylate, and the like.

26. A method according to claim 25, wherein the semiconductor material is one or more of the perovskite compounds.

27. A method according to claim 26, wherein the perovskite compounds are either inorganic halide perovskites or hybrid organic-inorganic halide perovskites.

28. A method according to claim 27, wherein the perovskite compound is the inorganic halide perovskite CsPbBrs, or the hybrid organic-inorganic halide perovskite MAPbh.

29. A method according to any one of claims 16 to 28, wherein the material of the cohesion particles is a polyethylene glycol or a polyamide.

30. A method according to any one of claims 16 to 29, wherein the non-solvent liquefier allows the solid suspension to flow so as to allow simple thin-film coating processes to be used, including doctor blade coating, bar coating or slot die coating and the like.

31. A method according to any one of claims 16 to 30, wherein the non-solvent liquefier is removed from the as-coated solid suspension by using drying temperatures in the range of 40°C to 100°C.

32. A method according to any one of claims 16 to 31 , wherein the liquefier is glycerol, ethylene glycol, ethyl cellulose, isopropyl alcohol, n-butanol or water and the like.

33. A method according to any one of claims 16 to 32, including the compaction of the solid particulate composite.

34. A method according to claim 33, wherein the compaction is conducted by a uniaxial hydraulic press, a roll press or a calendar.

35. A voltaic device including a semiconductor layer on a substrate, the semiconductor layer being a solid particulate composite of semiconductor particles and cohesion particles, wherein the cohesion particles are 10% to 45% v / v of the solid particulate composite.

36. A voltaic device including a semiconductor layer in accordance with the semiconductor layer of any one of claims 1 to 15.

37. A voltaic device including a semiconductor layer formed in accordance with the method of any one of claims 16 to 34.

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